linux/drivers/net/can/c_can/c_can_platform.c
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   1/*
   2 * Platform CAN bus driver for Bosch C_CAN controller
   3 *
   4 * Copyright (C) 2010 ST Microelectronics
   5 * Bhupesh Sharma <bhupesh.sharma@st.com>
   6 *
   7 * Borrowed heavily from the C_CAN driver originally written by:
   8 * Copyright (C) 2007
   9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
  10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
  11 *
  12 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
  13 * Bosch C_CAN user manual can be obtained from:
  14 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
  15 * users_manual_c_can.pdf
  16 *
  17 * This file is licensed under the terms of the GNU General Public
  18 * License version 2. This program is licensed "as is" without any
  19 * warranty of any kind, whether express or implied.
  20 */
  21
  22#include <linux/kernel.h>
  23#include <linux/module.h>
  24#include <linux/interrupt.h>
  25#include <linux/delay.h>
  26#include <linux/netdevice.h>
  27#include <linux/if_arp.h>
  28#include <linux/if_ether.h>
  29#include <linux/list.h>
  30#include <linux/io.h>
  31#include <linux/platform_device.h>
  32#include <linux/clk.h>
  33#include <linux/of.h>
  34#include <linux/of_device.h>
  35#include <linux/mfd/syscon.h>
  36#include <linux/regmap.h>
  37
  38#include <linux/can/dev.h>
  39
  40#include "c_can.h"
  41
  42#define DCAN_RAM_INIT_BIT               (1 << 3)
  43static DEFINE_SPINLOCK(raminit_lock);
  44/*
  45 * 16-bit c_can registers can be arranged differently in the memory
  46 * architecture of different implementations. For example: 16-bit
  47 * registers can be aligned to a 16-bit boundary or 32-bit boundary etc.
  48 * Handle the same by providing a common read/write interface.
  49 */
  50static u16 c_can_plat_read_reg_aligned_to_16bit(const struct c_can_priv *priv,
  51                                                enum reg index)
  52{
  53        return readw(priv->base + priv->regs[index]);
  54}
  55
  56static void c_can_plat_write_reg_aligned_to_16bit(const struct c_can_priv *priv,
  57                                                enum reg index, u16 val)
  58{
  59        writew(val, priv->base + priv->regs[index]);
  60}
  61
  62static u16 c_can_plat_read_reg_aligned_to_32bit(const struct c_can_priv *priv,
  63                                                enum reg index)
  64{
  65        return readw(priv->base + 2 * priv->regs[index]);
  66}
  67
  68static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv,
  69                                                enum reg index, u16 val)
  70{
  71        writew(val, priv->base + 2 * priv->regs[index]);
  72}
  73
  74static void c_can_hw_raminit_wait_syscon(const struct c_can_priv *priv,
  75                                         u32 mask, u32 val)
  76{
  77        const struct c_can_raminit *raminit = &priv->raminit_sys;
  78        int timeout = 0;
  79        u32 ctrl = 0;
  80
  81        /* We look only at the bits of our instance. */
  82        val &= mask;
  83        do {
  84                udelay(1);
  85                timeout++;
  86
  87                regmap_read(raminit->syscon, raminit->reg, &ctrl);
  88                if (timeout == 1000) {
  89                        dev_err(&priv->dev->dev, "%s: time out\n", __func__);
  90                        break;
  91                }
  92        } while ((ctrl & mask) != val);
  93}
  94
  95static void c_can_hw_raminit_syscon(const struct c_can_priv *priv, bool enable)
  96{
  97        const struct c_can_raminit *raminit = &priv->raminit_sys;
  98        u32 ctrl = 0;
  99        u32 mask;
 100
 101        spin_lock(&raminit_lock);
 102
 103        mask = 1 << raminit->bits.start | 1 << raminit->bits.done;
 104        regmap_read(raminit->syscon, raminit->reg, &ctrl);
 105
 106        /* We clear the start bit first. The start bit is
 107         * looking at the 0 -> transition, but is not self clearing;
 108         * NOTE: DONE must be written with 1 to clear it.
 109         * We can't clear the DONE bit here using regmap_update_bits()
 110         * as it will bypass the write if initial condition is START:0 DONE:1
 111         * e.g. on DRA7 which needs START pulse.
 112         */
 113        ctrl &= ~mask;  /* START = 0, DONE = 0 */
 114        regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl);
 115
 116        /* check if START bit is 0. Ignore DONE bit for now
 117         * as it can be either 0 or 1.
 118         */
 119        c_can_hw_raminit_wait_syscon(priv, 1 << raminit->bits.start, ctrl);
 120
 121        if (enable) {
 122                /* Clear DONE bit & set START bit. */
 123                ctrl |= 1 << raminit->bits.start;
 124                /* DONE must be written with 1 to clear it */
 125                ctrl |= 1 << raminit->bits.done;
 126                regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl);
 127                /* prevent further clearing of DONE bit */
 128                ctrl &= ~(1 << raminit->bits.done);
 129                /* clear START bit if start pulse is needed */
 130                if (raminit->needs_pulse) {
 131                        ctrl &= ~(1 << raminit->bits.start);
 132                        regmap_update_bits(raminit->syscon, raminit->reg,
 133                                           mask, ctrl);
 134                }
 135
 136                ctrl |= 1 << raminit->bits.done;
 137                c_can_hw_raminit_wait_syscon(priv, mask, ctrl);
 138        }
 139        spin_unlock(&raminit_lock);
 140}
 141
 142static u32 c_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index)
 143{
 144        u32 val;
 145
 146        val = priv->read_reg(priv, index);
 147        val |= ((u32) priv->read_reg(priv, index + 1)) << 16;
 148
 149        return val;
 150}
 151
 152static void c_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index,
 153                u32 val)
 154{
 155        priv->write_reg(priv, index + 1, val >> 16);
 156        priv->write_reg(priv, index, val);
 157}
 158
 159static u32 d_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index)
 160{
 161        return readl(priv->base + priv->regs[index]);
 162}
 163
 164static void d_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index,
 165                u32 val)
 166{
 167        writel(val, priv->base + priv->regs[index]);
 168}
 169
 170static void c_can_hw_raminit_wait(const struct c_can_priv *priv, u32 mask)
 171{
 172        while (priv->read_reg32(priv, C_CAN_FUNCTION_REG) & mask)
 173                udelay(1);
 174}
 175
 176static void c_can_hw_raminit(const struct c_can_priv *priv, bool enable)
 177{
 178        u32 ctrl;
 179
 180        ctrl = priv->read_reg32(priv, C_CAN_FUNCTION_REG);
 181        ctrl &= ~DCAN_RAM_INIT_BIT;
 182        priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl);
 183        c_can_hw_raminit_wait(priv, ctrl);
 184
 185        if (enable) {
 186                ctrl |= DCAN_RAM_INIT_BIT;
 187                priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl);
 188                c_can_hw_raminit_wait(priv, ctrl);
 189        }
 190}
 191
 192static const struct c_can_driver_data c_can_drvdata = {
 193        .id = BOSCH_C_CAN,
 194};
 195
 196static const struct c_can_driver_data d_can_drvdata = {
 197        .id = BOSCH_D_CAN,
 198};
 199
 200static const struct raminit_bits dra7_raminit_bits[] = {
 201        [0] = { .start = 3, .done = 1, },
 202        [1] = { .start = 5, .done = 2, },
 203};
 204
 205static const struct c_can_driver_data dra7_dcan_drvdata = {
 206        .id = BOSCH_D_CAN,
 207        .raminit_num = ARRAY_SIZE(dra7_raminit_bits),
 208        .raminit_bits = dra7_raminit_bits,
 209        .raminit_pulse = true,
 210};
 211
 212static const struct raminit_bits am3352_raminit_bits[] = {
 213        [0] = { .start = 0, .done = 8, },
 214        [1] = { .start = 1, .done = 9, },
 215};
 216
 217static const struct c_can_driver_data am3352_dcan_drvdata = {
 218        .id = BOSCH_D_CAN,
 219        .raminit_num = ARRAY_SIZE(am3352_raminit_bits),
 220        .raminit_bits = am3352_raminit_bits,
 221};
 222
 223static struct platform_device_id c_can_id_table[] = {
 224        {
 225                .name = KBUILD_MODNAME,
 226                .driver_data = (kernel_ulong_t)&c_can_drvdata,
 227        },
 228        {
 229                .name = "c_can",
 230                .driver_data = (kernel_ulong_t)&c_can_drvdata,
 231        },
 232        {
 233                .name = "d_can",
 234                .driver_data = (kernel_ulong_t)&d_can_drvdata,
 235        },
 236        { /* sentinel */ },
 237};
 238MODULE_DEVICE_TABLE(platform, c_can_id_table);
 239
 240static const struct of_device_id c_can_of_table[] = {
 241        { .compatible = "bosch,c_can", .data = &c_can_drvdata },
 242        { .compatible = "bosch,d_can", .data = &d_can_drvdata },
 243        { .compatible = "ti,dra7-d_can", .data = &dra7_dcan_drvdata },
 244        { .compatible = "ti,am3352-d_can", .data = &am3352_dcan_drvdata },
 245        { .compatible = "ti,am4372-d_can", .data = &am3352_dcan_drvdata },
 246        { /* sentinel */ },
 247};
 248MODULE_DEVICE_TABLE(of, c_can_of_table);
 249
 250static int c_can_plat_probe(struct platform_device *pdev)
 251{
 252        int ret;
 253        void __iomem *addr;
 254        struct net_device *dev;
 255        struct c_can_priv *priv;
 256        const struct of_device_id *match;
 257        struct resource *mem;
 258        int irq;
 259        struct clk *clk;
 260        const struct c_can_driver_data *drvdata;
 261        struct device_node *np = pdev->dev.of_node;
 262
 263        match = of_match_device(c_can_of_table, &pdev->dev);
 264        if (match) {
 265                drvdata = match->data;
 266        } else if (pdev->id_entry->driver_data) {
 267                drvdata = (struct c_can_driver_data *)
 268                        platform_get_device_id(pdev)->driver_data;
 269        } else {
 270                return -ENODEV;
 271        }
 272
 273        /* get the appropriate clk */
 274        clk = devm_clk_get(&pdev->dev, NULL);
 275        if (IS_ERR(clk)) {
 276                ret = PTR_ERR(clk);
 277                goto exit;
 278        }
 279
 280        /* get the platform data */
 281        irq = platform_get_irq(pdev, 0);
 282        if (irq <= 0) {
 283                ret = -ENODEV;
 284                goto exit;
 285        }
 286
 287        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 288        addr = devm_ioremap_resource(&pdev->dev, mem);
 289        if (IS_ERR(addr)) {
 290                ret =  PTR_ERR(addr);
 291                goto exit;
 292        }
 293
 294        /* allocate the c_can device */
 295        dev = alloc_c_can_dev();
 296        if (!dev) {
 297                ret = -ENOMEM;
 298                goto exit;
 299        }
 300
 301        priv = netdev_priv(dev);
 302        switch (drvdata->id) {
 303        case BOSCH_C_CAN:
 304                priv->regs = reg_map_c_can;
 305                switch (mem->flags & IORESOURCE_MEM_TYPE_MASK) {
 306                case IORESOURCE_MEM_32BIT:
 307                        priv->read_reg = c_can_plat_read_reg_aligned_to_32bit;
 308                        priv->write_reg = c_can_plat_write_reg_aligned_to_32bit;
 309                        priv->read_reg32 = c_can_plat_read_reg32;
 310                        priv->write_reg32 = c_can_plat_write_reg32;
 311                        break;
 312                case IORESOURCE_MEM_16BIT:
 313                default:
 314                        priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
 315                        priv->write_reg = c_can_plat_write_reg_aligned_to_16bit;
 316                        priv->read_reg32 = c_can_plat_read_reg32;
 317                        priv->write_reg32 = c_can_plat_write_reg32;
 318                        break;
 319                }
 320                break;
 321        case BOSCH_D_CAN:
 322                priv->regs = reg_map_d_can;
 323                priv->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES;
 324                priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
 325                priv->write_reg = c_can_plat_write_reg_aligned_to_16bit;
 326                priv->read_reg32 = d_can_plat_read_reg32;
 327                priv->write_reg32 = d_can_plat_write_reg32;
 328
 329                /* Check if we need custom RAMINIT via syscon. Mostly for TI
 330                 * platforms. Only supported with DT boot.
 331                 */
 332                if (np && of_property_read_bool(np, "syscon-raminit")) {
 333                        u32 id;
 334                        struct c_can_raminit *raminit = &priv->raminit_sys;
 335
 336                        ret = -EINVAL;
 337                        raminit->syscon = syscon_regmap_lookup_by_phandle(np,
 338                                                                          "syscon-raminit");
 339                        if (IS_ERR(raminit->syscon)) {
 340                                /* can fail with -EPROBE_DEFER */
 341                                ret = PTR_ERR(raminit->syscon);
 342                                free_c_can_dev(dev);
 343                                return ret;
 344                        }
 345
 346                        if (of_property_read_u32_index(np, "syscon-raminit", 1,
 347                                                       &raminit->reg)) {
 348                                dev_err(&pdev->dev,
 349                                        "couldn't get the RAMINIT reg. offset!\n");
 350                                goto exit_free_device;
 351                        }
 352
 353                        if (of_property_read_u32_index(np, "syscon-raminit", 2,
 354                                                       &id)) {
 355                                dev_err(&pdev->dev,
 356                                        "couldn't get the CAN instance ID\n");
 357                                goto exit_free_device;
 358                        }
 359
 360                        if (id >= drvdata->raminit_num) {
 361                                dev_err(&pdev->dev,
 362                                        "Invalid CAN instance ID\n");
 363                                goto exit_free_device;
 364                        }
 365
 366                        raminit->bits = drvdata->raminit_bits[id];
 367                        raminit->needs_pulse = drvdata->raminit_pulse;
 368
 369                        priv->raminit = c_can_hw_raminit_syscon;
 370                } else {
 371                        priv->raminit = c_can_hw_raminit;
 372                }
 373                break;
 374        default:
 375                ret = -EINVAL;
 376                goto exit_free_device;
 377        }
 378
 379        dev->irq = irq;
 380        priv->base = addr;
 381        priv->device = &pdev->dev;
 382        priv->can.clock.freq = clk_get_rate(clk);
 383        priv->priv = clk;
 384        priv->type = drvdata->id;
 385
 386        platform_set_drvdata(pdev, dev);
 387        SET_NETDEV_DEV(dev, &pdev->dev);
 388
 389        ret = register_c_can_dev(dev);
 390        if (ret) {
 391                dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
 392                        KBUILD_MODNAME, ret);
 393                goto exit_free_device;
 394        }
 395
 396        dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n",
 397                 KBUILD_MODNAME, priv->base, dev->irq);
 398        return 0;
 399
 400exit_free_device:
 401        free_c_can_dev(dev);
 402exit:
 403        dev_err(&pdev->dev, "probe failed\n");
 404
 405        return ret;
 406}
 407
 408static int c_can_plat_remove(struct platform_device *pdev)
 409{
 410        struct net_device *dev = platform_get_drvdata(pdev);
 411
 412        unregister_c_can_dev(dev);
 413
 414        free_c_can_dev(dev);
 415
 416        return 0;
 417}
 418
 419#ifdef CONFIG_PM
 420static int c_can_suspend(struct platform_device *pdev, pm_message_t state)
 421{
 422        int ret;
 423        struct net_device *ndev = platform_get_drvdata(pdev);
 424        struct c_can_priv *priv = netdev_priv(ndev);
 425
 426        if (priv->type != BOSCH_D_CAN) {
 427                dev_warn(&pdev->dev, "Not supported\n");
 428                return 0;
 429        }
 430
 431        if (netif_running(ndev)) {
 432                netif_stop_queue(ndev);
 433                netif_device_detach(ndev);
 434        }
 435
 436        ret = c_can_power_down(ndev);
 437        if (ret) {
 438                netdev_err(ndev, "failed to enter power down mode\n");
 439                return ret;
 440        }
 441
 442        priv->can.state = CAN_STATE_SLEEPING;
 443
 444        return 0;
 445}
 446
 447static int c_can_resume(struct platform_device *pdev)
 448{
 449        int ret;
 450        struct net_device *ndev = platform_get_drvdata(pdev);
 451        struct c_can_priv *priv = netdev_priv(ndev);
 452
 453        if (priv->type != BOSCH_D_CAN) {
 454                dev_warn(&pdev->dev, "Not supported\n");
 455                return 0;
 456        }
 457
 458        ret = c_can_power_up(ndev);
 459        if (ret) {
 460                netdev_err(ndev, "Still in power down mode\n");
 461                return ret;
 462        }
 463
 464        priv->can.state = CAN_STATE_ERROR_ACTIVE;
 465
 466        if (netif_running(ndev)) {
 467                netif_device_attach(ndev);
 468                netif_start_queue(ndev);
 469        }
 470
 471        return 0;
 472}
 473#else
 474#define c_can_suspend NULL
 475#define c_can_resume NULL
 476#endif
 477
 478static struct platform_driver c_can_plat_driver = {
 479        .driver = {
 480                .name = KBUILD_MODNAME,
 481                .of_match_table = c_can_of_table,
 482        },
 483        .probe = c_can_plat_probe,
 484        .remove = c_can_plat_remove,
 485        .suspend = c_can_suspend,
 486        .resume = c_can_resume,
 487        .id_table = c_can_id_table,
 488};
 489
 490module_platform_driver(c_can_plat_driver);
 491
 492MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
 493MODULE_LICENSE("GPL v2");
 494MODULE_DESCRIPTION("Platform CAN bus driver for Bosch C_CAN controller");
 495
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