linux/drivers/net/can/at91_can.c
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   1/*
   2 * at91_can.c - CAN network driver for AT91 SoC CAN controller
   3 *
   4 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
   5 * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de>
   6 *
   7 * This software may be distributed under the terms of the GNU General
   8 * Public License ("GPL") version 2 as distributed in the 'COPYING'
   9 * file from the main directory of the linux kernel source.
  10 *
  11 *
  12 * Your platform definition file should specify something like:
  13 *
  14 * static struct at91_can_data ek_can_data = {
  15 *      transceiver_switch = sam9263ek_transceiver_switch,
  16 * };
  17 *
  18 * at91_add_device_can(&ek_can_data);
  19 *
  20 */
  21
  22#include <linux/clk.h>
  23#include <linux/errno.h>
  24#include <linux/if_arp.h>
  25#include <linux/interrupt.h>
  26#include <linux/kernel.h>
  27#include <linux/module.h>
  28#include <linux/netdevice.h>
  29#include <linux/of.h>
  30#include <linux/platform_device.h>
  31#include <linux/rtnetlink.h>
  32#include <linux/skbuff.h>
  33#include <linux/spinlock.h>
  34#include <linux/string.h>
  35#include <linux/types.h>
  36#include <linux/platform_data/atmel.h>
  37
  38#include <linux/can/dev.h>
  39#include <linux/can/error.h>
  40#include <linux/can/led.h>
  41
  42#define AT91_MB_MASK(i)         ((1 << (i)) - 1)
  43
  44/* Common registers */
  45enum at91_reg {
  46        AT91_MR         = 0x000,
  47        AT91_IER        = 0x004,
  48        AT91_IDR        = 0x008,
  49        AT91_IMR        = 0x00C,
  50        AT91_SR         = 0x010,
  51        AT91_BR         = 0x014,
  52        AT91_TIM        = 0x018,
  53        AT91_TIMESTP    = 0x01C,
  54        AT91_ECR        = 0x020,
  55        AT91_TCR        = 0x024,
  56        AT91_ACR        = 0x028,
  57};
  58
  59/* Mailbox registers (0 <= i <= 15) */
  60#define AT91_MMR(i)             (enum at91_reg)(0x200 + ((i) * 0x20))
  61#define AT91_MAM(i)             (enum at91_reg)(0x204 + ((i) * 0x20))
  62#define AT91_MID(i)             (enum at91_reg)(0x208 + ((i) * 0x20))
  63#define AT91_MFID(i)            (enum at91_reg)(0x20C + ((i) * 0x20))
  64#define AT91_MSR(i)             (enum at91_reg)(0x210 + ((i) * 0x20))
  65#define AT91_MDL(i)             (enum at91_reg)(0x214 + ((i) * 0x20))
  66#define AT91_MDH(i)             (enum at91_reg)(0x218 + ((i) * 0x20))
  67#define AT91_MCR(i)             (enum at91_reg)(0x21C + ((i) * 0x20))
  68
  69/* Register bits */
  70#define AT91_MR_CANEN           BIT(0)
  71#define AT91_MR_LPM             BIT(1)
  72#define AT91_MR_ABM             BIT(2)
  73#define AT91_MR_OVL             BIT(3)
  74#define AT91_MR_TEOF            BIT(4)
  75#define AT91_MR_TTM             BIT(5)
  76#define AT91_MR_TIMFRZ          BIT(6)
  77#define AT91_MR_DRPT            BIT(7)
  78
  79#define AT91_SR_RBSY            BIT(29)
  80
  81#define AT91_MMR_PRIO_SHIFT     (16)
  82
  83#define AT91_MID_MIDE           BIT(29)
  84
  85#define AT91_MSR_MRTR           BIT(20)
  86#define AT91_MSR_MABT           BIT(22)
  87#define AT91_MSR_MRDY           BIT(23)
  88#define AT91_MSR_MMI            BIT(24)
  89
  90#define AT91_MCR_MRTR           BIT(20)
  91#define AT91_MCR_MTCR           BIT(23)
  92
  93/* Mailbox Modes */
  94enum at91_mb_mode {
  95        AT91_MB_MODE_DISABLED   = 0,
  96        AT91_MB_MODE_RX         = 1,
  97        AT91_MB_MODE_RX_OVRWR   = 2,
  98        AT91_MB_MODE_TX         = 3,
  99        AT91_MB_MODE_CONSUMER   = 4,
 100        AT91_MB_MODE_PRODUCER   = 5,
 101};
 102
 103/* Interrupt mask bits */
 104#define AT91_IRQ_ERRA           (1 << 16)
 105#define AT91_IRQ_WARN           (1 << 17)
 106#define AT91_IRQ_ERRP           (1 << 18)
 107#define AT91_IRQ_BOFF           (1 << 19)
 108#define AT91_IRQ_SLEEP          (1 << 20)
 109#define AT91_IRQ_WAKEUP         (1 << 21)
 110#define AT91_IRQ_TOVF           (1 << 22)
 111#define AT91_IRQ_TSTP           (1 << 23)
 112#define AT91_IRQ_CERR           (1 << 24)
 113#define AT91_IRQ_SERR           (1 << 25)
 114#define AT91_IRQ_AERR           (1 << 26)
 115#define AT91_IRQ_FERR           (1 << 27)
 116#define AT91_IRQ_BERR           (1 << 28)
 117
 118#define AT91_IRQ_ERR_ALL        (0x1fff0000)
 119#define AT91_IRQ_ERR_FRAME      (AT91_IRQ_CERR | AT91_IRQ_SERR | \
 120                                 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR)
 121#define AT91_IRQ_ERR_LINE       (AT91_IRQ_ERRA | AT91_IRQ_WARN | \
 122                                 AT91_IRQ_ERRP | AT91_IRQ_BOFF)
 123
 124#define AT91_IRQ_ALL            (0x1fffffff)
 125
 126enum at91_devtype {
 127        AT91_DEVTYPE_SAM9263,
 128        AT91_DEVTYPE_SAM9X5,
 129};
 130
 131struct at91_devtype_data {
 132        unsigned int rx_first;
 133        unsigned int rx_split;
 134        unsigned int rx_last;
 135        unsigned int tx_shift;
 136        enum at91_devtype type;
 137};
 138
 139struct at91_priv {
 140        struct can_priv can;            /* must be the first member! */
 141        struct net_device *dev;
 142        struct napi_struct napi;
 143
 144        void __iomem *reg_base;
 145
 146        u32 reg_sr;
 147        unsigned int tx_next;
 148        unsigned int tx_echo;
 149        unsigned int rx_next;
 150        struct at91_devtype_data devtype_data;
 151
 152        struct clk *clk;
 153        struct at91_can_data *pdata;
 154
 155        canid_t mb0_id;
 156};
 157
 158static const struct at91_devtype_data at91_at91sam9263_data = {
 159        .rx_first = 1,
 160        .rx_split = 8,
 161        .rx_last = 11,
 162        .tx_shift = 2,
 163        .type = AT91_DEVTYPE_SAM9263,
 164};
 165
 166static const struct at91_devtype_data at91_at91sam9x5_data = {
 167        .rx_first = 0,
 168        .rx_split = 4,
 169        .rx_last = 5,
 170        .tx_shift = 1,
 171        .type = AT91_DEVTYPE_SAM9X5,
 172};
 173
 174static const struct can_bittiming_const at91_bittiming_const = {
 175        .name           = KBUILD_MODNAME,
 176        .tseg1_min      = 4,
 177        .tseg1_max      = 16,
 178        .tseg2_min      = 2,
 179        .tseg2_max      = 8,
 180        .sjw_max        = 4,
 181        .brp_min        = 2,
 182        .brp_max        = 128,
 183        .brp_inc        = 1,
 184};
 185
 186#define AT91_IS(_model) \
 187static inline int at91_is_sam##_model(const struct at91_priv *priv) \
 188{ \
 189        return priv->devtype_data.type == AT91_DEVTYPE_SAM##_model; \
 190}
 191
 192AT91_IS(9263);
 193AT91_IS(9X5);
 194
 195static inline unsigned int get_mb_rx_first(const struct at91_priv *priv)
 196{
 197        return priv->devtype_data.rx_first;
 198}
 199
 200static inline unsigned int get_mb_rx_last(const struct at91_priv *priv)
 201{
 202        return priv->devtype_data.rx_last;
 203}
 204
 205static inline unsigned int get_mb_rx_split(const struct at91_priv *priv)
 206{
 207        return priv->devtype_data.rx_split;
 208}
 209
 210static inline unsigned int get_mb_rx_num(const struct at91_priv *priv)
 211{
 212        return get_mb_rx_last(priv) - get_mb_rx_first(priv) + 1;
 213}
 214
 215static inline unsigned int get_mb_rx_low_last(const struct at91_priv *priv)
 216{
 217        return get_mb_rx_split(priv) - 1;
 218}
 219
 220static inline unsigned int get_mb_rx_low_mask(const struct at91_priv *priv)
 221{
 222        return AT91_MB_MASK(get_mb_rx_split(priv)) &
 223                ~AT91_MB_MASK(get_mb_rx_first(priv));
 224}
 225
 226static inline unsigned int get_mb_tx_shift(const struct at91_priv *priv)
 227{
 228        return priv->devtype_data.tx_shift;
 229}
 230
 231static inline unsigned int get_mb_tx_num(const struct at91_priv *priv)
 232{
 233        return 1 << get_mb_tx_shift(priv);
 234}
 235
 236static inline unsigned int get_mb_tx_first(const struct at91_priv *priv)
 237{
 238        return get_mb_rx_last(priv) + 1;
 239}
 240
 241static inline unsigned int get_mb_tx_last(const struct at91_priv *priv)
 242{
 243        return get_mb_tx_first(priv) + get_mb_tx_num(priv) - 1;
 244}
 245
 246static inline unsigned int get_next_prio_shift(const struct at91_priv *priv)
 247{
 248        return get_mb_tx_shift(priv);
 249}
 250
 251static inline unsigned int get_next_prio_mask(const struct at91_priv *priv)
 252{
 253        return 0xf << get_mb_tx_shift(priv);
 254}
 255
 256static inline unsigned int get_next_mb_mask(const struct at91_priv *priv)
 257{
 258        return AT91_MB_MASK(get_mb_tx_shift(priv));
 259}
 260
 261static inline unsigned int get_next_mask(const struct at91_priv *priv)
 262{
 263        return get_next_mb_mask(priv) | get_next_prio_mask(priv);
 264}
 265
 266static inline unsigned int get_irq_mb_rx(const struct at91_priv *priv)
 267{
 268        return AT91_MB_MASK(get_mb_rx_last(priv) + 1) &
 269                ~AT91_MB_MASK(get_mb_rx_first(priv));
 270}
 271
 272static inline unsigned int get_irq_mb_tx(const struct at91_priv *priv)
 273{
 274        return AT91_MB_MASK(get_mb_tx_last(priv) + 1) &
 275                ~AT91_MB_MASK(get_mb_tx_first(priv));
 276}
 277
 278static inline unsigned int get_tx_next_mb(const struct at91_priv *priv)
 279{
 280        return (priv->tx_next & get_next_mb_mask(priv)) + get_mb_tx_first(priv);
 281}
 282
 283static inline unsigned int get_tx_next_prio(const struct at91_priv *priv)
 284{
 285        return (priv->tx_next >> get_next_prio_shift(priv)) & 0xf;
 286}
 287
 288static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv)
 289{
 290        return (priv->tx_echo & get_next_mb_mask(priv)) + get_mb_tx_first(priv);
 291}
 292
 293static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg)
 294{
 295        return __raw_readl(priv->reg_base + reg);
 296}
 297
 298static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg,
 299                u32 value)
 300{
 301        __raw_writel(value, priv->reg_base + reg);
 302}
 303
 304static inline void set_mb_mode_prio(const struct at91_priv *priv,
 305                unsigned int mb, enum at91_mb_mode mode, int prio)
 306{
 307        at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16));
 308}
 309
 310static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb,
 311                enum at91_mb_mode mode)
 312{
 313        set_mb_mode_prio(priv, mb, mode, 0);
 314}
 315
 316static inline u32 at91_can_id_to_reg_mid(canid_t can_id)
 317{
 318        u32 reg_mid;
 319
 320        if (can_id & CAN_EFF_FLAG)
 321                reg_mid = (can_id & CAN_EFF_MASK) | AT91_MID_MIDE;
 322        else
 323                reg_mid = (can_id & CAN_SFF_MASK) << 18;
 324
 325        return reg_mid;
 326}
 327
 328/*
 329 * Swtich transceiver on or off
 330 */
 331static void at91_transceiver_switch(const struct at91_priv *priv, int on)
 332{
 333        if (priv->pdata && priv->pdata->transceiver_switch)
 334                priv->pdata->transceiver_switch(on);
 335}
 336
 337static void at91_setup_mailboxes(struct net_device *dev)
 338{
 339        struct at91_priv *priv = netdev_priv(dev);
 340        unsigned int i;
 341        u32 reg_mid;
 342
 343        /*
 344         * Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first
 345         * mailbox is disabled. The next 11 mailboxes are used as a
 346         * reception FIFO. The last mailbox is configured with
 347         * overwrite option. The overwrite flag indicates a FIFO
 348         * overflow.
 349         */
 350        reg_mid = at91_can_id_to_reg_mid(priv->mb0_id);
 351        for (i = 0; i < get_mb_rx_first(priv); i++) {
 352                set_mb_mode(priv, i, AT91_MB_MODE_DISABLED);
 353                at91_write(priv, AT91_MID(i), reg_mid);
 354                at91_write(priv, AT91_MCR(i), 0x0);     /* clear dlc */
 355        }
 356
 357        for (i = get_mb_rx_first(priv); i < get_mb_rx_last(priv); i++)
 358                set_mb_mode(priv, i, AT91_MB_MODE_RX);
 359        set_mb_mode(priv, get_mb_rx_last(priv), AT91_MB_MODE_RX_OVRWR);
 360
 361        /* reset acceptance mask and id register */
 362        for (i = get_mb_rx_first(priv); i <= get_mb_rx_last(priv); i++) {
 363                at91_write(priv, AT91_MAM(i), 0x0);
 364                at91_write(priv, AT91_MID(i), AT91_MID_MIDE);
 365        }
 366
 367        /* The last 4 mailboxes are used for transmitting. */
 368        for (i = get_mb_tx_first(priv); i <= get_mb_tx_last(priv); i++)
 369                set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0);
 370
 371        /* Reset tx and rx helper pointers */
 372        priv->tx_next = priv->tx_echo = 0;
 373        priv->rx_next = get_mb_rx_first(priv);
 374}
 375
 376static int at91_set_bittiming(struct net_device *dev)
 377{
 378        const struct at91_priv *priv = netdev_priv(dev);
 379        const struct can_bittiming *bt = &priv->can.bittiming;
 380        u32 reg_br;
 381
 382        reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) |
 383                ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) |
 384                ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) |
 385                ((bt->phase_seg2 - 1) << 0);
 386
 387        netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br);
 388
 389        at91_write(priv, AT91_BR, reg_br);
 390
 391        return 0;
 392}
 393
 394static int at91_get_berr_counter(const struct net_device *dev,
 395                struct can_berr_counter *bec)
 396{
 397        const struct at91_priv *priv = netdev_priv(dev);
 398        u32 reg_ecr = at91_read(priv, AT91_ECR);
 399
 400        bec->rxerr = reg_ecr & 0xff;
 401        bec->txerr = reg_ecr >> 16;
 402
 403        return 0;
 404}
 405
 406static void at91_chip_start(struct net_device *dev)
 407{
 408        struct at91_priv *priv = netdev_priv(dev);
 409        u32 reg_mr, reg_ier;
 410
 411        /* disable interrupts */
 412        at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
 413
 414        /* disable chip */
 415        reg_mr = at91_read(priv, AT91_MR);
 416        at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
 417
 418        at91_set_bittiming(dev);
 419        at91_setup_mailboxes(dev);
 420        at91_transceiver_switch(priv, 1);
 421
 422        /* enable chip */
 423        if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
 424                reg_mr = AT91_MR_CANEN | AT91_MR_ABM;
 425        else
 426                reg_mr = AT91_MR_CANEN;
 427        at91_write(priv, AT91_MR, reg_mr);
 428
 429        priv->can.state = CAN_STATE_ERROR_ACTIVE;
 430
 431        /* Enable interrupts */
 432        reg_ier = get_irq_mb_rx(priv) | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME;
 433        at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
 434        at91_write(priv, AT91_IER, reg_ier);
 435}
 436
 437static void at91_chip_stop(struct net_device *dev, enum can_state state)
 438{
 439        struct at91_priv *priv = netdev_priv(dev);
 440        u32 reg_mr;
 441
 442        /* disable interrupts */
 443        at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
 444
 445        reg_mr = at91_read(priv, AT91_MR);
 446        at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
 447
 448        at91_transceiver_switch(priv, 0);
 449        priv->can.state = state;
 450}
 451
 452/*
 453 * theory of operation:
 454 *
 455 * According to the datasheet priority 0 is the highest priority, 15
 456 * is the lowest. If two mailboxes have the same priority level the
 457 * message of the mailbox with the lowest number is sent first.
 458 *
 459 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then
 460 * the next mailbox with prio 0, and so on, until all mailboxes are
 461 * used. Then we start from the beginning with mailbox
 462 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1
 463 * prio 1. When we reach the last mailbox with prio 15, we have to
 464 * stop sending, waiting for all messages to be delivered, then start
 465 * again with mailbox AT91_MB_TX_FIRST prio 0.
 466 *
 467 * We use the priv->tx_next as counter for the next transmission
 468 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits
 469 * encode the mailbox number, the upper 4 bits the mailbox priority:
 470 *
 471 * priv->tx_next = (prio << get_next_prio_shift(priv)) |
 472 *                 (mb - get_mb_tx_first(priv));
 473 *
 474 */
 475static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev)
 476{
 477        struct at91_priv *priv = netdev_priv(dev);
 478        struct net_device_stats *stats = &dev->stats;
 479        struct can_frame *cf = (struct can_frame *)skb->data;
 480        unsigned int mb, prio;
 481        u32 reg_mid, reg_mcr;
 482
 483        if (can_dropped_invalid_skb(dev, skb))
 484                return NETDEV_TX_OK;
 485
 486        mb = get_tx_next_mb(priv);
 487        prio = get_tx_next_prio(priv);
 488
 489        if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) {
 490                netif_stop_queue(dev);
 491
 492                netdev_err(dev, "BUG! TX buffer full when queue awake!\n");
 493                return NETDEV_TX_BUSY;
 494        }
 495        reg_mid = at91_can_id_to_reg_mid(cf->can_id);
 496        reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) |
 497                (cf->can_dlc << 16) | AT91_MCR_MTCR;
 498
 499        /* disable MB while writing ID (see datasheet) */
 500        set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED);
 501        at91_write(priv, AT91_MID(mb), reg_mid);
 502        set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio);
 503
 504        at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0));
 505        at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4));
 506
 507        /* This triggers transmission */
 508        at91_write(priv, AT91_MCR(mb), reg_mcr);
 509
 510        stats->tx_bytes += cf->can_dlc;
 511
 512        /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
 513        can_put_echo_skb(skb, dev, mb - get_mb_tx_first(priv));
 514
 515        /*
 516         * we have to stop the queue and deliver all messages in case
 517         * of a prio+mb counter wrap around. This is the case if
 518         * tx_next buffer prio and mailbox equals 0.
 519         *
 520         * also stop the queue if next buffer is still in use
 521         * (== not ready)
 522         */
 523        priv->tx_next++;
 524        if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) &
 525              AT91_MSR_MRDY) ||
 526            (priv->tx_next & get_next_mask(priv)) == 0)
 527                netif_stop_queue(dev);
 528
 529        /* Enable interrupt for this mailbox */
 530        at91_write(priv, AT91_IER, 1 << mb);
 531
 532        return NETDEV_TX_OK;
 533}
 534
 535/**
 536 * at91_activate_rx_low - activate lower rx mailboxes
 537 * @priv: a91 context
 538 *
 539 * Reenables the lower mailboxes for reception of new CAN messages
 540 */
 541static inline void at91_activate_rx_low(const struct at91_priv *priv)
 542{
 543        u32 mask = get_mb_rx_low_mask(priv);
 544        at91_write(priv, AT91_TCR, mask);
 545}
 546
 547/**
 548 * at91_activate_rx_mb - reactive single rx mailbox
 549 * @priv: a91 context
 550 * @mb: mailbox to reactivate
 551 *
 552 * Reenables given mailbox for reception of new CAN messages
 553 */
 554static inline void at91_activate_rx_mb(const struct at91_priv *priv,
 555                unsigned int mb)
 556{
 557        u32 mask = 1 << mb;
 558        at91_write(priv, AT91_TCR, mask);
 559}
 560
 561/**
 562 * at91_rx_overflow_err - send error frame due to rx overflow
 563 * @dev: net device
 564 */
 565static void at91_rx_overflow_err(struct net_device *dev)
 566{
 567        struct net_device_stats *stats = &dev->stats;
 568        struct sk_buff *skb;
 569        struct can_frame *cf;
 570
 571        netdev_dbg(dev, "RX buffer overflow\n");
 572        stats->rx_over_errors++;
 573        stats->rx_errors++;
 574
 575        skb = alloc_can_err_skb(dev, &cf);
 576        if (unlikely(!skb))
 577                return;
 578
 579        cf->can_id |= CAN_ERR_CRTL;
 580        cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
 581        netif_receive_skb(skb);
 582
 583        stats->rx_packets++;
 584        stats->rx_bytes += cf->can_dlc;
 585}
 586
 587/**
 588 * at91_read_mb - read CAN msg from mailbox (lowlevel impl)
 589 * @dev: net device
 590 * @mb: mailbox number to read from
 591 * @cf: can frame where to store message
 592 *
 593 * Reads a CAN message from the given mailbox and stores data into
 594 * given can frame. "mb" and "cf" must be valid.
 595 */
 596static void at91_read_mb(struct net_device *dev, unsigned int mb,
 597                struct can_frame *cf)
 598{
 599        const struct at91_priv *priv = netdev_priv(dev);
 600        u32 reg_msr, reg_mid;
 601
 602        reg_mid = at91_read(priv, AT91_MID(mb));
 603        if (reg_mid & AT91_MID_MIDE)
 604                cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
 605        else
 606                cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK;
 607
 608        reg_msr = at91_read(priv, AT91_MSR(mb));
 609        cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf);
 610
 611        if (reg_msr & AT91_MSR_MRTR)
 612                cf->can_id |= CAN_RTR_FLAG;
 613        else {
 614                *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb));
 615                *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb));
 616        }
 617
 618        /* allow RX of extended frames */
 619        at91_write(priv, AT91_MID(mb), AT91_MID_MIDE);
 620
 621        if (unlikely(mb == get_mb_rx_last(priv) && reg_msr & AT91_MSR_MMI))
 622                at91_rx_overflow_err(dev);
 623}
 624
 625/**
 626 * at91_read_msg - read CAN message from mailbox
 627 * @dev: net device
 628 * @mb: mail box to read from
 629 *
 630 * Reads a CAN message from given mailbox, and put into linux network
 631 * RX queue, does all housekeeping chores (stats, ...)
 632 */
 633static void at91_read_msg(struct net_device *dev, unsigned int mb)
 634{
 635        struct net_device_stats *stats = &dev->stats;
 636        struct can_frame *cf;
 637        struct sk_buff *skb;
 638
 639        skb = alloc_can_skb(dev, &cf);
 640        if (unlikely(!skb)) {
 641                stats->rx_dropped++;
 642                return;
 643        }
 644
 645        at91_read_mb(dev, mb, cf);
 646        netif_receive_skb(skb);
 647
 648        stats->rx_packets++;
 649        stats->rx_bytes += cf->can_dlc;
 650
 651        can_led_event(dev, CAN_LED_EVENT_RX);
 652}
 653
 654/**
 655 * at91_poll_rx - read multiple CAN messages from mailboxes
 656 * @dev: net device
 657 * @quota: max number of pkgs we're allowed to receive
 658 *
 659 * Theory of Operation:
 660 *
 661 * About 3/4 of the mailboxes (get_mb_rx_first()...get_mb_rx_last())
 662 * on the chip are reserved for RX. We split them into 2 groups. The
 663 * lower group ranges from get_mb_rx_first() to get_mb_rx_low_last().
 664 *
 665 * Like it or not, but the chip always saves a received CAN message
 666 * into the first free mailbox it finds (starting with the
 667 * lowest). This makes it very difficult to read the messages in the
 668 * right order from the chip. This is how we work around that problem:
 669 *
 670 * The first message goes into mb nr. 1 and issues an interrupt. All
 671 * rx ints are disabled in the interrupt handler and a napi poll is
 672 * scheduled. We read the mailbox, but do _not_ reenable the mb (to
 673 * receive another message).
 674 *
 675 *    lower mbxs      upper
 676 *     ____^______    __^__
 677 *    /           \  /     \
 678 * +-+-+-+-+-+-+-+-++-+-+-+-+
 679 * | |x|x|x|x|x|x|x|| | | | |
 680 * +-+-+-+-+-+-+-+-++-+-+-+-+
 681 *  0 0 0 0 0 0  0 0 0 0 1 1  \ mail
 682 *  0 1 2 3 4 5  6 7 8 9 0 1  / box
 683 *  ^
 684 *  |
 685 *   \
 686 *     unused, due to chip bug
 687 *
 688 * The variable priv->rx_next points to the next mailbox to read a
 689 * message from. As long we're in the lower mailboxes we just read the
 690 * mailbox but not reenable it.
 691 *
 692 * With completion of the last of the lower mailboxes, we reenable the
 693 * whole first group, but continue to look for filled mailboxes in the
 694 * upper mailboxes. Imagine the second group like overflow mailboxes,
 695 * which takes CAN messages if the lower goup is full. While in the
 696 * upper group we reenable the mailbox right after reading it. Giving
 697 * the chip more room to store messages.
 698 *
 699 * After finishing we look again in the lower group if we've still
 700 * quota.
 701 *
 702 */
 703static int at91_poll_rx(struct net_device *dev, int quota)
 704{
 705        struct at91_priv *priv = netdev_priv(dev);
 706        u32 reg_sr = at91_read(priv, AT91_SR);
 707        const unsigned long *addr = (unsigned long *)&reg_sr;
 708        unsigned int mb;
 709        int received = 0;
 710
 711        if (priv->rx_next > get_mb_rx_low_last(priv) &&
 712            reg_sr & get_mb_rx_low_mask(priv))
 713                netdev_info(dev,
 714                        "order of incoming frames cannot be guaranteed\n");
 715
 716 again:
 717        for (mb = find_next_bit(addr, get_mb_tx_first(priv), priv->rx_next);
 718             mb < get_mb_tx_first(priv) && quota > 0;
 719             reg_sr = at91_read(priv, AT91_SR),
 720             mb = find_next_bit(addr, get_mb_tx_first(priv), ++priv->rx_next)) {
 721                at91_read_msg(dev, mb);
 722
 723                /* reactivate mailboxes */
 724                if (mb == get_mb_rx_low_last(priv))
 725                        /* all lower mailboxed, if just finished it */
 726                        at91_activate_rx_low(priv);
 727                else if (mb > get_mb_rx_low_last(priv))
 728                        /* only the mailbox we read */
 729                        at91_activate_rx_mb(priv, mb);
 730
 731                received++;
 732                quota--;
 733        }
 734
 735        /* upper group completed, look again in lower */
 736        if (priv->rx_next > get_mb_rx_low_last(priv) &&
 737            quota > 0 && mb > get_mb_rx_last(priv)) {
 738                priv->rx_next = get_mb_rx_first(priv);
 739                goto again;
 740        }
 741
 742        return received;
 743}
 744
 745static void at91_poll_err_frame(struct net_device *dev,
 746                struct can_frame *cf, u32 reg_sr)
 747{
 748        struct at91_priv *priv = netdev_priv(dev);
 749
 750        /* CRC error */
 751        if (reg_sr & AT91_IRQ_CERR) {
 752                netdev_dbg(dev, "CERR irq\n");
 753                dev->stats.rx_errors++;
 754                priv->can.can_stats.bus_error++;
 755                cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 756        }
 757
 758        /* Stuffing Error */
 759        if (reg_sr & AT91_IRQ_SERR) {
 760                netdev_dbg(dev, "SERR irq\n");
 761                dev->stats.rx_errors++;
 762                priv->can.can_stats.bus_error++;
 763                cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 764                cf->data[2] |= CAN_ERR_PROT_STUFF;
 765        }
 766
 767        /* Acknowledgement Error */
 768        if (reg_sr & AT91_IRQ_AERR) {
 769                netdev_dbg(dev, "AERR irq\n");
 770                dev->stats.tx_errors++;
 771                cf->can_id |= CAN_ERR_ACK;
 772        }
 773
 774        /* Form error */
 775        if (reg_sr & AT91_IRQ_FERR) {
 776                netdev_dbg(dev, "FERR irq\n");
 777                dev->stats.rx_errors++;
 778                priv->can.can_stats.bus_error++;
 779                cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 780                cf->data[2] |= CAN_ERR_PROT_FORM;
 781        }
 782
 783        /* Bit Error */
 784        if (reg_sr & AT91_IRQ_BERR) {
 785                netdev_dbg(dev, "BERR irq\n");
 786                dev->stats.tx_errors++;
 787                priv->can.can_stats.bus_error++;
 788                cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 789                cf->data[2] |= CAN_ERR_PROT_BIT;
 790        }
 791}
 792
 793static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr)
 794{
 795        struct sk_buff *skb;
 796        struct can_frame *cf;
 797
 798        if (quota == 0)
 799                return 0;
 800
 801        skb = alloc_can_err_skb(dev, &cf);
 802        if (unlikely(!skb))
 803                return 0;
 804
 805        at91_poll_err_frame(dev, cf, reg_sr);
 806        netif_receive_skb(skb);
 807
 808        dev->stats.rx_packets++;
 809        dev->stats.rx_bytes += cf->can_dlc;
 810
 811        return 1;
 812}
 813
 814static int at91_poll(struct napi_struct *napi, int quota)
 815{
 816        struct net_device *dev = napi->dev;
 817        const struct at91_priv *priv = netdev_priv(dev);
 818        u32 reg_sr = at91_read(priv, AT91_SR);
 819        int work_done = 0;
 820
 821        if (reg_sr & get_irq_mb_rx(priv))
 822                work_done += at91_poll_rx(dev, quota - work_done);
 823
 824        /*
 825         * The error bits are clear on read,
 826         * so use saved value from irq handler.
 827         */
 828        reg_sr |= priv->reg_sr;
 829        if (reg_sr & AT91_IRQ_ERR_FRAME)
 830                work_done += at91_poll_err(dev, quota - work_done, reg_sr);
 831
 832        if (work_done < quota) {
 833                /* enable IRQs for frame errors and all mailboxes >= rx_next */
 834                u32 reg_ier = AT91_IRQ_ERR_FRAME;
 835                reg_ier |= get_irq_mb_rx(priv) & ~AT91_MB_MASK(priv->rx_next);
 836
 837                napi_complete(napi);
 838                at91_write(priv, AT91_IER, reg_ier);
 839        }
 840
 841        return work_done;
 842}
 843
 844/*
 845 * theory of operation:
 846 *
 847 * priv->tx_echo holds the number of the oldest can_frame put for
 848 * transmission into the hardware, but not yet ACKed by the CAN tx
 849 * complete IRQ.
 850 *
 851 * We iterate from priv->tx_echo to priv->tx_next and check if the
 852 * packet has been transmitted, echo it back to the CAN framework. If
 853 * we discover a not yet transmitted package, stop looking for more.
 854 *
 855 */
 856static void at91_irq_tx(struct net_device *dev, u32 reg_sr)
 857{
 858        struct at91_priv *priv = netdev_priv(dev);
 859        u32 reg_msr;
 860        unsigned int mb;
 861
 862        /* masking of reg_sr not needed, already done by at91_irq */
 863
 864        for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
 865                mb = get_tx_echo_mb(priv);
 866
 867                /* no event in mailbox? */
 868                if (!(reg_sr & (1 << mb)))
 869                        break;
 870
 871                /* Disable irq for this TX mailbox */
 872                at91_write(priv, AT91_IDR, 1 << mb);
 873
 874                /*
 875                 * only echo if mailbox signals us a transfer
 876                 * complete (MSR_MRDY). Otherwise it's a tansfer
 877                 * abort. "can_bus_off()" takes care about the skbs
 878                 * parked in the echo queue.
 879                 */
 880                reg_msr = at91_read(priv, AT91_MSR(mb));
 881                if (likely(reg_msr & AT91_MSR_MRDY &&
 882                           ~reg_msr & AT91_MSR_MABT)) {
 883                        /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
 884                        can_get_echo_skb(dev, mb - get_mb_tx_first(priv));
 885                        dev->stats.tx_packets++;
 886                        can_led_event(dev, CAN_LED_EVENT_TX);
 887                }
 888        }
 889
 890        /*
 891         * restart queue if we don't have a wrap around but restart if
 892         * we get a TX int for the last can frame directly before a
 893         * wrap around.
 894         */
 895        if ((priv->tx_next & get_next_mask(priv)) != 0 ||
 896            (priv->tx_echo & get_next_mask(priv)) == 0)
 897                netif_wake_queue(dev);
 898}
 899
 900static void at91_irq_err_state(struct net_device *dev,
 901                struct can_frame *cf, enum can_state new_state)
 902{
 903        struct at91_priv *priv = netdev_priv(dev);
 904        u32 reg_idr = 0, reg_ier = 0;
 905        struct can_berr_counter bec;
 906
 907        at91_get_berr_counter(dev, &bec);
 908
 909        switch (priv->can.state) {
 910        case CAN_STATE_ERROR_ACTIVE:
 911                /*
 912                 * from: ERROR_ACTIVE
 913                 * to  : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
 914                 * =>  : there was a warning int
 915                 */
 916                if (new_state >= CAN_STATE_ERROR_WARNING &&
 917                    new_state <= CAN_STATE_BUS_OFF) {
 918                        netdev_dbg(dev, "Error Warning IRQ\n");
 919                        priv->can.can_stats.error_warning++;
 920
 921                        cf->can_id |= CAN_ERR_CRTL;
 922                        cf->data[1] = (bec.txerr > bec.rxerr) ?
 923                                CAN_ERR_CRTL_TX_WARNING :
 924                                CAN_ERR_CRTL_RX_WARNING;
 925                }
 926        case CAN_STATE_ERROR_WARNING:   /* fallthrough */
 927                /*
 928                 * from: ERROR_ACTIVE, ERROR_WARNING
 929                 * to  : ERROR_PASSIVE, BUS_OFF
 930                 * =>  : error passive int
 931                 */
 932                if (new_state >= CAN_STATE_ERROR_PASSIVE &&
 933                    new_state <= CAN_STATE_BUS_OFF) {
 934                        netdev_dbg(dev, "Error Passive IRQ\n");
 935                        priv->can.can_stats.error_passive++;
 936
 937                        cf->can_id |= CAN_ERR_CRTL;
 938                        cf->data[1] = (bec.txerr > bec.rxerr) ?
 939                                CAN_ERR_CRTL_TX_PASSIVE :
 940                                CAN_ERR_CRTL_RX_PASSIVE;
 941                }
 942                break;
 943        case CAN_STATE_BUS_OFF:
 944                /*
 945                 * from: BUS_OFF
 946                 * to  : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE
 947                 */
 948                if (new_state <= CAN_STATE_ERROR_PASSIVE) {
 949                        cf->can_id |= CAN_ERR_RESTARTED;
 950
 951                        netdev_dbg(dev, "restarted\n");
 952                        priv->can.can_stats.restarts++;
 953
 954                        netif_carrier_on(dev);
 955                        netif_wake_queue(dev);
 956                }
 957                break;
 958        default:
 959                break;
 960        }
 961
 962
 963        /* process state changes depending on the new state */
 964        switch (new_state) {
 965        case CAN_STATE_ERROR_ACTIVE:
 966                /*
 967                 * actually we want to enable AT91_IRQ_WARN here, but
 968                 * it screws up the system under certain
 969                 * circumstances. so just enable AT91_IRQ_ERRP, thus
 970                 * the "fallthrough"
 971                 */
 972                netdev_dbg(dev, "Error Active\n");
 973                cf->can_id |= CAN_ERR_PROT;
 974                cf->data[2] = CAN_ERR_PROT_ACTIVE;
 975        case CAN_STATE_ERROR_WARNING:   /* fallthrough */
 976                reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF;
 977                reg_ier = AT91_IRQ_ERRP;
 978                break;
 979        case CAN_STATE_ERROR_PASSIVE:
 980                reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP;
 981                reg_ier = AT91_IRQ_BOFF;
 982                break;
 983        case CAN_STATE_BUS_OFF:
 984                reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP |
 985                        AT91_IRQ_WARN | AT91_IRQ_BOFF;
 986                reg_ier = 0;
 987
 988                cf->can_id |= CAN_ERR_BUSOFF;
 989
 990                netdev_dbg(dev, "bus-off\n");
 991                netif_carrier_off(dev);
 992                priv->can.can_stats.bus_off++;
 993
 994                /* turn off chip, if restart is disabled */
 995                if (!priv->can.restart_ms) {
 996                        at91_chip_stop(dev, CAN_STATE_BUS_OFF);
 997                        return;
 998                }
 999                break;
1000        default:
1001                break;
1002        }
1003
1004        at91_write(priv, AT91_IDR, reg_idr);
1005        at91_write(priv, AT91_IER, reg_ier);
1006}
1007
1008static int at91_get_state_by_bec(const struct net_device *dev,
1009                enum can_state *state)
1010{
1011        struct can_berr_counter bec;
1012        int err;
1013
1014        err = at91_get_berr_counter(dev, &bec);
1015        if (err)
1016                return err;
1017
1018        if (bec.txerr < 96 && bec.rxerr < 96)
1019                *state = CAN_STATE_ERROR_ACTIVE;
1020        else if (bec.txerr < 128 && bec.rxerr < 128)
1021                *state = CAN_STATE_ERROR_WARNING;
1022        else if (bec.txerr < 256 && bec.rxerr < 256)
1023                *state = CAN_STATE_ERROR_PASSIVE;
1024        else
1025                *state = CAN_STATE_BUS_OFF;
1026
1027        return 0;
1028}
1029
1030
1031static void at91_irq_err(struct net_device *dev)
1032{
1033        struct at91_priv *priv = netdev_priv(dev);
1034        struct sk_buff *skb;
1035        struct can_frame *cf;
1036        enum can_state new_state;
1037        u32 reg_sr;
1038        int err;
1039
1040        if (at91_is_sam9263(priv)) {
1041                reg_sr = at91_read(priv, AT91_SR);
1042
1043                /* we need to look at the unmasked reg_sr */
1044                if (unlikely(reg_sr & AT91_IRQ_BOFF))
1045                        new_state = CAN_STATE_BUS_OFF;
1046                else if (unlikely(reg_sr & AT91_IRQ_ERRP))
1047                        new_state = CAN_STATE_ERROR_PASSIVE;
1048                else if (unlikely(reg_sr & AT91_IRQ_WARN))
1049                        new_state = CAN_STATE_ERROR_WARNING;
1050                else if (likely(reg_sr & AT91_IRQ_ERRA))
1051                        new_state = CAN_STATE_ERROR_ACTIVE;
1052                else {
1053                        netdev_err(dev, "BUG! hardware in undefined state\n");
1054                        return;
1055                }
1056        } else {
1057                err = at91_get_state_by_bec(dev, &new_state);
1058                if (err)
1059                        return;
1060        }
1061
1062        /* state hasn't changed */
1063        if (likely(new_state == priv->can.state))
1064                return;
1065
1066        skb = alloc_can_err_skb(dev, &cf);
1067        if (unlikely(!skb))
1068                return;
1069
1070        at91_irq_err_state(dev, cf, new_state);
1071        netif_rx(skb);
1072
1073        dev->stats.rx_packets++;
1074        dev->stats.rx_bytes += cf->can_dlc;
1075
1076        priv->can.state = new_state;
1077}
1078
1079/*
1080 * interrupt handler
1081 */
1082static irqreturn_t at91_irq(int irq, void *dev_id)
1083{
1084        struct net_device *dev = dev_id;
1085        struct at91_priv *priv = netdev_priv(dev);
1086        irqreturn_t handled = IRQ_NONE;
1087        u32 reg_sr, reg_imr;
1088
1089        reg_sr = at91_read(priv, AT91_SR);
1090        reg_imr = at91_read(priv, AT91_IMR);
1091
1092        /* Ignore masked interrupts */
1093        reg_sr &= reg_imr;
1094        if (!reg_sr)
1095                goto exit;
1096
1097        handled = IRQ_HANDLED;
1098
1099        /* Receive or error interrupt? -> napi */
1100        if (reg_sr & (get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME)) {
1101                /*
1102                 * The error bits are clear on read,
1103                 * save for later use.
1104                 */
1105                priv->reg_sr = reg_sr;
1106                at91_write(priv, AT91_IDR,
1107                           get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME);
1108                napi_schedule(&priv->napi);
1109        }
1110
1111        /* Transmission complete interrupt */
1112        if (reg_sr & get_irq_mb_tx(priv))
1113                at91_irq_tx(dev, reg_sr);
1114
1115        at91_irq_err(dev);
1116
1117 exit:
1118        return handled;
1119}
1120
1121static int at91_open(struct net_device *dev)
1122{
1123        struct at91_priv *priv = netdev_priv(dev);
1124        int err;
1125
1126        err = clk_prepare_enable(priv->clk);
1127        if (err)
1128                return err;
1129
1130        /* check or determine and set bittime */
1131        err = open_candev(dev);
1132        if (err)
1133                goto out;
1134
1135        /* register interrupt handler */
1136        if (request_irq(dev->irq, at91_irq, IRQF_SHARED,
1137                        dev->name, dev)) {
1138                err = -EAGAIN;
1139                goto out_close;
1140        }
1141
1142        can_led_event(dev, CAN_LED_EVENT_OPEN);
1143
1144        /* start chip and queuing */
1145        at91_chip_start(dev);
1146        napi_enable(&priv->napi);
1147        netif_start_queue(dev);
1148
1149        return 0;
1150
1151 out_close:
1152        close_candev(dev);
1153 out:
1154        clk_disable_unprepare(priv->clk);
1155
1156        return err;
1157}
1158
1159/*
1160 * stop CAN bus activity
1161 */
1162static int at91_close(struct net_device *dev)
1163{
1164        struct at91_priv *priv = netdev_priv(dev);
1165
1166        netif_stop_queue(dev);
1167        napi_disable(&priv->napi);
1168        at91_chip_stop(dev, CAN_STATE_STOPPED);
1169
1170        free_irq(dev->irq, dev);
1171        clk_disable_unprepare(priv->clk);
1172
1173        close_candev(dev);
1174
1175        can_led_event(dev, CAN_LED_EVENT_STOP);
1176
1177        return 0;
1178}
1179
1180static int at91_set_mode(struct net_device *dev, enum can_mode mode)
1181{
1182        switch (mode) {
1183        case CAN_MODE_START:
1184                at91_chip_start(dev);
1185                netif_wake_queue(dev);
1186                break;
1187
1188        default:
1189                return -EOPNOTSUPP;
1190        }
1191
1192        return 0;
1193}
1194
1195static const struct net_device_ops at91_netdev_ops = {
1196        .ndo_open       = at91_open,
1197        .ndo_stop       = at91_close,
1198        .ndo_start_xmit = at91_start_xmit,
1199        .ndo_change_mtu = can_change_mtu,
1200};
1201
1202static ssize_t at91_sysfs_show_mb0_id(struct device *dev,
1203                struct device_attribute *attr, char *buf)
1204{
1205        struct at91_priv *priv = netdev_priv(to_net_dev(dev));
1206
1207        if (priv->mb0_id & CAN_EFF_FLAG)
1208                return snprintf(buf, PAGE_SIZE, "0x%08x\n", priv->mb0_id);
1209        else
1210                return snprintf(buf, PAGE_SIZE, "0x%03x\n", priv->mb0_id);
1211}
1212
1213static ssize_t at91_sysfs_set_mb0_id(struct device *dev,
1214                struct device_attribute *attr, const char *buf, size_t count)
1215{
1216        struct net_device *ndev = to_net_dev(dev);
1217        struct at91_priv *priv = netdev_priv(ndev);
1218        unsigned long can_id;
1219        ssize_t ret;
1220        int err;
1221
1222        rtnl_lock();
1223
1224        if (ndev->flags & IFF_UP) {
1225                ret = -EBUSY;
1226                goto out;
1227        }
1228
1229        err = kstrtoul(buf, 0, &can_id);
1230        if (err) {
1231                ret = err;
1232                goto out;
1233        }
1234
1235        if (can_id & CAN_EFF_FLAG)
1236                can_id &= CAN_EFF_MASK | CAN_EFF_FLAG;
1237        else
1238                can_id &= CAN_SFF_MASK;
1239
1240        priv->mb0_id = can_id;
1241        ret = count;
1242
1243 out:
1244        rtnl_unlock();
1245        return ret;
1246}
1247
1248static DEVICE_ATTR(mb0_id, S_IWUSR | S_IRUGO,
1249        at91_sysfs_show_mb0_id, at91_sysfs_set_mb0_id);
1250
1251static struct attribute *at91_sysfs_attrs[] = {
1252        &dev_attr_mb0_id.attr,
1253        NULL,
1254};
1255
1256static struct attribute_group at91_sysfs_attr_group = {
1257        .attrs = at91_sysfs_attrs,
1258};
1259
1260#if defined(CONFIG_OF)
1261static const struct of_device_id at91_can_dt_ids[] = {
1262        {
1263                .compatible = "atmel,at91sam9x5-can",
1264                .data = &at91_at91sam9x5_data,
1265        }, {
1266                .compatible = "atmel,at91sam9263-can",
1267                .data = &at91_at91sam9263_data,
1268        }, {
1269                /* sentinel */
1270        }
1271};
1272MODULE_DEVICE_TABLE(of, at91_can_dt_ids);
1273#endif
1274
1275static const struct at91_devtype_data *at91_can_get_driver_data(struct platform_device *pdev)
1276{
1277        if (pdev->dev.of_node) {
1278                const struct of_device_id *match;
1279
1280                match = of_match_node(at91_can_dt_ids, pdev->dev.of_node);
1281                if (!match) {
1282                        dev_err(&pdev->dev, "no matching node found in dtb\n");
1283                        return NULL;
1284                }
1285                return (const struct at91_devtype_data *)match->data;
1286        }
1287        return (const struct at91_devtype_data *)
1288                platform_get_device_id(pdev)->driver_data;
1289}
1290
1291static int at91_can_probe(struct platform_device *pdev)
1292{
1293        const struct at91_devtype_data *devtype_data;
1294        struct net_device *dev;
1295        struct at91_priv *priv;
1296        struct resource *res;
1297        struct clk *clk;
1298        void __iomem *addr;
1299        int err, irq;
1300
1301        devtype_data = at91_can_get_driver_data(pdev);
1302        if (!devtype_data) {
1303                dev_err(&pdev->dev, "no driver data\n");
1304                err = -ENODEV;
1305                goto exit;
1306        }
1307
1308        clk = clk_get(&pdev->dev, "can_clk");
1309        if (IS_ERR(clk)) {
1310                dev_err(&pdev->dev, "no clock defined\n");
1311                err = -ENODEV;
1312                goto exit;
1313        }
1314
1315        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1316        irq = platform_get_irq(pdev, 0);
1317        if (!res || irq <= 0) {
1318                err = -ENODEV;
1319                goto exit_put;
1320        }
1321
1322        if (!request_mem_region(res->start,
1323                                resource_size(res),
1324                                pdev->name)) {
1325                err = -EBUSY;
1326                goto exit_put;
1327        }
1328
1329        addr = ioremap_nocache(res->start, resource_size(res));
1330        if (!addr) {
1331                err = -ENOMEM;
1332                goto exit_release;
1333        }
1334
1335        dev = alloc_candev(sizeof(struct at91_priv),
1336                           1 << devtype_data->tx_shift);
1337        if (!dev) {
1338                err = -ENOMEM;
1339                goto exit_iounmap;
1340        }
1341
1342        dev->netdev_ops = &at91_netdev_ops;
1343        dev->irq = irq;
1344        dev->flags |= IFF_ECHO;
1345
1346        priv = netdev_priv(dev);
1347        priv->can.clock.freq = clk_get_rate(clk);
1348        priv->can.bittiming_const = &at91_bittiming_const;
1349        priv->can.do_set_mode = at91_set_mode;
1350        priv->can.do_get_berr_counter = at91_get_berr_counter;
1351        priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
1352                CAN_CTRLMODE_LISTENONLY;
1353        priv->dev = dev;
1354        priv->reg_base = addr;
1355        priv->devtype_data = *devtype_data;
1356        priv->clk = clk;
1357        priv->pdata = dev_get_platdata(&pdev->dev);
1358        priv->mb0_id = 0x7ff;
1359
1360        netif_napi_add(dev, &priv->napi, at91_poll, get_mb_rx_num(priv));
1361
1362        if (at91_is_sam9263(priv))
1363                dev->sysfs_groups[0] = &at91_sysfs_attr_group;
1364
1365        platform_set_drvdata(pdev, dev);
1366        SET_NETDEV_DEV(dev, &pdev->dev);
1367
1368        err = register_candev(dev);
1369        if (err) {
1370                dev_err(&pdev->dev, "registering netdev failed\n");
1371                goto exit_free;
1372        }
1373
1374        devm_can_led_init(dev);
1375
1376        dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1377                 priv->reg_base, dev->irq);
1378
1379        return 0;
1380
1381 exit_free:
1382        free_candev(dev);
1383 exit_iounmap:
1384        iounmap(addr);
1385 exit_release:
1386        release_mem_region(res->start, resource_size(res));
1387 exit_put:
1388        clk_put(clk);
1389 exit:
1390        return err;
1391}
1392
1393static int at91_can_remove(struct platform_device *pdev)
1394{
1395        struct net_device *dev = platform_get_drvdata(pdev);
1396        struct at91_priv *priv = netdev_priv(dev);
1397        struct resource *res;
1398
1399        unregister_netdev(dev);
1400
1401        iounmap(priv->reg_base);
1402
1403        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1404        release_mem_region(res->start, resource_size(res));
1405
1406        clk_put(priv->clk);
1407
1408        free_candev(dev);
1409
1410        return 0;
1411}
1412
1413static const struct platform_device_id at91_can_id_table[] = {
1414        {
1415                .name = "at91sam9x5_can",
1416                .driver_data = (kernel_ulong_t)&at91_at91sam9x5_data,
1417        }, {
1418                .name = "at91_can",
1419                .driver_data = (kernel_ulong_t)&at91_at91sam9263_data,
1420        }, {
1421                /* sentinel */
1422        }
1423};
1424MODULE_DEVICE_TABLE(platform, at91_can_id_table);
1425
1426static struct platform_driver at91_can_driver = {
1427        .probe = at91_can_probe,
1428        .remove = at91_can_remove,
1429        .driver = {
1430                .name = KBUILD_MODNAME,
1431                .of_match_table = of_match_ptr(at91_can_dt_ids),
1432        },
1433        .id_table = at91_can_id_table,
1434};
1435
1436module_platform_driver(at91_can_driver);
1437
1438MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
1439MODULE_LICENSE("GPL v2");
1440MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver");
1441
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