1
2
3
4
5
6
7
8
9
10
11
12
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/delay.h>
17#include <linux/mtd/nand.h>
18#include <linux/mtd/nand_ecc.h>
19#include <linux/mtd/partitions.h>
20#include <linux/mtd/mtd.h>
21#include <linux/of_platform.h>
22#include <linux/of_gpio.h>
23#include <linux/io.h>
24#include <linux/slab.h>
25#include <asm/fsl_lbc.h>
26
27#define FSL_UPM_WAIT_RUN_PATTERN 0x1
28#define FSL_UPM_WAIT_WRITE_BYTE 0x2
29#define FSL_UPM_WAIT_WRITE_BUFFER 0x4
30
31struct fsl_upm_nand {
32 struct device *dev;
33 struct mtd_info mtd;
34 struct nand_chip chip;
35 int last_ctrl;
36 struct mtd_partition *parts;
37 struct fsl_upm upm;
38 uint8_t upm_addr_offset;
39 uint8_t upm_cmd_offset;
40 void __iomem *io_base;
41 int rnb_gpio[NAND_MAX_CHIPS];
42 uint32_t mchip_offsets[NAND_MAX_CHIPS];
43 uint32_t mchip_count;
44 uint32_t mchip_number;
45 int chip_delay;
46 uint32_t wait_flags;
47};
48
49static inline struct fsl_upm_nand *to_fsl_upm_nand(struct mtd_info *mtdinfo)
50{
51 return container_of(mtdinfo, struct fsl_upm_nand, mtd);
52}
53
54static int fun_chip_ready(struct mtd_info *mtd)
55{
56 struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
57
58 if (gpio_get_value(fun->rnb_gpio[fun->mchip_number]))
59 return 1;
60
61 dev_vdbg(fun->dev, "busy\n");
62 return 0;
63}
64
65static void fun_wait_rnb(struct fsl_upm_nand *fun)
66{
67 if (fun->rnb_gpio[fun->mchip_number] >= 0) {
68 int cnt = 1000000;
69
70 while (--cnt && !fun_chip_ready(&fun->mtd))
71 cpu_relax();
72 if (!cnt)
73 dev_err(fun->dev, "tired waiting for RNB\n");
74 } else {
75 ndelay(100);
76 }
77}
78
79static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
80{
81 struct nand_chip *chip = mtd->priv;
82 struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
83 u32 mar;
84
85 if (!(ctrl & fun->last_ctrl)) {
86 fsl_upm_end_pattern(&fun->upm);
87
88 if (cmd == NAND_CMD_NONE)
89 return;
90
91 fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
92 }
93
94 if (ctrl & NAND_CTRL_CHANGE) {
95 if (ctrl & NAND_ALE)
96 fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
97 else if (ctrl & NAND_CLE)
98 fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
99 }
100
101 mar = (cmd << (32 - fun->upm.width)) |
102 fun->mchip_offsets[fun->mchip_number];
103 fsl_upm_run_pattern(&fun->upm, chip->IO_ADDR_R, mar);
104
105 if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
106 fun_wait_rnb(fun);
107}
108
109static void fun_select_chip(struct mtd_info *mtd, int mchip_nr)
110{
111 struct nand_chip *chip = mtd->priv;
112 struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
113
114 if (mchip_nr == -1) {
115 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
116 } else if (mchip_nr >= 0 && mchip_nr < NAND_MAX_CHIPS) {
117 fun->mchip_number = mchip_nr;
118 chip->IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr];
119 chip->IO_ADDR_W = chip->IO_ADDR_R;
120 } else {
121 BUG();
122 }
123}
124
125static uint8_t fun_read_byte(struct mtd_info *mtd)
126{
127 struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
128
129 return in_8(fun->chip.IO_ADDR_R);
130}
131
132static void fun_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
133{
134 struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
135 int i;
136
137 for (i = 0; i < len; i++)
138 buf[i] = in_8(fun->chip.IO_ADDR_R);
139}
140
141static void fun_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
142{
143 struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
144 int i;
145
146 for (i = 0; i < len; i++) {
147 out_8(fun->chip.IO_ADDR_W, buf[i]);
148 if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
149 fun_wait_rnb(fun);
150 }
151 if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
152 fun_wait_rnb(fun);
153}
154
155static int fun_chip_init(struct fsl_upm_nand *fun,
156 const struct device_node *upm_np,
157 const struct resource *io_res)
158{
159 int ret;
160 struct device_node *flash_np;
161 struct mtd_part_parser_data ppdata;
162
163 fun->chip.IO_ADDR_R = fun->io_base;
164 fun->chip.IO_ADDR_W = fun->io_base;
165 fun->chip.cmd_ctrl = fun_cmd_ctrl;
166 fun->chip.chip_delay = fun->chip_delay;
167 fun->chip.read_byte = fun_read_byte;
168 fun->chip.read_buf = fun_read_buf;
169 fun->chip.write_buf = fun_write_buf;
170 fun->chip.ecc.mode = NAND_ECC_SOFT;
171 if (fun->mchip_count > 1)
172 fun->chip.select_chip = fun_select_chip;
173
174 if (fun->rnb_gpio[0] >= 0)
175 fun->chip.dev_ready = fun_chip_ready;
176
177 fun->mtd.priv = &fun->chip;
178 fun->mtd.owner = THIS_MODULE;
179
180 flash_np = of_get_next_child(upm_np, NULL);
181 if (!flash_np)
182 return -ENODEV;
183
184 fun->mtd.name = kasprintf(GFP_KERNEL, "0x%llx.%s", (u64)io_res->start,
185 flash_np->name);
186 if (!fun->mtd.name) {
187 ret = -ENOMEM;
188 goto err;
189 }
190
191 ret = nand_scan(&fun->mtd, fun->mchip_count);
192 if (ret)
193 goto err;
194
195 ppdata.of_node = flash_np;
196 ret = mtd_device_parse_register(&fun->mtd, NULL, &ppdata, NULL, 0);
197err:
198 of_node_put(flash_np);
199 if (ret)
200 kfree(fun->mtd.name);
201 return ret;
202}
203
204static int fun_probe(struct platform_device *ofdev)
205{
206 struct fsl_upm_nand *fun;
207 struct resource io_res;
208 const __be32 *prop;
209 int rnb_gpio;
210 int ret;
211 int size;
212 int i;
213
214 fun = kzalloc(sizeof(*fun), GFP_KERNEL);
215 if (!fun)
216 return -ENOMEM;
217
218 ret = of_address_to_resource(ofdev->dev.of_node, 0, &io_res);
219 if (ret) {
220 dev_err(&ofdev->dev, "can't get IO base\n");
221 goto err1;
222 }
223
224 ret = fsl_upm_find(io_res.start, &fun->upm);
225 if (ret) {
226 dev_err(&ofdev->dev, "can't find UPM\n");
227 goto err1;
228 }
229
230 prop = of_get_property(ofdev->dev.of_node, "fsl,upm-addr-offset",
231 &size);
232 if (!prop || size != sizeof(uint32_t)) {
233 dev_err(&ofdev->dev, "can't get UPM address offset\n");
234 ret = -EINVAL;
235 goto err1;
236 }
237 fun->upm_addr_offset = *prop;
238
239 prop = of_get_property(ofdev->dev.of_node, "fsl,upm-cmd-offset", &size);
240 if (!prop || size != sizeof(uint32_t)) {
241 dev_err(&ofdev->dev, "can't get UPM command offset\n");
242 ret = -EINVAL;
243 goto err1;
244 }
245 fun->upm_cmd_offset = *prop;
246
247 prop = of_get_property(ofdev->dev.of_node,
248 "fsl,upm-addr-line-cs-offsets", &size);
249 if (prop && (size / sizeof(uint32_t)) > 0) {
250 fun->mchip_count = size / sizeof(uint32_t);
251 if (fun->mchip_count >= NAND_MAX_CHIPS) {
252 dev_err(&ofdev->dev, "too much multiple chips\n");
253 goto err1;
254 }
255 for (i = 0; i < fun->mchip_count; i++)
256 fun->mchip_offsets[i] = be32_to_cpu(prop[i]);
257 } else {
258 fun->mchip_count = 1;
259 }
260
261 for (i = 0; i < fun->mchip_count; i++) {
262 fun->rnb_gpio[i] = -1;
263 rnb_gpio = of_get_gpio(ofdev->dev.of_node, i);
264 if (rnb_gpio >= 0) {
265 ret = gpio_request(rnb_gpio, dev_name(&ofdev->dev));
266 if (ret) {
267 dev_err(&ofdev->dev,
268 "can't request RNB gpio #%d\n", i);
269 goto err2;
270 }
271 gpio_direction_input(rnb_gpio);
272 fun->rnb_gpio[i] = rnb_gpio;
273 } else if (rnb_gpio == -EINVAL) {
274 dev_err(&ofdev->dev, "RNB gpio #%d is invalid\n", i);
275 goto err2;
276 }
277 }
278
279 prop = of_get_property(ofdev->dev.of_node, "chip-delay", NULL);
280 if (prop)
281 fun->chip_delay = be32_to_cpup(prop);
282 else
283 fun->chip_delay = 50;
284
285 prop = of_get_property(ofdev->dev.of_node, "fsl,upm-wait-flags", &size);
286 if (prop && size == sizeof(uint32_t))
287 fun->wait_flags = be32_to_cpup(prop);
288 else
289 fun->wait_flags = FSL_UPM_WAIT_RUN_PATTERN |
290 FSL_UPM_WAIT_WRITE_BYTE;
291
292 fun->io_base = devm_ioremap_nocache(&ofdev->dev, io_res.start,
293 resource_size(&io_res));
294 if (!fun->io_base) {
295 ret = -ENOMEM;
296 goto err2;
297 }
298
299 fun->dev = &ofdev->dev;
300 fun->last_ctrl = NAND_CLE;
301
302 ret = fun_chip_init(fun, ofdev->dev.of_node, &io_res);
303 if (ret)
304 goto err2;
305
306 dev_set_drvdata(&ofdev->dev, fun);
307
308 return 0;
309err2:
310 for (i = 0; i < fun->mchip_count; i++) {
311 if (fun->rnb_gpio[i] < 0)
312 break;
313 gpio_free(fun->rnb_gpio[i]);
314 }
315err1:
316 kfree(fun);
317
318 return ret;
319}
320
321static int fun_remove(struct platform_device *ofdev)
322{
323 struct fsl_upm_nand *fun = dev_get_drvdata(&ofdev->dev);
324 int i;
325
326 nand_release(&fun->mtd);
327 kfree(fun->mtd.name);
328
329 for (i = 0; i < fun->mchip_count; i++) {
330 if (fun->rnb_gpio[i] < 0)
331 break;
332 gpio_free(fun->rnb_gpio[i]);
333 }
334
335 kfree(fun);
336
337 return 0;
338}
339
340static const struct of_device_id of_fun_match[] = {
341 { .compatible = "fsl,upm-nand" },
342 {},
343};
344MODULE_DEVICE_TABLE(of, of_fun_match);
345
346static struct platform_driver of_fun_driver = {
347 .driver = {
348 .name = "fsl,upm-nand",
349 .owner = THIS_MODULE,
350 .of_match_table = of_fun_match,
351 },
352 .probe = fun_probe,
353 .remove = fun_remove,
354};
355
356module_platform_driver(of_fun_driver);
357
358MODULE_LICENSE("GPL");
359MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>");
360MODULE_DESCRIPTION("Driver for NAND chips working through Freescale "
361 "LocalBus User-Programmable Machine");
362
