linux/drivers/mfd/rtsx_pcr.c
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   1/* Driver for Realtek PCI-Express card reader
   2 *
   3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of the GNU General Public License as published by the
   7 * Free Software Foundation; either version 2, or (at your option) any
   8 * later version.
   9 *
  10 * This program is distributed in the hope that it will be useful, but
  11 * WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13 * General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License along
  16 * with this program; if not, see <http://www.gnu.org/licenses/>.
  17 *
  18 * Author:
  19 *   Wei WANG <wei_wang@realsil.com.cn>
  20 */
  21
  22#include <linux/pci.h>
  23#include <linux/module.h>
  24#include <linux/slab.h>
  25#include <linux/dma-mapping.h>
  26#include <linux/highmem.h>
  27#include <linux/interrupt.h>
  28#include <linux/delay.h>
  29#include <linux/idr.h>
  30#include <linux/platform_device.h>
  31#include <linux/mfd/core.h>
  32#include <linux/mfd/rtsx_pci.h>
  33#include <asm/unaligned.h>
  34
  35#include "rtsx_pcr.h"
  36
  37static bool msi_en = true;
  38module_param(msi_en, bool, S_IRUGO | S_IWUSR);
  39MODULE_PARM_DESC(msi_en, "Enable MSI");
  40
  41static DEFINE_IDR(rtsx_pci_idr);
  42static DEFINE_SPINLOCK(rtsx_pci_lock);
  43
  44static struct mfd_cell rtsx_pcr_cells[] = {
  45        [RTSX_SD_CARD] = {
  46                .name = DRV_NAME_RTSX_PCI_SDMMC,
  47        },
  48        [RTSX_MS_CARD] = {
  49                .name = DRV_NAME_RTSX_PCI_MS,
  50        },
  51};
  52
  53static const struct pci_device_id rtsx_pci_ids[] = {
  54        { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  55        { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  56        { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  57        { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  58        { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  59        { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  60        { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  61        { 0, }
  62};
  63
  64MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
  65
  66void rtsx_pci_start_run(struct rtsx_pcr *pcr)
  67{
  68        /* If pci device removed, don't queue idle work any more */
  69        if (pcr->remove_pci)
  70                return;
  71
  72        if (pcr->state != PDEV_STAT_RUN) {
  73                pcr->state = PDEV_STAT_RUN;
  74                if (pcr->ops->enable_auto_blink)
  75                        pcr->ops->enable_auto_blink(pcr);
  76
  77                if (pcr->aspm_en)
  78                        rtsx_pci_write_config_byte(pcr, LCTLR, 0);
  79        }
  80
  81        mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
  82}
  83EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
  84
  85int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
  86{
  87        int i;
  88        u32 val = HAIMR_WRITE_START;
  89
  90        val |= (u32)(addr & 0x3FFF) << 16;
  91        val |= (u32)mask << 8;
  92        val |= (u32)data;
  93
  94        rtsx_pci_writel(pcr, RTSX_HAIMR, val);
  95
  96        for (i = 0; i < MAX_RW_REG_CNT; i++) {
  97                val = rtsx_pci_readl(pcr, RTSX_HAIMR);
  98                if ((val & HAIMR_TRANS_END) == 0) {
  99                        if (data != (u8)val)
 100                                return -EIO;
 101                        return 0;
 102                }
 103        }
 104
 105        return -ETIMEDOUT;
 106}
 107EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
 108
 109int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
 110{
 111        u32 val = HAIMR_READ_START;
 112        int i;
 113
 114        val |= (u32)(addr & 0x3FFF) << 16;
 115        rtsx_pci_writel(pcr, RTSX_HAIMR, val);
 116
 117        for (i = 0; i < MAX_RW_REG_CNT; i++) {
 118                val = rtsx_pci_readl(pcr, RTSX_HAIMR);
 119                if ((val & HAIMR_TRANS_END) == 0)
 120                        break;
 121        }
 122
 123        if (i >= MAX_RW_REG_CNT)
 124                return -ETIMEDOUT;
 125
 126        if (data)
 127                *data = (u8)(val & 0xFF);
 128
 129        return 0;
 130}
 131EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
 132
 133int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
 134{
 135        int err, i, finished = 0;
 136        u8 tmp;
 137
 138        rtsx_pci_init_cmd(pcr);
 139
 140        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
 141        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
 142        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
 143        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
 144
 145        err = rtsx_pci_send_cmd(pcr, 100);
 146        if (err < 0)
 147                return err;
 148
 149        for (i = 0; i < 100000; i++) {
 150                err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
 151                if (err < 0)
 152                        return err;
 153
 154                if (!(tmp & 0x80)) {
 155                        finished = 1;
 156                        break;
 157                }
 158        }
 159
 160        if (!finished)
 161                return -ETIMEDOUT;
 162
 163        return 0;
 164}
 165EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
 166
 167int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
 168{
 169        int err, i, finished = 0;
 170        u16 data;
 171        u8 *ptr, tmp;
 172
 173        rtsx_pci_init_cmd(pcr);
 174
 175        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
 176        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
 177
 178        err = rtsx_pci_send_cmd(pcr, 100);
 179        if (err < 0)
 180                return err;
 181
 182        for (i = 0; i < 100000; i++) {
 183                err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
 184                if (err < 0)
 185                        return err;
 186
 187                if (!(tmp & 0x80)) {
 188                        finished = 1;
 189                        break;
 190                }
 191        }
 192
 193        if (!finished)
 194                return -ETIMEDOUT;
 195
 196        rtsx_pci_init_cmd(pcr);
 197
 198        rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
 199        rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
 200
 201        err = rtsx_pci_send_cmd(pcr, 100);
 202        if (err < 0)
 203                return err;
 204
 205        ptr = rtsx_pci_get_cmd_data(pcr);
 206        data = ((u16)ptr[1] << 8) | ptr[0];
 207
 208        if (val)
 209                *val = data;
 210
 211        return 0;
 212}
 213EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
 214
 215void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
 216{
 217        rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
 218        rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
 219
 220        rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
 221        rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
 222}
 223EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
 224
 225void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
 226                u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
 227{
 228        unsigned long flags;
 229        u32 val = 0;
 230        u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
 231
 232        val |= (u32)(cmd_type & 0x03) << 30;
 233        val |= (u32)(reg_addr & 0x3FFF) << 16;
 234        val |= (u32)mask << 8;
 235        val |= (u32)data;
 236
 237        spin_lock_irqsave(&pcr->lock, flags);
 238        ptr += pcr->ci;
 239        if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
 240                put_unaligned_le32(val, ptr);
 241                ptr++;
 242                pcr->ci++;
 243        }
 244        spin_unlock_irqrestore(&pcr->lock, flags);
 245}
 246EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
 247
 248void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
 249{
 250        u32 val = 1 << 31;
 251
 252        rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 253
 254        val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
 255        /* Hardware Auto Response */
 256        val |= 0x40000000;
 257        rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
 258}
 259EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
 260
 261int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
 262{
 263        struct completion trans_done;
 264        u32 val = 1 << 31;
 265        long timeleft;
 266        unsigned long flags;
 267        int err = 0;
 268
 269        spin_lock_irqsave(&pcr->lock, flags);
 270
 271        /* set up data structures for the wakeup system */
 272        pcr->done = &trans_done;
 273        pcr->trans_result = TRANS_NOT_READY;
 274        init_completion(&trans_done);
 275
 276        rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 277
 278        val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
 279        /* Hardware Auto Response */
 280        val |= 0x40000000;
 281        rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
 282
 283        spin_unlock_irqrestore(&pcr->lock, flags);
 284
 285        /* Wait for TRANS_OK_INT */
 286        timeleft = wait_for_completion_interruptible_timeout(
 287                        &trans_done, msecs_to_jiffies(timeout));
 288        if (timeleft <= 0) {
 289                dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
 290                                __func__, __LINE__);
 291                err = -ETIMEDOUT;
 292                goto finish_send_cmd;
 293        }
 294
 295        spin_lock_irqsave(&pcr->lock, flags);
 296        if (pcr->trans_result == TRANS_RESULT_FAIL)
 297                err = -EINVAL;
 298        else if (pcr->trans_result == TRANS_RESULT_OK)
 299                err = 0;
 300        else if (pcr->trans_result == TRANS_NO_DEVICE)
 301                err = -ENODEV;
 302        spin_unlock_irqrestore(&pcr->lock, flags);
 303
 304finish_send_cmd:
 305        spin_lock_irqsave(&pcr->lock, flags);
 306        pcr->done = NULL;
 307        spin_unlock_irqrestore(&pcr->lock, flags);
 308
 309        if ((err < 0) && (err != -ENODEV))
 310                rtsx_pci_stop_cmd(pcr);
 311
 312        if (pcr->finish_me)
 313                complete(pcr->finish_me);
 314
 315        return err;
 316}
 317EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
 318
 319static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
 320                dma_addr_t addr, unsigned int len, int end)
 321{
 322        u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
 323        u64 val;
 324        u8 option = SG_VALID | SG_TRANS_DATA;
 325
 326        dev_dbg(&(pcr->pci->dev), "DMA addr: 0x%x, Len: 0x%x\n",
 327                        (unsigned int)addr, len);
 328
 329        if (end)
 330                option |= SG_END;
 331        val = ((u64)addr << 32) | ((u64)len << 12) | option;
 332
 333        put_unaligned_le64(val, ptr);
 334        pcr->sgi++;
 335}
 336
 337int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
 338                int num_sg, bool read, int timeout)
 339{
 340        int err = 0, count;
 341
 342        dev_dbg(&(pcr->pci->dev), "--> %s: num_sg = %d\n", __func__, num_sg);
 343        count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read);
 344        if (count < 1)
 345                return -EINVAL;
 346        dev_dbg(&(pcr->pci->dev), "DMA mapping count: %d\n", count);
 347
 348        err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout);
 349
 350        rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read);
 351
 352        return err;
 353}
 354EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
 355
 356int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
 357                int num_sg, bool read)
 358{
 359        enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
 360
 361        if (pcr->remove_pci)
 362                return -EINVAL;
 363
 364        if ((sglist == NULL) || (num_sg <= 0))
 365                return -EINVAL;
 366
 367        return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir);
 368}
 369EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg);
 370
 371void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
 372                int num_sg, bool read)
 373{
 374        enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
 375
 376        dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir);
 377}
 378EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg);
 379
 380int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
 381                int count, bool read, int timeout)
 382{
 383        struct completion trans_done;
 384        struct scatterlist *sg;
 385        dma_addr_t addr;
 386        long timeleft;
 387        unsigned long flags;
 388        unsigned int len;
 389        int i, err = 0;
 390        u32 val;
 391        u8 dir = read ? DEVICE_TO_HOST : HOST_TO_DEVICE;
 392
 393        if (pcr->remove_pci)
 394                return -ENODEV;
 395
 396        if ((sglist == NULL) || (count < 1))
 397                return -EINVAL;
 398
 399        val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
 400        pcr->sgi = 0;
 401        for_each_sg(sglist, sg, count, i) {
 402                addr = sg_dma_address(sg);
 403                len = sg_dma_len(sg);
 404                rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
 405        }
 406
 407        spin_lock_irqsave(&pcr->lock, flags);
 408
 409        pcr->done = &trans_done;
 410        pcr->trans_result = TRANS_NOT_READY;
 411        init_completion(&trans_done);
 412        rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
 413        rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
 414
 415        spin_unlock_irqrestore(&pcr->lock, flags);
 416
 417        timeleft = wait_for_completion_interruptible_timeout(
 418                        &trans_done, msecs_to_jiffies(timeout));
 419        if (timeleft <= 0) {
 420                dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
 421                                __func__, __LINE__);
 422                err = -ETIMEDOUT;
 423                goto out;
 424        }
 425
 426        spin_lock_irqsave(&pcr->lock, flags);
 427        if (pcr->trans_result == TRANS_RESULT_FAIL)
 428                err = -EINVAL;
 429        else if (pcr->trans_result == TRANS_NO_DEVICE)
 430                err = -ENODEV;
 431        spin_unlock_irqrestore(&pcr->lock, flags);
 432
 433out:
 434        spin_lock_irqsave(&pcr->lock, flags);
 435        pcr->done = NULL;
 436        spin_unlock_irqrestore(&pcr->lock, flags);
 437
 438        if ((err < 0) && (err != -ENODEV))
 439                rtsx_pci_stop_cmd(pcr);
 440
 441        if (pcr->finish_me)
 442                complete(pcr->finish_me);
 443
 444        return err;
 445}
 446EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer);
 447
 448int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
 449{
 450        int err;
 451        int i, j;
 452        u16 reg;
 453        u8 *ptr;
 454
 455        if (buf_len > 512)
 456                buf_len = 512;
 457
 458        ptr = buf;
 459        reg = PPBUF_BASE2;
 460        for (i = 0; i < buf_len / 256; i++) {
 461                rtsx_pci_init_cmd(pcr);
 462
 463                for (j = 0; j < 256; j++)
 464                        rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
 465
 466                err = rtsx_pci_send_cmd(pcr, 250);
 467                if (err < 0)
 468                        return err;
 469
 470                memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
 471                ptr += 256;
 472        }
 473
 474        if (buf_len % 256) {
 475                rtsx_pci_init_cmd(pcr);
 476
 477                for (j = 0; j < buf_len % 256; j++)
 478                        rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
 479
 480                err = rtsx_pci_send_cmd(pcr, 250);
 481                if (err < 0)
 482                        return err;
 483        }
 484
 485        memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
 486
 487        return 0;
 488}
 489EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
 490
 491int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
 492{
 493        int err;
 494        int i, j;
 495        u16 reg;
 496        u8 *ptr;
 497
 498        if (buf_len > 512)
 499                buf_len = 512;
 500
 501        ptr = buf;
 502        reg = PPBUF_BASE2;
 503        for (i = 0; i < buf_len / 256; i++) {
 504                rtsx_pci_init_cmd(pcr);
 505
 506                for (j = 0; j < 256; j++) {
 507                        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 508                                        reg++, 0xFF, *ptr);
 509                        ptr++;
 510                }
 511
 512                err = rtsx_pci_send_cmd(pcr, 250);
 513                if (err < 0)
 514                        return err;
 515        }
 516
 517        if (buf_len % 256) {
 518                rtsx_pci_init_cmd(pcr);
 519
 520                for (j = 0; j < buf_len % 256; j++) {
 521                        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 522                                        reg++, 0xFF, *ptr);
 523                        ptr++;
 524                }
 525
 526                err = rtsx_pci_send_cmd(pcr, 250);
 527                if (err < 0)
 528                        return err;
 529        }
 530
 531        return 0;
 532}
 533EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
 534
 535static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
 536{
 537        int err;
 538
 539        rtsx_pci_init_cmd(pcr);
 540
 541        while (*tbl & 0xFFFF0000) {
 542                rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 543                                (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
 544                tbl++;
 545        }
 546
 547        err = rtsx_pci_send_cmd(pcr, 100);
 548        if (err < 0)
 549                return err;
 550
 551        return 0;
 552}
 553
 554int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
 555{
 556        const u32 *tbl;
 557
 558        if (card == RTSX_SD_CARD)
 559                tbl = pcr->sd_pull_ctl_enable_tbl;
 560        else if (card == RTSX_MS_CARD)
 561                tbl = pcr->ms_pull_ctl_enable_tbl;
 562        else
 563                return -EINVAL;
 564
 565        return rtsx_pci_set_pull_ctl(pcr, tbl);
 566}
 567EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
 568
 569int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
 570{
 571        const u32 *tbl;
 572
 573        if (card == RTSX_SD_CARD)
 574                tbl = pcr->sd_pull_ctl_disable_tbl;
 575        else if (card == RTSX_MS_CARD)
 576                tbl = pcr->ms_pull_ctl_disable_tbl;
 577        else
 578                return -EINVAL;
 579
 580
 581        return rtsx_pci_set_pull_ctl(pcr, tbl);
 582}
 583EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
 584
 585static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
 586{
 587        pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
 588
 589        if (pcr->num_slots > 1)
 590                pcr->bier |= MS_INT_EN;
 591
 592        /* Enable Bus Interrupt */
 593        rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
 594
 595        dev_dbg(&(pcr->pci->dev), "RTSX_BIER: 0x%08x\n", pcr->bier);
 596}
 597
 598static inline u8 double_ssc_depth(u8 depth)
 599{
 600        return ((depth > 1) ? (depth - 1) : depth);
 601}
 602
 603static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
 604{
 605        if (div > CLK_DIV_1) {
 606                if (ssc_depth > (div - 1))
 607                        ssc_depth -= (div - 1);
 608                else
 609                        ssc_depth = SSC_DEPTH_4M;
 610        }
 611
 612        return ssc_depth;
 613}
 614
 615int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
 616                u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
 617{
 618        int err, clk;
 619        u8 n, clk_divider, mcu_cnt, div;
 620        u8 depth[] = {
 621                [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
 622                [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
 623                [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
 624                [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
 625                [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
 626        };
 627
 628        if (initial_mode) {
 629                /* We use 250k(around) here, in initial stage */
 630                clk_divider = SD_CLK_DIVIDE_128;
 631                card_clock = 30000000;
 632        } else {
 633                clk_divider = SD_CLK_DIVIDE_0;
 634        }
 635        err = rtsx_pci_write_register(pcr, SD_CFG1,
 636                        SD_CLK_DIVIDE_MASK, clk_divider);
 637        if (err < 0)
 638                return err;
 639
 640        card_clock /= 1000000;
 641        dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock);
 642
 643        clk = card_clock;
 644        if (!initial_mode && double_clk)
 645                clk = card_clock * 2;
 646        dev_dbg(&(pcr->pci->dev),
 647                        "Internal SSC clock: %dMHz (cur_clock = %d)\n",
 648                        clk, pcr->cur_clock);
 649
 650        if (clk == pcr->cur_clock)
 651                return 0;
 652
 653        if (pcr->ops->conv_clk_and_div_n)
 654                n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
 655        else
 656                n = (u8)(clk - 2);
 657        if ((clk <= 2) || (n > MAX_DIV_N_PCR))
 658                return -EINVAL;
 659
 660        mcu_cnt = (u8)(125/clk + 3);
 661        if (mcu_cnt > 15)
 662                mcu_cnt = 15;
 663
 664        /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
 665        div = CLK_DIV_1;
 666        while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) {
 667                if (pcr->ops->conv_clk_and_div_n) {
 668                        int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
 669                                        DIV_N_TO_CLK) * 2;
 670                        n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
 671                                        CLK_TO_DIV_N);
 672                } else {
 673                        n = (n + 2) * 2 - 2;
 674                }
 675                div++;
 676        }
 677        dev_dbg(&(pcr->pci->dev), "n = %d, div = %d\n", n, div);
 678
 679        ssc_depth = depth[ssc_depth];
 680        if (double_clk)
 681                ssc_depth = double_ssc_depth(ssc_depth);
 682
 683        ssc_depth = revise_ssc_depth(ssc_depth, div);
 684        dev_dbg(&(pcr->pci->dev), "ssc_depth = %d\n", ssc_depth);
 685
 686        rtsx_pci_init_cmd(pcr);
 687        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
 688                        CLK_LOW_FREQ, CLK_LOW_FREQ);
 689        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
 690                        0xFF, (div << 4) | mcu_cnt);
 691        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
 692        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
 693                        SSC_DEPTH_MASK, ssc_depth);
 694        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
 695        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
 696        if (vpclk) {
 697                rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 698                                PHASE_NOT_RESET, 0);
 699                rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 700                                PHASE_NOT_RESET, PHASE_NOT_RESET);
 701        }
 702
 703        err = rtsx_pci_send_cmd(pcr, 2000);
 704        if (err < 0)
 705                return err;
 706
 707        /* Wait SSC clock stable */
 708        udelay(10);
 709        err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
 710        if (err < 0)
 711                return err;
 712
 713        pcr->cur_clock = clk;
 714        return 0;
 715}
 716EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
 717
 718int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
 719{
 720        if (pcr->ops->card_power_on)
 721                return pcr->ops->card_power_on(pcr, card);
 722
 723        return 0;
 724}
 725EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
 726
 727int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
 728{
 729        if (pcr->ops->card_power_off)
 730                return pcr->ops->card_power_off(pcr, card);
 731
 732        return 0;
 733}
 734EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
 735
 736int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
 737{
 738        unsigned int cd_mask[] = {
 739                [RTSX_SD_CARD] = SD_EXIST,
 740                [RTSX_MS_CARD] = MS_EXIST
 741        };
 742
 743        if (!(pcr->flags & PCR_MS_PMOS)) {
 744                /* When using single PMOS, accessing card is not permitted
 745                 * if the existing card is not the designated one.
 746                 */
 747                if (pcr->card_exist & (~cd_mask[card]))
 748                        return -EIO;
 749        }
 750
 751        return 0;
 752}
 753EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check);
 754
 755int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 756{
 757        if (pcr->ops->switch_output_voltage)
 758                return pcr->ops->switch_output_voltage(pcr, voltage);
 759
 760        return 0;
 761}
 762EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
 763
 764unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
 765{
 766        unsigned int val;
 767
 768        val = rtsx_pci_readl(pcr, RTSX_BIPR);
 769        if (pcr->ops->cd_deglitch)
 770                val = pcr->ops->cd_deglitch(pcr);
 771
 772        return val;
 773}
 774EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
 775
 776void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
 777{
 778        struct completion finish;
 779
 780        pcr->finish_me = &finish;
 781        init_completion(&finish);
 782
 783        if (pcr->done)
 784                complete(pcr->done);
 785
 786        if (!pcr->remove_pci)
 787                rtsx_pci_stop_cmd(pcr);
 788
 789        wait_for_completion_interruptible_timeout(&finish,
 790                        msecs_to_jiffies(2));
 791        pcr->finish_me = NULL;
 792}
 793EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
 794
 795static void rtsx_pci_card_detect(struct work_struct *work)
 796{
 797        struct delayed_work *dwork;
 798        struct rtsx_pcr *pcr;
 799        unsigned long flags;
 800        unsigned int card_detect = 0, card_inserted, card_removed;
 801        u32 irq_status;
 802
 803        dwork = to_delayed_work(work);
 804        pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
 805
 806        dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
 807
 808        mutex_lock(&pcr->pcr_mutex);
 809        spin_lock_irqsave(&pcr->lock, flags);
 810
 811        irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
 812        dev_dbg(&(pcr->pci->dev), "irq_status: 0x%08x\n", irq_status);
 813
 814        irq_status &= CARD_EXIST;
 815        card_inserted = pcr->card_inserted & irq_status;
 816        card_removed = pcr->card_removed;
 817        pcr->card_inserted = 0;
 818        pcr->card_removed = 0;
 819
 820        spin_unlock_irqrestore(&pcr->lock, flags);
 821
 822        if (card_inserted || card_removed) {
 823                dev_dbg(&(pcr->pci->dev),
 824                                "card_inserted: 0x%x, card_removed: 0x%x\n",
 825                                card_inserted, card_removed);
 826
 827                if (pcr->ops->cd_deglitch)
 828                        card_inserted = pcr->ops->cd_deglitch(pcr);
 829
 830                card_detect = card_inserted | card_removed;
 831
 832                pcr->card_exist |= card_inserted;
 833                pcr->card_exist &= ~card_removed;
 834        }
 835
 836        mutex_unlock(&pcr->pcr_mutex);
 837
 838        if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
 839                pcr->slots[RTSX_SD_CARD].card_event(
 840                                pcr->slots[RTSX_SD_CARD].p_dev);
 841        if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
 842                pcr->slots[RTSX_MS_CARD].card_event(
 843                                pcr->slots[RTSX_MS_CARD].p_dev);
 844}
 845
 846static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
 847{
 848        struct rtsx_pcr *pcr = dev_id;
 849        u32 int_reg;
 850
 851        if (!pcr)
 852                return IRQ_NONE;
 853
 854        spin_lock(&pcr->lock);
 855
 856        int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
 857        /* Clear interrupt flag */
 858        rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
 859        if ((int_reg & pcr->bier) == 0) {
 860                spin_unlock(&pcr->lock);
 861                return IRQ_NONE;
 862        }
 863        if (int_reg == 0xFFFFFFFF) {
 864                spin_unlock(&pcr->lock);
 865                return IRQ_HANDLED;
 866        }
 867
 868        int_reg &= (pcr->bier | 0x7FFFFF);
 869
 870        if (int_reg & SD_INT) {
 871                if (int_reg & SD_EXIST) {
 872                        pcr->card_inserted |= SD_EXIST;
 873                } else {
 874                        pcr->card_removed |= SD_EXIST;
 875                        pcr->card_inserted &= ~SD_EXIST;
 876                }
 877        }
 878
 879        if (int_reg & MS_INT) {
 880                if (int_reg & MS_EXIST) {
 881                        pcr->card_inserted |= MS_EXIST;
 882                } else {
 883                        pcr->card_removed |= MS_EXIST;
 884                        pcr->card_inserted &= ~MS_EXIST;
 885                }
 886        }
 887
 888        if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
 889                if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
 890                        pcr->trans_result = TRANS_RESULT_FAIL;
 891                        if (pcr->done)
 892                                complete(pcr->done);
 893                } else if (int_reg & TRANS_OK_INT) {
 894                        pcr->trans_result = TRANS_RESULT_OK;
 895                        if (pcr->done)
 896                                complete(pcr->done);
 897                }
 898        }
 899
 900        if (pcr->card_inserted || pcr->card_removed)
 901                schedule_delayed_work(&pcr->carddet_work,
 902                                msecs_to_jiffies(200));
 903
 904        spin_unlock(&pcr->lock);
 905        return IRQ_HANDLED;
 906}
 907
 908static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
 909{
 910        dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n",
 911                        __func__, pcr->msi_en, pcr->pci->irq);
 912
 913        if (request_irq(pcr->pci->irq, rtsx_pci_isr,
 914                        pcr->msi_en ? 0 : IRQF_SHARED,
 915                        DRV_NAME_RTSX_PCI, pcr)) {
 916                dev_err(&(pcr->pci->dev),
 917                        "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
 918                        pcr->pci->irq);
 919                return -1;
 920        }
 921
 922        pcr->irq = pcr->pci->irq;
 923        pci_intx(pcr->pci, !pcr->msi_en);
 924
 925        return 0;
 926}
 927
 928static void rtsx_pci_idle_work(struct work_struct *work)
 929{
 930        struct delayed_work *dwork = to_delayed_work(work);
 931        struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
 932
 933        dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
 934
 935        mutex_lock(&pcr->pcr_mutex);
 936
 937        pcr->state = PDEV_STAT_IDLE;
 938
 939        if (pcr->ops->disable_auto_blink)
 940                pcr->ops->disable_auto_blink(pcr);
 941        if (pcr->ops->turn_off_led)
 942                pcr->ops->turn_off_led(pcr);
 943
 944        if (pcr->aspm_en)
 945                rtsx_pci_write_config_byte(pcr, LCTLR, pcr->aspm_en);
 946
 947        mutex_unlock(&pcr->pcr_mutex);
 948}
 949
 950#ifdef CONFIG_PM
 951static void rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state)
 952{
 953        if (pcr->ops->turn_off_led)
 954                pcr->ops->turn_off_led(pcr);
 955
 956        rtsx_pci_writel(pcr, RTSX_BIER, 0);
 957        pcr->bier = 0;
 958
 959        rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
 960        rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state);
 961
 962        if (pcr->ops->force_power_down)
 963                pcr->ops->force_power_down(pcr, pm_state);
 964}
 965#endif
 966
 967static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
 968{
 969        int err;
 970
 971        rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 972
 973        rtsx_pci_enable_bus_int(pcr);
 974
 975        /* Power on SSC */
 976        err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
 977        if (err < 0)
 978                return err;
 979
 980        /* Wait SSC power stable */
 981        udelay(200);
 982
 983        if (pcr->ops->optimize_phy) {
 984                err = pcr->ops->optimize_phy(pcr);
 985                if (err < 0)
 986                        return err;
 987        }
 988
 989        rtsx_pci_init_cmd(pcr);
 990
 991        /* Set mcu_cnt to 7 to ensure data can be sampled properly */
 992        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
 993
 994        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
 995        /* Disable card clock */
 996        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
 997        /* Reset delink mode */
 998        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
 999        /* Card driving select */
1000        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
1001                        0xFF, pcr->card_drive_sel);
1002        /* Enable SSC Clock */
1003        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
1004                        0xFF, SSC_8X_EN | SSC_SEL_4M);
1005        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
1006        /* Disable cd_pwr_save */
1007        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
1008        /* Clear Link Ready Interrupt */
1009        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
1010                        LINK_RDY_INT, LINK_RDY_INT);
1011        /* Enlarge the estimation window of PERST# glitch
1012         * to reduce the chance of invalid card interrupt
1013         */
1014        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
1015        /* Update RC oscillator to 400k
1016         * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
1017         *                1: 2M  0: 400k
1018         */
1019        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
1020        /* Set interrupt write clear
1021         * bit 1: U_elbi_if_rd_clr_en
1022         *      1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
1023         *      0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
1024         */
1025        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
1026
1027        err = rtsx_pci_send_cmd(pcr, 100);
1028        if (err < 0)
1029                return err;
1030
1031        rtsx_pci_write_config_byte(pcr, LCTLR, 0);
1032
1033        /* Enable clk_request_n to enable clock power management */
1034        rtsx_pci_write_config_byte(pcr, 0x81, 1);
1035        /* Enter L1 when host tx idle */
1036        rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
1037
1038        if (pcr->ops->extra_init_hw) {
1039                err = pcr->ops->extra_init_hw(pcr);
1040                if (err < 0)
1041                        return err;
1042        }
1043
1044        /* No CD interrupt if probing driver with card inserted.
1045         * So we need to initialize pcr->card_exist here.
1046         */
1047        if (pcr->ops->cd_deglitch)
1048                pcr->card_exist = pcr->ops->cd_deglitch(pcr);
1049        else
1050                pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
1051
1052        return 0;
1053}
1054
1055static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1056{
1057        int err;
1058
1059        spin_lock_init(&pcr->lock);
1060        mutex_init(&pcr->pcr_mutex);
1061
1062        switch (PCI_PID(pcr)) {
1063        default:
1064        case 0x5209:
1065                rts5209_init_params(pcr);
1066                break;
1067
1068        case 0x5229:
1069                rts5229_init_params(pcr);
1070                break;
1071
1072        case 0x5289:
1073                rtl8411_init_params(pcr);
1074                break;
1075
1076        case 0x5227:
1077                rts5227_init_params(pcr);
1078                break;
1079
1080        case 0x5249:
1081                rts5249_init_params(pcr);
1082                break;
1083
1084        case 0x5287:
1085                rtl8411b_init_params(pcr);
1086                break;
1087
1088        case 0x5286:
1089                rtl8402_init_params(pcr);
1090                break;
1091        }
1092
1093        dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n",
1094                        PCI_PID(pcr), pcr->ic_version);
1095
1096        pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1097                        GFP_KERNEL);
1098        if (!pcr->slots)
1099                return -ENOMEM;
1100
1101        if (pcr->ops->fetch_vendor_settings)
1102                pcr->ops->fetch_vendor_settings(pcr);
1103
1104        dev_dbg(&(pcr->pci->dev), "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
1105        dev_dbg(&(pcr->pci->dev), "pcr->sd30_drive_sel_1v8 = 0x%x\n",
1106                        pcr->sd30_drive_sel_1v8);
1107        dev_dbg(&(pcr->pci->dev), "pcr->sd30_drive_sel_3v3 = 0x%x\n",
1108                        pcr->sd30_drive_sel_3v3);
1109        dev_dbg(&(pcr->pci->dev), "pcr->card_drive_sel = 0x%x\n",
1110                        pcr->card_drive_sel);
1111        dev_dbg(&(pcr->pci->dev), "pcr->flags = 0x%x\n", pcr->flags);
1112
1113        pcr->state = PDEV_STAT_IDLE;
1114        err = rtsx_pci_init_hw(pcr);
1115        if (err < 0) {
1116                kfree(pcr->slots);
1117                return err;
1118        }
1119
1120        return 0;
1121}
1122
1123static int rtsx_pci_probe(struct pci_dev *pcidev,
1124                          const struct pci_device_id *id)
1125{
1126        struct rtsx_pcr *pcr;
1127        struct pcr_handle *handle;
1128        u32 base, len;
1129        int ret, i;
1130
1131        dev_dbg(&(pcidev->dev),
1132                ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1133                pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1134                (int)pcidev->revision);
1135
1136        ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
1137        if (ret < 0)
1138                return ret;
1139
1140        ret = pci_enable_device(pcidev);
1141        if (ret)
1142                return ret;
1143
1144        ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1145        if (ret)
1146                goto disable;
1147
1148        pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1149        if (!pcr) {
1150                ret = -ENOMEM;
1151                goto release_pci;
1152        }
1153
1154        handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1155        if (!handle) {
1156                ret = -ENOMEM;
1157                goto free_pcr;
1158        }
1159        handle->pcr = pcr;
1160
1161        idr_preload(GFP_KERNEL);
1162        spin_lock(&rtsx_pci_lock);
1163        ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
1164        if (ret >= 0)
1165                pcr->id = ret;
1166        spin_unlock(&rtsx_pci_lock);
1167        idr_preload_end();
1168        if (ret < 0)
1169                goto free_handle;
1170
1171        pcr->pci = pcidev;
1172        dev_set_drvdata(&pcidev->dev, handle);
1173
1174        len = pci_resource_len(pcidev, 0);
1175        base = pci_resource_start(pcidev, 0);
1176        pcr->remap_addr = ioremap_nocache(base, len);
1177        if (!pcr->remap_addr) {
1178                ret = -ENOMEM;
1179                goto free_handle;
1180        }
1181
1182        pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1183                        RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1184                        GFP_KERNEL);
1185        if (pcr->rtsx_resv_buf == NULL) {
1186                ret = -ENXIO;
1187                goto unmap;
1188        }
1189        pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1190        pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1191        pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1192        pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1193
1194        pcr->card_inserted = 0;
1195        pcr->card_removed = 0;
1196        INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1197        INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1198
1199        pcr->msi_en = msi_en;
1200        if (pcr->msi_en) {
1201                ret = pci_enable_msi(pcidev);
1202                if (ret)
1203                        pcr->msi_en = false;
1204        }
1205
1206        ret = rtsx_pci_acquire_irq(pcr);
1207        if (ret < 0)
1208                goto disable_msi;
1209
1210        pci_set_master(pcidev);
1211        synchronize_irq(pcr->irq);
1212
1213        ret = rtsx_pci_init_chip(pcr);
1214        if (ret < 0)
1215                goto disable_irq;
1216
1217        for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1218                rtsx_pcr_cells[i].platform_data = handle;
1219                rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1220        }
1221        ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1222                        ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1223        if (ret < 0)
1224                goto disable_irq;
1225
1226        schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1227
1228        return 0;
1229
1230disable_irq:
1231        free_irq(pcr->irq, (void *)pcr);
1232disable_msi:
1233        if (pcr->msi_en)
1234                pci_disable_msi(pcr->pci);
1235        dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1236                        pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1237unmap:
1238        iounmap(pcr->remap_addr);
1239free_handle:
1240        kfree(handle);
1241free_pcr:
1242        kfree(pcr);
1243release_pci:
1244        pci_release_regions(pcidev);
1245disable:
1246        pci_disable_device(pcidev);
1247
1248        return ret;
1249}
1250
1251static void rtsx_pci_remove(struct pci_dev *pcidev)
1252{
1253        struct pcr_handle *handle = pci_get_drvdata(pcidev);
1254        struct rtsx_pcr *pcr = handle->pcr;
1255
1256        pcr->remove_pci = true;
1257
1258        /* Disable interrupts at the pcr level */
1259        spin_lock_irq(&pcr->lock);
1260        rtsx_pci_writel(pcr, RTSX_BIER, 0);
1261        pcr->bier = 0;
1262        spin_unlock_irq(&pcr->lock);
1263
1264        cancel_delayed_work_sync(&pcr->carddet_work);
1265        cancel_delayed_work_sync(&pcr->idle_work);
1266
1267        mfd_remove_devices(&pcidev->dev);
1268
1269        dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1270                        pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1271        free_irq(pcr->irq, (void *)pcr);
1272        if (pcr->msi_en)
1273                pci_disable_msi(pcr->pci);
1274        iounmap(pcr->remap_addr);
1275
1276        pci_release_regions(pcidev);
1277        pci_disable_device(pcidev);
1278
1279        spin_lock(&rtsx_pci_lock);
1280        idr_remove(&rtsx_pci_idr, pcr->id);
1281        spin_unlock(&rtsx_pci_lock);
1282
1283        kfree(pcr->slots);
1284        kfree(pcr);
1285        kfree(handle);
1286
1287        dev_dbg(&(pcidev->dev),
1288                ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1289                pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1290}
1291
1292#ifdef CONFIG_PM
1293
1294static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
1295{
1296        struct pcr_handle *handle;
1297        struct rtsx_pcr *pcr;
1298
1299        dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1300
1301        handle = pci_get_drvdata(pcidev);
1302        pcr = handle->pcr;
1303
1304        cancel_delayed_work(&pcr->carddet_work);
1305        cancel_delayed_work(&pcr->idle_work);
1306
1307        mutex_lock(&pcr->pcr_mutex);
1308
1309        rtsx_pci_power_off(pcr, HOST_ENTER_S3);
1310
1311        pci_save_state(pcidev);
1312        pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1313        pci_disable_device(pcidev);
1314        pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1315
1316        mutex_unlock(&pcr->pcr_mutex);
1317        return 0;
1318}
1319
1320static int rtsx_pci_resume(struct pci_dev *pcidev)
1321{
1322        struct pcr_handle *handle;
1323        struct rtsx_pcr *pcr;
1324        int ret = 0;
1325
1326        dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1327
1328        handle = pci_get_drvdata(pcidev);
1329        pcr = handle->pcr;
1330
1331        mutex_lock(&pcr->pcr_mutex);
1332
1333        pci_set_power_state(pcidev, PCI_D0);
1334        pci_restore_state(pcidev);
1335        ret = pci_enable_device(pcidev);
1336        if (ret)
1337                goto out;
1338        pci_set_master(pcidev);
1339
1340        ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1341        if (ret)
1342                goto out;
1343
1344        ret = rtsx_pci_init_hw(pcr);
1345        if (ret)
1346                goto out;
1347
1348        schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1349
1350out:
1351        mutex_unlock(&pcr->pcr_mutex);
1352        return ret;
1353}
1354
1355static void rtsx_pci_shutdown(struct pci_dev *pcidev)
1356{
1357        struct pcr_handle *handle;
1358        struct rtsx_pcr *pcr;
1359
1360        dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1361
1362        handle = pci_get_drvdata(pcidev);
1363        pcr = handle->pcr;
1364        rtsx_pci_power_off(pcr, HOST_ENTER_S1);
1365
1366        pci_disable_device(pcidev);
1367}
1368
1369#else /* CONFIG_PM */
1370
1371#define rtsx_pci_suspend NULL
1372#define rtsx_pci_resume NULL
1373#define rtsx_pci_shutdown NULL
1374
1375#endif /* CONFIG_PM */
1376
1377static struct pci_driver rtsx_pci_driver = {
1378        .name = DRV_NAME_RTSX_PCI,
1379        .id_table = rtsx_pci_ids,
1380        .probe = rtsx_pci_probe,
1381        .remove = rtsx_pci_remove,
1382        .suspend = rtsx_pci_suspend,
1383        .resume = rtsx_pci_resume,
1384        .shutdown = rtsx_pci_shutdown,
1385};
1386module_pci_driver(rtsx_pci_driver);
1387
1388MODULE_LICENSE("GPL");
1389MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1390MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");
1391
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