linux/drivers/media/i2c/s5k5baf.c
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   1/*
   2 * Driver for Samsung S5K5BAF UXGA 1/5" 2M CMOS Image Sensor
   3 * with embedded SoC ISP.
   4 *
   5 * Copyright (C) 2013, Samsung Electronics Co., Ltd.
   6 * Andrzej Hajda <a.hajda@samsung.com>
   7 *
   8 * Based on S5K6AA driver authored by Sylwester Nawrocki
   9 * Copyright (C) 2013, Samsung Electronics Co., Ltd.
  10 *
  11 * This program is free software; you can redistribute it and/or modify
  12 * it under the terms of the GNU General Public License version 2 as
  13 * published by the Free Software Foundation.
  14 */
  15
  16#include <linux/clk.h>
  17#include <linux/delay.h>
  18#include <linux/firmware.h>
  19#include <linux/gpio.h>
  20#include <linux/i2c.h>
  21#include <linux/media.h>
  22#include <linux/module.h>
  23#include <linux/of_gpio.h>
  24#include <linux/of_graph.h>
  25#include <linux/regulator/consumer.h>
  26#include <linux/slab.h>
  27
  28#include <media/media-entity.h>
  29#include <media/v4l2-ctrls.h>
  30#include <media/v4l2-device.h>
  31#include <media/v4l2-subdev.h>
  32#include <media/v4l2-mediabus.h>
  33#include <media/v4l2-of.h>
  34
  35static int debug;
  36module_param(debug, int, 0644);
  37
  38#define S5K5BAF_DRIVER_NAME             "s5k5baf"
  39#define S5K5BAF_DEFAULT_MCLK_FREQ       24000000U
  40#define S5K5BAF_CLK_NAME                "mclk"
  41
  42#define S5K5BAF_FW_FILENAME             "s5k5baf-cfg.bin"
  43#define S5K5BAF_FW_TAG                  "SF00"
  44#define S5K5BAG_FW_TAG_LEN              2
  45#define S5K5BAG_FW_MAX_COUNT            16
  46
  47#define S5K5BAF_CIS_WIDTH               1600
  48#define S5K5BAF_CIS_HEIGHT              1200
  49#define S5K5BAF_WIN_WIDTH_MIN           8
  50#define S5K5BAF_WIN_HEIGHT_MIN          8
  51#define S5K5BAF_GAIN_RED_DEF            127
  52#define S5K5BAF_GAIN_GREEN_DEF          95
  53#define S5K5BAF_GAIN_BLUE_DEF           180
  54/* Default number of MIPI CSI-2 data lanes used */
  55#define S5K5BAF_DEF_NUM_LANES           1
  56
  57#define AHB_MSB_ADDR_PTR                0xfcfc
  58
  59/*
  60 * Register interface pages (the most significant word of the address)
  61 */
  62#define PAGE_IF_HW                      0xd000
  63#define PAGE_IF_SW                      0x7000
  64
  65/*
  66 * H/W register Interface (PAGE_IF_HW)
  67 */
  68#define REG_SW_LOAD_COMPLETE            0x0014
  69#define REG_CMDWR_PAGE                  0x0028
  70#define REG_CMDWR_ADDR                  0x002a
  71#define REG_CMDRD_PAGE                  0x002c
  72#define REG_CMDRD_ADDR                  0x002e
  73#define REG_CMD_BUF                     0x0f12
  74#define REG_SET_HOST_INT                0x1000
  75#define REG_CLEAR_HOST_INT              0x1030
  76#define REG_PATTERN_SET                 0x3100
  77#define REG_PATTERN_WIDTH               0x3118
  78#define REG_PATTERN_HEIGHT              0x311a
  79#define REG_PATTERN_PARAM               0x311c
  80
  81/*
  82 * S/W register interface (PAGE_IF_SW)
  83 */
  84
  85/* Firmware revision information */
  86#define REG_FW_APIVER                   0x012e
  87#define  S5K5BAF_FW_APIVER              0x0001
  88#define REG_FW_REVISION                 0x0130
  89#define REG_FW_SENSOR_ID                0x0152
  90
  91/* Initialization parameters */
  92/* Master clock frequency in KHz */
  93#define REG_I_INCLK_FREQ_L              0x01b8
  94#define REG_I_INCLK_FREQ_H              0x01ba
  95#define  MIN_MCLK_FREQ_KHZ              6000U
  96#define  MAX_MCLK_FREQ_KHZ              48000U
  97#define REG_I_USE_NPVI_CLOCKS           0x01c6
  98#define  NPVI_CLOCKS                    1
  99#define REG_I_USE_NMIPI_CLOCKS          0x01c8
 100#define  NMIPI_CLOCKS                   1
 101#define REG_I_BLOCK_INTERNAL_PLL_CALC   0x01ca
 102
 103/* Clock configurations, n = 0..2. REG_I_* frequency unit is 4 kHz. */
 104#define REG_I_OPCLK_4KHZ(n)             ((n) * 6 + 0x01cc)
 105#define REG_I_MIN_OUTRATE_4KHZ(n)       ((n) * 6 + 0x01ce)
 106#define REG_I_MAX_OUTRATE_4KHZ(n)       ((n) * 6 + 0x01d0)
 107#define  SCLK_PVI_FREQ                  24000
 108#define  SCLK_MIPI_FREQ                 48000
 109#define  PCLK_MIN_FREQ                  6000
 110#define  PCLK_MAX_FREQ                  48000
 111#define REG_I_USE_REGS_API              0x01de
 112#define REG_I_INIT_PARAMS_UPDATED       0x01e0
 113#define REG_I_ERROR_INFO                0x01e2
 114
 115/* General purpose parameters */
 116#define REG_USER_BRIGHTNESS             0x01e4
 117#define REG_USER_CONTRAST               0x01e6
 118#define REG_USER_SATURATION             0x01e8
 119#define REG_USER_SHARPBLUR              0x01ea
 120
 121#define REG_G_SPEC_EFFECTS              0x01ee
 122#define REG_G_ENABLE_PREV               0x01f0
 123#define REG_G_ENABLE_PREV_CHG           0x01f2
 124#define REG_G_NEW_CFG_SYNC              0x01f8
 125#define REG_G_PREVREQ_IN_WIDTH          0x01fa
 126#define REG_G_PREVREQ_IN_HEIGHT         0x01fc
 127#define REG_G_PREVREQ_IN_XOFFS          0x01fe
 128#define REG_G_PREVREQ_IN_YOFFS          0x0200
 129#define REG_G_PREVZOOM_IN_WIDTH         0x020a
 130#define REG_G_PREVZOOM_IN_HEIGHT        0x020c
 131#define REG_G_PREVZOOM_IN_XOFFS         0x020e
 132#define REG_G_PREVZOOM_IN_YOFFS         0x0210
 133#define REG_G_INPUTS_CHANGE_REQ         0x021a
 134#define REG_G_ACTIVE_PREV_CFG           0x021c
 135#define REG_G_PREV_CFG_CHG              0x021e
 136#define REG_G_PREV_OPEN_AFTER_CH        0x0220
 137#define REG_G_PREV_CFG_ERROR            0x0222
 138#define  CFG_ERROR_RANGE                0x0b
 139#define REG_G_PREV_CFG_BYPASS_CHANGED   0x022a
 140#define REG_G_ACTUAL_P_FR_TIME          0x023a
 141#define REG_G_ACTUAL_P_OUT_RATE         0x023c
 142#define REG_G_ACTUAL_C_FR_TIME          0x023e
 143#define REG_G_ACTUAL_C_OUT_RATE         0x0240
 144
 145/* Preview control section. n = 0...4. */
 146#define PREG(n, x)                      ((n) * 0x26 + x)
 147#define REG_P_OUT_WIDTH(n)              PREG(n, 0x0242)
 148#define REG_P_OUT_HEIGHT(n)             PREG(n, 0x0244)
 149#define REG_P_FMT(n)                    PREG(n, 0x0246)
 150#define REG_P_MAX_OUT_RATE(n)           PREG(n, 0x0248)
 151#define REG_P_MIN_OUT_RATE(n)           PREG(n, 0x024a)
 152#define REG_P_PVI_MASK(n)               PREG(n, 0x024c)
 153#define  PVI_MASK_MIPI                  0x52
 154#define REG_P_CLK_INDEX(n)              PREG(n, 0x024e)
 155#define  CLK_PVI_INDEX                  0
 156#define  CLK_MIPI_INDEX                 NPVI_CLOCKS
 157#define REG_P_FR_RATE_TYPE(n)           PREG(n, 0x0250)
 158#define  FR_RATE_DYNAMIC                0
 159#define  FR_RATE_FIXED                  1
 160#define  FR_RATE_FIXED_ACCURATE         2
 161#define REG_P_FR_RATE_Q_TYPE(n)         PREG(n, 0x0252)
 162#define  FR_RATE_Q_DYNAMIC              0
 163#define  FR_RATE_Q_BEST_FRRATE          1 /* Binning enabled */
 164#define  FR_RATE_Q_BEST_QUALITY         2 /* Binning disabled */
 165/* Frame period in 0.1 ms units */
 166#define REG_P_MAX_FR_TIME(n)            PREG(n, 0x0254)
 167#define REG_P_MIN_FR_TIME(n)            PREG(n, 0x0256)
 168#define  S5K5BAF_MIN_FR_TIME            333  /* x100 us */
 169#define  S5K5BAF_MAX_FR_TIME            6500 /* x100 us */
 170/* The below 5 registers are for "device correction" values */
 171#define REG_P_SATURATION(n)             PREG(n, 0x0258)
 172#define REG_P_SHARP_BLUR(n)             PREG(n, 0x025a)
 173#define REG_P_GLAMOUR(n)                PREG(n, 0x025c)
 174#define REG_P_COLORTEMP(n)              PREG(n, 0x025e)
 175#define REG_P_GAMMA_INDEX(n)            PREG(n, 0x0260)
 176#define REG_P_PREV_MIRROR(n)            PREG(n, 0x0262)
 177#define REG_P_CAP_MIRROR(n)             PREG(n, 0x0264)
 178#define REG_P_CAP_ROTATION(n)           PREG(n, 0x0266)
 179
 180/* Extended image property controls */
 181/* Exposure time in 10 us units */
 182#define REG_SF_USR_EXPOSURE_L           0x03bc
 183#define REG_SF_USR_EXPOSURE_H           0x03be
 184#define REG_SF_USR_EXPOSURE_CHG         0x03c0
 185#define REG_SF_USR_TOT_GAIN             0x03c2
 186#define REG_SF_USR_TOT_GAIN_CHG         0x03c4
 187#define REG_SF_RGAIN                    0x03c6
 188#define REG_SF_RGAIN_CHG                0x03c8
 189#define REG_SF_GGAIN                    0x03ca
 190#define REG_SF_GGAIN_CHG                0x03cc
 191#define REG_SF_BGAIN                    0x03ce
 192#define REG_SF_BGAIN_CHG                0x03d0
 193#define REG_SF_WBGAIN_CHG               0x03d2
 194#define REG_SF_FLICKER_QUANT            0x03d4
 195#define REG_SF_FLICKER_QUANT_CHG        0x03d6
 196
 197/* Output interface (parallel/MIPI) setup */
 198#define REG_OIF_EN_MIPI_LANES           0x03f2
 199#define REG_OIF_EN_PACKETS              0x03f4
 200#define  EN_PACKETS_CSI2                0xc3
 201#define REG_OIF_CFG_CHG                 0x03f6
 202
 203/* Auto-algorithms enable mask */
 204#define REG_DBG_AUTOALG_EN              0x03f8
 205#define  AALG_ALL_EN                    BIT(0)
 206#define  AALG_AE_EN                     BIT(1)
 207#define  AALG_DIVLEI_EN                 BIT(2)
 208#define  AALG_WB_EN                     BIT(3)
 209#define  AALG_USE_WB_FOR_ISP            BIT(4)
 210#define  AALG_FLICKER_EN                BIT(5)
 211#define  AALG_FIT_EN                    BIT(6)
 212#define  AALG_WRHW_EN                   BIT(7)
 213
 214/* Pointers to color correction matrices */
 215#define REG_PTR_CCM_HORIZON             0x06d0
 216#define REG_PTR_CCM_INCANDESCENT        0x06d4
 217#define REG_PTR_CCM_WARM_WHITE          0x06d8
 218#define REG_PTR_CCM_COOL_WHITE          0x06dc
 219#define REG_PTR_CCM_DL50                0x06e0
 220#define REG_PTR_CCM_DL65                0x06e4
 221#define REG_PTR_CCM_OUTDOOR             0x06ec
 222
 223#define REG_ARR_CCM(n)                  (0x2800 + 36 * (n))
 224
 225static const char * const s5k5baf_supply_names[] = {
 226        "vdda",         /* Analog power supply 2.8V (2.6V to 3.0V) */
 227        "vddreg",       /* Regulator input power supply 1.8V (1.7V to 1.9V)
 228                           or 2.8V (2.6V to 3.0) */
 229        "vddio",        /* I/O power supply 1.8V (1.65V to 1.95V)
 230                           or 2.8V (2.5V to 3.1V) */
 231};
 232#define S5K5BAF_NUM_SUPPLIES ARRAY_SIZE(s5k5baf_supply_names)
 233
 234struct s5k5baf_gpio {
 235        int gpio;
 236        int level;
 237};
 238
 239enum s5k5baf_gpio_id {
 240        STBY,
 241        RST,
 242        NUM_GPIOS,
 243};
 244
 245#define PAD_CIS 0
 246#define PAD_OUT 1
 247#define NUM_CIS_PADS 1
 248#define NUM_ISP_PADS 2
 249
 250struct s5k5baf_pixfmt {
 251        enum v4l2_mbus_pixelcode code;
 252        u32 colorspace;
 253        /* REG_P_FMT(x) register value */
 254        u16 reg_p_fmt;
 255};
 256
 257struct s5k5baf_ctrls {
 258        struct v4l2_ctrl_handler handler;
 259        struct { /* Auto / manual white balance cluster */
 260                struct v4l2_ctrl *awb;
 261                struct v4l2_ctrl *gain_red;
 262                struct v4l2_ctrl *gain_blue;
 263        };
 264        struct { /* Mirror cluster */
 265                struct v4l2_ctrl *hflip;
 266                struct v4l2_ctrl *vflip;
 267        };
 268        struct { /* Auto exposure / manual exposure and gain cluster */
 269                struct v4l2_ctrl *auto_exp;
 270                struct v4l2_ctrl *exposure;
 271                struct v4l2_ctrl *gain;
 272        };
 273};
 274
 275enum {
 276        S5K5BAF_FW_ID_PATCH,
 277        S5K5BAF_FW_ID_CCM,
 278        S5K5BAF_FW_ID_CIS,
 279};
 280
 281struct s5k5baf_fw {
 282        u16 count;
 283        struct {
 284                u16 id;
 285                u16 offset;
 286        } seq[0];
 287        u16 data[0];
 288};
 289
 290struct s5k5baf {
 291        struct s5k5baf_gpio gpios[NUM_GPIOS];
 292        enum v4l2_mbus_type bus_type;
 293        u8 nlanes;
 294        struct regulator_bulk_data supplies[S5K5BAF_NUM_SUPPLIES];
 295
 296        struct clk *clock;
 297        u32 mclk_frequency;
 298
 299        struct s5k5baf_fw *fw;
 300
 301        struct v4l2_subdev cis_sd;
 302        struct media_pad cis_pad;
 303
 304        struct v4l2_subdev sd;
 305        struct media_pad pads[NUM_ISP_PADS];
 306
 307        /* protects the struct members below */
 308        struct mutex lock;
 309
 310        int error;
 311
 312        struct v4l2_rect crop_sink;
 313        struct v4l2_rect compose;
 314        struct v4l2_rect crop_source;
 315        /* index to s5k5baf_formats array */
 316        int pixfmt;
 317        /* actual frame interval in 100us */
 318        u16 fiv;
 319        /* requested frame interval in 100us */
 320        u16 req_fiv;
 321        /* cache for REG_DBG_AUTOALG_EN register */
 322        u16 auto_alg;
 323
 324        struct s5k5baf_ctrls ctrls;
 325
 326        unsigned int streaming:1;
 327        unsigned int apply_cfg:1;
 328        unsigned int apply_crop:1;
 329        unsigned int valid_auto_alg:1;
 330        unsigned int power;
 331};
 332
 333static const struct s5k5baf_pixfmt s5k5baf_formats[] = {
 334        { V4L2_MBUS_FMT_VYUY8_2X8,      V4L2_COLORSPACE_JPEG,   5 },
 335        /* range 16-240 */
 336        { V4L2_MBUS_FMT_VYUY8_2X8,      V4L2_COLORSPACE_REC709, 6 },
 337        { V4L2_MBUS_FMT_RGB565_2X8_BE,  V4L2_COLORSPACE_JPEG,   0 },
 338};
 339
 340static struct v4l2_rect s5k5baf_cis_rect = {
 341        0, 0, S5K5BAF_CIS_WIDTH, S5K5BAF_CIS_HEIGHT
 342};
 343
 344/* Setfile contains set of I2C command sequences. Each sequence has its ID.
 345 * setfile format:
 346 *      u8 magic[4];
 347 *      u16 count;              number of sequences
 348 *      struct {
 349 *              u16 id;         sequence id
 350 *              u16 offset;     sequence offset in data array
 351 *      } seq[count];
 352 *      u16 data[*];            array containing sequences
 353 *
 354 */
 355static int s5k5baf_fw_parse(struct device *dev, struct s5k5baf_fw **fw,
 356                            size_t count, const u16 *data)
 357{
 358        struct s5k5baf_fw *f;
 359        u16 *d, i, *end;
 360        int ret;
 361
 362        if (count < S5K5BAG_FW_TAG_LEN + 1) {
 363                dev_err(dev, "firmware file too short (%zu)\n", count);
 364                return -EINVAL;
 365        }
 366
 367        ret = memcmp(data, S5K5BAF_FW_TAG, S5K5BAG_FW_TAG_LEN * sizeof(u16));
 368        if (ret != 0) {
 369                dev_err(dev, "invalid firmware magic number\n");
 370                return -EINVAL;
 371        }
 372
 373        data += S5K5BAG_FW_TAG_LEN;
 374        count -= S5K5BAG_FW_TAG_LEN;
 375
 376        d = devm_kzalloc(dev, count * sizeof(u16), GFP_KERNEL);
 377
 378        for (i = 0; i < count; ++i)
 379                d[i] = le16_to_cpu(data[i]);
 380
 381        f = (struct s5k5baf_fw *)d;
 382        if (count < 1 + 2 * f->count) {
 383                dev_err(dev, "invalid firmware header (count=%d size=%zu)\n",
 384                        f->count, 2 * (count + S5K5BAG_FW_TAG_LEN));
 385                return -EINVAL;
 386        }
 387        end = d + count;
 388        d += 1 + 2 * f->count;
 389
 390        for (i = 0; i < f->count; ++i) {
 391                if (f->seq[i].offset + d <= end)
 392                        continue;
 393                dev_err(dev, "invalid firmware header (seq=%d)\n", i);
 394                return -EINVAL;
 395        }
 396
 397        *fw = f;
 398
 399        return 0;
 400}
 401
 402static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
 403{
 404        return &container_of(ctrl->handler, struct s5k5baf, ctrls.handler)->sd;
 405}
 406
 407static inline bool s5k5baf_is_cis_subdev(struct v4l2_subdev *sd)
 408{
 409        return sd->entity.type == MEDIA_ENT_T_V4L2_SUBDEV_SENSOR;
 410}
 411
 412static inline struct s5k5baf *to_s5k5baf(struct v4l2_subdev *sd)
 413{
 414        if (s5k5baf_is_cis_subdev(sd))
 415                return container_of(sd, struct s5k5baf, cis_sd);
 416        else
 417                return container_of(sd, struct s5k5baf, sd);
 418}
 419
 420static u16 s5k5baf_i2c_read(struct s5k5baf *state, u16 addr)
 421{
 422        struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
 423        __be16 w, r;
 424        struct i2c_msg msg[] = {
 425                { .addr = c->addr, .flags = 0,
 426                  .len = 2, .buf = (u8 *)&w },
 427                { .addr = c->addr, .flags = I2C_M_RD,
 428                  .len = 2, .buf = (u8 *)&r },
 429        };
 430        int ret;
 431
 432        if (state->error)
 433                return 0;
 434
 435        w = cpu_to_be16(addr);
 436        ret = i2c_transfer(c->adapter, msg, 2);
 437        r = be16_to_cpu(r);
 438
 439        v4l2_dbg(3, debug, c, "i2c_read: 0x%04x : 0x%04x\n", addr, r);
 440
 441        if (ret != 2) {
 442                v4l2_err(c, "i2c_read: error during transfer (%d)\n", ret);
 443                state->error = ret;
 444        }
 445        return r;
 446}
 447
 448static void s5k5baf_i2c_write(struct s5k5baf *state, u16 addr, u16 val)
 449{
 450        u8 buf[4] = { addr >> 8, addr & 0xFF, val >> 8, val & 0xFF };
 451        struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
 452        int ret;
 453
 454        if (state->error)
 455                return;
 456
 457        ret = i2c_master_send(c, buf, 4);
 458        v4l2_dbg(3, debug, c, "i2c_write: 0x%04x : 0x%04x\n", addr, val);
 459
 460        if (ret != 4) {
 461                v4l2_err(c, "i2c_write: error during transfer (%d)\n", ret);
 462                state->error = ret;
 463        }
 464}
 465
 466static u16 s5k5baf_read(struct s5k5baf *state, u16 addr)
 467{
 468        s5k5baf_i2c_write(state, REG_CMDRD_ADDR, addr);
 469        return s5k5baf_i2c_read(state, REG_CMD_BUF);
 470}
 471
 472static void s5k5baf_write(struct s5k5baf *state, u16 addr, u16 val)
 473{
 474        s5k5baf_i2c_write(state, REG_CMDWR_ADDR, addr);
 475        s5k5baf_i2c_write(state, REG_CMD_BUF, val);
 476}
 477
 478static void s5k5baf_write_arr_seq(struct s5k5baf *state, u16 addr,
 479                                  u16 count, const u16 *seq)
 480{
 481        struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
 482        __be16 buf[65];
 483
 484        s5k5baf_i2c_write(state, REG_CMDWR_ADDR, addr);
 485        if (state->error)
 486                return;
 487
 488        v4l2_dbg(3, debug, c, "i2c_write_seq(count=%d): %*ph\n", count,
 489                 min(2 * count, 64), seq);
 490
 491        buf[0] = __constant_cpu_to_be16(REG_CMD_BUF);
 492
 493        while (count > 0) {
 494                int n = min_t(int, count, ARRAY_SIZE(buf) - 1);
 495                int ret, i;
 496
 497                for (i = 1; i <= n; ++i)
 498                        buf[i] = cpu_to_be16(*seq++);
 499
 500                i *= 2;
 501                ret = i2c_master_send(c, (char *)buf, i);
 502                if (ret != i) {
 503                        v4l2_err(c, "i2c_write_seq: error during transfer (%d)\n", ret);
 504                        state->error = ret;
 505                        break;
 506                }
 507
 508                count -= n;
 509        }
 510}
 511
 512#define s5k5baf_write_seq(state, addr, seq...) \
 513        s5k5baf_write_arr_seq(state, addr, sizeof((char[]){ seq }), \
 514                              (const u16 []){ seq });
 515
 516/* add items count at the beginning of the list */
 517#define NSEQ(seq...) sizeof((char[]){ seq }), seq
 518
 519/*
 520 * s5k5baf_write_nseq() - Writes sequences of values to sensor memory via i2c
 521 * @nseq: sequence of u16 words in format:
 522 *      (N, address, value[1]...value[N-1])*,0
 523 * Ex.:
 524 *      u16 seq[] = { NSEQ(0x4000, 1, 1), NSEQ(0x4010, 640, 480), 0 };
 525 *      ret = s5k5baf_write_nseq(c, seq);
 526 */
 527static void s5k5baf_write_nseq(struct s5k5baf *state, const u16 *nseq)
 528{
 529        int count;
 530
 531        while ((count = *nseq++)) {
 532                u16 addr = *nseq++;
 533                --count;
 534
 535                s5k5baf_write_arr_seq(state, addr, count, nseq);
 536                nseq += count;
 537        }
 538}
 539
 540static void s5k5baf_synchronize(struct s5k5baf *state, int timeout, u16 addr)
 541{
 542        unsigned long end = jiffies + msecs_to_jiffies(timeout);
 543        u16 reg;
 544
 545        s5k5baf_write(state, addr, 1);
 546        do {
 547                reg = s5k5baf_read(state, addr);
 548                if (state->error || !reg)
 549                        return;
 550                usleep_range(5000, 10000);
 551        } while (time_is_after_jiffies(end));
 552
 553        v4l2_err(&state->sd, "timeout on register synchronize (%#x)\n", addr);
 554        state->error = -ETIMEDOUT;
 555}
 556
 557static u16 *s5k5baf_fw_get_seq(struct s5k5baf *state, u16 seq_id)
 558{
 559        struct s5k5baf_fw *fw = state->fw;
 560        u16 *data;
 561        int i;
 562
 563        if (fw == NULL)
 564                return NULL;
 565
 566        data = fw->data + 2 * fw->count;
 567
 568        for (i = 0; i < fw->count; ++i) {
 569                if (fw->seq[i].id == seq_id)
 570                        return data + fw->seq[i].offset;
 571        }
 572
 573        return NULL;
 574}
 575
 576static void s5k5baf_hw_patch(struct s5k5baf *state)
 577{
 578        u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_PATCH);
 579
 580        if (seq)
 581                s5k5baf_write_nseq(state, seq);
 582}
 583
 584static void s5k5baf_hw_set_clocks(struct s5k5baf *state)
 585{
 586        unsigned long mclk = state->mclk_frequency / 1000;
 587        u16 status;
 588        static const u16 nseq_clk_cfg[] = {
 589                NSEQ(REG_I_USE_NPVI_CLOCKS,
 590                  NPVI_CLOCKS, NMIPI_CLOCKS, 0,
 591                  SCLK_PVI_FREQ / 4, PCLK_MIN_FREQ / 4, PCLK_MAX_FREQ / 4,
 592                  SCLK_MIPI_FREQ / 4, PCLK_MIN_FREQ / 4, PCLK_MAX_FREQ / 4),
 593                NSEQ(REG_I_USE_REGS_API, 1),
 594                0
 595        };
 596
 597        s5k5baf_write_seq(state, REG_I_INCLK_FREQ_L, mclk & 0xffff, mclk >> 16);
 598        s5k5baf_write_nseq(state, nseq_clk_cfg);
 599
 600        s5k5baf_synchronize(state, 250, REG_I_INIT_PARAMS_UPDATED);
 601        status = s5k5baf_read(state, REG_I_ERROR_INFO);
 602        if (!state->error && status) {
 603                v4l2_err(&state->sd, "error configuring PLL (%d)\n", status);
 604                state->error = -EINVAL;
 605        }
 606}
 607
 608/* set custom color correction matrices for various illuminations */
 609static void s5k5baf_hw_set_ccm(struct s5k5baf *state)
 610{
 611        u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_CCM);
 612
 613        if (seq)
 614                s5k5baf_write_nseq(state, seq);
 615}
 616
 617/* CIS sensor tuning, based on undocumented android driver code */
 618static void s5k5baf_hw_set_cis(struct s5k5baf *state)
 619{
 620        u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_CIS);
 621
 622        if (!seq)
 623                return;
 624
 625        s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_HW);
 626        s5k5baf_write_nseq(state, seq);
 627        s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_SW);
 628}
 629
 630static void s5k5baf_hw_sync_cfg(struct s5k5baf *state)
 631{
 632        s5k5baf_write(state, REG_G_PREV_CFG_CHG, 1);
 633        if (state->apply_crop) {
 634                s5k5baf_write(state, REG_G_INPUTS_CHANGE_REQ, 1);
 635                s5k5baf_write(state, REG_G_PREV_CFG_BYPASS_CHANGED, 1);
 636        }
 637        s5k5baf_synchronize(state, 500, REG_G_NEW_CFG_SYNC);
 638}
 639/* Set horizontal and vertical image flipping */
 640static void s5k5baf_hw_set_mirror(struct s5k5baf *state)
 641{
 642        u16 flip = state->ctrls.vflip->val | (state->ctrls.vflip->val << 1);
 643
 644        s5k5baf_write(state, REG_P_PREV_MIRROR(0), flip);
 645        if (state->streaming)
 646                s5k5baf_hw_sync_cfg(state);
 647}
 648
 649static void s5k5baf_hw_set_alg(struct s5k5baf *state, u16 alg, bool enable)
 650{
 651        u16 cur_alg, new_alg;
 652
 653        if (!state->valid_auto_alg)
 654                cur_alg = s5k5baf_read(state, REG_DBG_AUTOALG_EN);
 655        else
 656                cur_alg = state->auto_alg;
 657
 658        new_alg = enable ? (cur_alg | alg) : (cur_alg & ~alg);
 659
 660        if (new_alg != cur_alg)
 661                s5k5baf_write(state, REG_DBG_AUTOALG_EN, new_alg);
 662
 663        if (state->error)
 664                return;
 665
 666        state->valid_auto_alg = 1;
 667        state->auto_alg = new_alg;
 668}
 669
 670/* Configure auto/manual white balance and R/G/B gains */
 671static void s5k5baf_hw_set_awb(struct s5k5baf *state, int awb)
 672{
 673        struct s5k5baf_ctrls *ctrls = &state->ctrls;
 674
 675        if (!awb)
 676                s5k5baf_write_seq(state, REG_SF_RGAIN,
 677                                  ctrls->gain_red->val, 1,
 678                                  S5K5BAF_GAIN_GREEN_DEF, 1,
 679                                  ctrls->gain_blue->val, 1,
 680                                  1);
 681
 682        s5k5baf_hw_set_alg(state, AALG_WB_EN, awb);
 683}
 684
 685/* Program FW with exposure time, 'exposure' in us units */
 686static void s5k5baf_hw_set_user_exposure(struct s5k5baf *state, int exposure)
 687{
 688        unsigned int time = exposure / 10;
 689
 690        s5k5baf_write_seq(state, REG_SF_USR_EXPOSURE_L,
 691                          time & 0xffff, time >> 16, 1);
 692}
 693
 694static void s5k5baf_hw_set_user_gain(struct s5k5baf *state, int gain)
 695{
 696        s5k5baf_write_seq(state, REG_SF_USR_TOT_GAIN, gain, 1);
 697}
 698
 699/* Set auto/manual exposure and total gain */
 700static void s5k5baf_hw_set_auto_exposure(struct s5k5baf *state, int value)
 701{
 702        if (value == V4L2_EXPOSURE_AUTO) {
 703                s5k5baf_hw_set_alg(state, AALG_AE_EN | AALG_DIVLEI_EN, true);
 704        } else {
 705                unsigned int exp_time = state->ctrls.exposure->val;
 706
 707                s5k5baf_hw_set_user_exposure(state, exp_time);
 708                s5k5baf_hw_set_user_gain(state, state->ctrls.gain->val);
 709                s5k5baf_hw_set_alg(state, AALG_AE_EN | AALG_DIVLEI_EN, false);
 710        }
 711}
 712
 713static void s5k5baf_hw_set_anti_flicker(struct s5k5baf *state, int v)
 714{
 715        if (v == V4L2_CID_POWER_LINE_FREQUENCY_AUTO) {
 716                s5k5baf_hw_set_alg(state, AALG_FLICKER_EN, true);
 717        } else {
 718                /* The V4L2_CID_LINE_FREQUENCY control values match
 719                 * the register values */
 720                s5k5baf_write_seq(state, REG_SF_FLICKER_QUANT, v, 1);
 721                s5k5baf_hw_set_alg(state, AALG_FLICKER_EN, false);
 722        }
 723}
 724
 725static void s5k5baf_hw_set_colorfx(struct s5k5baf *state, int val)
 726{
 727        static const u16 colorfx[] = {
 728                [V4L2_COLORFX_NONE] = 0,
 729                [V4L2_COLORFX_BW] = 1,
 730                [V4L2_COLORFX_NEGATIVE] = 2,
 731                [V4L2_COLORFX_SEPIA] = 3,
 732                [V4L2_COLORFX_SKY_BLUE] = 4,
 733                [V4L2_COLORFX_SKETCH] = 5,
 734        };
 735
 736        s5k5baf_write(state, REG_G_SPEC_EFFECTS, colorfx[val]);
 737}
 738
 739static int s5k5baf_find_pixfmt(struct v4l2_mbus_framefmt *mf)
 740{
 741        int i, c = -1;
 742
 743        for (i = 0; i < ARRAY_SIZE(s5k5baf_formats); i++) {
 744                if (mf->colorspace != s5k5baf_formats[i].colorspace)
 745                        continue;
 746                if (mf->code == s5k5baf_formats[i].code)
 747                        return i;
 748                if (c < 0)
 749                        c = i;
 750        }
 751        return (c < 0) ? 0 : c;
 752}
 753
 754static int s5k5baf_clear_error(struct s5k5baf *state)
 755{
 756        int ret = state->error;
 757
 758        state->error = 0;
 759        return ret;
 760}
 761
 762static int s5k5baf_hw_set_video_bus(struct s5k5baf *state)
 763{
 764        u16 en_pkts;
 765
 766        if (state->bus_type == V4L2_MBUS_CSI2)
 767                en_pkts = EN_PACKETS_CSI2;
 768        else
 769                en_pkts = 0;
 770
 771        s5k5baf_write_seq(state, REG_OIF_EN_MIPI_LANES,
 772                          state->nlanes, en_pkts, 1);
 773
 774        return s5k5baf_clear_error(state);
 775}
 776
 777static u16 s5k5baf_get_cfg_error(struct s5k5baf *state)
 778{
 779        u16 err = s5k5baf_read(state, REG_G_PREV_CFG_ERROR);
 780        if (err)
 781                s5k5baf_write(state, REG_G_PREV_CFG_ERROR, 0);
 782        return err;
 783}
 784
 785static void s5k5baf_hw_set_fiv(struct s5k5baf *state, u16 fiv)
 786{
 787        s5k5baf_write(state, REG_P_MAX_FR_TIME(0), fiv);
 788        s5k5baf_hw_sync_cfg(state);
 789}
 790
 791static void s5k5baf_hw_find_min_fiv(struct s5k5baf *state)
 792{
 793        u16 err, fiv;
 794        int n;
 795
 796        fiv = s5k5baf_read(state,  REG_G_ACTUAL_P_FR_TIME);
 797        if (state->error)
 798                return;
 799
 800        for (n = 5; n > 0; --n) {
 801                s5k5baf_hw_set_fiv(state, fiv);
 802                err = s5k5baf_get_cfg_error(state);
 803                if (state->error)
 804                        return;
 805                switch (err) {
 806                case CFG_ERROR_RANGE:
 807                        ++fiv;
 808                        break;
 809                case 0:
 810                        state->fiv = fiv;
 811                        v4l2_info(&state->sd,
 812                                  "found valid frame interval: %d00us\n", fiv);
 813                        return;
 814                default:
 815                        v4l2_err(&state->sd,
 816                                 "error setting frame interval: %d\n", err);
 817                        state->error = -EINVAL;
 818                }
 819        };
 820        v4l2_err(&state->sd, "cannot find correct frame interval\n");
 821        state->error = -ERANGE;
 822}
 823
 824static void s5k5baf_hw_validate_cfg(struct s5k5baf *state)
 825{
 826        u16 err;
 827
 828        err = s5k5baf_get_cfg_error(state);
 829        if (state->error)
 830                return;
 831
 832        switch (err) {
 833        case 0:
 834                state->apply_cfg = 1;
 835                return;
 836        case CFG_ERROR_RANGE:
 837                s5k5baf_hw_find_min_fiv(state);
 838                if (!state->error)
 839                        state->apply_cfg = 1;
 840                return;
 841        default:
 842                v4l2_err(&state->sd,
 843                         "error setting format: %d\n", err);
 844                state->error = -EINVAL;
 845        }
 846}
 847
 848static void s5k5baf_rescale(struct v4l2_rect *r, const struct v4l2_rect *v,
 849                            const struct v4l2_rect *n,
 850                            const struct v4l2_rect *d)
 851{
 852        r->left = v->left * n->width / d->width;
 853        r->top = v->top * n->height / d->height;
 854        r->width = v->width * n->width / d->width;
 855        r->height = v->height * n->height / d->height;
 856}
 857
 858static int s5k5baf_hw_set_crop_rects(struct s5k5baf *state)
 859{
 860        struct v4l2_rect *p, r;
 861        u16 err;
 862        int ret;
 863
 864        p = &state->crop_sink;
 865        s5k5baf_write_seq(state, REG_G_PREVREQ_IN_WIDTH, p->width, p->height,
 866                          p->left, p->top);
 867
 868        s5k5baf_rescale(&r, &state->crop_source, &state->crop_sink,
 869                        &state->compose);
 870        s5k5baf_write_seq(state, REG_G_PREVZOOM_IN_WIDTH, r.width, r.height,
 871                          r.left, r.top);
 872
 873        s5k5baf_synchronize(state, 500, REG_G_INPUTS_CHANGE_REQ);
 874        s5k5baf_synchronize(state, 500, REG_G_PREV_CFG_BYPASS_CHANGED);
 875        err = s5k5baf_get_cfg_error(state);
 876        ret = s5k5baf_clear_error(state);
 877        if (ret < 0)
 878                return ret;
 879
 880        switch (err) {
 881        case 0:
 882                break;
 883        case CFG_ERROR_RANGE:
 884                /* retry crop with frame interval set to max */
 885                s5k5baf_hw_set_fiv(state, S5K5BAF_MAX_FR_TIME);
 886                err = s5k5baf_get_cfg_error(state);
 887                ret = s5k5baf_clear_error(state);
 888                if (ret < 0)
 889                        return ret;
 890                if (err) {
 891                        v4l2_err(&state->sd,
 892                                 "crop error on max frame interval: %d\n", err);
 893                        state->error = -EINVAL;
 894                }
 895                s5k5baf_hw_set_fiv(state, state->req_fiv);
 896                s5k5baf_hw_validate_cfg(state);
 897                break;
 898        default:
 899                v4l2_err(&state->sd, "crop error: %d\n", err);
 900                return -EINVAL;
 901        }
 902
 903        if (!state->apply_cfg)
 904                return 0;
 905
 906        p = &state->crop_source;
 907        s5k5baf_write_seq(state, REG_P_OUT_WIDTH(0), p->width, p->height);
 908        s5k5baf_hw_set_fiv(state, state->req_fiv);
 909        s5k5baf_hw_validate_cfg(state);
 910
 911        return s5k5baf_clear_error(state);
 912}
 913
 914static void s5k5baf_hw_set_config(struct s5k5baf *state)
 915{
 916        u16 reg_fmt = s5k5baf_formats[state->pixfmt].reg_p_fmt;
 917        struct v4l2_rect *r = &state->crop_source;
 918
 919        s5k5baf_write_seq(state, REG_P_OUT_WIDTH(0),
 920                          r->width, r->height, reg_fmt,
 921                          PCLK_MAX_FREQ >> 2, PCLK_MIN_FREQ >> 2,
 922                          PVI_MASK_MIPI, CLK_MIPI_INDEX,
 923                          FR_RATE_FIXED, FR_RATE_Q_DYNAMIC,
 924                          state->req_fiv, S5K5BAF_MIN_FR_TIME);
 925        s5k5baf_hw_sync_cfg(state);
 926        s5k5baf_hw_validate_cfg(state);
 927}
 928
 929
 930static void s5k5baf_hw_set_test_pattern(struct s5k5baf *state, int id)
 931{
 932        s5k5baf_i2c_write(state, REG_PATTERN_WIDTH, 800);
 933        s5k5baf_i2c_write(state, REG_PATTERN_HEIGHT, 511);
 934        s5k5baf_i2c_write(state, REG_PATTERN_PARAM, 0);
 935        s5k5baf_i2c_write(state, REG_PATTERN_SET, id);
 936}
 937
 938static void s5k5baf_gpio_assert(struct s5k5baf *state, int id)
 939{
 940        struct s5k5baf_gpio *gpio = &state->gpios[id];
 941
 942        gpio_set_value(gpio->gpio, gpio->level);
 943}
 944
 945static void s5k5baf_gpio_deassert(struct s5k5baf *state, int id)
 946{
 947        struct s5k5baf_gpio *gpio = &state->gpios[id];
 948
 949        gpio_set_value(gpio->gpio, !gpio->level);
 950}
 951
 952static int s5k5baf_power_on(struct s5k5baf *state)
 953{
 954        int ret;
 955
 956        ret = regulator_bulk_enable(S5K5BAF_NUM_SUPPLIES, state->supplies);
 957        if (ret < 0)
 958                goto err;
 959
 960        ret = clk_set_rate(state->clock, state->mclk_frequency);
 961        if (ret < 0)
 962                goto err_reg_dis;
 963
 964        ret = clk_prepare_enable(state->clock);
 965        if (ret < 0)
 966                goto err_reg_dis;
 967
 968        v4l2_dbg(1, debug, &state->sd, "clock frequency: %ld\n",
 969                 clk_get_rate(state->clock));
 970
 971        s5k5baf_gpio_deassert(state, STBY);
 972        usleep_range(50, 100);
 973        s5k5baf_gpio_deassert(state, RST);
 974        return 0;
 975
 976err_reg_dis:
 977        regulator_bulk_disable(S5K5BAF_NUM_SUPPLIES, state->supplies);
 978err:
 979        v4l2_err(&state->sd, "%s() failed (%d)\n", __func__, ret);
 980        return ret;
 981}
 982
 983static int s5k5baf_power_off(struct s5k5baf *state)
 984{
 985        int ret;
 986
 987        state->streaming = 0;
 988        state->apply_cfg = 0;
 989        state->apply_crop = 0;
 990
 991        s5k5baf_gpio_assert(state, RST);
 992        s5k5baf_gpio_assert(state, STBY);
 993
 994        if (!IS_ERR(state->clock))
 995                clk_disable_unprepare(state->clock);
 996
 997        ret = regulator_bulk_disable(S5K5BAF_NUM_SUPPLIES,
 998                                        state->supplies);
 999        if (ret < 0)
1000                v4l2_err(&state->sd, "failed to disable regulators\n");
1001
1002        return 0;
1003}
1004
1005static void s5k5baf_hw_init(struct s5k5baf *state)
1006{
1007        s5k5baf_i2c_write(state, AHB_MSB_ADDR_PTR, PAGE_IF_HW);
1008        s5k5baf_i2c_write(state, REG_CLEAR_HOST_INT, 0);
1009        s5k5baf_i2c_write(state, REG_SW_LOAD_COMPLETE, 1);
1010        s5k5baf_i2c_write(state, REG_CMDRD_PAGE, PAGE_IF_SW);
1011        s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_SW);
1012}
1013
1014/*
1015 * V4L2 subdev core and video operations
1016 */
1017
1018static void s5k5baf_initialize_data(struct s5k5baf *state)
1019{
1020        state->pixfmt = 0;
1021        state->req_fiv = 10000 / 15;
1022        state->fiv = state->req_fiv;
1023        state->valid_auto_alg = 0;
1024}
1025
1026static int s5k5baf_load_setfile(struct s5k5baf *state)
1027{
1028        struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
1029        const struct firmware *fw;
1030        int ret;
1031
1032        ret = request_firmware(&fw, S5K5BAF_FW_FILENAME, &c->dev);
1033        if (ret < 0) {
1034                dev_warn(&c->dev, "firmware file (%s) not loaded\n",
1035                         S5K5BAF_FW_FILENAME);
1036                return ret;
1037        }
1038
1039        ret = s5k5baf_fw_parse(&c->dev, &state->fw, fw->size / 2,
1040                               (u16 *)fw->data);
1041
1042        release_firmware(fw);
1043
1044        return ret;
1045}
1046
1047static int s5k5baf_set_power(struct v4l2_subdev *sd, int on)
1048{
1049        struct s5k5baf *state = to_s5k5baf(sd);
1050        int ret = 0;
1051
1052        mutex_lock(&state->lock);
1053
1054        if (!on != state->power)
1055                goto out;
1056
1057        if (on) {
1058                if (state->fw == NULL)
1059                        s5k5baf_load_setfile(state);
1060
1061                s5k5baf_initialize_data(state);
1062                ret = s5k5baf_power_on(state);
1063                if (ret < 0)
1064                        goto out;
1065
1066                s5k5baf_hw_init(state);
1067                s5k5baf_hw_patch(state);
1068                s5k5baf_i2c_write(state, REG_SET_HOST_INT, 1);
1069                s5k5baf_hw_set_clocks(state);
1070
1071                ret = s5k5baf_hw_set_video_bus(state);
1072                if (ret < 0)
1073                        goto out;
1074
1075                s5k5baf_hw_set_cis(state);
1076                s5k5baf_hw_set_ccm(state);
1077
1078                ret = s5k5baf_clear_error(state);
1079                if (!ret)
1080                        state->power++;
1081        } else {
1082                s5k5baf_power_off(state);
1083                state->power--;
1084        }
1085
1086out:
1087        mutex_unlock(&state->lock);
1088
1089        if (!ret && on)
1090                ret = v4l2_ctrl_handler_setup(&state->ctrls.handler);
1091
1092        return ret;
1093}
1094
1095static void s5k5baf_hw_set_stream(struct s5k5baf *state, int enable)
1096{
1097        s5k5baf_write_seq(state, REG_G_ENABLE_PREV, enable, 1);
1098}
1099
1100static int s5k5baf_s_stream(struct v4l2_subdev *sd, int on)
1101{
1102        struct s5k5baf *state = to_s5k5baf(sd);
1103        int ret;
1104
1105        mutex_lock(&state->lock);
1106
1107        if (state->streaming == !!on) {
1108                ret = 0;
1109                goto out;
1110        }
1111
1112        if (on) {
1113                s5k5baf_hw_set_config(state);
1114                ret = s5k5baf_hw_set_crop_rects(state);
1115                if (ret < 0)
1116                        goto out;
1117                s5k5baf_hw_set_stream(state, 1);
1118                s5k5baf_i2c_write(state, 0xb0cc, 0x000b);
1119        } else {
1120                s5k5baf_hw_set_stream(state, 0);
1121        }
1122        ret = s5k5baf_clear_error(state);
1123        if (!ret)
1124                state->streaming = !state->streaming;
1125
1126out:
1127        mutex_unlock(&state->lock);
1128
1129        return ret;
1130}
1131
1132static int s5k5baf_g_frame_interval(struct v4l2_subdev *sd,
1133                                   struct v4l2_subdev_frame_interval *fi)
1134{
1135        struct s5k5baf *state = to_s5k5baf(sd);
1136
1137        mutex_lock(&state->lock);
1138        fi->interval.numerator = state->fiv;
1139        fi->interval.denominator = 10000;
1140        mutex_unlock(&state->lock);
1141
1142        return 0;
1143}
1144
1145static void s5k5baf_set_frame_interval(struct s5k5baf *state,
1146                                       struct v4l2_subdev_frame_interval *fi)
1147{
1148        struct v4l2_fract *i = &fi->interval;
1149
1150        if (fi->interval.denominator == 0)
1151                state->req_fiv = S5K5BAF_MAX_FR_TIME;
1152        else
1153                state->req_fiv = clamp_t(u32,
1154                                         i->numerator * 10000 / i->denominator,
1155                                         S5K5BAF_MIN_FR_TIME,
1156                                         S5K5BAF_MAX_FR_TIME);
1157
1158        state->fiv = state->req_fiv;
1159        if (state->apply_cfg) {
1160                s5k5baf_hw_set_fiv(state, state->req_fiv);
1161                s5k5baf_hw_validate_cfg(state);
1162        }
1163        *i = (struct v4l2_fract){ state->fiv, 10000 };
1164        if (state->fiv == state->req_fiv)
1165                v4l2_info(&state->sd, "frame interval changed to %d00us\n",
1166                          state->fiv);
1167}
1168
1169static int s5k5baf_s_frame_interval(struct v4l2_subdev *sd,
1170                                   struct v4l2_subdev_frame_interval *fi)
1171{
1172        struct s5k5baf *state = to_s5k5baf(sd);
1173
1174        mutex_lock(&state->lock);
1175        s5k5baf_set_frame_interval(state, fi);
1176        mutex_unlock(&state->lock);
1177        return 0;
1178}
1179
1180/*
1181 * V4L2 subdev pad level and video operations
1182 */
1183static int s5k5baf_enum_frame_interval(struct v4l2_subdev *sd,
1184                              struct v4l2_subdev_fh *fh,
1185                              struct v4l2_subdev_frame_interval_enum *fie)
1186{
1187        if (fie->index > S5K5BAF_MAX_FR_TIME - S5K5BAF_MIN_FR_TIME ||
1188            fie->pad != PAD_CIS)
1189                return -EINVAL;
1190
1191        v4l_bound_align_image(&fie->width, S5K5BAF_WIN_WIDTH_MIN,
1192                              S5K5BAF_CIS_WIDTH, 1,
1193                              &fie->height, S5K5BAF_WIN_HEIGHT_MIN,
1194                              S5K5BAF_CIS_HEIGHT, 1, 0);
1195
1196        fie->interval.numerator = S5K5BAF_MIN_FR_TIME + fie->index;
1197        fie->interval.denominator = 10000;
1198
1199        return 0;
1200}
1201
1202static int s5k5baf_enum_mbus_code(struct v4l2_subdev *sd,
1203                                 struct v4l2_subdev_fh *fh,
1204                                 struct v4l2_subdev_mbus_code_enum *code)
1205{
1206        if (code->pad == PAD_CIS) {
1207                if (code->index > 0)
1208                        return -EINVAL;
1209                code->code = V4L2_MBUS_FMT_FIXED;
1210                return 0;
1211        }
1212
1213        if (code->index >= ARRAY_SIZE(s5k5baf_formats))
1214                return -EINVAL;
1215
1216        code->code = s5k5baf_formats[code->index].code;
1217        return 0;
1218}
1219
1220static int s5k5baf_enum_frame_size(struct v4l2_subdev *sd,
1221                                  struct v4l2_subdev_fh *fh,
1222                                  struct v4l2_subdev_frame_size_enum *fse)
1223{
1224        int i;
1225
1226        if (fse->index > 0)
1227                return -EINVAL;
1228
1229        if (fse->pad == PAD_CIS) {
1230                fse->code = V4L2_MBUS_FMT_FIXED;
1231                fse->min_width = S5K5BAF_CIS_WIDTH;
1232                fse->max_width = S5K5BAF_CIS_WIDTH;
1233                fse->min_height = S5K5BAF_CIS_HEIGHT;
1234                fse->max_height = S5K5BAF_CIS_HEIGHT;
1235                return 0;
1236        }
1237
1238        i = ARRAY_SIZE(s5k5baf_formats);
1239        while (--i)
1240                if (fse->code == s5k5baf_formats[i].code)
1241                        break;
1242        fse->code = s5k5baf_formats[i].code;
1243        fse->min_width = S5K5BAF_WIN_WIDTH_MIN;
1244        fse->max_width = S5K5BAF_CIS_WIDTH;
1245        fse->max_height = S5K5BAF_WIN_HEIGHT_MIN;
1246        fse->min_height = S5K5BAF_CIS_HEIGHT;
1247
1248        return 0;
1249}
1250
1251static void s5k5baf_try_cis_format(struct v4l2_mbus_framefmt *mf)
1252{
1253        mf->width = S5K5BAF_CIS_WIDTH;
1254        mf->height = S5K5BAF_CIS_HEIGHT;
1255        mf->code = V4L2_MBUS_FMT_FIXED;
1256        mf->colorspace = V4L2_COLORSPACE_JPEG;
1257        mf->field = V4L2_FIELD_NONE;
1258}
1259
1260static int s5k5baf_try_isp_format(struct v4l2_mbus_framefmt *mf)
1261{
1262        int pixfmt;
1263
1264        v4l_bound_align_image(&mf->width, S5K5BAF_WIN_WIDTH_MIN,
1265                              S5K5BAF_CIS_WIDTH, 1,
1266                              &mf->height, S5K5BAF_WIN_HEIGHT_MIN,
1267                              S5K5BAF_CIS_HEIGHT, 1, 0);
1268
1269        pixfmt = s5k5baf_find_pixfmt(mf);
1270
1271        mf->colorspace = s5k5baf_formats[pixfmt].colorspace;
1272        mf->code = s5k5baf_formats[pixfmt].code;
1273        mf->field = V4L2_FIELD_NONE;
1274
1275        return pixfmt;
1276}
1277
1278static int s5k5baf_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1279                          struct v4l2_subdev_format *fmt)
1280{
1281        struct s5k5baf *state = to_s5k5baf(sd);
1282        const struct s5k5baf_pixfmt *pixfmt;
1283        struct v4l2_mbus_framefmt *mf;
1284
1285        if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1286                mf = v4l2_subdev_get_try_format(fh, fmt->pad);
1287                fmt->format = *mf;
1288                return 0;
1289        }
1290
1291        mf = &fmt->format;
1292        if (fmt->pad == PAD_CIS) {
1293                s5k5baf_try_cis_format(mf);
1294                return 0;
1295        }
1296        mf->field = V4L2_FIELD_NONE;
1297        mutex_lock(&state->lock);
1298        pixfmt = &s5k5baf_formats[state->pixfmt];
1299        mf->width = state->crop_source.width;
1300        mf->height = state->crop_source.height;
1301        mf->code = pixfmt->code;
1302        mf->colorspace = pixfmt->colorspace;
1303        mutex_unlock(&state->lock);
1304
1305        return 0;
1306}
1307
1308static int s5k5baf_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1309                          struct v4l2_subdev_format *fmt)
1310{
1311        struct v4l2_mbus_framefmt *mf = &fmt->format;
1312        struct s5k5baf *state = to_s5k5baf(sd);
1313        const struct s5k5baf_pixfmt *pixfmt;
1314        int ret = 0;
1315
1316        if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1317                *v4l2_subdev_get_try_format(fh, fmt->pad) = *mf;
1318                return 0;
1319        }
1320
1321        if (fmt->pad == PAD_CIS) {
1322                s5k5baf_try_cis_format(mf);
1323                return 0;
1324        }
1325
1326        mutex_lock(&state->lock);
1327
1328        if (state->streaming) {
1329                mutex_unlock(&state->lock);
1330                return -EBUSY;
1331        }
1332
1333        state->pixfmt = s5k5baf_try_isp_format(mf);
1334        pixfmt = &s5k5baf_formats[state->pixfmt];
1335        mf->code = pixfmt->code;
1336        mf->colorspace = pixfmt->colorspace;
1337        mf->width = state->crop_source.width;
1338        mf->height = state->crop_source.height;
1339
1340        mutex_unlock(&state->lock);
1341        return ret;
1342}
1343
1344enum selection_rect { R_CIS, R_CROP_SINK, R_COMPOSE, R_CROP_SOURCE, R_INVALID };
1345
1346static enum selection_rect s5k5baf_get_sel_rect(u32 pad, u32 target)
1347{
1348        switch (target) {
1349        case V4L2_SEL_TGT_CROP_BOUNDS:
1350                return pad ? R_COMPOSE : R_CIS;
1351        case V4L2_SEL_TGT_CROP:
1352                return pad ? R_CROP_SOURCE : R_CROP_SINK;
1353        case V4L2_SEL_TGT_COMPOSE_BOUNDS:
1354                return pad ? R_INVALID : R_CROP_SINK;
1355        case V4L2_SEL_TGT_COMPOSE:
1356                return pad ? R_INVALID : R_COMPOSE;
1357        default:
1358                return R_INVALID;
1359        }
1360}
1361
1362static int s5k5baf_is_bound_target(u32 target)
1363{
1364        return target == V4L2_SEL_TGT_CROP_BOUNDS ||
1365                target == V4L2_SEL_TGT_COMPOSE_BOUNDS;
1366}
1367
1368static int s5k5baf_get_selection(struct v4l2_subdev *sd,
1369                                 struct v4l2_subdev_fh *fh,
1370                                 struct v4l2_subdev_selection *sel)
1371{
1372        static enum selection_rect rtype;
1373        struct s5k5baf *state = to_s5k5baf(sd);
1374
1375        rtype = s5k5baf_get_sel_rect(sel->pad, sel->target);
1376
1377        switch (rtype) {
1378        case R_INVALID:
1379                return -EINVAL;
1380        case R_CIS:
1381                sel->r = s5k5baf_cis_rect;
1382                return 0;
1383        default:
1384                break;
1385        }
1386
1387        if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
1388                if (rtype == R_COMPOSE)
1389                        sel->r = *v4l2_subdev_get_try_compose(fh, sel->pad);
1390                else
1391                        sel->r = *v4l2_subdev_get_try_crop(fh, sel->pad);
1392                return 0;
1393        }
1394
1395        mutex_lock(&state->lock);
1396        switch (rtype) {
1397        case R_CROP_SINK:
1398                sel->r = state->crop_sink;
1399                break;
1400        case R_COMPOSE:
1401                sel->r = state->compose;
1402                break;
1403        case R_CROP_SOURCE:
1404                sel->r = state->crop_source;
1405                break;
1406        default:
1407                break;
1408        }
1409        if (s5k5baf_is_bound_target(sel->target)) {
1410                sel->r.left = 0;
1411                sel->r.top = 0;
1412        }
1413        mutex_unlock(&state->lock);
1414
1415        return 0;
1416}
1417
1418/* bounds range [start, start+len) to [0, max) and aligns to 2 */
1419static void s5k5baf_bound_range(u32 *start, u32 *len, u32 max)
1420{
1421        if (*len > max)
1422                *len = max;
1423        if (*start + *len > max)
1424                *start = max - *len;
1425        *start &= ~1;
1426        *len &= ~1;
1427        if (*len < S5K5BAF_WIN_WIDTH_MIN)
1428                *len = S5K5BAF_WIN_WIDTH_MIN;
1429}
1430
1431static void s5k5baf_bound_rect(struct v4l2_rect *r, u32 width, u32 height)
1432{
1433        s5k5baf_bound_range(&r->left, &r->width, width);
1434        s5k5baf_bound_range(&r->top, &r->height, height);
1435}
1436
1437static void s5k5baf_set_rect_and_adjust(struct v4l2_rect **rects,
1438                                        enum selection_rect first,
1439                                        struct v4l2_rect *v)
1440{
1441        struct v4l2_rect *r, *br;
1442        enum selection_rect i = first;
1443
1444        *rects[first] = *v;
1445        do {
1446                r = rects[i];
1447                br = rects[i - 1];
1448                s5k5baf_bound_rect(r, br->width, br->height);
1449        } while (++i != R_INVALID);
1450        *v = *rects[first];
1451}
1452
1453static bool s5k5baf_cmp_rect(const struct v4l2_rect *r1,
1454                             const struct v4l2_rect *r2)
1455{
1456        return !memcmp(r1, r2, sizeof(*r1));
1457}
1458
1459static int s5k5baf_set_selection(struct v4l2_subdev *sd,
1460                                 struct v4l2_subdev_fh *fh,
1461                                 struct v4l2_subdev_selection *sel)
1462{
1463        static enum selection_rect rtype;
1464        struct s5k5baf *state = to_s5k5baf(sd);
1465        struct v4l2_rect **rects;
1466        int ret = 0;
1467
1468        rtype = s5k5baf_get_sel_rect(sel->pad, sel->target);
1469        if (rtype == R_INVALID || s5k5baf_is_bound_target(sel->target))
1470                return -EINVAL;
1471
1472        /* allow only scaling on compose */
1473        if (rtype == R_COMPOSE) {
1474                sel->r.left = 0;
1475                sel->r.top = 0;
1476        }
1477
1478        if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
1479                rects = (struct v4l2_rect * []) {
1480                                &s5k5baf_cis_rect,
1481                                v4l2_subdev_get_try_crop(fh, PAD_CIS),
1482                                v4l2_subdev_get_try_compose(fh, PAD_CIS),
1483                                v4l2_subdev_get_try_crop(fh, PAD_OUT)
1484                        };
1485                s5k5baf_set_rect_and_adjust(rects, rtype, &sel->r);
1486                return 0;
1487        }
1488
1489        rects = (struct v4l2_rect * []) {
1490                        &s5k5baf_cis_rect,
1491                        &state->crop_sink,
1492                        &state->compose,
1493                        &state->crop_source
1494                };
1495        mutex_lock(&state->lock);
1496        if (state->streaming) {
1497                /* adjust sel->r to avoid output resolution change */
1498                if (rtype < R_CROP_SOURCE) {
1499                        if (sel->r.width < state->crop_source.width)
1500                                sel->r.width = state->crop_source.width;
1501                        if (sel->r.height < state->crop_source.height)
1502                                sel->r.height = state->crop_source.height;
1503                } else {
1504                        sel->r.width = state->crop_source.width;
1505                        sel->r.height = state->crop_source.height;
1506                }
1507        }
1508        s5k5baf_set_rect_and_adjust(rects, rtype, &sel->r);
1509        if (!s5k5baf_cmp_rect(&state->crop_sink, &s5k5baf_cis_rect) ||
1510            !s5k5baf_cmp_rect(&state->compose, &s5k5baf_cis_rect))
1511                state->apply_crop = 1;
1512        if (state->streaming)
1513                ret = s5k5baf_hw_set_crop_rects(state);
1514        mutex_unlock(&state->lock);
1515
1516        return ret;
1517}
1518
1519static const struct v4l2_subdev_pad_ops s5k5baf_cis_pad_ops = {
1520        .enum_mbus_code         = s5k5baf_enum_mbus_code,
1521        .enum_frame_size        = s5k5baf_enum_frame_size,
1522        .get_fmt                = s5k5baf_get_fmt,
1523        .set_fmt                = s5k5baf_set_fmt,
1524};
1525
1526static const struct v4l2_subdev_pad_ops s5k5baf_pad_ops = {
1527        .enum_mbus_code         = s5k5baf_enum_mbus_code,
1528        .enum_frame_size        = s5k5baf_enum_frame_size,
1529        .enum_frame_interval    = s5k5baf_enum_frame_interval,
1530        .get_fmt                = s5k5baf_get_fmt,
1531        .set_fmt                = s5k5baf_set_fmt,
1532        .get_selection          = s5k5baf_get_selection,
1533        .set_selection          = s5k5baf_set_selection,
1534};
1535
1536static const struct v4l2_subdev_video_ops s5k5baf_video_ops = {
1537        .g_frame_interval       = s5k5baf_g_frame_interval,
1538        .s_frame_interval       = s5k5baf_s_frame_interval,
1539        .s_stream               = s5k5baf_s_stream,
1540};
1541
1542/*
1543 * V4L2 subdev controls
1544 */
1545
1546static int s5k5baf_s_ctrl(struct v4l2_ctrl *ctrl)
1547{
1548        struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
1549        struct s5k5baf *state = to_s5k5baf(sd);
1550        int ret;
1551
1552        v4l2_dbg(1, debug, sd, "ctrl: %s, value: %d\n", ctrl->name, ctrl->val);
1553
1554        mutex_lock(&state->lock);
1555
1556        if (state->power == 0)
1557                goto unlock;
1558
1559        switch (ctrl->id) {
1560        case V4L2_CID_AUTO_WHITE_BALANCE:
1561                s5k5baf_hw_set_awb(state, ctrl->val);
1562                break;
1563
1564        case V4L2_CID_BRIGHTNESS:
1565                s5k5baf_write(state, REG_USER_BRIGHTNESS, ctrl->val);
1566                break;
1567
1568        case V4L2_CID_COLORFX:
1569                s5k5baf_hw_set_colorfx(state, ctrl->val);
1570                break;
1571
1572        case V4L2_CID_CONTRAST:
1573                s5k5baf_write(state, REG_USER_CONTRAST, ctrl->val);
1574                break;
1575
1576        case V4L2_CID_EXPOSURE_AUTO:
1577                s5k5baf_hw_set_auto_exposure(state, ctrl->val);
1578                break;
1579
1580        case V4L2_CID_HFLIP:
1581                s5k5baf_hw_set_mirror(state);
1582                break;
1583
1584        case V4L2_CID_POWER_LINE_FREQUENCY:
1585                s5k5baf_hw_set_anti_flicker(state, ctrl->val);
1586                break;
1587
1588        case V4L2_CID_SATURATION:
1589                s5k5baf_write(state, REG_USER_SATURATION, ctrl->val);
1590                break;
1591
1592        case V4L2_CID_SHARPNESS:
1593                s5k5baf_write(state, REG_USER_SHARPBLUR, ctrl->val);
1594                break;
1595
1596        case V4L2_CID_WHITE_BALANCE_TEMPERATURE:
1597                s5k5baf_write(state, REG_P_COLORTEMP(0), ctrl->val);
1598                if (state->apply_cfg)
1599                        s5k5baf_hw_sync_cfg(state);
1600                break;
1601
1602        case V4L2_CID_TEST_PATTERN:
1603                s5k5baf_hw_set_test_pattern(state, ctrl->val);
1604                break;
1605        }
1606unlock:
1607        ret = s5k5baf_clear_error(state);
1608        mutex_unlock(&state->lock);
1609        return ret;
1610}
1611
1612static const struct v4l2_ctrl_ops s5k5baf_ctrl_ops = {
1613        .s_ctrl = s5k5baf_s_ctrl,
1614};
1615
1616static const char * const s5k5baf_test_pattern_menu[] = {
1617        "Disabled",
1618        "Blank",
1619        "Bars",
1620        "Gradients",
1621        "Textile",
1622        "Textile2",
1623        "Squares"
1624};
1625
1626static int s5k5baf_initialize_ctrls(struct s5k5baf *state)
1627{
1628        const struct v4l2_ctrl_ops *ops = &s5k5baf_ctrl_ops;
1629        struct s5k5baf_ctrls *ctrls = &state->ctrls;
1630        struct v4l2_ctrl_handler *hdl = &ctrls->handler;
1631        int ret;
1632
1633        ret = v4l2_ctrl_handler_init(hdl, 16);
1634        if (ret < 0) {
1635                v4l2_err(&state->sd, "cannot init ctrl handler (%d)\n", ret);
1636                return ret;
1637        }
1638
1639        /* Auto white balance cluster */
1640        ctrls->awb = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_WHITE_BALANCE,
1641                                       0, 1, 1, 1);
1642        ctrls->gain_red = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
1643                                            0, 255, 1, S5K5BAF_GAIN_RED_DEF);
1644        ctrls->gain_blue = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
1645                                             0, 255, 1, S5K5BAF_GAIN_BLUE_DEF);
1646        v4l2_ctrl_auto_cluster(3, &ctrls->awb, 0, false);
1647
1648        ctrls->hflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
1649        ctrls->vflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
1650        v4l2_ctrl_cluster(2, &ctrls->hflip);
1651
1652        ctrls->auto_exp = v4l2_ctrl_new_std_menu(hdl, ops,
1653                                V4L2_CID_EXPOSURE_AUTO,
1654                                V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO);
1655        /* Exposure time: x 1 us */
1656        ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE,
1657                                            0, 6000000U, 1, 100000U);
1658        /* Total gain: 256 <=> 1x */
1659        ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN,
1660                                        0, 256, 1, 256);
1661        v4l2_ctrl_auto_cluster(3, &ctrls->auto_exp, 0, false);
1662
1663        v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_POWER_LINE_FREQUENCY,
1664                               V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
1665                               V4L2_CID_POWER_LINE_FREQUENCY_AUTO);
1666
1667        v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_COLORFX,
1668                               V4L2_COLORFX_SKY_BLUE, ~0x6f, V4L2_COLORFX_NONE);
1669
1670        v4l2_ctrl_new_std(hdl, ops, V4L2_CID_WHITE_BALANCE_TEMPERATURE,
1671                          0, 256, 1, 0);
1672
1673        v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION, -127, 127, 1, 0);
1674        v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -127, 127, 1, 0);
1675        v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -127, 127, 1, 0);
1676        v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SHARPNESS, -127, 127, 1, 0);
1677
1678        v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN,
1679                                     ARRAY_SIZE(s5k5baf_test_pattern_menu) - 1,
1680                                     0, 0, s5k5baf_test_pattern_menu);
1681
1682        if (hdl->error) {
1683                v4l2_err(&state->sd, "error creating controls (%d)\n",
1684                         hdl->error);
1685                ret = hdl->error;
1686                v4l2_ctrl_handler_free(hdl);
1687                return ret;
1688        }
1689
1690        state->sd.ctrl_handler = hdl;
1691        return 0;
1692}
1693
1694/*
1695 * V4L2 subdev internal operations
1696 */
1697static int s5k5baf_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1698{
1699        struct v4l2_mbus_framefmt *mf;
1700
1701        mf = v4l2_subdev_get_try_format(fh, PAD_CIS);
1702        s5k5baf_try_cis_format(mf);
1703
1704        if (s5k5baf_is_cis_subdev(sd))
1705                return 0;
1706
1707        mf = v4l2_subdev_get_try_format(fh, PAD_OUT);
1708        mf->colorspace = s5k5baf_formats[0].colorspace;
1709        mf->code = s5k5baf_formats[0].code;
1710        mf->width = s5k5baf_cis_rect.width;
1711        mf->height = s5k5baf_cis_rect.height;
1712        mf->field = V4L2_FIELD_NONE;
1713
1714        *v4l2_subdev_get_try_crop(fh, PAD_CIS) = s5k5baf_cis_rect;
1715        *v4l2_subdev_get_try_compose(fh, PAD_CIS) = s5k5baf_cis_rect;
1716        *v4l2_subdev_get_try_crop(fh, PAD_OUT) = s5k5baf_cis_rect;
1717
1718        return 0;
1719}
1720
1721static int s5k5baf_check_fw_revision(struct s5k5baf *state)
1722{
1723        u16 api_ver = 0, fw_rev = 0, s_id = 0;
1724        int ret;
1725
1726        api_ver = s5k5baf_read(state, REG_FW_APIVER);
1727        fw_rev = s5k5baf_read(state, REG_FW_REVISION) & 0xff;
1728        s_id = s5k5baf_read(state, REG_FW_SENSOR_ID);
1729        ret = s5k5baf_clear_error(state);
1730        if (ret < 0)
1731                return ret;
1732
1733        v4l2_info(&state->sd, "FW API=%#x, revision=%#x sensor_id=%#x\n",
1734                  api_ver, fw_rev, s_id);
1735
1736        if (api_ver != S5K5BAF_FW_APIVER) {
1737                v4l2_err(&state->sd, "FW API version not supported\n");
1738                return -ENODEV;
1739        }
1740
1741        return 0;
1742}
1743
1744static int s5k5baf_registered(struct v4l2_subdev *sd)
1745{
1746        struct s5k5baf *state = to_s5k5baf(sd);
1747        int ret;
1748
1749        ret = v4l2_device_register_subdev(sd->v4l2_dev, &state->cis_sd);
1750        if (ret < 0)
1751                v4l2_err(sd, "failed to register subdev %s\n",
1752                         state->cis_sd.name);
1753        else
1754                ret = media_entity_create_link(&state->cis_sd.entity, PAD_CIS,
1755                                               &state->sd.entity, PAD_CIS,
1756                                               MEDIA_LNK_FL_IMMUTABLE |
1757                                               MEDIA_LNK_FL_ENABLED);
1758        return ret;
1759}
1760
1761static void s5k5baf_unregistered(struct v4l2_subdev *sd)
1762{
1763        struct s5k5baf *state = to_s5k5baf(sd);
1764        v4l2_device_unregister_subdev(&state->cis_sd);
1765}
1766
1767static const struct v4l2_subdev_ops s5k5baf_cis_subdev_ops = {
1768        .pad    = &s5k5baf_cis_pad_ops,
1769};
1770
1771static const struct v4l2_subdev_internal_ops s5k5baf_cis_subdev_internal_ops = {
1772        .open = s5k5baf_open,
1773};
1774
1775static const struct v4l2_subdev_internal_ops s5k5baf_subdev_internal_ops = {
1776        .registered = s5k5baf_registered,
1777        .unregistered = s5k5baf_unregistered,
1778        .open = s5k5baf_open,
1779};
1780
1781static const struct v4l2_subdev_core_ops s5k5baf_core_ops = {
1782        .s_power = s5k5baf_set_power,
1783        .log_status = v4l2_ctrl_subdev_log_status,
1784};
1785
1786static const struct v4l2_subdev_ops s5k5baf_subdev_ops = {
1787        .core = &s5k5baf_core_ops,
1788        .pad = &s5k5baf_pad_ops,
1789        .video = &s5k5baf_video_ops,
1790};
1791
1792static int s5k5baf_configure_gpios(struct s5k5baf *state)
1793{
1794        static const char const *name[] = { "S5K5BAF_STBY", "S5K5BAF_RST" };
1795        struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
1796        struct s5k5baf_gpio *g = state->gpios;
1797        int ret, i;
1798
1799        for (i = 0; i < NUM_GPIOS; ++i) {
1800                int flags = GPIOF_DIR_OUT;
1801                if (g[i].level)
1802                        flags |= GPIOF_INIT_HIGH;
1803                ret = devm_gpio_request_one(&c->dev, g[i].gpio, flags, name[i]);
1804                if (ret < 0) {
1805                        v4l2_err(c, "failed to request gpio %s\n", name[i]);
1806                        return ret;
1807                }
1808        }
1809        return 0;
1810}
1811
1812static int s5k5baf_parse_gpios(struct s5k5baf_gpio *gpios, struct device *dev)
1813{
1814        static const char * const names[] = {
1815                "stbyn-gpios",
1816                "rstn-gpios",
1817        };
1818        struct device_node *node = dev->of_node;
1819        enum of_gpio_flags flags;
1820        int ret, i;
1821
1822        for (i = 0; i < NUM_GPIOS; ++i) {
1823                ret = of_get_named_gpio_flags(node, names[i], 0, &flags);
1824                if (ret < 0) {
1825                        dev_err(dev, "no %s GPIO pin provided\n", names[i]);
1826                        return ret;
1827                }
1828                gpios[i].gpio = ret;
1829                gpios[i].level = !(flags & OF_GPIO_ACTIVE_LOW);
1830        }
1831
1832        return 0;
1833}
1834
1835static int s5k5baf_parse_device_node(struct s5k5baf *state, struct device *dev)
1836{
1837        struct device_node *node = dev->of_node;
1838        struct device_node *node_ep;
1839        struct v4l2_of_endpoint ep;
1840        int ret;
1841
1842        if (!node) {
1843                dev_err(dev, "no device-tree node provided\n");
1844                return -EINVAL;
1845        }
1846
1847        ret = of_property_read_u32(node, "clock-frequency",
1848                                   &state->mclk_frequency);
1849        if (ret < 0) {
1850                state->mclk_frequency = S5K5BAF_DEFAULT_MCLK_FREQ;
1851                dev_info(dev, "using default %u Hz clock frequency\n",
1852                         state->mclk_frequency);
1853        }
1854
1855        ret = s5k5baf_parse_gpios(state->gpios, dev);
1856        if (ret < 0)
1857                return ret;
1858
1859        node_ep = of_graph_get_next_endpoint(node, NULL);
1860        if (!node_ep) {
1861                dev_err(dev, "no endpoint defined at node %s\n",
1862                        node->full_name);
1863                return -EINVAL;
1864        }
1865
1866        v4l2_of_parse_endpoint(node_ep, &ep);
1867        of_node_put(node_ep);
1868        state->bus_type = ep.bus_type;
1869
1870        switch (state->bus_type) {
1871        case V4L2_MBUS_CSI2:
1872                state->nlanes = ep.bus.mipi_csi2.num_data_lanes;
1873                break;
1874        case V4L2_MBUS_PARALLEL:
1875                break;
1876        default:
1877                dev_err(dev, "unsupported bus in endpoint defined at node %s\n",
1878                        node->full_name);
1879                return -EINVAL;
1880        }
1881
1882        return 0;
1883}
1884
1885static int s5k5baf_configure_subdevs(struct s5k5baf *state,
1886                                     struct i2c_client *c)
1887{
1888        struct v4l2_subdev *sd;
1889        int ret;
1890
1891        sd = &state->cis_sd;
1892        v4l2_subdev_init(sd, &s5k5baf_cis_subdev_ops);
1893        sd->owner = THIS_MODULE;
1894        v4l2_set_subdevdata(sd, state);
1895        snprintf(sd->name, sizeof(sd->name), "S5K5BAF-CIS %d-%04x",
1896                 i2c_adapter_id(c->adapter), c->addr);
1897
1898        sd->internal_ops = &s5k5baf_cis_subdev_internal_ops;
1899        sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1900
1901        state->cis_pad.flags = MEDIA_PAD_FL_SOURCE;
1902        sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV_SENSOR;
1903        ret = media_entity_init(&sd->entity, NUM_CIS_PADS, &state->cis_pad, 0);
1904        if (ret < 0)
1905                goto err;
1906
1907        sd = &state->sd;
1908        v4l2_i2c_subdev_init(sd, c, &s5k5baf_subdev_ops);
1909        snprintf(sd->name, sizeof(sd->name), "S5K5BAF-ISP %d-%04x",
1910                 i2c_adapter_id(c->adapter), c->addr);
1911
1912        sd->internal_ops = &s5k5baf_subdev_internal_ops;
1913        sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1914
1915        state->pads[PAD_CIS].flags = MEDIA_PAD_FL_SINK;
1916        state->pads[PAD_OUT].flags = MEDIA_PAD_FL_SOURCE;
1917        sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV;
1918        ret = media_entity_init(&sd->entity, NUM_ISP_PADS, state->pads, 0);
1919
1920        if (!ret)
1921                return 0;
1922
1923        media_entity_cleanup(&state->cis_sd.entity);
1924err:
1925        dev_err(&c->dev, "cannot init media entity %s\n", sd->name);
1926        return ret;
1927}
1928
1929static int s5k5baf_configure_regulators(struct s5k5baf *state)
1930{
1931        struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
1932        int ret;
1933        int i;
1934
1935        for (i = 0; i < S5K5BAF_NUM_SUPPLIES; i++)
1936                state->supplies[i].supply = s5k5baf_supply_names[i];
1937
1938        ret = devm_regulator_bulk_get(&c->dev, S5K5BAF_NUM_SUPPLIES,
1939                                      state->supplies);
1940        if (ret < 0)
1941                v4l2_err(c, "failed to get regulators\n");
1942        return ret;
1943}
1944
1945static int s5k5baf_probe(struct i2c_client *c,
1946                        const struct i2c_device_id *id)
1947{
1948        struct s5k5baf *state;
1949        int ret;
1950
1951        state = devm_kzalloc(&c->dev, sizeof(*state), GFP_KERNEL);
1952        if (!state)
1953                return -ENOMEM;
1954
1955        mutex_init(&state->lock);
1956        state->crop_sink = s5k5baf_cis_rect;
1957        state->compose = s5k5baf_cis_rect;
1958        state->crop_source = s5k5baf_cis_rect;
1959
1960        ret = s5k5baf_parse_device_node(state, &c->dev);
1961        if (ret < 0)
1962                return ret;
1963
1964        ret = s5k5baf_configure_subdevs(state, c);
1965        if (ret < 0)
1966                return ret;
1967
1968        ret = s5k5baf_configure_gpios(state);
1969        if (ret < 0)
1970                goto err_me;
1971
1972        ret = s5k5baf_configure_regulators(state);
1973        if (ret < 0)
1974                goto err_me;
1975
1976        state->clock = devm_clk_get(state->sd.dev, S5K5BAF_CLK_NAME);
1977        if (IS_ERR(state->clock)) {
1978                ret = -EPROBE_DEFER;
1979                goto err_me;
1980        }
1981
1982        ret = s5k5baf_power_on(state);
1983        if (ret < 0) {
1984                ret = -EPROBE_DEFER;
1985                goto err_me;
1986        }
1987        s5k5baf_hw_init(state);
1988        ret = s5k5baf_check_fw_revision(state);
1989
1990        s5k5baf_power_off(state);
1991        if (ret < 0)
1992                goto err_me;
1993
1994        ret = s5k5baf_initialize_ctrls(state);
1995        if (ret < 0)
1996                goto err_me;
1997
1998        ret = v4l2_async_register_subdev(&state->sd);
1999        if (ret < 0)
2000                goto err_ctrl;
2001
2002        return 0;
2003
2004err_ctrl:
2005        v4l2_ctrl_handler_free(state->sd.ctrl_handler);
2006err_me:
2007        media_entity_cleanup(&state->sd.entity);
2008        media_entity_cleanup(&state->cis_sd.entity);
2009        return ret;
2010}
2011
2012static int s5k5baf_remove(struct i2c_client *c)
2013{
2014        struct v4l2_subdev *sd = i2c_get_clientdata(c);
2015        struct s5k5baf *state = to_s5k5baf(sd);
2016
2017        v4l2_async_unregister_subdev(sd);
2018        v4l2_ctrl_handler_free(sd->ctrl_handler);
2019        media_entity_cleanup(&sd->entity);
2020
2021        sd = &state->cis_sd;
2022        v4l2_device_unregister_subdev(sd);
2023        media_entity_cleanup(&sd->entity);
2024
2025        return 0;
2026}
2027
2028static const struct i2c_device_id s5k5baf_id[] = {
2029        { S5K5BAF_DRIVER_NAME, 0 },
2030        { },
2031};
2032MODULE_DEVICE_TABLE(i2c, s5k5baf_id);
2033
2034static const struct of_device_id s5k5baf_of_match[] = {
2035        { .compatible = "samsung,s5k5baf" },
2036        { }
2037};
2038MODULE_DEVICE_TABLE(of, s5k5baf_of_match);
2039
2040static struct i2c_driver s5k5baf_i2c_driver = {
2041        .driver = {
2042                .of_match_table = s5k5baf_of_match,
2043                .name = S5K5BAF_DRIVER_NAME
2044        },
2045        .probe          = s5k5baf_probe,
2046        .remove         = s5k5baf_remove,
2047        .id_table       = s5k5baf_id,
2048};
2049
2050module_i2c_driver(s5k5baf_i2c_driver);
2051
2052MODULE_DESCRIPTION("Samsung S5K5BAF(X) UXGA camera driver");
2053MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
2054MODULE_LICENSE("GPL v2");
2055
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