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24#include <linux/interrupt.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27#include <linux/delay.h>
28#include <linux/mISDNhw.h>
29#include <linux/slab.h>
30#include "w6692.h"
31
32#define W6692_REV "2.0"
33
34#define DBUSY_TIMER_VALUE 80
35
36enum {
37 W6692_ASUS,
38 W6692_WINBOND,
39 W6692_USR
40};
41
42
43struct w6692map {
44 u_int subtype;
45 char *name;
46};
47
48static const struct w6692map w6692_map[] =
49{
50 {W6692_ASUS, "Dynalink/AsusCom IS64PH"},
51 {W6692_WINBOND, "Winbond W6692"},
52 {W6692_USR, "USR W6692"}
53};
54
55#ifndef PCI_VENDOR_ID_USR
56#define PCI_VENDOR_ID_USR 0x16ec
57#define PCI_DEVICE_ID_USR_6692 0x3409
58#endif
59
60struct w6692_ch {
61 struct bchannel bch;
62 u32 addr;
63 struct timer_list timer;
64 u8 b_mode;
65};
66
67struct w6692_hw {
68 struct list_head list;
69 struct pci_dev *pdev;
70 char name[MISDN_MAX_IDLEN];
71 u32 irq;
72 u32 irqcnt;
73 u32 addr;
74 u32 fmask;
75 int subtype;
76 spinlock_t lock;
77 u8 imask;
78 u8 pctl;
79 u8 xaddr;
80 u8 xdata;
81 u8 state;
82 struct w6692_ch bc[2];
83 struct dchannel dch;
84 char log[64];
85};
86
87static LIST_HEAD(Cards);
88static DEFINE_RWLOCK(card_lock);
89
90static int w6692_cnt;
91static int debug;
92static u32 led;
93static u32 pots;
94
95static void
96_set_debug(struct w6692_hw *card)
97{
98 card->dch.debug = debug;
99 card->bc[0].bch.debug = debug;
100 card->bc[1].bch.debug = debug;
101}
102
103static int
104set_debug(const char *val, struct kernel_param *kp)
105{
106 int ret;
107 struct w6692_hw *card;
108
109 ret = param_set_uint(val, kp);
110 if (!ret) {
111 read_lock(&card_lock);
112 list_for_each_entry(card, &Cards, list)
113 _set_debug(card);
114 read_unlock(&card_lock);
115 }
116 return ret;
117}
118
119MODULE_AUTHOR("Karsten Keil");
120MODULE_LICENSE("GPL v2");
121MODULE_VERSION(W6692_REV);
122module_param_call(debug, set_debug, param_get_uint, &debug, S_IRUGO | S_IWUSR);
123MODULE_PARM_DESC(debug, "W6692 debug mask");
124module_param(led, uint, S_IRUGO | S_IWUSR);
125MODULE_PARM_DESC(led, "W6692 LED support bitmask (one bit per card)");
126module_param(pots, uint, S_IRUGO | S_IWUSR);
127MODULE_PARM_DESC(pots, "W6692 POTS support bitmask (one bit per card)");
128
129static inline u8
130ReadW6692(struct w6692_hw *card, u8 offset)
131{
132 return inb(card->addr + offset);
133}
134
135static inline void
136WriteW6692(struct w6692_hw *card, u8 offset, u8 value)
137{
138 outb(value, card->addr + offset);
139}
140
141static inline u8
142ReadW6692B(struct w6692_ch *bc, u8 offset)
143{
144 return inb(bc->addr + offset);
145}
146
147static inline void
148WriteW6692B(struct w6692_ch *bc, u8 offset, u8 value)
149{
150 outb(value, bc->addr + offset);
151}
152
153static void
154enable_hwirq(struct w6692_hw *card)
155{
156 WriteW6692(card, W_IMASK, card->imask);
157}
158
159static void
160disable_hwirq(struct w6692_hw *card)
161{
162 WriteW6692(card, W_IMASK, 0xff);
163}
164
165static const char *W6692Ver[] = {"V00", "V01", "V10", "V11"};
166
167static void
168W6692Version(struct w6692_hw *card)
169{
170 int val;
171
172 val = ReadW6692(card, W_D_RBCH);
173 pr_notice("%s: Winbond W6692 version: %s\n", card->name,
174 W6692Ver[(val >> 6) & 3]);
175}
176
177static void
178w6692_led_handler(struct w6692_hw *card, int on)
179{
180 if ((!(card->fmask & led)) || card->subtype == W6692_USR)
181 return;
182 if (on) {
183 card->xdata &= 0xfb;
184 WriteW6692(card, W_XDATA, card->xdata);
185 } else {
186 card->xdata |= 0x04;
187 WriteW6692(card, W_XDATA, card->xdata);
188 }
189}
190
191static void
192ph_command(struct w6692_hw *card, u8 cmd)
193{
194 pr_debug("%s: ph_command %x\n", card->name, cmd);
195 WriteW6692(card, W_CIX, cmd);
196}
197
198static void
199W6692_new_ph(struct w6692_hw *card)
200{
201 if (card->state == W_L1CMD_RST)
202 ph_command(card, W_L1CMD_DRC);
203 schedule_event(&card->dch, FLG_PHCHANGE);
204}
205
206static void
207W6692_ph_bh(struct dchannel *dch)
208{
209 struct w6692_hw *card = dch->hw;
210
211 switch (card->state) {
212 case W_L1CMD_RST:
213 dch->state = 0;
214 l1_event(dch->l1, HW_RESET_IND);
215 break;
216 case W_L1IND_CD:
217 dch->state = 3;
218 l1_event(dch->l1, HW_DEACT_CNF);
219 break;
220 case W_L1IND_DRD:
221 dch->state = 3;
222 l1_event(dch->l1, HW_DEACT_IND);
223 break;
224 case W_L1IND_CE:
225 dch->state = 4;
226 l1_event(dch->l1, HW_POWERUP_IND);
227 break;
228 case W_L1IND_LD:
229 if (dch->state <= 5) {
230 dch->state = 5;
231 l1_event(dch->l1, ANYSIGNAL);
232 } else {
233 dch->state = 8;
234 l1_event(dch->l1, LOSTFRAMING);
235 }
236 break;
237 case W_L1IND_ARD:
238 dch->state = 6;
239 l1_event(dch->l1, INFO2);
240 break;
241 case W_L1IND_AI8:
242 dch->state = 7;
243 l1_event(dch->l1, INFO4_P8);
244 break;
245 case W_L1IND_AI10:
246 dch->state = 7;
247 l1_event(dch->l1, INFO4_P10);
248 break;
249 default:
250 pr_debug("%s: TE unknown state %02x dch state %02x\n",
251 card->name, card->state, dch->state);
252 break;
253 }
254 pr_debug("%s: TE newstate %02x\n", card->name, dch->state);
255}
256
257static void
258W6692_empty_Dfifo(struct w6692_hw *card, int count)
259{
260 struct dchannel *dch = &card->dch;
261 u8 *ptr;
262
263 pr_debug("%s: empty_Dfifo %d\n", card->name, count);
264 if (!dch->rx_skb) {
265 dch->rx_skb = mI_alloc_skb(card->dch.maxlen, GFP_ATOMIC);
266 if (!dch->rx_skb) {
267 pr_info("%s: D receive out of memory\n", card->name);
268 WriteW6692(card, W_D_CMDR, W_D_CMDR_RACK);
269 return;
270 }
271 }
272 if ((dch->rx_skb->len + count) >= dch->maxlen) {
273 pr_debug("%s: empty_Dfifo overrun %d\n", card->name,
274 dch->rx_skb->len + count);
275 WriteW6692(card, W_D_CMDR, W_D_CMDR_RACK);
276 return;
277 }
278 ptr = skb_put(dch->rx_skb, count);
279 insb(card->addr + W_D_RFIFO, ptr, count);
280 WriteW6692(card, W_D_CMDR, W_D_CMDR_RACK);
281 if (debug & DEBUG_HW_DFIFO) {
282 snprintf(card->log, 63, "D-recv %s %d ",
283 card->name, count);
284 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, ptr, count);
285 }
286}
287
288static void
289W6692_fill_Dfifo(struct w6692_hw *card)
290{
291 struct dchannel *dch = &card->dch;
292 int count;
293 u8 *ptr;
294 u8 cmd = W_D_CMDR_XMS;
295
296 pr_debug("%s: fill_Dfifo\n", card->name);
297 if (!dch->tx_skb)
298 return;
299 count = dch->tx_skb->len - dch->tx_idx;
300 if (count <= 0)
301 return;
302 if (count > W_D_FIFO_THRESH)
303 count = W_D_FIFO_THRESH;
304 else
305 cmd |= W_D_CMDR_XME;
306 ptr = dch->tx_skb->data + dch->tx_idx;
307 dch->tx_idx += count;
308 outsb(card->addr + W_D_XFIFO, ptr, count);
309 WriteW6692(card, W_D_CMDR, cmd);
310 if (test_and_set_bit(FLG_BUSY_TIMER, &dch->Flags)) {
311 pr_debug("%s: fill_Dfifo dbusytimer running\n", card->name);
312 del_timer(&dch->timer);
313 }
314 init_timer(&dch->timer);
315 dch->timer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
316 add_timer(&dch->timer);
317 if (debug & DEBUG_HW_DFIFO) {
318 snprintf(card->log, 63, "D-send %s %d ",
319 card->name, count);
320 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, ptr, count);
321 }
322}
323
324static void
325d_retransmit(struct w6692_hw *card)
326{
327 struct dchannel *dch = &card->dch;
328
329 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
330 del_timer(&dch->timer);
331#ifdef FIXME
332 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
333 dchannel_sched_event(dch, D_CLEARBUSY);
334#endif
335 if (test_bit(FLG_TX_BUSY, &dch->Flags)) {
336
337 dch->tx_idx = 0;
338 W6692_fill_Dfifo(card);
339 } else if (dch->tx_skb) {
340 pr_info("%s: %s without TX_BUSY\n", card->name, __func__);
341 test_and_set_bit(FLG_TX_BUSY, &dch->Flags);
342 dch->tx_idx = 0;
343 W6692_fill_Dfifo(card);
344 } else {
345 pr_info("%s: XDU no TX_BUSY\n", card->name);
346 if (get_next_dframe(dch))
347 W6692_fill_Dfifo(card);
348 }
349}
350
351static void
352handle_rxD(struct w6692_hw *card) {
353 u8 stat;
354 int count;
355
356 stat = ReadW6692(card, W_D_RSTA);
357 if (stat & (W_D_RSTA_RDOV | W_D_RSTA_CRCE | W_D_RSTA_RMB)) {
358 if (stat & W_D_RSTA_RDOV) {
359 pr_debug("%s: D-channel RDOV\n", card->name);
360#ifdef ERROR_STATISTIC
361 card->dch.err_rx++;
362#endif
363 }
364 if (stat & W_D_RSTA_CRCE) {
365 pr_debug("%s: D-channel CRC error\n", card->name);
366#ifdef ERROR_STATISTIC
367 card->dch.err_crc++;
368#endif
369 }
370 if (stat & W_D_RSTA_RMB) {
371 pr_debug("%s: D-channel ABORT\n", card->name);
372#ifdef ERROR_STATISTIC
373 card->dch.err_rx++;
374#endif
375 }
376 if (card->dch.rx_skb)
377 dev_kfree_skb(card->dch.rx_skb);
378 card->dch.rx_skb = NULL;
379 WriteW6692(card, W_D_CMDR, W_D_CMDR_RACK | W_D_CMDR_RRST);
380 } else {
381 count = ReadW6692(card, W_D_RBCL) & (W_D_FIFO_THRESH - 1);
382 if (count == 0)
383 count = W_D_FIFO_THRESH;
384 W6692_empty_Dfifo(card, count);
385 recv_Dchannel(&card->dch);
386 }
387}
388
389static void
390handle_txD(struct w6692_hw *card) {
391 if (test_and_clear_bit(FLG_BUSY_TIMER, &card->dch.Flags))
392 del_timer(&card->dch.timer);
393 if (card->dch.tx_skb && card->dch.tx_idx < card->dch.tx_skb->len) {
394 W6692_fill_Dfifo(card);
395 } else {
396 if (card->dch.tx_skb)
397 dev_kfree_skb(card->dch.tx_skb);
398 if (get_next_dframe(&card->dch))
399 W6692_fill_Dfifo(card);
400 }
401}
402
403static void
404handle_statusD(struct w6692_hw *card)
405{
406 struct dchannel *dch = &card->dch;
407 u8 exval, v1, cir;
408
409 exval = ReadW6692(card, W_D_EXIR);
410
411 pr_debug("%s: D_EXIR %02x\n", card->name, exval);
412 if (exval & (W_D_EXI_XDUN | W_D_EXI_XCOL)) {
413
414 pr_debug("%s: D-channel underrun/collision\n", card->name);
415#ifdef ERROR_STATISTIC
416 dch->err_tx++;
417#endif
418 d_retransmit(card);
419 }
420 if (exval & W_D_EXI_RDOV) {
421 pr_debug("%s: D-channel RDOV\n", card->name);
422 WriteW6692(card, W_D_CMDR, W_D_CMDR_RRST);
423 }
424 if (exval & W_D_EXI_TIN2)
425 pr_debug("%s: spurious TIN2 interrupt\n", card->name);
426 if (exval & W_D_EXI_MOC) {
427 v1 = ReadW6692(card, W_MOSR);
428 pr_debug("%s: spurious MOC interrupt MOSR %02x\n",
429 card->name, v1);
430 }
431 if (exval & W_D_EXI_ISC) {
432 cir = ReadW6692(card, W_CIR);
433 pr_debug("%s: ISC CIR %02X\n", card->name, cir);
434 if (cir & W_CIR_ICC) {
435 v1 = cir & W_CIR_COD_MASK;
436 pr_debug("%s: ph_state_change %x -> %x\n", card->name,
437 dch->state, v1);
438 card->state = v1;
439 if (card->fmask & led) {
440 switch (v1) {
441 case W_L1IND_AI8:
442 case W_L1IND_AI10:
443 w6692_led_handler(card, 1);
444 break;
445 default:
446 w6692_led_handler(card, 0);
447 break;
448 }
449 }
450 W6692_new_ph(card);
451 }
452 if (cir & W_CIR_SCC) {
453 v1 = ReadW6692(card, W_SQR);
454 pr_debug("%s: SCC SQR %02X\n", card->name, v1);
455 }
456 }
457 if (exval & W_D_EXI_WEXP)
458 pr_debug("%s: spurious WEXP interrupt!\n", card->name);
459 if (exval & W_D_EXI_TEXP)
460 pr_debug("%s: spurious TEXP interrupt!\n", card->name);
461}
462
463static void
464W6692_empty_Bfifo(struct w6692_ch *wch, int count)
465{
466 struct w6692_hw *card = wch->bch.hw;
467 u8 *ptr;
468
469 pr_debug("%s: empty_Bfifo %d\n", card->name, count);
470 if (unlikely(wch->bch.state == ISDN_P_NONE)) {
471 pr_debug("%s: empty_Bfifo ISDN_P_NONE\n", card->name);
472 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT);
473 if (wch->bch.rx_skb)
474 skb_trim(wch->bch.rx_skb, 0);
475 return;
476 }
477 if (!wch->bch.rx_skb) {
478 wch->bch.rx_skb = mI_alloc_skb(wch->bch.maxlen, GFP_ATOMIC);
479 if (unlikely(!wch->bch.rx_skb)) {
480 pr_info("%s: B receive out of memory\n", card->name);
481 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK |
482 W_B_CMDR_RACT);
483 return;
484 }
485 }
486 if (wch->bch.rx_skb->len + count > wch->bch.maxlen) {
487 pr_debug("%s: empty_Bfifo incoming packet too large\n",
488 card->name);
489 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT);
490 skb_trim(wch->bch.rx_skb, 0);
491 return;
492 }
493 ptr = skb_put(wch->bch.rx_skb, count);
494 insb(wch->addr + W_B_RFIFO, ptr, count);
495 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT);
496 if (debug & DEBUG_HW_DFIFO) {
497 snprintf(card->log, 63, "B%1d-recv %s %d ",
498 wch->bch.nr, card->name, count);
499 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, ptr, count);
500 }
501}
502
503static void
504W6692_fill_Bfifo(struct w6692_ch *wch)
505{
506 struct w6692_hw *card = wch->bch.hw;
507 int count;
508 u8 *ptr, cmd = W_B_CMDR_RACT | W_B_CMDR_XMS;
509
510 pr_debug("%s: fill Bfifo\n", card->name);
511 if (!wch->bch.tx_skb)
512 return;
513 count = wch->bch.tx_skb->len - wch->bch.tx_idx;
514 if (count <= 0)
515 return;
516 ptr = wch->bch.tx_skb->data + wch->bch.tx_idx;
517 if (count > W_B_FIFO_THRESH)
518 count = W_B_FIFO_THRESH;
519 else if (test_bit(FLG_HDLC, &wch->bch.Flags))
520 cmd |= W_B_CMDR_XME;
521
522 pr_debug("%s: fill Bfifo%d/%d\n", card->name,
523 count, wch->bch.tx_idx);
524 wch->bch.tx_idx += count;
525 outsb(wch->addr + W_B_XFIFO, ptr, count);
526 WriteW6692B(wch, W_B_CMDR, cmd);
527 if (debug & DEBUG_HW_DFIFO) {
528 snprintf(card->log, 63, "B%1d-send %s %d ",
529 wch->bch.nr, card->name, count);
530 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, ptr, count);
531 }
532}
533
534#if 0
535static int
536setvolume(struct w6692_ch *wch, int mic, struct sk_buff *skb)
537{
538 struct w6692_hw *card = wch->bch.hw;
539 u16 *vol = (u16 *)skb->data;
540 u8 val;
541
542 if ((!(card->fmask & pots)) ||
543 !test_bit(FLG_TRANSPARENT, &wch->bch.Flags))
544 return -ENODEV;
545 if (skb->len < 2)
546 return -EINVAL;
547 if (*vol > 7)
548 return -EINVAL;
549 val = *vol & 7;
550 val = 7 - val;
551 if (mic) {
552 val <<= 3;
553 card->xaddr &= 0xc7;
554 } else {
555 card->xaddr &= 0xf8;
556 }
557 card->xaddr |= val;
558 WriteW6692(card, W_XADDR, card->xaddr);
559 return 0;
560}
561
562static int
563enable_pots(struct w6692_ch *wch)
564{
565 struct w6692_hw *card = wch->bch.hw;
566
567 if ((!(card->fmask & pots)) ||
568 !test_bit(FLG_TRANSPARENT, &wch->bch.Flags))
569 return -ENODEV;
570 wch->b_mode |= W_B_MODE_EPCM | W_B_MODE_BSW0;
571 WriteW6692B(wch, W_B_MODE, wch->b_mode);
572 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_XRST);
573 card->pctl |= ((wch->bch.nr & 2) ? W_PCTL_PCX : 0);
574 WriteW6692(card, W_PCTL, card->pctl);
575 return 0;
576}
577#endif
578
579static int
580disable_pots(struct w6692_ch *wch)
581{
582 struct w6692_hw *card = wch->bch.hw;
583
584 if (!(card->fmask & pots))
585 return -ENODEV;
586 wch->b_mode &= ~(W_B_MODE_EPCM | W_B_MODE_BSW0);
587 WriteW6692B(wch, W_B_MODE, wch->b_mode);
588 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_RACT |
589 W_B_CMDR_XRST);
590 return 0;
591}
592
593static int
594w6692_mode(struct w6692_ch *wch, u32 pr)
595{
596 struct w6692_hw *card;
597
598 card = wch->bch.hw;
599 pr_debug("%s: B%d protocol %x-->%x\n", card->name,
600 wch->bch.nr, wch->bch.state, pr);
601 switch (pr) {
602 case ISDN_P_NONE:
603 if ((card->fmask & pots) && (wch->b_mode & W_B_MODE_EPCM))
604 disable_pots(wch);
605 wch->b_mode = 0;
606 mISDN_clear_bchannel(&wch->bch);
607 WriteW6692B(wch, W_B_MODE, wch->b_mode);
608 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_XRST);
609 test_and_clear_bit(FLG_HDLC, &wch->bch.Flags);
610 test_and_clear_bit(FLG_TRANSPARENT, &wch->bch.Flags);
611 break;
612 case ISDN_P_B_RAW:
613 wch->b_mode = W_B_MODE_MMS;
614 WriteW6692B(wch, W_B_MODE, wch->b_mode);
615 WriteW6692B(wch, W_B_EXIM, 0);
616 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_RACT |
617 W_B_CMDR_XRST);
618 test_and_set_bit(FLG_TRANSPARENT, &wch->bch.Flags);
619 break;
620 case ISDN_P_B_HDLC:
621 wch->b_mode = W_B_MODE_ITF;
622 WriteW6692B(wch, W_B_MODE, wch->b_mode);
623 WriteW6692B(wch, W_B_ADM1, 0xff);
624 WriteW6692B(wch, W_B_ADM2, 0xff);
625 WriteW6692B(wch, W_B_EXIM, 0);
626 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_RACT |
627 W_B_CMDR_XRST);
628 test_and_set_bit(FLG_HDLC, &wch->bch.Flags);
629 break;
630 default:
631 pr_info("%s: protocol %x not known\n", card->name, pr);
632 return -ENOPROTOOPT;
633 }
634 wch->bch.state = pr;
635 return 0;
636}
637
638static void
639send_next(struct w6692_ch *wch)
640{
641 if (wch->bch.tx_skb && wch->bch.tx_idx < wch->bch.tx_skb->len)
642 W6692_fill_Bfifo(wch);
643 else {
644 if (wch->bch.tx_skb) {
645
646 if (test_bit(FLG_TRANSPARENT, &wch->bch.Flags))
647 confirm_Bsend(&wch->bch);
648 dev_kfree_skb(wch->bch.tx_skb);
649 }
650 if (get_next_bframe(&wch->bch))
651 W6692_fill_Bfifo(wch);
652 }
653}
654
655static void
656W6692B_interrupt(struct w6692_hw *card, int ch)
657{
658 struct w6692_ch *wch = &card->bc[ch];
659 int count;
660 u8 stat, star = 0;
661
662 stat = ReadW6692B(wch, W_B_EXIR);
663 pr_debug("%s: B%d EXIR %02x\n", card->name, wch->bch.nr, stat);
664 if (stat & W_B_EXI_RME) {
665 star = ReadW6692B(wch, W_B_STAR);
666 if (star & (W_B_STAR_RDOV | W_B_STAR_CRCE | W_B_STAR_RMB)) {
667 if ((star & W_B_STAR_RDOV) &&
668 test_bit(FLG_ACTIVE, &wch->bch.Flags)) {
669 pr_debug("%s: B%d RDOV proto=%x\n", card->name,
670 wch->bch.nr, wch->bch.state);
671#ifdef ERROR_STATISTIC
672 wch->bch.err_rdo++;
673#endif
674 }
675 if (test_bit(FLG_HDLC, &wch->bch.Flags)) {
676 if (star & W_B_STAR_CRCE) {
677 pr_debug("%s: B%d CRC error\n",
678 card->name, wch->bch.nr);
679#ifdef ERROR_STATISTIC
680 wch->bch.err_crc++;
681#endif
682 }
683 if (star & W_B_STAR_RMB) {
684 pr_debug("%s: B%d message abort\n",
685 card->name, wch->bch.nr);
686#ifdef ERROR_STATISTIC
687 wch->bch.err_inv++;
688#endif
689 }
690 }
691 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK |
692 W_B_CMDR_RRST | W_B_CMDR_RACT);
693 if (wch->bch.rx_skb)
694 skb_trim(wch->bch.rx_skb, 0);
695 } else {
696 count = ReadW6692B(wch, W_B_RBCL) &
697 (W_B_FIFO_THRESH - 1);
698 if (count == 0)
699 count = W_B_FIFO_THRESH;
700 W6692_empty_Bfifo(wch, count);
701 recv_Bchannel(&wch->bch, 0);
702 }
703 }
704 if (stat & W_B_EXI_RMR) {
705 if (!(stat & W_B_EXI_RME))
706 star = ReadW6692B(wch, W_B_STAR);
707 if (star & W_B_STAR_RDOV) {
708 pr_debug("%s: B%d RDOV proto=%x\n", card->name,
709 wch->bch.nr, wch->bch.state);
710#ifdef ERROR_STATISTIC
711 wch->bch.err_rdo++;
712#endif
713 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK |
714 W_B_CMDR_RRST | W_B_CMDR_RACT);
715 } else {
716 W6692_empty_Bfifo(wch, W_B_FIFO_THRESH);
717 if (test_bit(FLG_TRANSPARENT, &wch->bch.Flags) &&
718 wch->bch.rx_skb && (wch->bch.rx_skb->len > 0))
719 recv_Bchannel(&wch->bch, 0);
720 }
721 }
722 if (stat & W_B_EXI_RDOV) {
723
724 if (!(star & W_B_STAR_RDOV)) {
725 pr_debug("%s: B%d RDOV IRQ proto=%x\n", card->name,
726 wch->bch.nr, wch->bch.state);
727#ifdef ERROR_STATISTIC
728 wch->bch.err_rdo++;
729#endif
730 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK |
731 W_B_CMDR_RRST | W_B_CMDR_RACT);
732 }
733 }
734 if (stat & W_B_EXI_XFR) {
735 if (!(stat & (W_B_EXI_RME | W_B_EXI_RMR))) {
736 star = ReadW6692B(wch, W_B_STAR);
737 pr_debug("%s: B%d star %02x\n", card->name,
738 wch->bch.nr, star);
739 }
740 if (star & W_B_STAR_XDOW) {
741 pr_debug("%s: B%d XDOW proto=%x\n", card->name,
742 wch->bch.nr, wch->bch.state);
743#ifdef ERROR_STATISTIC
744 wch->bch.err_xdu++;
745#endif
746 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_XRST |
747 W_B_CMDR_RACT);
748
749 if (wch->bch.tx_skb) {
750 if (!test_bit(FLG_TRANSPARENT, &wch->bch.Flags))
751 wch->bch.tx_idx = 0;
752 }
753 }
754 send_next(wch);
755 if (stat & W_B_EXI_XDUN)
756 return;
757 }
758 if (stat & W_B_EXI_XDUN) {
759 pr_debug("%s: B%d XDUN proto=%x\n", card->name,
760 wch->bch.nr, wch->bch.state);
761#ifdef ERROR_STATISTIC
762 wch->bch.err_xdu++;
763#endif
764 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_XRST | W_B_CMDR_RACT);
765
766 if (wch->bch.tx_skb) {
767 if (!test_bit(FLG_TRANSPARENT, &wch->bch.Flags))
768 wch->bch.tx_idx = 0;
769 }
770 send_next(wch);
771 }
772}
773
774static irqreturn_t
775w6692_irq(int intno, void *dev_id)
776{
777 struct w6692_hw *card = dev_id;
778 u8 ista;
779
780 spin_lock(&card->lock);
781 ista = ReadW6692(card, W_ISTA);
782 if ((ista | card->imask) == card->imask) {
783
784 spin_unlock(&card->lock);
785 return IRQ_NONE;
786 }
787 card->irqcnt++;
788 pr_debug("%s: ista %02x\n", card->name, ista);
789 ista &= ~card->imask;
790 if (ista & W_INT_B1_EXI)
791 W6692B_interrupt(card, 0);
792 if (ista & W_INT_B2_EXI)
793 W6692B_interrupt(card, 1);
794 if (ista & W_INT_D_RME)
795 handle_rxD(card);
796 if (ista & W_INT_D_RMR)
797 W6692_empty_Dfifo(card, W_D_FIFO_THRESH);
798 if (ista & W_INT_D_XFR)
799 handle_txD(card);
800 if (ista & W_INT_D_EXI)
801 handle_statusD(card);
802 if (ista & (W_INT_XINT0 | W_INT_XINT1))
803 pr_debug("%s: W6692 spurious XINT!\n", card->name);
804
805 spin_unlock(&card->lock);
806 return IRQ_HANDLED;
807}
808
809static void
810dbusy_timer_handler(struct dchannel *dch)
811{
812 struct w6692_hw *card = dch->hw;
813 int rbch, star;
814 u_long flags;
815
816 if (test_bit(FLG_BUSY_TIMER, &dch->Flags)) {
817 spin_lock_irqsave(&card->lock, flags);
818 rbch = ReadW6692(card, W_D_RBCH);
819 star = ReadW6692(card, W_D_STAR);
820 pr_debug("%s: D-Channel Busy RBCH %02x STAR %02x\n",
821 card->name, rbch, star);
822 if (star & W_D_STAR_XBZ)
823 test_and_set_bit(FLG_L1_BUSY, &dch->Flags);
824 else {
825
826 test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags);
827 if (dch->tx_idx)
828 dch->tx_idx = 0;
829 else
830 pr_info("%s: W6692 D-Channel Busy no tx_idx\n",
831 card->name);
832
833 WriteW6692(card, W_D_CMDR, W_D_CMDR_XRST);
834 }
835 spin_unlock_irqrestore(&card->lock, flags);
836 }
837}
838
839void initW6692(struct w6692_hw *card)
840{
841 u8 val;
842
843 card->dch.timer.function = (void *)dbusy_timer_handler;
844 card->dch.timer.data = (u_long)&card->dch;
845 init_timer(&card->dch.timer);
846 w6692_mode(&card->bc[0], ISDN_P_NONE);
847 w6692_mode(&card->bc[1], ISDN_P_NONE);
848 WriteW6692(card, W_D_CTL, 0x00);
849 disable_hwirq(card);
850 WriteW6692(card, W_D_SAM, 0xff);
851 WriteW6692(card, W_D_TAM, 0xff);
852 WriteW6692(card, W_D_MODE, W_D_MODE_RACT);
853 card->state = W_L1CMD_RST;
854 ph_command(card, W_L1CMD_RST);
855 ph_command(card, W_L1CMD_ECK);
856
857 card->imask = 0x18;
858 WriteW6692(card, W_D_EXIM, 0x00);
859 WriteW6692B(&card->bc[0], W_B_EXIM, 0);
860 WriteW6692B(&card->bc[1], W_B_EXIM, 0);
861
862 WriteW6692(card, W_D_CMDR, W_D_CMDR_RRST | W_D_CMDR_XRST);
863
864 WriteW6692B(&card->bc[0], W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_XRST);
865 WriteW6692B(&card->bc[1], W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_XRST);
866
867 if (card->subtype == W6692_USR) {
868
869
870
871
872 card->pctl = 0x80;
873 card->xdata = 0;
874 WriteW6692(card, W_PCTL, card->pctl);
875 WriteW6692(card, W_XDATA, card->xdata);
876 } else {
877 card->pctl = W_PCTL_OE5 | W_PCTL_OE4 | W_PCTL_OE2 |
878 W_PCTL_OE1 | W_PCTL_OE0;
879 card->xaddr = 0x00;
880 if (card->fmask & pots)
881 card->xdata |= 0x06;
882 if (card->fmask & led)
883 card->xdata |= 0x04;
884 if ((card->fmask & pots) || (card->fmask & led)) {
885 WriteW6692(card, W_PCTL, card->pctl);
886 WriteW6692(card, W_XADDR, card->xaddr);
887 WriteW6692(card, W_XDATA, card->xdata);
888 val = ReadW6692(card, W_XADDR);
889 if (debug & DEBUG_HW)
890 pr_notice("%s: W_XADDR=%02x\n",
891 card->name, val);
892 }
893 }
894}
895
896static void
897reset_w6692(struct w6692_hw *card)
898{
899 WriteW6692(card, W_D_CTL, W_D_CTL_SRST);
900 mdelay(10);
901 WriteW6692(card, W_D_CTL, 0);
902}
903
904static int
905init_card(struct w6692_hw *card)
906{
907 int cnt = 3;
908 u_long flags;
909
910 spin_lock_irqsave(&card->lock, flags);
911 disable_hwirq(card);
912 spin_unlock_irqrestore(&card->lock, flags);
913 if (request_irq(card->irq, w6692_irq, IRQF_SHARED, card->name, card)) {
914 pr_info("%s: couldn't get interrupt %d\n", card->name,
915 card->irq);
916 return -EIO;
917 }
918 while (cnt--) {
919 spin_lock_irqsave(&card->lock, flags);
920 initW6692(card);
921 enable_hwirq(card);
922 spin_unlock_irqrestore(&card->lock, flags);
923
924 msleep_interruptible(10);
925 if (debug & DEBUG_HW)
926 pr_notice("%s: IRQ %d count %d\n", card->name,
927 card->irq, card->irqcnt);
928 if (!card->irqcnt) {
929 pr_info("%s: IRQ(%d) getting no IRQs during init %d\n",
930 card->name, card->irq, 3 - cnt);
931 reset_w6692(card);
932 } else
933 return 0;
934 }
935 free_irq(card->irq, card);
936 return -EIO;
937}
938
939static int
940w6692_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
941{
942 struct bchannel *bch = container_of(ch, struct bchannel, ch);
943 struct w6692_ch *bc = container_of(bch, struct w6692_ch, bch);
944 struct w6692_hw *card = bch->hw;
945 int ret = -EINVAL;
946 struct mISDNhead *hh = mISDN_HEAD_P(skb);
947 u32 id;
948 u_long flags;
949
950 switch (hh->prim) {
951 case PH_DATA_REQ:
952 spin_lock_irqsave(&card->lock, flags);
953 ret = bchannel_senddata(bch, skb);
954 if (ret > 0) {
955 id = hh->id;
956 ret = 0;
957 W6692_fill_Bfifo(bc);
958 spin_unlock_irqrestore(&card->lock, flags);
959 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
960 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
961 } else
962 spin_unlock_irqrestore(&card->lock, flags);
963 return ret;
964 case PH_ACTIVATE_REQ:
965 spin_lock_irqsave(&card->lock, flags);
966 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
967 ret = w6692_mode(bc, ch->protocol);
968 else
969 ret = 0;
970 spin_unlock_irqrestore(&card->lock, flags);
971 if (!ret)
972 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
973 NULL, GFP_KERNEL);
974 break;
975 case PH_DEACTIVATE_REQ:
976 spin_lock_irqsave(&card->lock, flags);
977 mISDN_clear_bchannel(bch);
978 w6692_mode(bc, ISDN_P_NONE);
979 spin_unlock_irqrestore(&card->lock, flags);
980 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
981 NULL, GFP_KERNEL);
982 ret = 0;
983 break;
984 default:
985 pr_info("%s: %s unknown prim(%x,%x)\n",
986 card->name, __func__, hh->prim, hh->id);
987 ret = -EINVAL;
988 }
989 if (!ret)
990 dev_kfree_skb(skb);
991 return ret;
992}
993
994static int
995channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
996{
997 int ret = 0;
998
999 switch (cq->op) {
1000 case MISDN_CTRL_GETOP:
1001 cq->op = 0;
1002 break;
1003
1004 case MISDN_CTRL_FILL_EMPTY:
1005 default:
1006 pr_info("%s: unknown Op %x\n", __func__, cq->op);
1007 ret = -EINVAL;
1008 break;
1009 }
1010 return ret;
1011}
1012
1013static int
1014open_bchannel(struct w6692_hw *card, struct channel_req *rq)
1015{
1016 struct bchannel *bch;
1017
1018 if (rq->adr.channel > 2)
1019 return -EINVAL;
1020 if (rq->protocol == ISDN_P_NONE)
1021 return -EINVAL;
1022 bch = &card->bc[rq->adr.channel - 1].bch;
1023 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
1024 return -EBUSY;
1025 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
1026 bch->ch.protocol = rq->protocol;
1027 rq->ch = &bch->ch;
1028 return 0;
1029}
1030
1031static int
1032channel_ctrl(struct w6692_hw *card, struct mISDN_ctrl_req *cq)
1033{
1034 int ret = 0;
1035
1036 switch (cq->op) {
1037 case MISDN_CTRL_GETOP:
1038 cq->op = 0;
1039 break;
1040 default:
1041 pr_info("%s: unknown CTRL OP %x\n", card->name, cq->op);
1042 ret = -EINVAL;
1043 break;
1044 }
1045 return ret;
1046}
1047
1048static int
1049w6692_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
1050{
1051 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1052 struct w6692_ch *bc = container_of(bch, struct w6692_ch, bch);
1053 struct w6692_hw *card = bch->hw;
1054 int ret = -EINVAL;
1055 u_long flags;
1056
1057 pr_debug("%s: %s cmd:%x %p\n", card->name, __func__, cmd, arg);
1058 switch (cmd) {
1059 case CLOSE_CHANNEL:
1060 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1061 if (test_bit(FLG_ACTIVE, &bch->Flags)) {
1062 spin_lock_irqsave(&card->lock, flags);
1063 mISDN_freebchannel(bch);
1064 w6692_mode(bc, ISDN_P_NONE);
1065 spin_unlock_irqrestore(&card->lock, flags);
1066 } else {
1067 skb_queue_purge(&bch->rqueue);
1068 bch->rcount = 0;
1069 }
1070 ch->protocol = ISDN_P_NONE;
1071 ch->peer = NULL;
1072 module_put(THIS_MODULE);
1073 ret = 0;
1074 break;
1075 case CONTROL_CHANNEL:
1076 ret = channel_bctrl(bch, arg);
1077 break;
1078 default:
1079 pr_info("%s: %s unknown prim(%x)\n",
1080 card->name, __func__, cmd);
1081 }
1082 return ret;
1083}
1084
1085static int
1086w6692_l2l1D(struct mISDNchannel *ch, struct sk_buff *skb)
1087{
1088 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1089 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1090 struct w6692_hw *card = container_of(dch, struct w6692_hw, dch);
1091 int ret = -EINVAL;
1092 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1093 u32 id;
1094 u_long flags;
1095
1096 switch (hh->prim) {
1097 case PH_DATA_REQ:
1098 spin_lock_irqsave(&card->lock, flags);
1099 ret = dchannel_senddata(dch, skb);
1100 if (ret > 0) {
1101 id = hh->id;
1102 W6692_fill_Dfifo(card);
1103 ret = 0;
1104 spin_unlock_irqrestore(&card->lock, flags);
1105 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1106 } else
1107 spin_unlock_irqrestore(&card->lock, flags);
1108 return ret;
1109 case PH_ACTIVATE_REQ:
1110 ret = l1_event(dch->l1, hh->prim);
1111 break;
1112 case PH_DEACTIVATE_REQ:
1113 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1114 ret = l1_event(dch->l1, hh->prim);
1115 break;
1116 }
1117
1118 if (!ret)
1119 dev_kfree_skb(skb);
1120 return ret;
1121}
1122
1123static int
1124w6692_l1callback(struct dchannel *dch, u32 cmd)
1125{
1126 struct w6692_hw *card = container_of(dch, struct w6692_hw, dch);
1127 u_long flags;
1128
1129 pr_debug("%s: cmd(%x) state(%02x)\n", card->name, cmd, card->state);
1130 switch (cmd) {
1131 case INFO3_P8:
1132 spin_lock_irqsave(&card->lock, flags);
1133 ph_command(card, W_L1CMD_AR8);
1134 spin_unlock_irqrestore(&card->lock, flags);
1135 break;
1136 case INFO3_P10:
1137 spin_lock_irqsave(&card->lock, flags);
1138 ph_command(card, W_L1CMD_AR10);
1139 spin_unlock_irqrestore(&card->lock, flags);
1140 break;
1141 case HW_RESET_REQ:
1142 spin_lock_irqsave(&card->lock, flags);
1143 if (card->state != W_L1IND_DRD)
1144 ph_command(card, W_L1CMD_RST);
1145 ph_command(card, W_L1CMD_ECK);
1146 spin_unlock_irqrestore(&card->lock, flags);
1147 break;
1148 case HW_DEACT_REQ:
1149 skb_queue_purge(&dch->squeue);
1150 if (dch->tx_skb) {
1151 dev_kfree_skb(dch->tx_skb);
1152 dch->tx_skb = NULL;
1153 }
1154 dch->tx_idx = 0;
1155 if (dch->rx_skb) {
1156 dev_kfree_skb(dch->rx_skb);
1157 dch->rx_skb = NULL;
1158 }
1159 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1160 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1161 del_timer(&dch->timer);
1162 break;
1163 case HW_POWERUP_REQ:
1164 spin_lock_irqsave(&card->lock, flags);
1165 ph_command(card, W_L1CMD_ECK);
1166 spin_unlock_irqrestore(&card->lock, flags);
1167 break;
1168 case PH_ACTIVATE_IND:
1169 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
1170 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1171 GFP_ATOMIC);
1172 break;
1173 case PH_DEACTIVATE_IND:
1174 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1175 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1176 GFP_ATOMIC);
1177 break;
1178 default:
1179 pr_debug("%s: %s unknown command %x\n", card->name,
1180 __func__, cmd);
1181 return -1;
1182 }
1183 return 0;
1184}
1185
1186static int
1187open_dchannel(struct w6692_hw *card, struct channel_req *rq)
1188{
1189 pr_debug("%s: %s dev(%d) open from %p\n", card->name, __func__,
1190 card->dch.dev.id, __builtin_return_address(1));
1191 if (rq->protocol != ISDN_P_TE_S0)
1192 return -EINVAL;
1193 if (rq->adr.channel == 1)
1194
1195 return -EINVAL;
1196 rq->ch = &card->dch.dev.D;
1197 rq->ch->protocol = rq->protocol;
1198 if (card->dch.state == 7)
1199 _queue_data(rq->ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
1200 0, NULL, GFP_KERNEL);
1201 return 0;
1202}
1203
1204static int
1205w6692_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
1206{
1207 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1208 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1209 struct w6692_hw *card = container_of(dch, struct w6692_hw, dch);
1210 struct channel_req *rq;
1211 int err = 0;
1212
1213 pr_debug("%s: DCTRL: %x %p\n", card->name, cmd, arg);
1214 switch (cmd) {
1215 case OPEN_CHANNEL:
1216 rq = arg;
1217 if (rq->protocol == ISDN_P_TE_S0)
1218 err = open_dchannel(card, rq);
1219 else
1220 err = open_bchannel(card, rq);
1221 if (err)
1222 break;
1223 if (!try_module_get(THIS_MODULE))
1224 pr_info("%s: cannot get module\n", card->name);
1225 break;
1226 case CLOSE_CHANNEL:
1227 pr_debug("%s: dev(%d) close from %p\n", card->name,
1228 dch->dev.id, __builtin_return_address(0));
1229 module_put(THIS_MODULE);
1230 break;
1231 case CONTROL_CHANNEL:
1232 err = channel_ctrl(card, arg);
1233 break;
1234 default:
1235 pr_debug("%s: unknown DCTRL command %x\n", card->name, cmd);
1236 return -EINVAL;
1237 }
1238 return err;
1239}
1240
1241static int
1242setup_w6692(struct w6692_hw *card)
1243{
1244 u32 val;
1245
1246 if (!request_region(card->addr, 256, card->name)) {
1247 pr_info("%s: config port %x-%x already in use\n", card->name,
1248 card->addr, card->addr + 255);
1249 return -EIO;
1250 }
1251 W6692Version(card);
1252 card->bc[0].addr = card->addr;
1253 card->bc[1].addr = card->addr + 0x40;
1254 val = ReadW6692(card, W_ISTA);
1255 if (debug & DEBUG_HW)
1256 pr_notice("%s ISTA=%02x\n", card->name, val);
1257 val = ReadW6692(card, W_IMASK);
1258 if (debug & DEBUG_HW)
1259 pr_notice("%s IMASK=%02x\n", card->name, val);
1260 val = ReadW6692(card, W_D_EXIR);
1261 if (debug & DEBUG_HW)
1262 pr_notice("%s D_EXIR=%02x\n", card->name, val);
1263 val = ReadW6692(card, W_D_EXIM);
1264 if (debug & DEBUG_HW)
1265 pr_notice("%s D_EXIM=%02x\n", card->name, val);
1266 val = ReadW6692(card, W_D_RSTA);
1267 if (debug & DEBUG_HW)
1268 pr_notice("%s D_RSTA=%02x\n", card->name, val);
1269 return 0;
1270}
1271
1272static void
1273release_card(struct w6692_hw *card)
1274{
1275 u_long flags;
1276
1277 spin_lock_irqsave(&card->lock, flags);
1278 disable_hwirq(card);
1279 w6692_mode(&card->bc[0], ISDN_P_NONE);
1280 w6692_mode(&card->bc[1], ISDN_P_NONE);
1281 if ((card->fmask & led) || card->subtype == W6692_USR) {
1282 card->xdata |= 0x04;
1283 WriteW6692(card, W_XDATA, card->xdata);
1284 }
1285 spin_unlock_irqrestore(&card->lock, flags);
1286 free_irq(card->irq, card);
1287 l1_event(card->dch.l1, CLOSE_CHANNEL);
1288 mISDN_unregister_device(&card->dch.dev);
1289 release_region(card->addr, 256);
1290 mISDN_freebchannel(&card->bc[1].bch);
1291 mISDN_freebchannel(&card->bc[0].bch);
1292 mISDN_freedchannel(&card->dch);
1293 write_lock_irqsave(&card_lock, flags);
1294 list_del(&card->list);
1295 write_unlock_irqrestore(&card_lock, flags);
1296 pci_disable_device(card->pdev);
1297 pci_set_drvdata(card->pdev, NULL);
1298 kfree(card);
1299}
1300
1301static int
1302setup_instance(struct w6692_hw *card)
1303{
1304 int i, err;
1305 u_long flags;
1306
1307 snprintf(card->name, MISDN_MAX_IDLEN - 1, "w6692.%d", w6692_cnt + 1);
1308 write_lock_irqsave(&card_lock, flags);
1309 list_add_tail(&card->list, &Cards);
1310 write_unlock_irqrestore(&card_lock, flags);
1311 card->fmask = (1 << w6692_cnt);
1312 _set_debug(card);
1313 spin_lock_init(&card->lock);
1314 mISDN_initdchannel(&card->dch, MAX_DFRAME_LEN_L1, W6692_ph_bh);
1315 card->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0);
1316 card->dch.dev.D.send = w6692_l2l1D;
1317 card->dch.dev.D.ctrl = w6692_dctrl;
1318 card->dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
1319 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
1320 card->dch.hw = card;
1321 card->dch.dev.nrbchan = 2;
1322 for (i = 0; i < 2; i++) {
1323 mISDN_initbchannel(&card->bc[i].bch, MAX_DATA_MEM);
1324 card->bc[i].bch.hw = card;
1325 card->bc[i].bch.nr = i + 1;
1326 card->bc[i].bch.ch.nr = i + 1;
1327 card->bc[i].bch.ch.send = w6692_l2l1B;
1328 card->bc[i].bch.ch.ctrl = w6692_bctrl;
1329 set_channelmap(i + 1, card->dch.dev.channelmap);
1330 list_add(&card->bc[i].bch.ch.list, &card->dch.dev.bchannels);
1331 }
1332 err = setup_w6692(card);
1333 if (err)
1334 goto error_setup;
1335 err = mISDN_register_device(&card->dch.dev, &card->pdev->dev,
1336 card->name);
1337 if (err)
1338 goto error_reg;
1339 err = init_card(card);
1340 if (err)
1341 goto error_init;
1342 err = create_l1(&card->dch, w6692_l1callback);
1343 if (!err) {
1344 w6692_cnt++;
1345 pr_notice("W6692 %d cards installed\n", w6692_cnt);
1346 return 0;
1347 }
1348
1349 free_irq(card->irq, card);
1350error_init:
1351 mISDN_unregister_device(&card->dch.dev);
1352error_reg:
1353 release_region(card->addr, 256);
1354error_setup:
1355 mISDN_freebchannel(&card->bc[1].bch);
1356 mISDN_freebchannel(&card->bc[0].bch);
1357 mISDN_freedchannel(&card->dch);
1358 write_lock_irqsave(&card_lock, flags);
1359 list_del(&card->list);
1360 write_unlock_irqrestore(&card_lock, flags);
1361 kfree(card);
1362 return err;
1363}
1364
1365static int __devinit
1366w6692_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1367{
1368 int err = -ENOMEM;
1369 struct w6692_hw *card;
1370 struct w6692map *m = (struct w6692map *)ent->driver_data;
1371
1372 card = kzalloc(sizeof(struct w6692_hw), GFP_KERNEL);
1373 if (!card) {
1374 pr_info("No kmem for w6692 card\n");
1375 return err;
1376 }
1377 card->pdev = pdev;
1378 card->subtype = m->subtype;
1379 err = pci_enable_device(pdev);
1380 if (err) {
1381 kfree(card);
1382 return err;
1383 }
1384
1385 printk(KERN_INFO "mISDN_w6692: found adapter %s at %s\n",
1386 m->name, pci_name(pdev));
1387
1388 card->addr = pci_resource_start(pdev, 1);
1389 card->irq = pdev->irq;
1390 pci_set_drvdata(pdev, card);
1391 err = setup_instance(card);
1392 if (err)
1393 pci_set_drvdata(pdev, NULL);
1394 return err;
1395}
1396
1397static void __devexit
1398w6692_remove_pci(struct pci_dev *pdev)
1399{
1400 struct w6692_hw *card = pci_get_drvdata(pdev);
1401
1402 if (card)
1403 release_card(card);
1404 else
1405 if (debug)
1406 pr_notice("%s: drvdata already removed\n", __func__);
1407}
1408
1409static struct pci_device_id w6692_ids[] = {
1410 { PCI_VENDOR_ID_DYNALINK, PCI_DEVICE_ID_DYNALINK_IS64PH,
1411 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (ulong)&w6692_map[0]},
1412 { PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_6692,
1413 PCI_VENDOR_ID_USR, PCI_DEVICE_ID_USR_6692, 0, 0,
1414 (ulong)&w6692_map[2]},
1415 { PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_6692,
1416 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (ulong)&w6692_map[1]},
1417 { }
1418};
1419MODULE_DEVICE_TABLE(pci, w6692_ids);
1420
1421static struct pci_driver w6692_driver = {
1422 .name = "w6692",
1423 .probe = w6692_probe,
1424 .remove = __devexit_p(w6692_remove_pci),
1425 .id_table = w6692_ids,
1426};
1427
1428static int __init w6692_init(void)
1429{
1430 int err;
1431
1432 pr_notice("Winbond W6692 PCI driver Rev. %s\n", W6692_REV);
1433
1434 err = pci_register_driver(&w6692_driver);
1435 return err;
1436}
1437
1438static void __exit w6692_cleanup(void)
1439{
1440 pci_unregister_driver(&w6692_driver);
1441}
1442
1443module_init(w6692_init);
1444module_exit(w6692_cleanup);
1445
