linux/drivers/iio/adc/xilinx-xadc-core.c
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   1/*
   2 * Xilinx XADC driver
   3 *
   4 * Copyright 2013-2014 Analog Devices Inc.
   5 *  Author: Lars-Peter Clauen <lars@metafoo.de>
   6 *
   7 * Licensed under the GPL-2.
   8 *
   9 * Documentation for the parts can be found at:
  10 *  - XADC hardmacro: Xilinx UG480
  11 *  - ZYNQ XADC interface: Xilinx UG585
  12 *  - AXI XADC interface: Xilinx PG019
  13 */
  14
  15#include <linux/clk.h>
  16#include <linux/device.h>
  17#include <linux/err.h>
  18#include <linux/interrupt.h>
  19#include <linux/io.h>
  20#include <linux/kernel.h>
  21#include <linux/module.h>
  22#include <linux/of.h>
  23#include <linux/platform_device.h>
  24#include <linux/slab.h>
  25#include <linux/sysfs.h>
  26
  27#include <linux/iio/buffer.h>
  28#include <linux/iio/events.h>
  29#include <linux/iio/iio.h>
  30#include <linux/iio/sysfs.h>
  31#include <linux/iio/trigger.h>
  32#include <linux/iio/trigger_consumer.h>
  33#include <linux/iio/triggered_buffer.h>
  34
  35#include "xilinx-xadc.h"
  36
  37static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
  38
  39/* ZYNQ register definitions */
  40#define XADC_ZYNQ_REG_CFG       0x00
  41#define XADC_ZYNQ_REG_INTSTS    0x04
  42#define XADC_ZYNQ_REG_INTMSK    0x08
  43#define XADC_ZYNQ_REG_STATUS    0x0c
  44#define XADC_ZYNQ_REG_CFIFO     0x10
  45#define XADC_ZYNQ_REG_DFIFO     0x14
  46#define XADC_ZYNQ_REG_CTL               0x18
  47
  48#define XADC_ZYNQ_CFG_ENABLE            BIT(31)
  49#define XADC_ZYNQ_CFG_CFIFOTH_MASK      (0xf << 20)
  50#define XADC_ZYNQ_CFG_CFIFOTH_OFFSET    20
  51#define XADC_ZYNQ_CFG_DFIFOTH_MASK      (0xf << 16)
  52#define XADC_ZYNQ_CFG_DFIFOTH_OFFSET    16
  53#define XADC_ZYNQ_CFG_WEDGE             BIT(13)
  54#define XADC_ZYNQ_CFG_REDGE             BIT(12)
  55#define XADC_ZYNQ_CFG_TCKRATE_MASK      (0x3 << 8)
  56#define XADC_ZYNQ_CFG_TCKRATE_DIV2      (0x0 << 8)
  57#define XADC_ZYNQ_CFG_TCKRATE_DIV4      (0x1 << 8)
  58#define XADC_ZYNQ_CFG_TCKRATE_DIV8      (0x2 << 8)
  59#define XADC_ZYNQ_CFG_TCKRATE_DIV16     (0x3 << 8)
  60#define XADC_ZYNQ_CFG_IGAP_MASK         0x1f
  61#define XADC_ZYNQ_CFG_IGAP(x)           (x)
  62
  63#define XADC_ZYNQ_INT_CFIFO_LTH         BIT(9)
  64#define XADC_ZYNQ_INT_DFIFO_GTH         BIT(8)
  65#define XADC_ZYNQ_INT_ALARM_MASK        0xff
  66#define XADC_ZYNQ_INT_ALARM_OFFSET      0
  67
  68#define XADC_ZYNQ_STATUS_CFIFO_LVL_MASK (0xf << 16)
  69#define XADC_ZYNQ_STATUS_CFIFO_LVL_OFFSET       16
  70#define XADC_ZYNQ_STATUS_DFIFO_LVL_MASK (0xf << 12)
  71#define XADC_ZYNQ_STATUS_DFIFO_LVL_OFFSET       12
  72#define XADC_ZYNQ_STATUS_CFIFOF         BIT(11)
  73#define XADC_ZYNQ_STATUS_CFIFOE         BIT(10)
  74#define XADC_ZYNQ_STATUS_DFIFOF         BIT(9)
  75#define XADC_ZYNQ_STATUS_DFIFOE         BIT(8)
  76#define XADC_ZYNQ_STATUS_OT             BIT(7)
  77#define XADC_ZYNQ_STATUS_ALM(x)         BIT(x)
  78
  79#define XADC_ZYNQ_CTL_RESET             BIT(4)
  80
  81#define XADC_ZYNQ_CMD_NOP               0x00
  82#define XADC_ZYNQ_CMD_READ              0x01
  83#define XADC_ZYNQ_CMD_WRITE             0x02
  84
  85#define XADC_ZYNQ_CMD(cmd, addr, data) (((cmd) << 26) | ((addr) << 16) | (data))
  86
  87/* AXI register definitions */
  88#define XADC_AXI_REG_RESET              0x00
  89#define XADC_AXI_REG_STATUS             0x04
  90#define XADC_AXI_REG_ALARM_STATUS       0x08
  91#define XADC_AXI_REG_CONVST             0x0c
  92#define XADC_AXI_REG_XADC_RESET         0x10
  93#define XADC_AXI_REG_GIER               0x5c
  94#define XADC_AXI_REG_IPISR              0x60
  95#define XADC_AXI_REG_IPIER              0x68
  96#define XADC_AXI_ADC_REG_OFFSET         0x200
  97
  98#define XADC_AXI_RESET_MAGIC            0xa
  99#define XADC_AXI_GIER_ENABLE            BIT(31)
 100
 101#define XADC_AXI_INT_EOS                BIT(4)
 102#define XADC_AXI_INT_ALARM_MASK         0x3c0f
 103
 104#define XADC_FLAGS_BUFFERED BIT(0)
 105
 106static void xadc_write_reg(struct xadc *xadc, unsigned int reg,
 107        uint32_t val)
 108{
 109        writel(val, xadc->base + reg);
 110}
 111
 112static void xadc_read_reg(struct xadc *xadc, unsigned int reg,
 113        uint32_t *val)
 114{
 115        *val = readl(xadc->base + reg);
 116}
 117
 118/*
 119 * The ZYNQ interface uses two asynchronous FIFOs for communication with the
 120 * XADC. Reads and writes to the XADC register are performed by submitting a
 121 * request to the command FIFO (CFIFO), once the request has been completed the
 122 * result can be read from the data FIFO (DFIFO). The method currently used in
 123 * this driver is to submit the request for a read/write operation, then go to
 124 * sleep and wait for an interrupt that signals that a response is available in
 125 * the data FIFO.
 126 */
 127
 128static void xadc_zynq_write_fifo(struct xadc *xadc, uint32_t *cmd,
 129        unsigned int n)
 130{
 131        unsigned int i;
 132
 133        for (i = 0; i < n; i++)
 134                xadc_write_reg(xadc, XADC_ZYNQ_REG_CFIFO, cmd[i]);
 135}
 136
 137static void xadc_zynq_drain_fifo(struct xadc *xadc)
 138{
 139        uint32_t status, tmp;
 140
 141        xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
 142
 143        while (!(status & XADC_ZYNQ_STATUS_DFIFOE)) {
 144                xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
 145                xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
 146        }
 147}
 148
 149static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask,
 150        unsigned int val)
 151{
 152        xadc->zynq_intmask &= ~mask;
 153        xadc->zynq_intmask |= val;
 154
 155        xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK,
 156                xadc->zynq_intmask | xadc->zynq_masked_alarm);
 157}
 158
 159static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg,
 160        uint16_t val)
 161{
 162        uint32_t cmd[1];
 163        uint32_t tmp;
 164        int ret;
 165
 166        spin_lock_irq(&xadc->lock);
 167        xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
 168                        XADC_ZYNQ_INT_DFIFO_GTH);
 169
 170        reinit_completion(&xadc->completion);
 171
 172        cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val);
 173        xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
 174        xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
 175        tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
 176        tmp |= 0 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
 177        xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
 178
 179        xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
 180        spin_unlock_irq(&xadc->lock);
 181
 182        ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
 183        if (ret == 0)
 184                ret = -EIO;
 185        else
 186                ret = 0;
 187
 188        xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
 189
 190        return ret;
 191}
 192
 193static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg,
 194        uint16_t *val)
 195{
 196        uint32_t cmd[2];
 197        uint32_t resp, tmp;
 198        int ret;
 199
 200        cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_READ, reg, 0);
 201        cmd[1] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_NOP, 0, 0);
 202
 203        spin_lock_irq(&xadc->lock);
 204        xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
 205                        XADC_ZYNQ_INT_DFIFO_GTH);
 206        xadc_zynq_drain_fifo(xadc);
 207        reinit_completion(&xadc->completion);
 208
 209        xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
 210        xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
 211        tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
 212        tmp |= 1 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
 213        xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
 214
 215        xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
 216        spin_unlock_irq(&xadc->lock);
 217        ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
 218        if (ret == 0)
 219                ret = -EIO;
 220        if (ret < 0)
 221                return ret;
 222
 223        xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
 224        xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
 225
 226        *val = resp & 0xffff;
 227
 228        return 0;
 229}
 230
 231static unsigned int xadc_zynq_transform_alarm(unsigned int alarm)
 232{
 233        return ((alarm & 0x80) >> 4) |
 234                ((alarm & 0x78) << 1) |
 235                (alarm & 0x07);
 236}
 237
 238/*
 239 * The ZYNQ threshold interrupts are level sensitive. Since we can't make the
 240 * threshold condition go way from within the interrupt handler, this means as
 241 * soon as a threshold condition is present we would enter the interrupt handler
 242 * again and again. To work around this we mask all active thresholds interrupts
 243 * in the interrupt handler and start a timer. In this timer we poll the
 244 * interrupt status and only if the interrupt is inactive we unmask it again.
 245 */
 246static void xadc_zynq_unmask_worker(struct work_struct *work)
 247{
 248        struct xadc *xadc = container_of(work, struct xadc, zynq_unmask_work.work);
 249        unsigned int misc_sts, unmask;
 250
 251        xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &misc_sts);
 252
 253        misc_sts &= XADC_ZYNQ_INT_ALARM_MASK;
 254
 255        spin_lock_irq(&xadc->lock);
 256
 257        /* Clear those bits which are not active anymore */
 258        unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;
 259        xadc->zynq_masked_alarm &= misc_sts;
 260
 261        /* Also clear those which are masked out anyway */
 262        xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;
 263
 264        /* Clear the interrupts before we unmask them */
 265        xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);
 266
 267        xadc_zynq_update_intmsk(xadc, 0, 0);
 268
 269        spin_unlock_irq(&xadc->lock);
 270
 271        /* if still pending some alarm re-trigger the timer */
 272        if (xadc->zynq_masked_alarm) {
 273                schedule_delayed_work(&xadc->zynq_unmask_work,
 274                                msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
 275        }
 276}
 277
 278static irqreturn_t xadc_zynq_threaded_interrupt_handler(int irq, void *devid)
 279{
 280        struct iio_dev *indio_dev = devid;
 281        struct xadc *xadc = iio_priv(indio_dev);
 282        unsigned int alarm;
 283
 284        spin_lock_irq(&xadc->lock);
 285        alarm = xadc->zynq_alarm;
 286        xadc->zynq_alarm = 0;
 287        spin_unlock_irq(&xadc->lock);
 288
 289        xadc_handle_events(indio_dev, xadc_zynq_transform_alarm(alarm));
 290
 291        /* unmask the required interrupts in timer. */
 292        schedule_delayed_work(&xadc->zynq_unmask_work,
 293                        msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
 294
 295        return IRQ_HANDLED;
 296}
 297
 298static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid)
 299{
 300        struct iio_dev *indio_dev = devid;
 301        struct xadc *xadc = iio_priv(indio_dev);
 302        irqreturn_t ret = IRQ_HANDLED;
 303        uint32_t status;
 304
 305        xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
 306
 307        status &= ~(xadc->zynq_intmask | xadc->zynq_masked_alarm);
 308
 309        if (!status)
 310                return IRQ_NONE;
 311
 312        spin_lock(&xadc->lock);
 313
 314        xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status);
 315
 316        if (status & XADC_ZYNQ_INT_DFIFO_GTH) {
 317                xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
 318                        XADC_ZYNQ_INT_DFIFO_GTH);
 319                complete(&xadc->completion);
 320        }
 321
 322        status &= XADC_ZYNQ_INT_ALARM_MASK;
 323        if (status) {
 324                xadc->zynq_alarm |= status;
 325                xadc->zynq_masked_alarm |= status;
 326                /*
 327                 * mask the current event interrupt,
 328                 * unmask it when the interrupt is no more active.
 329                 */
 330                xadc_zynq_update_intmsk(xadc, 0, 0);
 331                ret = IRQ_WAKE_THREAD;
 332        }
 333        spin_unlock(&xadc->lock);
 334
 335        return ret;
 336}
 337
 338#define XADC_ZYNQ_TCK_RATE_MAX 50000000
 339#define XADC_ZYNQ_IGAP_DEFAULT 20
 340
 341static int xadc_zynq_setup(struct platform_device *pdev,
 342        struct iio_dev *indio_dev, int irq)
 343{
 344        struct xadc *xadc = iio_priv(indio_dev);
 345        unsigned long pcap_rate;
 346        unsigned int tck_div;
 347        unsigned int div;
 348        unsigned int igap;
 349        unsigned int tck_rate;
 350
 351        /* TODO: Figure out how to make igap and tck_rate configurable */
 352        igap = XADC_ZYNQ_IGAP_DEFAULT;
 353        tck_rate = XADC_ZYNQ_TCK_RATE_MAX;
 354
 355        xadc->zynq_intmask = ~0;
 356
 357        pcap_rate = clk_get_rate(xadc->clk);
 358
 359        if (tck_rate > XADC_ZYNQ_TCK_RATE_MAX)
 360                tck_rate = XADC_ZYNQ_TCK_RATE_MAX;
 361        if (tck_rate > pcap_rate / 2) {
 362                div = 2;
 363        } else {
 364                div = pcap_rate / tck_rate;
 365                if (pcap_rate / div > XADC_ZYNQ_TCK_RATE_MAX)
 366                        div++;
 367        }
 368
 369        if (div <= 3)
 370                tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV2;
 371        else if (div <= 7)
 372                tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV4;
 373        else if (div <= 15)
 374                tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV8;
 375        else
 376                tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV16;
 377
 378        xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, XADC_ZYNQ_CTL_RESET);
 379        xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, 0);
 380        xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);
 381        xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);
 382        xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE |
 383                        XADC_ZYNQ_CFG_REDGE | XADC_ZYNQ_CFG_WEDGE |
 384                        tck_div | XADC_ZYNQ_CFG_IGAP(igap));
 385
 386        return 0;
 387}
 388
 389static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)
 390{
 391        unsigned int div;
 392        uint32_t val;
 393
 394        xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val);
 395
 396        switch (val & XADC_ZYNQ_CFG_TCKRATE_MASK) {
 397        case XADC_ZYNQ_CFG_TCKRATE_DIV4:
 398                div = 4;
 399                break;
 400        case XADC_ZYNQ_CFG_TCKRATE_DIV8:
 401                div = 8;
 402                break;
 403        case XADC_ZYNQ_CFG_TCKRATE_DIV16:
 404                div = 16;
 405                break;
 406        default:
 407                div = 2;
 408                break;
 409        }
 410
 411        return clk_get_rate(xadc->clk) / div;
 412}
 413
 414static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm)
 415{
 416        unsigned long flags;
 417        uint32_t status;
 418
 419        /* Move OT to bit 7 */
 420        alarm = ((alarm & 0x08) << 4) | ((alarm & 0xf0) >> 1) | (alarm & 0x07);
 421
 422        spin_lock_irqsave(&xadc->lock, flags);
 423
 424        /* Clear previous interrupts if any. */
 425        xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
 426        xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm);
 427
 428        xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK,
 429                ~alarm & XADC_ZYNQ_INT_ALARM_MASK);
 430
 431        spin_unlock_irqrestore(&xadc->lock, flags);
 432}
 433
 434static const struct xadc_ops xadc_zynq_ops = {
 435        .read = xadc_zynq_read_adc_reg,
 436        .write = xadc_zynq_write_adc_reg,
 437        .setup = xadc_zynq_setup,
 438        .get_dclk_rate = xadc_zynq_get_dclk_rate,
 439        .interrupt_handler = xadc_zynq_interrupt_handler,
 440        .threaded_interrupt_handler = xadc_zynq_threaded_interrupt_handler,
 441        .update_alarm = xadc_zynq_update_alarm,
 442};
 443
 444static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg,
 445        uint16_t *val)
 446{
 447        uint32_t val32;
 448
 449        xadc_read_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, &val32);
 450        *val = val32 & 0xffff;
 451
 452        return 0;
 453}
 454
 455static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg,
 456        uint16_t val)
 457{
 458        xadc_write_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, val);
 459
 460        return 0;
 461}
 462
 463static int xadc_axi_setup(struct platform_device *pdev,
 464        struct iio_dev *indio_dev, int irq)
 465{
 466        struct xadc *xadc = iio_priv(indio_dev);
 467
 468        xadc_write_reg(xadc, XADC_AXI_REG_RESET, XADC_AXI_RESET_MAGIC);
 469        xadc_write_reg(xadc, XADC_AXI_REG_GIER, XADC_AXI_GIER_ENABLE);
 470
 471        return 0;
 472}
 473
 474static irqreturn_t xadc_axi_interrupt_handler(int irq, void *devid)
 475{
 476        struct iio_dev *indio_dev = devid;
 477        struct xadc *xadc = iio_priv(indio_dev);
 478        uint32_t status, mask;
 479        unsigned int events;
 480
 481        xadc_read_reg(xadc, XADC_AXI_REG_IPISR, &status);
 482        xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &mask);
 483        status &= mask;
 484
 485        if (!status)
 486                return IRQ_NONE;
 487
 488        if ((status & XADC_AXI_INT_EOS) && xadc->trigger)
 489                iio_trigger_poll(xadc->trigger);
 490
 491        if (status & XADC_AXI_INT_ALARM_MASK) {
 492                /*
 493                 * The order of the bits in the AXI-XADC status register does
 494                 * not match the order of the bits in the XADC alarm enable
 495                 * register. xadc_handle_events() expects the events to be in
 496                 * the same order as the XADC alarm enable register.
 497                 */
 498                events = (status & 0x000e) >> 1;
 499                events |= (status & 0x0001) << 3;
 500                events |= (status & 0x3c00) >> 6;
 501                xadc_handle_events(indio_dev, events);
 502        }
 503
 504        xadc_write_reg(xadc, XADC_AXI_REG_IPISR, status);
 505
 506        return IRQ_HANDLED;
 507}
 508
 509static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)
 510{
 511        uint32_t val;
 512        unsigned long flags;
 513
 514        /*
 515         * The order of the bits in the AXI-XADC status register does not match
 516         * the order of the bits in the XADC alarm enable register. We get
 517         * passed the alarm mask in the same order as in the XADC alarm enable
 518         * register.
 519         */
 520        alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) |
 521                        ((alarm & 0xf0) << 6);
 522
 523        spin_lock_irqsave(&xadc->lock, flags);
 524        xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
 525        val &= ~XADC_AXI_INT_ALARM_MASK;
 526        val |= alarm;
 527        xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
 528        spin_unlock_irqrestore(&xadc->lock, flags);
 529}
 530
 531static unsigned long xadc_axi_get_dclk(struct xadc *xadc)
 532{
 533        return clk_get_rate(xadc->clk);
 534}
 535
 536static const struct xadc_ops xadc_axi_ops = {
 537        .read = xadc_axi_read_adc_reg,
 538        .write = xadc_axi_write_adc_reg,
 539        .setup = xadc_axi_setup,
 540        .get_dclk_rate = xadc_axi_get_dclk,
 541        .update_alarm = xadc_axi_update_alarm,
 542        .interrupt_handler = xadc_axi_interrupt_handler,
 543        .flags = XADC_FLAGS_BUFFERED,
 544};
 545
 546static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
 547        uint16_t mask, uint16_t val)
 548{
 549        uint16_t tmp;
 550        int ret;
 551
 552        ret = _xadc_read_adc_reg(xadc, reg, &tmp);
 553        if (ret)
 554                return ret;
 555
 556        return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val);
 557}
 558
 559static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
 560        uint16_t mask, uint16_t val)
 561{
 562        int ret;
 563
 564        mutex_lock(&xadc->mutex);
 565        ret = _xadc_update_adc_reg(xadc, reg, mask, val);
 566        mutex_unlock(&xadc->mutex);
 567
 568        return ret;
 569}
 570
 571static unsigned long xadc_get_dclk_rate(struct xadc *xadc)
 572{
 573        return xadc->ops->get_dclk_rate(xadc);
 574}
 575
 576static int xadc_update_scan_mode(struct iio_dev *indio_dev,
 577        const unsigned long *mask)
 578{
 579        struct xadc *xadc = iio_priv(indio_dev);
 580        unsigned int n;
 581
 582        n = bitmap_weight(mask, indio_dev->masklength);
 583
 584        kfree(xadc->data);
 585        xadc->data = kcalloc(n, sizeof(*xadc->data), GFP_KERNEL);
 586        if (!xadc->data)
 587                return -ENOMEM;
 588
 589        return 0;
 590}
 591
 592static unsigned int xadc_scan_index_to_channel(unsigned int scan_index)
 593{
 594        switch (scan_index) {
 595        case 5:
 596                return XADC_REG_VCCPINT;
 597        case 6:
 598                return XADC_REG_VCCPAUX;
 599        case 7:
 600                return XADC_REG_VCCO_DDR;
 601        case 8:
 602                return XADC_REG_TEMP;
 603        case 9:
 604                return XADC_REG_VCCINT;
 605        case 10:
 606                return XADC_REG_VCCAUX;
 607        case 11:
 608                return XADC_REG_VPVN;
 609        case 12:
 610                return XADC_REG_VREFP;
 611        case 13:
 612                return XADC_REG_VREFN;
 613        case 14:
 614                return XADC_REG_VCCBRAM;
 615        default:
 616                return XADC_REG_VAUX(scan_index - 16);
 617        }
 618}
 619
 620static irqreturn_t xadc_trigger_handler(int irq, void *p)
 621{
 622        struct iio_poll_func *pf = p;
 623        struct iio_dev *indio_dev = pf->indio_dev;
 624        struct xadc *xadc = iio_priv(indio_dev);
 625        unsigned int chan;
 626        int i, j;
 627
 628        if (!xadc->data)
 629                goto out;
 630
 631        j = 0;
 632        for_each_set_bit(i, indio_dev->active_scan_mask,
 633                indio_dev->masklength) {
 634                chan = xadc_scan_index_to_channel(i);
 635                xadc_read_adc_reg(xadc, chan, &xadc->data[j]);
 636                j++;
 637        }
 638
 639        iio_push_to_buffers(indio_dev, xadc->data);
 640
 641out:
 642        iio_trigger_notify_done(indio_dev->trig);
 643
 644        return IRQ_HANDLED;
 645}
 646
 647static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
 648{
 649        struct xadc *xadc = iio_trigger_get_drvdata(trigger);
 650        unsigned long flags;
 651        unsigned int convst;
 652        unsigned int val;
 653        int ret = 0;
 654
 655        mutex_lock(&xadc->mutex);
 656
 657        if (state) {
 658                /* Only one of the two triggers can be active at the a time. */
 659                if (xadc->trigger != NULL) {
 660                        ret = -EBUSY;
 661                        goto err_out;
 662                } else {
 663                        xadc->trigger = trigger;
 664                        if (trigger == xadc->convst_trigger)
 665                                convst = XADC_CONF0_EC;
 666                        else
 667                                convst = 0;
 668                }
 669                ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC,
 670                                        convst);
 671                if (ret)
 672                        goto err_out;
 673        } else {
 674                xadc->trigger = NULL;
 675        }
 676
 677        spin_lock_irqsave(&xadc->lock, flags);
 678        xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
 679        xadc_write_reg(xadc, XADC_AXI_REG_IPISR, val & XADC_AXI_INT_EOS);
 680        if (state)
 681                val |= XADC_AXI_INT_EOS;
 682        else
 683                val &= ~XADC_AXI_INT_EOS;
 684        xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
 685        spin_unlock_irqrestore(&xadc->lock, flags);
 686
 687err_out:
 688        mutex_unlock(&xadc->mutex);
 689
 690        return ret;
 691}
 692
 693static const struct iio_trigger_ops xadc_trigger_ops = {
 694        .owner = THIS_MODULE,
 695        .set_trigger_state = &xadc_trigger_set_state,
 696};
 697
 698static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev,
 699        const char *name)
 700{
 701        struct iio_trigger *trig;
 702        int ret;
 703
 704        trig = iio_trigger_alloc("%s%d-%s", indio_dev->name,
 705                                indio_dev->id, name);
 706        if (trig == NULL)
 707                return ERR_PTR(-ENOMEM);
 708
 709        trig->dev.parent = indio_dev->dev.parent;
 710        trig->ops = &xadc_trigger_ops;
 711        iio_trigger_set_drvdata(trig, iio_priv(indio_dev));
 712
 713        ret = iio_trigger_register(trig);
 714        if (ret)
 715                goto error_free_trig;
 716
 717        return trig;
 718
 719error_free_trig:
 720        iio_trigger_free(trig);
 721        return ERR_PTR(ret);
 722}
 723
 724static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)
 725{
 726        uint16_t val;
 727
 728        switch (seq_mode) {
 729        case XADC_CONF1_SEQ_SIMULTANEOUS:
 730        case XADC_CONF1_SEQ_INDEPENDENT:
 731                val = XADC_CONF2_PD_ADC_B;
 732                break;
 733        default:
 734                val = 0;
 735                break;
 736        }
 737
 738        return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK,
 739                val);
 740}
 741
 742static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)
 743{
 744        unsigned int aux_scan_mode = scan_mode >> 16;
 745
 746        if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)
 747                return XADC_CONF1_SEQ_SIMULTANEOUS;
 748
 749        if ((aux_scan_mode & 0xff00) == 0 ||
 750                (aux_scan_mode & 0x00ff) == 0)
 751                return XADC_CONF1_SEQ_CONTINUOUS;
 752
 753        return XADC_CONF1_SEQ_SIMULTANEOUS;
 754}
 755
 756static int xadc_postdisable(struct iio_dev *indio_dev)
 757{
 758        struct xadc *xadc = iio_priv(indio_dev);
 759        unsigned long scan_mask;
 760        int ret;
 761        int i;
 762
 763        scan_mask = 1; /* Run calibration as part of the sequence */
 764        for (i = 0; i < indio_dev->num_channels; i++)
 765                scan_mask |= BIT(indio_dev->channels[i].scan_index);
 766
 767        /* Enable all channels and calibration */
 768        ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
 769        if (ret)
 770                return ret;
 771
 772        ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
 773        if (ret)
 774                return ret;
 775
 776        ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
 777                XADC_CONF1_SEQ_CONTINUOUS);
 778        if (ret)
 779                return ret;
 780
 781        return xadc_power_adc_b(xadc, XADC_CONF1_SEQ_CONTINUOUS);
 782}
 783
 784static int xadc_preenable(struct iio_dev *indio_dev)
 785{
 786        struct xadc *xadc = iio_priv(indio_dev);
 787        unsigned long scan_mask;
 788        int seq_mode;
 789        int ret;
 790
 791        ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
 792                XADC_CONF1_SEQ_DEFAULT);
 793        if (ret)
 794                goto err;
 795
 796        scan_mask = *indio_dev->active_scan_mask;
 797        seq_mode = xadc_get_seq_mode(xadc, scan_mask);
 798
 799        ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
 800        if (ret)
 801                goto err;
 802
 803        ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
 804        if (ret)
 805                goto err;
 806
 807        ret = xadc_power_adc_b(xadc, seq_mode);
 808        if (ret)
 809                goto err;
 810
 811        ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
 812                seq_mode);
 813        if (ret)
 814                goto err;
 815
 816        return 0;
 817err:
 818        xadc_postdisable(indio_dev);
 819        return ret;
 820}
 821
 822static struct iio_buffer_setup_ops xadc_buffer_ops = {
 823        .preenable = &xadc_preenable,
 824        .postenable = &iio_triggered_buffer_postenable,
 825        .predisable = &iio_triggered_buffer_predisable,
 826        .postdisable = &xadc_postdisable,
 827};
 828
 829static int xadc_read_raw(struct iio_dev *indio_dev,
 830        struct iio_chan_spec const *chan, int *val, int *val2, long info)
 831{
 832        struct xadc *xadc = iio_priv(indio_dev);
 833        unsigned int div;
 834        uint16_t val16;
 835        int ret;
 836
 837        switch (info) {
 838        case IIO_CHAN_INFO_RAW:
 839                if (iio_buffer_enabled(indio_dev))
 840                        return -EBUSY;
 841                ret = xadc_read_adc_reg(xadc, chan->address, &val16);
 842                if (ret < 0)
 843                        return ret;
 844
 845                val16 >>= 4;
 846                if (chan->scan_type.sign == 'u')
 847                        *val = val16;
 848                else
 849                        *val = sign_extend32(val16, 11);
 850
 851                return IIO_VAL_INT;
 852        case IIO_CHAN_INFO_SCALE:
 853                switch (chan->type) {
 854                case IIO_VOLTAGE:
 855                        /* V = (val * 3.0) / 4096 */
 856                        switch (chan->address) {
 857                        case XADC_REG_VCCINT:
 858                        case XADC_REG_VCCAUX:
 859                        case XADC_REG_VCCBRAM:
 860                        case XADC_REG_VCCPINT:
 861                        case XADC_REG_VCCPAUX:
 862                        case XADC_REG_VCCO_DDR:
 863                                *val = 3000;
 864                                break;
 865                        default:
 866                                *val = 1000;
 867                                break;
 868                        }
 869                        *val2 = 12;
 870                        return IIO_VAL_FRACTIONAL_LOG2;
 871                case IIO_TEMP:
 872                        /* Temp in C = (val * 503.975) / 4096 - 273.15 */
 873                        *val = 503975;
 874                        *val2 = 12;
 875                        return IIO_VAL_FRACTIONAL_LOG2;
 876                default:
 877                        return -EINVAL;
 878                }
 879        case IIO_CHAN_INFO_OFFSET:
 880                /* Only the temperature channel has an offset */
 881                *val = -((273150 << 12) / 503975);
 882                return IIO_VAL_INT;
 883        case IIO_CHAN_INFO_SAMP_FREQ:
 884                ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16);
 885                if (ret)
 886                        return ret;
 887
 888                div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET;
 889                if (div < 2)
 890                        div = 2;
 891
 892                *val = xadc_get_dclk_rate(xadc) / div / 26;
 893
 894                return IIO_VAL_INT;
 895        default:
 896                return -EINVAL;
 897        }
 898}
 899
 900static int xadc_write_raw(struct iio_dev *indio_dev,
 901        struct iio_chan_spec const *chan, int val, int val2, long info)
 902{
 903        struct xadc *xadc = iio_priv(indio_dev);
 904        unsigned long clk_rate = xadc_get_dclk_rate(xadc);
 905        unsigned int div;
 906
 907        if (info != IIO_CHAN_INFO_SAMP_FREQ)
 908                return -EINVAL;
 909
 910        if (val <= 0)
 911                return -EINVAL;
 912
 913        /* Max. 150 kSPS */
 914        if (val > 150000)
 915                val = 150000;
 916
 917        val *= 26;
 918
 919        /* Min 1MHz */
 920        if (val < 1000000)
 921                val = 1000000;
 922
 923        /*
 924         * We want to round down, but only if we do not exceed the 150 kSPS
 925         * limit.
 926         */
 927        div = clk_rate / val;
 928        if (clk_rate / div / 26 > 150000)
 929                div++;
 930        if (div < 2)
 931                div = 2;
 932        else if (div > 0xff)
 933                div = 0xff;
 934
 935        return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK,
 936                div << XADC_CONF2_DIV_OFFSET);
 937}
 938
 939static const struct iio_event_spec xadc_temp_events[] = {
 940        {
 941                .type = IIO_EV_TYPE_THRESH,
 942                .dir = IIO_EV_DIR_RISING,
 943                .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
 944                                BIT(IIO_EV_INFO_VALUE) |
 945                                BIT(IIO_EV_INFO_HYSTERESIS),
 946        },
 947};
 948
 949/* Separate values for upper and lower thresholds, but only a shared enabled */
 950static const struct iio_event_spec xadc_voltage_events[] = {
 951        {
 952                .type = IIO_EV_TYPE_THRESH,
 953                .dir = IIO_EV_DIR_RISING,
 954                .mask_separate = BIT(IIO_EV_INFO_VALUE),
 955        }, {
 956                .type = IIO_EV_TYPE_THRESH,
 957                .dir = IIO_EV_DIR_FALLING,
 958                .mask_separate = BIT(IIO_EV_INFO_VALUE),
 959        }, {
 960                .type = IIO_EV_TYPE_THRESH,
 961                .dir = IIO_EV_DIR_EITHER,
 962                .mask_separate = BIT(IIO_EV_INFO_ENABLE),
 963        },
 964};
 965
 966#define XADC_CHAN_TEMP(_chan, _scan_index, _addr) { \
 967        .type = IIO_TEMP, \
 968        .indexed = 1, \
 969        .channel = (_chan), \
 970        .address = (_addr), \
 971        .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
 972                BIT(IIO_CHAN_INFO_SCALE) | \
 973                BIT(IIO_CHAN_INFO_OFFSET), \
 974        .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
 975        .event_spec = xadc_temp_events, \
 976        .num_event_specs = ARRAY_SIZE(xadc_temp_events), \
 977        .scan_index = (_scan_index), \
 978        .scan_type = { \
 979                .sign = 'u', \
 980                .realbits = 12, \
 981                .storagebits = 16, \
 982                .shift = 4, \
 983                .endianness = IIO_CPU, \
 984        }, \
 985}
 986
 987#define XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) { \
 988        .type = IIO_VOLTAGE, \
 989        .indexed = 1, \
 990        .channel = (_chan), \
 991        .address = (_addr), \
 992        .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
 993                BIT(IIO_CHAN_INFO_SCALE), \
 994        .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
 995        .event_spec = (_alarm) ? xadc_voltage_events : NULL, \
 996        .num_event_specs = (_alarm) ? ARRAY_SIZE(xadc_voltage_events) : 0, \
 997        .scan_index = (_scan_index), \
 998        .scan_type = { \
 999                .sign = 'u', \
1000                .realbits = 12, \
1001                .storagebits = 16, \
1002                .shift = 4, \
1003                .endianness = IIO_CPU, \
1004        }, \
1005        .extend_name = _ext, \
1006}
1007
1008static const struct iio_chan_spec xadc_channels[] = {
1009        XADC_CHAN_TEMP(0, 8, XADC_REG_TEMP),
1010        XADC_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
1011        XADC_CHAN_VOLTAGE(1, 10, XADC_REG_VCCINT, "vccaux", true),
1012        XADC_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
1013        XADC_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpint", true),
1014        XADC_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpaux", true),
1015        XADC_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccoddr", true),
1016        XADC_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
1017        XADC_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
1018        XADC_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
1019        XADC_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
1020        XADC_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
1021        XADC_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
1022        XADC_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
1023        XADC_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
1024        XADC_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
1025        XADC_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
1026        XADC_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
1027        XADC_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
1028        XADC_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
1029        XADC_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
1030        XADC_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
1031        XADC_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
1032        XADC_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
1033        XADC_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
1034        XADC_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
1035};
1036
1037static const struct iio_info xadc_info = {
1038        .read_raw = &xadc_read_raw,
1039        .write_raw = &xadc_write_raw,
1040        .read_event_config = &xadc_read_event_config,
1041        .write_event_config = &xadc_write_event_config,
1042        .read_event_value = &xadc_read_event_value,
1043        .write_event_value = &xadc_write_event_value,
1044        .update_scan_mode = &xadc_update_scan_mode,
1045        .driver_module = THIS_MODULE,
1046};
1047
1048static const struct of_device_id xadc_of_match_table[] = {
1049        { .compatible = "xlnx,zynq-xadc-1.00.a", (void *)&xadc_zynq_ops },
1050        { .compatible = "xlnx,axi-xadc-1.00.a", (void *)&xadc_axi_ops },
1051        { },
1052};
1053MODULE_DEVICE_TABLE(of, xadc_of_match_table);
1054
1055static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np,
1056        unsigned int *conf)
1057{
1058        struct xadc *xadc = iio_priv(indio_dev);
1059        struct iio_chan_spec *channels, *chan;
1060        struct device_node *chan_node, *child;
1061        unsigned int num_channels;
1062        const char *external_mux;
1063        u32 ext_mux_chan;
1064        int reg;
1065        int ret;
1066
1067        *conf = 0;
1068
1069        ret = of_property_read_string(np, "xlnx,external-mux", &external_mux);
1070        if (ret < 0 || strcasecmp(external_mux, "none") == 0)
1071                xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE;
1072        else if (strcasecmp(external_mux, "single") == 0)
1073                xadc->external_mux_mode = XADC_EXTERNAL_MUX_SINGLE;
1074        else if (strcasecmp(external_mux, "dual") == 0)
1075                xadc->external_mux_mode = XADC_EXTERNAL_MUX_DUAL;
1076        else
1077                return -EINVAL;
1078
1079        if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) {
1080                ret = of_property_read_u32(np, "xlnx,external-mux-channel",
1081                                        &ext_mux_chan);
1082                if (ret < 0)
1083                        return ret;
1084
1085                if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_SINGLE) {
1086                        if (ext_mux_chan == 0)
1087                                ext_mux_chan = XADC_REG_VPVN;
1088                        else if (ext_mux_chan <= 16)
1089                                ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
1090                        else
1091                                return -EINVAL;
1092                } else {
1093                        if (ext_mux_chan > 0 && ext_mux_chan <= 8)
1094                                ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
1095                        else
1096                                return -EINVAL;
1097                }
1098
1099                *conf |= XADC_CONF0_MUX | XADC_CONF0_CHAN(ext_mux_chan);
1100        }
1101
1102        channels = kmemdup(xadc_channels, sizeof(xadc_channels), GFP_KERNEL);
1103        if (!channels)
1104                return -ENOMEM;
1105
1106        num_channels = 9;
1107        chan = &channels[9];
1108
1109        chan_node = of_get_child_by_name(np, "xlnx,channels");
1110        if (chan_node) {
1111                for_each_child_of_node(chan_node, child) {
1112                        if (num_channels >= ARRAY_SIZE(xadc_channels)) {
1113                                of_node_put(child);
1114                                break;
1115                        }
1116
1117                        ret = of_property_read_u32(child, "reg", &reg);
1118                        if (ret || reg > 16)
1119                                continue;
1120
1121                        if (of_property_read_bool(child, "xlnx,bipolar"))
1122                                chan->scan_type.sign = 's';
1123
1124                        if (reg == 0) {
1125                                chan->scan_index = 11;
1126                                chan->address = XADC_REG_VPVN;
1127                        } else {
1128                                chan->scan_index = 15 + reg;
1129                                chan->address = XADC_REG_VAUX(reg - 1);
1130                        }
1131                        num_channels++;
1132                        chan++;
1133                }
1134        }
1135        of_node_put(chan_node);
1136
1137        indio_dev->num_channels = num_channels;
1138        indio_dev->channels = krealloc(channels, sizeof(*channels) *
1139                                        num_channels, GFP_KERNEL);
1140        /* If we can't resize the channels array, just use the original */
1141        if (!indio_dev->channels)
1142                indio_dev->channels = channels;
1143
1144        return 0;
1145}
1146
1147static int xadc_probe(struct platform_device *pdev)
1148{
1149        const struct of_device_id *id;
1150        struct iio_dev *indio_dev;
1151        unsigned int bipolar_mask;
1152        struct resource *mem;
1153        unsigned int conf0;
1154        struct xadc *xadc;
1155        int ret;
1156        int irq;
1157        int i;
1158
1159        if (!pdev->dev.of_node)
1160                return -ENODEV;
1161
1162        id = of_match_node(xadc_of_match_table, pdev->dev.of_node);
1163        if (!id)
1164                return -EINVAL;
1165
1166        irq = platform_get_irq(pdev, 0);
1167        if (irq <= 0)
1168                return -ENXIO;
1169
1170        indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*xadc));
1171        if (!indio_dev)
1172                return -ENOMEM;
1173
1174        xadc = iio_priv(indio_dev);
1175        xadc->ops = id->data;
1176        init_completion(&xadc->completion);
1177        mutex_init(&xadc->mutex);
1178        spin_lock_init(&xadc->lock);
1179        INIT_DELAYED_WORK(&xadc->zynq_unmask_work, xadc_zynq_unmask_worker);
1180
1181        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1182        xadc->base = devm_ioremap_resource(&pdev->dev, mem);
1183        if (IS_ERR(xadc->base))
1184                return PTR_ERR(xadc->base);
1185
1186        indio_dev->dev.parent = &pdev->dev;
1187        indio_dev->dev.of_node = pdev->dev.of_node;
1188        indio_dev->name = "xadc";
1189        indio_dev->modes = INDIO_DIRECT_MODE;
1190        indio_dev->info = &xadc_info;
1191
1192        ret = xadc_parse_dt(indio_dev, pdev->dev.of_node, &conf0);
1193        if (ret)
1194                goto err_device_free;
1195
1196        if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
1197                ret = iio_triggered_buffer_setup(indio_dev,
1198                        &iio_pollfunc_store_time, &xadc_trigger_handler,
1199                        &xadc_buffer_ops);
1200                if (ret)
1201                        goto err_device_free;
1202
1203                xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst");
1204                if (IS_ERR(xadc->convst_trigger)) {
1205                        ret = PTR_ERR(xadc->convst_trigger);
1206                        goto err_triggered_buffer_cleanup;
1207                }
1208                xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev,
1209                        "samplerate");
1210                if (IS_ERR(xadc->samplerate_trigger)) {
1211                        ret = PTR_ERR(xadc->samplerate_trigger);
1212                        goto err_free_convst_trigger;
1213                }
1214        }
1215
1216        xadc->clk = devm_clk_get(&pdev->dev, NULL);
1217        if (IS_ERR(xadc->clk)) {
1218                ret = PTR_ERR(xadc->clk);
1219                goto err_free_samplerate_trigger;
1220        }
1221        clk_prepare_enable(xadc->clk);
1222
1223        ret = xadc->ops->setup(pdev, indio_dev, irq);
1224        if (ret)
1225                goto err_free_samplerate_trigger;
1226
1227        ret = request_threaded_irq(irq, xadc->ops->interrupt_handler,
1228                                xadc->ops->threaded_interrupt_handler,
1229                                0, dev_name(&pdev->dev), indio_dev);
1230        if (ret)
1231                goto err_clk_disable_unprepare;
1232
1233        for (i = 0; i < 16; i++)
1234                xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i),
1235                        &xadc->threshold[i]);
1236
1237        ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0);
1238        if (ret)
1239                goto err_free_irq;
1240
1241        bipolar_mask = 0;
1242        for (i = 0; i < indio_dev->num_channels; i++) {
1243                if (indio_dev->channels[i].scan_type.sign == 's')
1244                        bipolar_mask |= BIT(indio_dev->channels[i].scan_index);
1245        }
1246
1247        ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(0), bipolar_mask);
1248        if (ret)
1249                goto err_free_irq;
1250        ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1),
1251                bipolar_mask >> 16);
1252        if (ret)
1253                goto err_free_irq;
1254
1255        /* Disable all alarms */
1256        xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_ALARM_MASK,
1257                XADC_CONF1_ALARM_MASK);
1258
1259        /* Set thresholds to min/max */
1260        for (i = 0; i < 16; i++) {
1261                /*
1262                 * Set max voltage threshold and both temperature thresholds to
1263                 * 0xffff, min voltage threshold to 0.
1264                 */
1265                if (i % 8 < 4 || i == 7)
1266                        xadc->threshold[i] = 0xffff;
1267                else
1268                        xadc->threshold[i] = 0;
1269                xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(i),
1270                        xadc->threshold[i]);
1271        }
1272
1273        /* Go to non-buffered mode */
1274        xadc_postdisable(indio_dev);
1275
1276        ret = iio_device_register(indio_dev);
1277        if (ret)
1278                goto err_free_irq;
1279
1280        platform_set_drvdata(pdev, indio_dev);
1281
1282        return 0;
1283
1284err_free_irq:
1285        free_irq(irq, indio_dev);
1286err_free_samplerate_trigger:
1287        if (xadc->ops->flags & XADC_FLAGS_BUFFERED)
1288                iio_trigger_free(xadc->samplerate_trigger);
1289err_free_convst_trigger:
1290        if (xadc->ops->flags & XADC_FLAGS_BUFFERED)
1291                iio_trigger_free(xadc->convst_trigger);
1292err_triggered_buffer_cleanup:
1293        if (xadc->ops->flags & XADC_FLAGS_BUFFERED)
1294                iio_triggered_buffer_cleanup(indio_dev);
1295err_clk_disable_unprepare:
1296        clk_disable_unprepare(xadc->clk);
1297err_device_free:
1298        kfree(indio_dev->channels);
1299
1300        return ret;
1301}
1302
1303static int xadc_remove(struct platform_device *pdev)
1304{
1305        struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1306        struct xadc *xadc = iio_priv(indio_dev);
1307        int irq = platform_get_irq(pdev, 0);
1308
1309        iio_device_unregister(indio_dev);
1310        if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
1311                iio_trigger_free(xadc->samplerate_trigger);
1312                iio_trigger_free(xadc->convst_trigger);
1313                iio_triggered_buffer_cleanup(indio_dev);
1314        }
1315        free_irq(irq, indio_dev);
1316        clk_disable_unprepare(xadc->clk);
1317        cancel_delayed_work(&xadc->zynq_unmask_work);
1318        kfree(xadc->data);
1319        kfree(indio_dev->channels);
1320
1321        return 0;
1322}
1323
1324static struct platform_driver xadc_driver = {
1325        .probe = xadc_probe,
1326        .remove = xadc_remove,
1327        .driver = {
1328                .name = "xadc",
1329                .of_match_table = xadc_of_match_table,
1330        },
1331};
1332module_platform_driver(xadc_driver);
1333
1334MODULE_LICENSE("GPL v2");
1335MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1336MODULE_DESCRIPTION("Xilinx XADC IIO driver");
1337
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