linux/drivers/i2c/busses/i2c-tegra.c
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   1/*
   2 * drivers/i2c/busses/i2c-tegra.c
   3 *
   4 * Copyright (C) 2010 Google, Inc.
   5 * Author: Colin Cross <ccross@android.com>
   6 *
   7 * This software is licensed under the terms of the GNU General Public
   8 * License version 2, as published by the Free Software Foundation, and
   9 * may be copied, distributed, and modified under those terms.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 */
  17
  18#include <linux/kernel.h>
  19#include <linux/init.h>
  20#include <linux/platform_device.h>
  21#include <linux/clk.h>
  22#include <linux/err.h>
  23#include <linux/i2c.h>
  24#include <linux/io.h>
  25#include <linux/interrupt.h>
  26#include <linux/delay.h>
  27#include <linux/slab.h>
  28#include <linux/of_device.h>
  29#include <linux/module.h>
  30#include <linux/reset.h>
  31
  32#include <asm/unaligned.h>
  33
  34#define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
  35#define BYTES_PER_FIFO_WORD 4
  36
  37#define I2C_CNFG                                0x000
  38#define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
  39#define I2C_CNFG_PACKET_MODE_EN                 (1<<10)
  40#define I2C_CNFG_NEW_MASTER_FSM                 (1<<11)
  41#define I2C_CNFG_MULTI_MASTER_MODE              (1<<17)
  42#define I2C_STATUS                              0x01C
  43#define I2C_SL_CNFG                             0x020
  44#define I2C_SL_CNFG_NACK                        (1<<1)
  45#define I2C_SL_CNFG_NEWSL                       (1<<2)
  46#define I2C_SL_ADDR1                            0x02c
  47#define I2C_SL_ADDR2                            0x030
  48#define I2C_TX_FIFO                             0x050
  49#define I2C_RX_FIFO                             0x054
  50#define I2C_PACKET_TRANSFER_STATUS              0x058
  51#define I2C_FIFO_CONTROL                        0x05c
  52#define I2C_FIFO_CONTROL_TX_FLUSH               (1<<1)
  53#define I2C_FIFO_CONTROL_RX_FLUSH               (1<<0)
  54#define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
  55#define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
  56#define I2C_FIFO_STATUS                         0x060
  57#define I2C_FIFO_STATUS_TX_MASK                 0xF0
  58#define I2C_FIFO_STATUS_TX_SHIFT                4
  59#define I2C_FIFO_STATUS_RX_MASK                 0x0F
  60#define I2C_FIFO_STATUS_RX_SHIFT                0
  61#define I2C_INT_MASK                            0x064
  62#define I2C_INT_STATUS                          0x068
  63#define I2C_INT_PACKET_XFER_COMPLETE            (1<<7)
  64#define I2C_INT_ALL_PACKETS_XFER_COMPLETE       (1<<6)
  65#define I2C_INT_TX_FIFO_OVERFLOW                (1<<5)
  66#define I2C_INT_RX_FIFO_UNDERFLOW               (1<<4)
  67#define I2C_INT_NO_ACK                          (1<<3)
  68#define I2C_INT_ARBITRATION_LOST                (1<<2)
  69#define I2C_INT_TX_FIFO_DATA_REQ                (1<<1)
  70#define I2C_INT_RX_FIFO_DATA_REQ                (1<<0)
  71#define I2C_CLK_DIVISOR                         0x06c
  72#define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT     16
  73#define I2C_CLK_MULTIPLIER_STD_FAST_MODE        8
  74
  75#define DVC_CTRL_REG1                           0x000
  76#define DVC_CTRL_REG1_INTR_EN                   (1<<10)
  77#define DVC_CTRL_REG2                           0x004
  78#define DVC_CTRL_REG3                           0x008
  79#define DVC_CTRL_REG3_SW_PROG                   (1<<26)
  80#define DVC_CTRL_REG3_I2C_DONE_INTR_EN          (1<<30)
  81#define DVC_STATUS                              0x00c
  82#define DVC_STATUS_I2C_DONE_INTR                (1<<30)
  83
  84#define I2C_ERR_NONE                            0x00
  85#define I2C_ERR_NO_ACK                          0x01
  86#define I2C_ERR_ARBITRATION_LOST                0x02
  87#define I2C_ERR_UNKNOWN_INTERRUPT               0x04
  88
  89#define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
  90#define PACKET_HEADER0_PACKET_ID_SHIFT          16
  91#define PACKET_HEADER0_CONT_ID_SHIFT            12
  92#define PACKET_HEADER0_PROTOCOL_I2C             (1<<4)
  93
  94#define I2C_HEADER_HIGHSPEED_MODE               (1<<22)
  95#define I2C_HEADER_CONT_ON_NAK                  (1<<21)
  96#define I2C_HEADER_SEND_START_BYTE              (1<<20)
  97#define I2C_HEADER_READ                         (1<<19)
  98#define I2C_HEADER_10BIT_ADDR                   (1<<18)
  99#define I2C_HEADER_IE_ENABLE                    (1<<17)
 100#define I2C_HEADER_REPEAT_START                 (1<<16)
 101#define I2C_HEADER_CONTINUE_XFER                (1<<15)
 102#define I2C_HEADER_MASTER_ADDR_SHIFT            12
 103#define I2C_HEADER_SLAVE_ADDR_SHIFT             1
 104
 105#define I2C_CONFIG_LOAD                         0x08C
 106#define I2C_MSTR_CONFIG_LOAD                    (1 << 0)
 107#define I2C_SLV_CONFIG_LOAD                     (1 << 1)
 108#define I2C_TIMEOUT_CONFIG_LOAD                 (1 << 2)
 109
 110#define I2C_CLKEN_OVERRIDE                      0x090
 111#define I2C_MST_CORE_CLKEN_OVR                  (1 << 0)
 112
 113/*
 114 * msg_end_type: The bus control which need to be send at end of transfer.
 115 * @MSG_END_STOP: Send stop pulse at end of transfer.
 116 * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
 117 * @MSG_END_CONTINUE: The following on message is coming and so do not send
 118 *              stop or repeat start.
 119 */
 120enum msg_end_type {
 121        MSG_END_STOP,
 122        MSG_END_REPEAT_START,
 123        MSG_END_CONTINUE,
 124};
 125
 126/**
 127 * struct tegra_i2c_hw_feature : Different HW support on Tegra
 128 * @has_continue_xfer_support: Continue transfer supports.
 129 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
 130 *              complete interrupt per packet basis.
 131 * @has_single_clk_source: The i2c controller has single clock source. Tegra30
 132 *              and earlier Socs has two clock sources i.e. div-clk and
 133 *              fast-clk.
 134 * @has_config_load_reg: Has the config load register to load the new
 135 *              configuration.
 136 * @clk_divisor_hs_mode: Clock divisor in HS mode.
 137 * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
 138 *              applicable if there is no fast clock source i.e. single clock
 139 *              source.
 140 */
 141
 142struct tegra_i2c_hw_feature {
 143        bool has_continue_xfer_support;
 144        bool has_per_pkt_xfer_complete_irq;
 145        bool has_single_clk_source;
 146        bool has_config_load_reg;
 147        int clk_divisor_hs_mode;
 148        int clk_divisor_std_fast_mode;
 149        u16 clk_divisor_fast_plus_mode;
 150        bool has_multi_master_mode;
 151        bool has_slcg_override_reg;
 152};
 153
 154/**
 155 * struct tegra_i2c_dev - per device i2c context
 156 * @dev: device reference for power management
 157 * @hw: Tegra i2c hw feature.
 158 * @adapter: core i2c layer adapter information
 159 * @div_clk: clock reference for div clock of i2c controller.
 160 * @fast_clk: clock reference for fast clock of i2c controller.
 161 * @base: ioremapped registers cookie
 162 * @cont_id: i2c controller id, used for for packet header
 163 * @irq: irq number of transfer complete interrupt
 164 * @is_dvc: identifies the DVC i2c controller, has a different register layout
 165 * @msg_complete: transfer completion notifier
 166 * @msg_err: error code for completed message
 167 * @msg_buf: pointer to current message data
 168 * @msg_buf_remaining: size of unsent data in the message buffer
 169 * @msg_read: identifies read transfers
 170 * @bus_clk_rate: current i2c bus clock rate
 171 * @is_suspended: prevents i2c controller accesses after suspend is called
 172 */
 173struct tegra_i2c_dev {
 174        struct device *dev;
 175        const struct tegra_i2c_hw_feature *hw;
 176        struct i2c_adapter adapter;
 177        struct clk *div_clk;
 178        struct clk *fast_clk;
 179        struct reset_control *rst;
 180        void __iomem *base;
 181        int cont_id;
 182        int irq;
 183        bool irq_disabled;
 184        int is_dvc;
 185        struct completion msg_complete;
 186        int msg_err;
 187        u8 *msg_buf;
 188        size_t msg_buf_remaining;
 189        int msg_read;
 190        u32 bus_clk_rate;
 191        u16 clk_divisor_non_hs_mode;
 192        bool is_suspended;
 193        bool is_multimaster_mode;
 194};
 195
 196static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
 197{
 198        writel(val, i2c_dev->base + reg);
 199}
 200
 201static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 202{
 203        return readl(i2c_dev->base + reg);
 204}
 205
 206/*
 207 * i2c_writel and i2c_readl will offset the register if necessary to talk
 208 * to the I2C block inside the DVC block
 209 */
 210static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
 211        unsigned long reg)
 212{
 213        if (i2c_dev->is_dvc)
 214                reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 215        return reg;
 216}
 217
 218static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 219        unsigned long reg)
 220{
 221        writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 222
 223        /* Read back register to make sure that register writes completed */
 224        if (reg != I2C_TX_FIFO)
 225                readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 226}
 227
 228static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 229{
 230        return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 231}
 232
 233static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
 234        unsigned long reg, int len)
 235{
 236        writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 237}
 238
 239static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
 240        unsigned long reg, int len)
 241{
 242        readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 243}
 244
 245static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 246{
 247        u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 248        int_mask &= ~mask;
 249        i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 250}
 251
 252static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 253{
 254        u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 255        int_mask |= mask;
 256        i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 257}
 258
 259static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 260{
 261        unsigned long timeout = jiffies + HZ;
 262        u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
 263        val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
 264        i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 265
 266        while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
 267                (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
 268                if (time_after(jiffies, timeout)) {
 269                        dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
 270                        return -ETIMEDOUT;
 271                }
 272                msleep(1);
 273        }
 274        return 0;
 275}
 276
 277static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 278{
 279        u32 val;
 280        int rx_fifo_avail;
 281        u8 *buf = i2c_dev->msg_buf;
 282        size_t buf_remaining = i2c_dev->msg_buf_remaining;
 283        int words_to_transfer;
 284
 285        val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 286        rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
 287                I2C_FIFO_STATUS_RX_SHIFT;
 288
 289        /* Rounds down to not include partial word at the end of buf */
 290        words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 291        if (words_to_transfer > rx_fifo_avail)
 292                words_to_transfer = rx_fifo_avail;
 293
 294        i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 295
 296        buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 297        buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 298        rx_fifo_avail -= words_to_transfer;
 299
 300        /*
 301         * If there is a partial word at the end of buf, handle it manually to
 302         * prevent overwriting past the end of buf
 303         */
 304        if (rx_fifo_avail > 0 && buf_remaining > 0) {
 305                BUG_ON(buf_remaining > 3);
 306                val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 307                val = cpu_to_le32(val);
 308                memcpy(buf, &val, buf_remaining);
 309                buf_remaining = 0;
 310                rx_fifo_avail--;
 311        }
 312
 313        BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
 314        i2c_dev->msg_buf_remaining = buf_remaining;
 315        i2c_dev->msg_buf = buf;
 316        return 0;
 317}
 318
 319static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 320{
 321        u32 val;
 322        int tx_fifo_avail;
 323        u8 *buf = i2c_dev->msg_buf;
 324        size_t buf_remaining = i2c_dev->msg_buf_remaining;
 325        int words_to_transfer;
 326
 327        val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 328        tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
 329                I2C_FIFO_STATUS_TX_SHIFT;
 330
 331        /* Rounds down to not include partial word at the end of buf */
 332        words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 333
 334        /* It's very common to have < 4 bytes, so optimize that case. */
 335        if (words_to_transfer) {
 336                if (words_to_transfer > tx_fifo_avail)
 337                        words_to_transfer = tx_fifo_avail;
 338
 339                /*
 340                 * Update state before writing to FIFO.  If this casues us
 341                 * to finish writing all bytes (AKA buf_remaining goes to 0) we
 342                 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
 343                 * not maskable).  We need to make sure that the isr sees
 344                 * buf_remaining as 0 and doesn't call us back re-entrantly.
 345                 */
 346                buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 347                tx_fifo_avail -= words_to_transfer;
 348                i2c_dev->msg_buf_remaining = buf_remaining;
 349                i2c_dev->msg_buf = buf +
 350                        words_to_transfer * BYTES_PER_FIFO_WORD;
 351                barrier();
 352
 353                i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 354
 355                buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 356        }
 357
 358        /*
 359         * If there is a partial word at the end of buf, handle it manually to
 360         * prevent reading past the end of buf, which could cross a page
 361         * boundary and fault.
 362         */
 363        if (tx_fifo_avail > 0 && buf_remaining > 0) {
 364                BUG_ON(buf_remaining > 3);
 365                memcpy(&val, buf, buf_remaining);
 366                val = le32_to_cpu(val);
 367
 368                /* Again update before writing to FIFO to make sure isr sees. */
 369                i2c_dev->msg_buf_remaining = 0;
 370                i2c_dev->msg_buf = NULL;
 371                barrier();
 372
 373                i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 374        }
 375
 376        return 0;
 377}
 378
 379/*
 380 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 381 * block.  This block is identical to the rest of the I2C blocks, except that
 382 * it only supports master mode, it has registers moved around, and it needs
 383 * some extra init to get it into I2C mode.  The register moves are handled
 384 * by i2c_readl and i2c_writel
 385 */
 386static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 387{
 388        u32 val = 0;
 389        val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 390        val |= DVC_CTRL_REG3_SW_PROG;
 391        val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
 392        dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 393
 394        val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 395        val |= DVC_CTRL_REG1_INTR_EN;
 396        dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 397}
 398
 399static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev)
 400{
 401        int ret;
 402        if (!i2c_dev->hw->has_single_clk_source) {
 403                ret = clk_enable(i2c_dev->fast_clk);
 404                if (ret < 0) {
 405                        dev_err(i2c_dev->dev,
 406                                "Enabling fast clk failed, err %d\n", ret);
 407                        return ret;
 408                }
 409        }
 410        ret = clk_enable(i2c_dev->div_clk);
 411        if (ret < 0) {
 412                dev_err(i2c_dev->dev,
 413                        "Enabling div clk failed, err %d\n", ret);
 414                clk_disable(i2c_dev->fast_clk);
 415        }
 416        return ret;
 417}
 418
 419static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev)
 420{
 421        clk_disable(i2c_dev->div_clk);
 422        if (!i2c_dev->hw->has_single_clk_source)
 423                clk_disable(i2c_dev->fast_clk);
 424}
 425
 426static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 427{
 428        u32 val;
 429        int err = 0;
 430        u32 clk_divisor;
 431        unsigned long timeout = jiffies + HZ;
 432
 433        err = tegra_i2c_clock_enable(i2c_dev);
 434        if (err < 0) {
 435                dev_err(i2c_dev->dev, "Clock enable failed %d\n", err);
 436                return err;
 437        }
 438
 439        reset_control_assert(i2c_dev->rst);
 440        udelay(2);
 441        reset_control_deassert(i2c_dev->rst);
 442
 443        if (i2c_dev->is_dvc)
 444                tegra_dvc_init(i2c_dev);
 445
 446        val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
 447                (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
 448
 449        if (i2c_dev->hw->has_multi_master_mode)
 450                val |= I2C_CNFG_MULTI_MASTER_MODE;
 451
 452        i2c_writel(i2c_dev, val, I2C_CNFG);
 453        i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 454
 455        /* Make sure clock divisor programmed correctly */
 456        clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
 457        clk_divisor |= i2c_dev->clk_divisor_non_hs_mode <<
 458                                        I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
 459        i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
 460
 461        if (!i2c_dev->is_dvc) {
 462                u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
 463                sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
 464                i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
 465                i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
 466                i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
 467
 468        }
 469
 470        val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
 471                0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
 472        i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 473
 474        if (tegra_i2c_flush_fifos(i2c_dev))
 475                err = -ETIMEDOUT;
 476
 477        if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
 478                i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
 479
 480        if (i2c_dev->hw->has_config_load_reg) {
 481                i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
 482                while (i2c_readl(i2c_dev, I2C_CONFIG_LOAD) != 0) {
 483                        if (time_after(jiffies, timeout)) {
 484                                dev_warn(i2c_dev->dev,
 485                                        "timeout waiting for config load\n");
 486                                err = -ETIMEDOUT;
 487                                goto err;
 488                        }
 489                        msleep(1);
 490                }
 491        }
 492
 493        if (i2c_dev->irq_disabled) {
 494                i2c_dev->irq_disabled = 0;
 495                enable_irq(i2c_dev->irq);
 496        }
 497
 498err:
 499        tegra_i2c_clock_disable(i2c_dev);
 500        return err;
 501}
 502
 503static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 504{
 505        u32 status;
 506        const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 507        struct tegra_i2c_dev *i2c_dev = dev_id;
 508
 509        status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 510
 511        if (status == 0) {
 512                dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
 513                         i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 514                         i2c_readl(i2c_dev, I2C_STATUS),
 515                         i2c_readl(i2c_dev, I2C_CNFG));
 516                i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 517
 518                if (!i2c_dev->irq_disabled) {
 519                        disable_irq_nosync(i2c_dev->irq);
 520                        i2c_dev->irq_disabled = 1;
 521                }
 522                goto err;
 523        }
 524
 525        if (unlikely(status & status_err)) {
 526                if (status & I2C_INT_NO_ACK)
 527                        i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 528                if (status & I2C_INT_ARBITRATION_LOST)
 529                        i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 530                goto err;
 531        }
 532
 533        if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 534                if (i2c_dev->msg_buf_remaining)
 535                        tegra_i2c_empty_rx_fifo(i2c_dev);
 536                else
 537                        BUG();
 538        }
 539
 540        if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 541                if (i2c_dev->msg_buf_remaining)
 542                        tegra_i2c_fill_tx_fifo(i2c_dev);
 543                else
 544                        tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
 545        }
 546
 547        i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 548        if (i2c_dev->is_dvc)
 549                dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 550
 551        if (status & I2C_INT_PACKET_XFER_COMPLETE) {
 552                BUG_ON(i2c_dev->msg_buf_remaining);
 553                complete(&i2c_dev->msg_complete);
 554        }
 555        return IRQ_HANDLED;
 556err:
 557        /* An error occurred, mask all interrupts */
 558        tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
 559                I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
 560                I2C_INT_RX_FIFO_DATA_REQ);
 561        i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 562        if (i2c_dev->is_dvc)
 563                dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 564
 565        complete(&i2c_dev->msg_complete);
 566        return IRQ_HANDLED;
 567}
 568
 569static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
 570        struct i2c_msg *msg, enum msg_end_type end_state)
 571{
 572        u32 packet_header;
 573        u32 int_mask;
 574        unsigned long time_left;
 575
 576        tegra_i2c_flush_fifos(i2c_dev);
 577
 578        if (msg->len == 0)
 579                return -EINVAL;
 580
 581        i2c_dev->msg_buf = msg->buf;
 582        i2c_dev->msg_buf_remaining = msg->len;
 583        i2c_dev->msg_err = I2C_ERR_NONE;
 584        i2c_dev->msg_read = (msg->flags & I2C_M_RD);
 585        reinit_completion(&i2c_dev->msg_complete);
 586
 587        packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
 588                        PACKET_HEADER0_PROTOCOL_I2C |
 589                        (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
 590                        (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
 591        i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 592
 593        packet_header = msg->len - 1;
 594        i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 595
 596        packet_header = I2C_HEADER_IE_ENABLE;
 597        if (end_state == MSG_END_CONTINUE)
 598                packet_header |= I2C_HEADER_CONTINUE_XFER;
 599        else if (end_state == MSG_END_REPEAT_START)
 600                packet_header |= I2C_HEADER_REPEAT_START;
 601        if (msg->flags & I2C_M_TEN) {
 602                packet_header |= msg->addr;
 603                packet_header |= I2C_HEADER_10BIT_ADDR;
 604        } else {
 605                packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
 606        }
 607        if (msg->flags & I2C_M_IGNORE_NAK)
 608                packet_header |= I2C_HEADER_CONT_ON_NAK;
 609        if (msg->flags & I2C_M_RD)
 610                packet_header |= I2C_HEADER_READ;
 611        i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 612
 613        if (!(msg->flags & I2C_M_RD))
 614                tegra_i2c_fill_tx_fifo(i2c_dev);
 615
 616        int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 617        if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
 618                int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
 619        if (msg->flags & I2C_M_RD)
 620                int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
 621        else if (i2c_dev->msg_buf_remaining)
 622                int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
 623        tegra_i2c_unmask_irq(i2c_dev, int_mask);
 624        dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
 625                i2c_readl(i2c_dev, I2C_INT_MASK));
 626
 627        time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
 628                                                TEGRA_I2C_TIMEOUT);
 629        tegra_i2c_mask_irq(i2c_dev, int_mask);
 630
 631        if (time_left == 0) {
 632                dev_err(i2c_dev->dev, "i2c transfer timed out\n");
 633
 634                tegra_i2c_init(i2c_dev);
 635                return -ETIMEDOUT;
 636        }
 637
 638        dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
 639                time_left, completion_done(&i2c_dev->msg_complete),
 640                i2c_dev->msg_err);
 641
 642        if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
 643                return 0;
 644
 645        /*
 646         * NACK interrupt is generated before the I2C controller generates the
 647         * STOP condition on the bus. So wait for 2 clock periods before resetting
 648         * the controller so that STOP condition has been delivered properly.
 649         */
 650        if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
 651                udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
 652
 653        tegra_i2c_init(i2c_dev);
 654        if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
 655                if (msg->flags & I2C_M_IGNORE_NAK)
 656                        return 0;
 657                return -EREMOTEIO;
 658        }
 659
 660        return -EIO;
 661}
 662
 663static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 664        int num)
 665{
 666        struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 667        int i;
 668        int ret = 0;
 669
 670        if (i2c_dev->is_suspended)
 671                return -EBUSY;
 672
 673        ret = tegra_i2c_clock_enable(i2c_dev);
 674        if (ret < 0) {
 675                dev_err(i2c_dev->dev, "Clock enable failed %d\n", ret);
 676                return ret;
 677        }
 678
 679        for (i = 0; i < num; i++) {
 680                enum msg_end_type end_type = MSG_END_STOP;
 681                if (i < (num - 1)) {
 682                        if (msgs[i + 1].flags & I2C_M_NOSTART)
 683                                end_type = MSG_END_CONTINUE;
 684                        else
 685                                end_type = MSG_END_REPEAT_START;
 686                }
 687                ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
 688                if (ret)
 689                        break;
 690        }
 691        tegra_i2c_clock_disable(i2c_dev);
 692        return ret ?: i;
 693}
 694
 695static u32 tegra_i2c_func(struct i2c_adapter *adap)
 696{
 697        struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 698        u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
 699                  I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
 700
 701        if (i2c_dev->hw->has_continue_xfer_support)
 702                ret |= I2C_FUNC_NOSTART;
 703        return ret;
 704}
 705
 706static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
 707{
 708        struct device_node *np = i2c_dev->dev->of_node;
 709        int ret;
 710
 711        ret = of_property_read_u32(np, "clock-frequency",
 712                        &i2c_dev->bus_clk_rate);
 713        if (ret)
 714                i2c_dev->bus_clk_rate = 100000; /* default clock rate */
 715
 716        i2c_dev->is_multimaster_mode = of_property_read_bool(np,
 717                        "multi-master");
 718}
 719
 720static const struct i2c_algorithm tegra_i2c_algo = {
 721        .master_xfer    = tegra_i2c_xfer,
 722        .functionality  = tegra_i2c_func,
 723};
 724
 725/* payload size is only 12 bit */
 726static struct i2c_adapter_quirks tegra_i2c_quirks = {
 727        .max_read_len = 4096,
 728        .max_write_len = 4096,
 729};
 730
 731static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
 732        .has_continue_xfer_support = false,
 733        .has_per_pkt_xfer_complete_irq = false,
 734        .has_single_clk_source = false,
 735        .clk_divisor_hs_mode = 3,
 736        .clk_divisor_std_fast_mode = 0,
 737        .clk_divisor_fast_plus_mode = 0,
 738        .has_config_load_reg = false,
 739        .has_multi_master_mode = false,
 740        .has_slcg_override_reg = false,
 741};
 742
 743static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
 744        .has_continue_xfer_support = true,
 745        .has_per_pkt_xfer_complete_irq = false,
 746        .has_single_clk_source = false,
 747        .clk_divisor_hs_mode = 3,
 748        .clk_divisor_std_fast_mode = 0,
 749        .clk_divisor_fast_plus_mode = 0,
 750        .has_config_load_reg = false,
 751        .has_multi_master_mode = false,
 752        .has_slcg_override_reg = false,
 753};
 754
 755static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
 756        .has_continue_xfer_support = true,
 757        .has_per_pkt_xfer_complete_irq = true,
 758        .has_single_clk_source = true,
 759        .clk_divisor_hs_mode = 1,
 760        .clk_divisor_std_fast_mode = 0x19,
 761        .clk_divisor_fast_plus_mode = 0x10,
 762        .has_config_load_reg = false,
 763        .has_multi_master_mode = false,
 764        .has_slcg_override_reg = false,
 765};
 766
 767static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
 768        .has_continue_xfer_support = true,
 769        .has_per_pkt_xfer_complete_irq = true,
 770        .has_single_clk_source = true,
 771        .clk_divisor_hs_mode = 1,
 772        .clk_divisor_std_fast_mode = 0x19,
 773        .clk_divisor_fast_plus_mode = 0x10,
 774        .has_config_load_reg = true,
 775        .has_multi_master_mode = false,
 776        .has_slcg_override_reg = true,
 777};
 778
 779static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
 780        .has_continue_xfer_support = true,
 781        .has_per_pkt_xfer_complete_irq = true,
 782        .has_single_clk_source = true,
 783        .clk_divisor_hs_mode = 1,
 784        .clk_divisor_std_fast_mode = 0x19,
 785        .clk_divisor_fast_plus_mode = 0x10,
 786        .has_config_load_reg = true,
 787        .has_multi_master_mode = true,
 788        .has_slcg_override_reg = true,
 789};
 790
 791/* Match table for of_platform binding */
 792static const struct of_device_id tegra_i2c_of_match[] = {
 793        { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
 794        { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
 795        { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
 796        { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
 797        { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
 798        { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
 799        {},
 800};
 801MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
 802
 803static int tegra_i2c_probe(struct platform_device *pdev)
 804{
 805        struct tegra_i2c_dev *i2c_dev;
 806        struct resource *res;
 807        struct clk *div_clk;
 808        struct clk *fast_clk;
 809        void __iomem *base;
 810        int irq;
 811        int ret = 0;
 812        int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE;
 813
 814        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 815        base = devm_ioremap_resource(&pdev->dev, res);
 816        if (IS_ERR(base))
 817                return PTR_ERR(base);
 818
 819        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 820        if (!res) {
 821                dev_err(&pdev->dev, "no irq resource\n");
 822                return -EINVAL;
 823        }
 824        irq = res->start;
 825
 826        div_clk = devm_clk_get(&pdev->dev, "div-clk");
 827        if (IS_ERR(div_clk)) {
 828                dev_err(&pdev->dev, "missing controller clock");
 829                return PTR_ERR(div_clk);
 830        }
 831
 832        i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
 833        if (!i2c_dev)
 834                return -ENOMEM;
 835
 836        i2c_dev->base = base;
 837        i2c_dev->div_clk = div_clk;
 838        i2c_dev->adapter.algo = &tegra_i2c_algo;
 839        i2c_dev->adapter.quirks = &tegra_i2c_quirks;
 840        i2c_dev->irq = irq;
 841        i2c_dev->cont_id = pdev->id;
 842        i2c_dev->dev = &pdev->dev;
 843
 844        i2c_dev->rst = devm_reset_control_get(&pdev->dev, "i2c");
 845        if (IS_ERR(i2c_dev->rst)) {
 846                dev_err(&pdev->dev, "missing controller reset");
 847                return PTR_ERR(i2c_dev->rst);
 848        }
 849
 850        tegra_i2c_parse_dt(i2c_dev);
 851
 852        i2c_dev->hw = &tegra20_i2c_hw;
 853
 854        if (pdev->dev.of_node) {
 855                i2c_dev->hw = of_device_get_match_data(&pdev->dev);
 856                i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
 857                                                "nvidia,tegra20-i2c-dvc");
 858        } else if (pdev->id == 3) {
 859                i2c_dev->is_dvc = 1;
 860        }
 861        init_completion(&i2c_dev->msg_complete);
 862
 863        if (!i2c_dev->hw->has_single_clk_source) {
 864                fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
 865                if (IS_ERR(fast_clk)) {
 866                        dev_err(&pdev->dev, "missing fast clock");
 867                        return PTR_ERR(fast_clk);
 868                }
 869                i2c_dev->fast_clk = fast_clk;
 870        }
 871
 872        platform_set_drvdata(pdev, i2c_dev);
 873
 874        if (!i2c_dev->hw->has_single_clk_source) {
 875                ret = clk_prepare(i2c_dev->fast_clk);
 876                if (ret < 0) {
 877                        dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
 878                        return ret;
 879                }
 880        }
 881
 882        i2c_dev->clk_divisor_non_hs_mode =
 883                        i2c_dev->hw->clk_divisor_std_fast_mode;
 884        if (i2c_dev->hw->clk_divisor_fast_plus_mode &&
 885                (i2c_dev->bus_clk_rate == 1000000))
 886                i2c_dev->clk_divisor_non_hs_mode =
 887                        i2c_dev->hw->clk_divisor_fast_plus_mode;
 888
 889        clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1);
 890        ret = clk_set_rate(i2c_dev->div_clk,
 891                           i2c_dev->bus_clk_rate * clk_multiplier);
 892        if (ret) {
 893                dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret);
 894                goto unprepare_fast_clk;
 895        }
 896
 897        ret = clk_prepare(i2c_dev->div_clk);
 898        if (ret < 0) {
 899                dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
 900                goto unprepare_fast_clk;
 901        }
 902
 903        if (i2c_dev->is_multimaster_mode) {
 904                ret = clk_enable(i2c_dev->div_clk);
 905                if (ret < 0) {
 906                        dev_err(i2c_dev->dev, "div_clk enable failed %d\n",
 907                                ret);
 908                        goto unprepare_div_clk;
 909                }
 910        }
 911
 912        ret = tegra_i2c_init(i2c_dev);
 913        if (ret) {
 914                dev_err(&pdev->dev, "Failed to initialize i2c controller");
 915                goto disable_div_clk;
 916        }
 917
 918        ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
 919                        tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
 920        if (ret) {
 921                dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
 922                goto disable_div_clk;
 923        }
 924
 925        i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
 926        i2c_dev->adapter.owner = THIS_MODULE;
 927        i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
 928        strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
 929                sizeof(i2c_dev->adapter.name));
 930        i2c_dev->adapter.dev.parent = &pdev->dev;
 931        i2c_dev->adapter.nr = pdev->id;
 932        i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
 933
 934        ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
 935        if (ret) {
 936                dev_err(&pdev->dev, "Failed to add I2C adapter\n");
 937                goto disable_div_clk;
 938        }
 939
 940        return 0;
 941
 942disable_div_clk:
 943        if (i2c_dev->is_multimaster_mode)
 944                clk_disable(i2c_dev->div_clk);
 945
 946unprepare_div_clk:
 947        clk_unprepare(i2c_dev->div_clk);
 948
 949unprepare_fast_clk:
 950        if (!i2c_dev->hw->has_single_clk_source)
 951                clk_unprepare(i2c_dev->fast_clk);
 952
 953        return ret;
 954}
 955
 956static int tegra_i2c_remove(struct platform_device *pdev)
 957{
 958        struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 959        i2c_del_adapter(&i2c_dev->adapter);
 960
 961        if (i2c_dev->is_multimaster_mode)
 962                clk_disable(i2c_dev->div_clk);
 963
 964        clk_unprepare(i2c_dev->div_clk);
 965        if (!i2c_dev->hw->has_single_clk_source)
 966                clk_unprepare(i2c_dev->fast_clk);
 967
 968        return 0;
 969}
 970
 971#ifdef CONFIG_PM_SLEEP
 972static int tegra_i2c_suspend(struct device *dev)
 973{
 974        struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 975
 976        i2c_lock_adapter(&i2c_dev->adapter);
 977        i2c_dev->is_suspended = true;
 978        i2c_unlock_adapter(&i2c_dev->adapter);
 979
 980        return 0;
 981}
 982
 983static int tegra_i2c_resume(struct device *dev)
 984{
 985        struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 986        int ret;
 987
 988        i2c_lock_adapter(&i2c_dev->adapter);
 989
 990        ret = tegra_i2c_init(i2c_dev);
 991
 992        if (ret) {
 993                i2c_unlock_adapter(&i2c_dev->adapter);
 994                return ret;
 995        }
 996
 997        i2c_dev->is_suspended = false;
 998
 999        i2c_unlock_adapter(&i2c_dev->adapter);
1000
1001        return 0;
1002}
1003
1004static SIMPLE_DEV_PM_OPS(tegra_i2c_pm, tegra_i2c_suspend, tegra_i2c_resume);
1005#define TEGRA_I2C_PM    (&tegra_i2c_pm)
1006#else
1007#define TEGRA_I2C_PM    NULL
1008#endif
1009
1010static struct platform_driver tegra_i2c_driver = {
1011        .probe   = tegra_i2c_probe,
1012        .remove  = tegra_i2c_remove,
1013        .driver  = {
1014                .name  = "tegra-i2c",
1015                .of_match_table = tegra_i2c_of_match,
1016                .pm    = TEGRA_I2C_PM,
1017        },
1018};
1019
1020static int __init tegra_i2c_init_driver(void)
1021{
1022        return platform_driver_register(&tegra_i2c_driver);
1023}
1024
1025static void __exit tegra_i2c_exit_driver(void)
1026{
1027        platform_driver_unregister(&tegra_i2c_driver);
1028}
1029
1030subsys_initcall(tegra_i2c_init_driver);
1031module_exit(tegra_i2c_exit_driver);
1032
1033MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1034MODULE_AUTHOR("Colin Cross");
1035MODULE_LICENSE("GPL v2");
1036
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