linux/drivers/i2c/busses/i2c-tegra.c
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   1/*
   2 * drivers/i2c/busses/i2c-tegra.c
   3 *
   4 * Copyright (C) 2010 Google, Inc.
   5 * Author: Colin Cross <ccross@android.com>
   6 *
   7 * This software is licensed under the terms of the GNU General Public
   8 * License version 2, as published by the Free Software Foundation, and
   9 * may be copied, distributed, and modified under those terms.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 */
  17
  18#include <linux/kernel.h>
  19#include <linux/init.h>
  20#include <linux/platform_device.h>
  21#include <linux/clk.h>
  22#include <linux/err.h>
  23#include <linux/i2c.h>
  24#include <linux/io.h>
  25#include <linux/interrupt.h>
  26#include <linux/delay.h>
  27#include <linux/slab.h>
  28#include <linux/of_device.h>
  29#include <linux/module.h>
  30#include <linux/reset.h>
  31
  32#include <asm/unaligned.h>
  33
  34#define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
  35#define BYTES_PER_FIFO_WORD 4
  36
  37#define I2C_CNFG                                0x000
  38#define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
  39#define I2C_CNFG_PACKET_MODE_EN                 (1<<10)
  40#define I2C_CNFG_NEW_MASTER_FSM                 (1<<11)
  41#define I2C_STATUS                              0x01C
  42#define I2C_SL_CNFG                             0x020
  43#define I2C_SL_CNFG_NACK                        (1<<1)
  44#define I2C_SL_CNFG_NEWSL                       (1<<2)
  45#define I2C_SL_ADDR1                            0x02c
  46#define I2C_SL_ADDR2                            0x030
  47#define I2C_TX_FIFO                             0x050
  48#define I2C_RX_FIFO                             0x054
  49#define I2C_PACKET_TRANSFER_STATUS              0x058
  50#define I2C_FIFO_CONTROL                        0x05c
  51#define I2C_FIFO_CONTROL_TX_FLUSH               (1<<1)
  52#define I2C_FIFO_CONTROL_RX_FLUSH               (1<<0)
  53#define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
  54#define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
  55#define I2C_FIFO_STATUS                         0x060
  56#define I2C_FIFO_STATUS_TX_MASK                 0xF0
  57#define I2C_FIFO_STATUS_TX_SHIFT                4
  58#define I2C_FIFO_STATUS_RX_MASK                 0x0F
  59#define I2C_FIFO_STATUS_RX_SHIFT                0
  60#define I2C_INT_MASK                            0x064
  61#define I2C_INT_STATUS                          0x068
  62#define I2C_INT_PACKET_XFER_COMPLETE            (1<<7)
  63#define I2C_INT_ALL_PACKETS_XFER_COMPLETE       (1<<6)
  64#define I2C_INT_TX_FIFO_OVERFLOW                (1<<5)
  65#define I2C_INT_RX_FIFO_UNDERFLOW               (1<<4)
  66#define I2C_INT_NO_ACK                          (1<<3)
  67#define I2C_INT_ARBITRATION_LOST                (1<<2)
  68#define I2C_INT_TX_FIFO_DATA_REQ                (1<<1)
  69#define I2C_INT_RX_FIFO_DATA_REQ                (1<<0)
  70#define I2C_CLK_DIVISOR                         0x06c
  71#define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT     16
  72#define I2C_CLK_MULTIPLIER_STD_FAST_MODE        8
  73
  74#define DVC_CTRL_REG1                           0x000
  75#define DVC_CTRL_REG1_INTR_EN                   (1<<10)
  76#define DVC_CTRL_REG2                           0x004
  77#define DVC_CTRL_REG3                           0x008
  78#define DVC_CTRL_REG3_SW_PROG                   (1<<26)
  79#define DVC_CTRL_REG3_I2C_DONE_INTR_EN          (1<<30)
  80#define DVC_STATUS                              0x00c
  81#define DVC_STATUS_I2C_DONE_INTR                (1<<30)
  82
  83#define I2C_ERR_NONE                            0x00
  84#define I2C_ERR_NO_ACK                          0x01
  85#define I2C_ERR_ARBITRATION_LOST                0x02
  86#define I2C_ERR_UNKNOWN_INTERRUPT               0x04
  87
  88#define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
  89#define PACKET_HEADER0_PACKET_ID_SHIFT          16
  90#define PACKET_HEADER0_CONT_ID_SHIFT            12
  91#define PACKET_HEADER0_PROTOCOL_I2C             (1<<4)
  92
  93#define I2C_HEADER_HIGHSPEED_MODE               (1<<22)
  94#define I2C_HEADER_CONT_ON_NAK                  (1<<21)
  95#define I2C_HEADER_SEND_START_BYTE              (1<<20)
  96#define I2C_HEADER_READ                         (1<<19)
  97#define I2C_HEADER_10BIT_ADDR                   (1<<18)
  98#define I2C_HEADER_IE_ENABLE                    (1<<17)
  99#define I2C_HEADER_REPEAT_START                 (1<<16)
 100#define I2C_HEADER_CONTINUE_XFER                (1<<15)
 101#define I2C_HEADER_MASTER_ADDR_SHIFT            12
 102#define I2C_HEADER_SLAVE_ADDR_SHIFT             1
 103/*
 104 * msg_end_type: The bus control which need to be send at end of transfer.
 105 * @MSG_END_STOP: Send stop pulse at end of transfer.
 106 * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
 107 * @MSG_END_CONTINUE: The following on message is coming and so do not send
 108 *              stop or repeat start.
 109 */
 110enum msg_end_type {
 111        MSG_END_STOP,
 112        MSG_END_REPEAT_START,
 113        MSG_END_CONTINUE,
 114};
 115
 116/**
 117 * struct tegra_i2c_hw_feature : Different HW support on Tegra
 118 * @has_continue_xfer_support: Continue transfer supports.
 119 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
 120 *              complete interrupt per packet basis.
 121 * @has_single_clk_source: The i2c controller has single clock source. Tegra30
 122 *              and earlier Socs has two clock sources i.e. div-clk and
 123 *              fast-clk.
 124 * @clk_divisor_hs_mode: Clock divisor in HS mode.
 125 * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
 126 *              applicable if there is no fast clock source i.e. single clock
 127 *              source.
 128 */
 129
 130struct tegra_i2c_hw_feature {
 131        bool has_continue_xfer_support;
 132        bool has_per_pkt_xfer_complete_irq;
 133        bool has_single_clk_source;
 134        int clk_divisor_hs_mode;
 135        int clk_divisor_std_fast_mode;
 136};
 137
 138/**
 139 * struct tegra_i2c_dev - per device i2c context
 140 * @dev: device reference for power management
 141 * @hw: Tegra i2c hw feature.
 142 * @adapter: core i2c layer adapter information
 143 * @div_clk: clock reference for div clock of i2c controller.
 144 * @fast_clk: clock reference for fast clock of i2c controller.
 145 * @base: ioremapped registers cookie
 146 * @cont_id: i2c controller id, used for for packet header
 147 * @irq: irq number of transfer complete interrupt
 148 * @is_dvc: identifies the DVC i2c controller, has a different register layout
 149 * @msg_complete: transfer completion notifier
 150 * @msg_err: error code for completed message
 151 * @msg_buf: pointer to current message data
 152 * @msg_buf_remaining: size of unsent data in the message buffer
 153 * @msg_read: identifies read transfers
 154 * @bus_clk_rate: current i2c bus clock rate
 155 * @is_suspended: prevents i2c controller accesses after suspend is called
 156 */
 157struct tegra_i2c_dev {
 158        struct device *dev;
 159        const struct tegra_i2c_hw_feature *hw;
 160        struct i2c_adapter adapter;
 161        struct clk *div_clk;
 162        struct clk *fast_clk;
 163        struct reset_control *rst;
 164        void __iomem *base;
 165        int cont_id;
 166        int irq;
 167        bool irq_disabled;
 168        int is_dvc;
 169        struct completion msg_complete;
 170        int msg_err;
 171        u8 *msg_buf;
 172        size_t msg_buf_remaining;
 173        int msg_read;
 174        u32 bus_clk_rate;
 175        bool is_suspended;
 176};
 177
 178static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
 179{
 180        writel(val, i2c_dev->base + reg);
 181}
 182
 183static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 184{
 185        return readl(i2c_dev->base + reg);
 186}
 187
 188/*
 189 * i2c_writel and i2c_readl will offset the register if necessary to talk
 190 * to the I2C block inside the DVC block
 191 */
 192static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
 193        unsigned long reg)
 194{
 195        if (i2c_dev->is_dvc)
 196                reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 197        return reg;
 198}
 199
 200static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 201        unsigned long reg)
 202{
 203        writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 204
 205        /* Read back register to make sure that register writes completed */
 206        if (reg != I2C_TX_FIFO)
 207                readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 208}
 209
 210static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 211{
 212        return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 213}
 214
 215static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
 216        unsigned long reg, int len)
 217{
 218        writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 219}
 220
 221static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
 222        unsigned long reg, int len)
 223{
 224        readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 225}
 226
 227static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 228{
 229        u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 230        int_mask &= ~mask;
 231        i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 232}
 233
 234static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 235{
 236        u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 237        int_mask |= mask;
 238        i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 239}
 240
 241static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 242{
 243        unsigned long timeout = jiffies + HZ;
 244        u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
 245        val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
 246        i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 247
 248        while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
 249                (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
 250                if (time_after(jiffies, timeout)) {
 251                        dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
 252                        return -ETIMEDOUT;
 253                }
 254                msleep(1);
 255        }
 256        return 0;
 257}
 258
 259static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 260{
 261        u32 val;
 262        int rx_fifo_avail;
 263        u8 *buf = i2c_dev->msg_buf;
 264        size_t buf_remaining = i2c_dev->msg_buf_remaining;
 265        int words_to_transfer;
 266
 267        val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 268        rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
 269                I2C_FIFO_STATUS_RX_SHIFT;
 270
 271        /* Rounds down to not include partial word at the end of buf */
 272        words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 273        if (words_to_transfer > rx_fifo_avail)
 274                words_to_transfer = rx_fifo_avail;
 275
 276        i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 277
 278        buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 279        buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 280        rx_fifo_avail -= words_to_transfer;
 281
 282        /*
 283         * If there is a partial word at the end of buf, handle it manually to
 284         * prevent overwriting past the end of buf
 285         */
 286        if (rx_fifo_avail > 0 && buf_remaining > 0) {
 287                BUG_ON(buf_remaining > 3);
 288                val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 289                memcpy(buf, &val, buf_remaining);
 290                buf_remaining = 0;
 291                rx_fifo_avail--;
 292        }
 293
 294        BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
 295        i2c_dev->msg_buf_remaining = buf_remaining;
 296        i2c_dev->msg_buf = buf;
 297        return 0;
 298}
 299
 300static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 301{
 302        u32 val;
 303        int tx_fifo_avail;
 304        u8 *buf = i2c_dev->msg_buf;
 305        size_t buf_remaining = i2c_dev->msg_buf_remaining;
 306        int words_to_transfer;
 307
 308        val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 309        tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
 310                I2C_FIFO_STATUS_TX_SHIFT;
 311
 312        /* Rounds down to not include partial word at the end of buf */
 313        words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 314
 315        /* It's very common to have < 4 bytes, so optimize that case. */
 316        if (words_to_transfer) {
 317                if (words_to_transfer > tx_fifo_avail)
 318                        words_to_transfer = tx_fifo_avail;
 319
 320                /*
 321                 * Update state before writing to FIFO.  If this casues us
 322                 * to finish writing all bytes (AKA buf_remaining goes to 0) we
 323                 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
 324                 * not maskable).  We need to make sure that the isr sees
 325                 * buf_remaining as 0 and doesn't call us back re-entrantly.
 326                 */
 327                buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 328                tx_fifo_avail -= words_to_transfer;
 329                i2c_dev->msg_buf_remaining = buf_remaining;
 330                i2c_dev->msg_buf = buf +
 331                        words_to_transfer * BYTES_PER_FIFO_WORD;
 332                barrier();
 333
 334                i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 335
 336                buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 337        }
 338
 339        /*
 340         * If there is a partial word at the end of buf, handle it manually to
 341         * prevent reading past the end of buf, which could cross a page
 342         * boundary and fault.
 343         */
 344        if (tx_fifo_avail > 0 && buf_remaining > 0) {
 345                BUG_ON(buf_remaining > 3);
 346                memcpy(&val, buf, buf_remaining);
 347
 348                /* Again update before writing to FIFO to make sure isr sees. */
 349                i2c_dev->msg_buf_remaining = 0;
 350                i2c_dev->msg_buf = NULL;
 351                barrier();
 352
 353                i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 354        }
 355
 356        return 0;
 357}
 358
 359/*
 360 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 361 * block.  This block is identical to the rest of the I2C blocks, except that
 362 * it only supports master mode, it has registers moved around, and it needs
 363 * some extra init to get it into I2C mode.  The register moves are handled
 364 * by i2c_readl and i2c_writel
 365 */
 366static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 367{
 368        u32 val = 0;
 369        val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 370        val |= DVC_CTRL_REG3_SW_PROG;
 371        val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
 372        dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 373
 374        val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 375        val |= DVC_CTRL_REG1_INTR_EN;
 376        dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 377}
 378
 379static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev)
 380{
 381        int ret;
 382        if (!i2c_dev->hw->has_single_clk_source) {
 383                ret = clk_enable(i2c_dev->fast_clk);
 384                if (ret < 0) {
 385                        dev_err(i2c_dev->dev,
 386                                "Enabling fast clk failed, err %d\n", ret);
 387                        return ret;
 388                }
 389        }
 390        ret = clk_enable(i2c_dev->div_clk);
 391        if (ret < 0) {
 392                dev_err(i2c_dev->dev,
 393                        "Enabling div clk failed, err %d\n", ret);
 394                clk_disable(i2c_dev->fast_clk);
 395        }
 396        return ret;
 397}
 398
 399static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev)
 400{
 401        clk_disable(i2c_dev->div_clk);
 402        if (!i2c_dev->hw->has_single_clk_source)
 403                clk_disable(i2c_dev->fast_clk);
 404}
 405
 406static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 407{
 408        u32 val;
 409        int err = 0;
 410        u32 clk_divisor;
 411
 412        err = tegra_i2c_clock_enable(i2c_dev);
 413        if (err < 0) {
 414                dev_err(i2c_dev->dev, "Clock enable failed %d\n", err);
 415                return err;
 416        }
 417
 418        reset_control_assert(i2c_dev->rst);
 419        udelay(2);
 420        reset_control_deassert(i2c_dev->rst);
 421
 422        if (i2c_dev->is_dvc)
 423                tegra_dvc_init(i2c_dev);
 424
 425        val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
 426                (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
 427        i2c_writel(i2c_dev, val, I2C_CNFG);
 428        i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 429
 430        /* Make sure clock divisor programmed correctly */
 431        clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
 432        clk_divisor |= i2c_dev->hw->clk_divisor_std_fast_mode <<
 433                                        I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
 434        i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
 435
 436        if (!i2c_dev->is_dvc) {
 437                u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
 438                sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
 439                i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
 440                i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
 441                i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
 442
 443        }
 444
 445        val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
 446                0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
 447        i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 448
 449        if (tegra_i2c_flush_fifos(i2c_dev))
 450                err = -ETIMEDOUT;
 451
 452        tegra_i2c_clock_disable(i2c_dev);
 453
 454        if (i2c_dev->irq_disabled) {
 455                i2c_dev->irq_disabled = 0;
 456                enable_irq(i2c_dev->irq);
 457        }
 458
 459        return err;
 460}
 461
 462static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 463{
 464        u32 status;
 465        const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 466        struct tegra_i2c_dev *i2c_dev = dev_id;
 467
 468        status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 469
 470        if (status == 0) {
 471                dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
 472                         i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 473                         i2c_readl(i2c_dev, I2C_STATUS),
 474                         i2c_readl(i2c_dev, I2C_CNFG));
 475                i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 476
 477                if (!i2c_dev->irq_disabled) {
 478                        disable_irq_nosync(i2c_dev->irq);
 479                        i2c_dev->irq_disabled = 1;
 480                }
 481                goto err;
 482        }
 483
 484        if (unlikely(status & status_err)) {
 485                if (status & I2C_INT_NO_ACK)
 486                        i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 487                if (status & I2C_INT_ARBITRATION_LOST)
 488                        i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 489                goto err;
 490        }
 491
 492        if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 493                if (i2c_dev->msg_buf_remaining)
 494                        tegra_i2c_empty_rx_fifo(i2c_dev);
 495                else
 496                        BUG();
 497        }
 498
 499        if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 500                if (i2c_dev->msg_buf_remaining)
 501                        tegra_i2c_fill_tx_fifo(i2c_dev);
 502                else
 503                        tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
 504        }
 505
 506        i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 507        if (i2c_dev->is_dvc)
 508                dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 509
 510        if (status & I2C_INT_PACKET_XFER_COMPLETE) {
 511                BUG_ON(i2c_dev->msg_buf_remaining);
 512                complete(&i2c_dev->msg_complete);
 513        }
 514        return IRQ_HANDLED;
 515err:
 516        /* An error occurred, mask all interrupts */
 517        tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
 518                I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
 519                I2C_INT_RX_FIFO_DATA_REQ);
 520        i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 521        if (i2c_dev->is_dvc)
 522                dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 523
 524        complete(&i2c_dev->msg_complete);
 525        return IRQ_HANDLED;
 526}
 527
 528static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
 529        struct i2c_msg *msg, enum msg_end_type end_state)
 530{
 531        u32 packet_header;
 532        u32 int_mask;
 533        int ret;
 534
 535        tegra_i2c_flush_fifos(i2c_dev);
 536
 537        if (msg->len == 0)
 538                return -EINVAL;
 539
 540        i2c_dev->msg_buf = msg->buf;
 541        i2c_dev->msg_buf_remaining = msg->len;
 542        i2c_dev->msg_err = I2C_ERR_NONE;
 543        i2c_dev->msg_read = (msg->flags & I2C_M_RD);
 544        reinit_completion(&i2c_dev->msg_complete);
 545
 546        packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
 547                        PACKET_HEADER0_PROTOCOL_I2C |
 548                        (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
 549                        (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
 550        i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 551
 552        packet_header = msg->len - 1;
 553        i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 554
 555        packet_header = I2C_HEADER_IE_ENABLE;
 556        if (end_state == MSG_END_CONTINUE)
 557                packet_header |= I2C_HEADER_CONTINUE_XFER;
 558        else if (end_state == MSG_END_REPEAT_START)
 559                packet_header |= I2C_HEADER_REPEAT_START;
 560        if (msg->flags & I2C_M_TEN) {
 561                packet_header |= msg->addr;
 562                packet_header |= I2C_HEADER_10BIT_ADDR;
 563        } else {
 564                packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
 565        }
 566        if (msg->flags & I2C_M_IGNORE_NAK)
 567                packet_header |= I2C_HEADER_CONT_ON_NAK;
 568        if (msg->flags & I2C_M_RD)
 569                packet_header |= I2C_HEADER_READ;
 570        i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 571
 572        if (!(msg->flags & I2C_M_RD))
 573                tegra_i2c_fill_tx_fifo(i2c_dev);
 574
 575        int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 576        if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
 577                int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
 578        if (msg->flags & I2C_M_RD)
 579                int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
 580        else if (i2c_dev->msg_buf_remaining)
 581                int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
 582        tegra_i2c_unmask_irq(i2c_dev, int_mask);
 583        dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
 584                i2c_readl(i2c_dev, I2C_INT_MASK));
 585
 586        ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
 587        tegra_i2c_mask_irq(i2c_dev, int_mask);
 588
 589        if (ret == 0) {
 590                dev_err(i2c_dev->dev, "i2c transfer timed out\n");
 591
 592                tegra_i2c_init(i2c_dev);
 593                return -ETIMEDOUT;
 594        }
 595
 596        dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
 597                ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
 598
 599        if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
 600                return 0;
 601
 602        /*
 603         * NACK interrupt is generated before the I2C controller generates the
 604         * STOP condition on the bus. So wait for 2 clock periods before resetting
 605         * the controller so that STOP condition has been delivered properly.
 606         */
 607        if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
 608                udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
 609
 610        tegra_i2c_init(i2c_dev);
 611        if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
 612                if (msg->flags & I2C_M_IGNORE_NAK)
 613                        return 0;
 614                return -EREMOTEIO;
 615        }
 616
 617        return -EIO;
 618}
 619
 620static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 621        int num)
 622{
 623        struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 624        int i;
 625        int ret = 0;
 626
 627        if (i2c_dev->is_suspended)
 628                return -EBUSY;
 629
 630        ret = tegra_i2c_clock_enable(i2c_dev);
 631        if (ret < 0) {
 632                dev_err(i2c_dev->dev, "Clock enable failed %d\n", ret);
 633                return ret;
 634        }
 635
 636        for (i = 0; i < num; i++) {
 637                enum msg_end_type end_type = MSG_END_STOP;
 638                if (i < (num - 1)) {
 639                        if (msgs[i + 1].flags & I2C_M_NOSTART)
 640                                end_type = MSG_END_CONTINUE;
 641                        else
 642                                end_type = MSG_END_REPEAT_START;
 643                }
 644                ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
 645                if (ret)
 646                        break;
 647        }
 648        tegra_i2c_clock_disable(i2c_dev);
 649        return ret ?: i;
 650}
 651
 652static u32 tegra_i2c_func(struct i2c_adapter *adap)
 653{
 654        struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 655        u32 ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
 656                                I2C_FUNC_PROTOCOL_MANGLING;
 657
 658        if (i2c_dev->hw->has_continue_xfer_support)
 659                ret |= I2C_FUNC_NOSTART;
 660        return ret;
 661}
 662
 663static const struct i2c_algorithm tegra_i2c_algo = {
 664        .master_xfer    = tegra_i2c_xfer,
 665        .functionality  = tegra_i2c_func,
 666};
 667
 668static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
 669        .has_continue_xfer_support = false,
 670        .has_per_pkt_xfer_complete_irq = false,
 671        .has_single_clk_source = false,
 672        .clk_divisor_hs_mode = 3,
 673        .clk_divisor_std_fast_mode = 0,
 674};
 675
 676static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
 677        .has_continue_xfer_support = true,
 678        .has_per_pkt_xfer_complete_irq = false,
 679        .has_single_clk_source = false,
 680        .clk_divisor_hs_mode = 3,
 681        .clk_divisor_std_fast_mode = 0,
 682};
 683
 684static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
 685        .has_continue_xfer_support = true,
 686        .has_per_pkt_xfer_complete_irq = true,
 687        .has_single_clk_source = true,
 688        .clk_divisor_hs_mode = 1,
 689        .clk_divisor_std_fast_mode = 0x19,
 690};
 691
 692/* Match table for of_platform binding */
 693static const struct of_device_id tegra_i2c_of_match[] = {
 694        { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
 695        { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
 696        { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
 697        { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
 698        {},
 699};
 700MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
 701
 702static int tegra_i2c_probe(struct platform_device *pdev)
 703{
 704        struct tegra_i2c_dev *i2c_dev;
 705        struct resource *res;
 706        struct clk *div_clk;
 707        struct clk *fast_clk;
 708        void __iomem *base;
 709        int irq;
 710        int ret = 0;
 711        int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE;
 712
 713        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 714        base = devm_ioremap_resource(&pdev->dev, res);
 715        if (IS_ERR(base))
 716                return PTR_ERR(base);
 717
 718        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 719        if (!res) {
 720                dev_err(&pdev->dev, "no irq resource\n");
 721                return -EINVAL;
 722        }
 723        irq = res->start;
 724
 725        div_clk = devm_clk_get(&pdev->dev, "div-clk");
 726        if (IS_ERR(div_clk)) {
 727                dev_err(&pdev->dev, "missing controller clock");
 728                return PTR_ERR(div_clk);
 729        }
 730
 731        i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
 732        if (!i2c_dev)
 733                return -ENOMEM;
 734
 735        i2c_dev->base = base;
 736        i2c_dev->div_clk = div_clk;
 737        i2c_dev->adapter.algo = &tegra_i2c_algo;
 738        i2c_dev->irq = irq;
 739        i2c_dev->cont_id = pdev->id;
 740        i2c_dev->dev = &pdev->dev;
 741
 742        i2c_dev->rst = devm_reset_control_get(&pdev->dev, "i2c");
 743        if (IS_ERR(i2c_dev->rst)) {
 744                dev_err(&pdev->dev, "missing controller reset");
 745                return PTR_ERR(i2c_dev->rst);
 746        }
 747
 748        ret = of_property_read_u32(i2c_dev->dev->of_node, "clock-frequency",
 749                                        &i2c_dev->bus_clk_rate);
 750        if (ret)
 751                i2c_dev->bus_clk_rate = 100000; /* default clock rate */
 752
 753        i2c_dev->hw = &tegra20_i2c_hw;
 754
 755        if (pdev->dev.of_node) {
 756                const struct of_device_id *match;
 757                match = of_match_device(tegra_i2c_of_match, &pdev->dev);
 758                i2c_dev->hw = match->data;
 759                i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
 760                                                "nvidia,tegra20-i2c-dvc");
 761        } else if (pdev->id == 3) {
 762                i2c_dev->is_dvc = 1;
 763        }
 764        init_completion(&i2c_dev->msg_complete);
 765
 766        if (!i2c_dev->hw->has_single_clk_source) {
 767                fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
 768                if (IS_ERR(fast_clk)) {
 769                        dev_err(&pdev->dev, "missing fast clock");
 770                        return PTR_ERR(fast_clk);
 771                }
 772                i2c_dev->fast_clk = fast_clk;
 773        }
 774
 775        platform_set_drvdata(pdev, i2c_dev);
 776
 777        if (!i2c_dev->hw->has_single_clk_source) {
 778                ret = clk_prepare(i2c_dev->fast_clk);
 779                if (ret < 0) {
 780                        dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
 781                        return ret;
 782                }
 783        }
 784
 785        clk_multiplier *= (i2c_dev->hw->clk_divisor_std_fast_mode + 1);
 786        ret = clk_set_rate(i2c_dev->div_clk,
 787                           i2c_dev->bus_clk_rate * clk_multiplier);
 788        if (ret) {
 789                dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret);
 790                goto unprepare_fast_clk;
 791        }
 792
 793        ret = clk_prepare(i2c_dev->div_clk);
 794        if (ret < 0) {
 795                dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
 796                goto unprepare_fast_clk;
 797        }
 798
 799        ret = tegra_i2c_init(i2c_dev);
 800        if (ret) {
 801                dev_err(&pdev->dev, "Failed to initialize i2c controller");
 802                goto unprepare_div_clk;
 803        }
 804
 805        ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
 806                        tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
 807        if (ret) {
 808                dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
 809                goto unprepare_div_clk;
 810        }
 811
 812        i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
 813        i2c_dev->adapter.owner = THIS_MODULE;
 814        i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
 815        strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
 816                sizeof(i2c_dev->adapter.name));
 817        i2c_dev->adapter.algo = &tegra_i2c_algo;
 818        i2c_dev->adapter.dev.parent = &pdev->dev;
 819        i2c_dev->adapter.nr = pdev->id;
 820        i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
 821
 822        ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
 823        if (ret) {
 824                dev_err(&pdev->dev, "Failed to add I2C adapter\n");
 825                goto unprepare_div_clk;
 826        }
 827
 828        return 0;
 829
 830unprepare_div_clk:
 831        clk_unprepare(i2c_dev->div_clk);
 832
 833unprepare_fast_clk:
 834        if (!i2c_dev->hw->has_single_clk_source)
 835                clk_unprepare(i2c_dev->fast_clk);
 836
 837        return ret;
 838}
 839
 840static int tegra_i2c_remove(struct platform_device *pdev)
 841{
 842        struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 843        i2c_del_adapter(&i2c_dev->adapter);
 844
 845        clk_unprepare(i2c_dev->div_clk);
 846        if (!i2c_dev->hw->has_single_clk_source)
 847                clk_unprepare(i2c_dev->fast_clk);
 848
 849        return 0;
 850}
 851
 852#ifdef CONFIG_PM_SLEEP
 853static int tegra_i2c_suspend(struct device *dev)
 854{
 855        struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 856
 857        i2c_lock_adapter(&i2c_dev->adapter);
 858        i2c_dev->is_suspended = true;
 859        i2c_unlock_adapter(&i2c_dev->adapter);
 860
 861        return 0;
 862}
 863
 864static int tegra_i2c_resume(struct device *dev)
 865{
 866        struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 867        int ret;
 868
 869        i2c_lock_adapter(&i2c_dev->adapter);
 870
 871        ret = tegra_i2c_init(i2c_dev);
 872
 873        if (ret) {
 874                i2c_unlock_adapter(&i2c_dev->adapter);
 875                return ret;
 876        }
 877
 878        i2c_dev->is_suspended = false;
 879
 880        i2c_unlock_adapter(&i2c_dev->adapter);
 881
 882        return 0;
 883}
 884
 885static SIMPLE_DEV_PM_OPS(tegra_i2c_pm, tegra_i2c_suspend, tegra_i2c_resume);
 886#define TEGRA_I2C_PM    (&tegra_i2c_pm)
 887#else
 888#define TEGRA_I2C_PM    NULL
 889#endif
 890
 891static struct platform_driver tegra_i2c_driver = {
 892        .probe   = tegra_i2c_probe,
 893        .remove  = tegra_i2c_remove,
 894        .driver  = {
 895                .name  = "tegra-i2c",
 896                .of_match_table = tegra_i2c_of_match,
 897                .pm    = TEGRA_I2C_PM,
 898        },
 899};
 900
 901static int __init tegra_i2c_init_driver(void)
 902{
 903        return platform_driver_register(&tegra_i2c_driver);
 904}
 905
 906static void __exit tegra_i2c_exit_driver(void)
 907{
 908        platform_driver_unregister(&tegra_i2c_driver);
 909}
 910
 911subsys_initcall(tegra_i2c_init_driver);
 912module_exit(tegra_i2c_exit_driver);
 913
 914MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
 915MODULE_AUTHOR("Colin Cross");
 916MODULE_LICENSE("GPL v2");
 917
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