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20#include <linux/clk.h>
21#include <linux/completion.h>
22#include <linux/dma-mapping.h>
23#include <linux/dmaengine.h>
24#include <linux/err.h>
25#include <linux/i2c.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/module.h>
29#include <linux/of.h>
30#include <linux/of_device.h>
31#include <linux/of_i2c.h>
32#include <linux/platform_device.h>
33#include <linux/slab.h>
34#include <linux/platform_data/dma-atmel.h>
35
36#define TWI_CLK_HZ 100000
37#define AT91_I2C_TIMEOUT msecs_to_jiffies(100)
38#define AT91_I2C_DMA_THRESHOLD 8
39
40
41#define AT91_TWI_CR 0x0000
42#define AT91_TWI_START 0x0001
43#define AT91_TWI_STOP 0x0002
44#define AT91_TWI_MSEN 0x0004
45#define AT91_TWI_SVDIS 0x0020
46#define AT91_TWI_QUICK 0x0040
47#define AT91_TWI_SWRST 0x0080
48
49#define AT91_TWI_MMR 0x0004
50#define AT91_TWI_IADRSZ_1 0x0100
51#define AT91_TWI_MREAD 0x1000
52
53#define AT91_TWI_IADR 0x000c
54
55#define AT91_TWI_CWGR 0x0010
56
57#define AT91_TWI_SR 0x0020
58#define AT91_TWI_TXCOMP 0x0001
59#define AT91_TWI_RXRDY 0x0002
60#define AT91_TWI_TXRDY 0x0004
61
62#define AT91_TWI_OVRE 0x0040
63#define AT91_TWI_UNRE 0x0080
64#define AT91_TWI_NACK 0x0100
65
66#define AT91_TWI_IER 0x0024
67#define AT91_TWI_IDR 0x0028
68#define AT91_TWI_IMR 0x002c
69#define AT91_TWI_RHR 0x0030
70#define AT91_TWI_THR 0x0034
71
72struct at91_twi_pdata {
73 unsigned clk_max_div;
74 unsigned clk_offset;
75 bool has_unre_flag;
76 bool has_dma_support;
77 struct at_dma_slave dma_slave;
78};
79
80struct at91_twi_dma {
81 struct dma_chan *chan_rx;
82 struct dma_chan *chan_tx;
83 struct scatterlist sg;
84 struct dma_async_tx_descriptor *data_desc;
85 enum dma_data_direction direction;
86 bool buf_mapped;
87 bool xfer_in_progress;
88};
89
90struct at91_twi_dev {
91 struct device *dev;
92 void __iomem *base;
93 struct completion cmd_complete;
94 struct clk *clk;
95 u8 *buf;
96 size_t buf_len;
97 struct i2c_msg *msg;
98 int irq;
99 unsigned imr;
100 unsigned transfer_status;
101 struct i2c_adapter adapter;
102 unsigned twi_cwgr_reg;
103 struct at91_twi_pdata *pdata;
104 bool use_dma;
105 struct at91_twi_dma dma;
106};
107
108static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg)
109{
110 return readl_relaxed(dev->base + reg);
111}
112
113static void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val)
114{
115 writel_relaxed(val, dev->base + reg);
116}
117
118static void at91_disable_twi_interrupts(struct at91_twi_dev *dev)
119{
120 at91_twi_write(dev, AT91_TWI_IDR,
121 AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY);
122}
123
124static void at91_twi_irq_save(struct at91_twi_dev *dev)
125{
126 dev->imr = at91_twi_read(dev, AT91_TWI_IMR) & 0x7;
127 at91_disable_twi_interrupts(dev);
128}
129
130static void at91_twi_irq_restore(struct at91_twi_dev *dev)
131{
132 at91_twi_write(dev, AT91_TWI_IER, dev->imr);
133}
134
135static void at91_init_twi_bus(struct at91_twi_dev *dev)
136{
137 at91_disable_twi_interrupts(dev);
138 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST);
139 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSEN);
140 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVDIS);
141 at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg);
142}
143
144
145
146
147
148static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
149{
150 int ckdiv, cdiv, div;
151 struct at91_twi_pdata *pdata = dev->pdata;
152 int offset = pdata->clk_offset;
153 int max_ckdiv = pdata->clk_max_div;
154
155 div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
156 2 * twi_clk) - offset);
157 ckdiv = fls(div >> 8);
158 cdiv = div >> ckdiv;
159
160 if (ckdiv > max_ckdiv) {
161 dev_warn(dev->dev, "%d exceeds ckdiv max value which is %d.\n",
162 ckdiv, max_ckdiv);
163 ckdiv = max_ckdiv;
164 cdiv = 255;
165 }
166
167 dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv;
168 dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
169}
170
171static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
172{
173 struct at91_twi_dma *dma = &dev->dma;
174
175 at91_twi_irq_save(dev);
176
177 if (dma->xfer_in_progress) {
178 if (dma->direction == DMA_FROM_DEVICE)
179 dmaengine_terminate_all(dma->chan_rx);
180 else
181 dmaengine_terminate_all(dma->chan_tx);
182 dma->xfer_in_progress = false;
183 }
184 if (dma->buf_mapped) {
185 dma_unmap_single(dev->dev, sg_dma_address(&dma->sg),
186 dev->buf_len, dma->direction);
187 dma->buf_mapped = false;
188 }
189
190 at91_twi_irq_restore(dev);
191}
192
193static void at91_twi_write_next_byte(struct at91_twi_dev *dev)
194{
195 if (dev->buf_len <= 0)
196 return;
197
198 at91_twi_write(dev, AT91_TWI_THR, *dev->buf);
199
200
201 if (--dev->buf_len == 0)
202 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
203
204 dev_dbg(dev->dev, "wrote 0x%x, to go %d\n", *dev->buf, dev->buf_len);
205
206 ++dev->buf;
207}
208
209static void at91_twi_write_data_dma_callback(void *data)
210{
211 struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
212
213 dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg),
214 dev->buf_len, DMA_MEM_TO_DEV);
215
216 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
217}
218
219static void at91_twi_write_data_dma(struct at91_twi_dev *dev)
220{
221 dma_addr_t dma_addr;
222 struct dma_async_tx_descriptor *txdesc;
223 struct at91_twi_dma *dma = &dev->dma;
224 struct dma_chan *chan_tx = dma->chan_tx;
225
226 if (dev->buf_len <= 0)
227 return;
228
229 dma->direction = DMA_TO_DEVICE;
230
231 at91_twi_irq_save(dev);
232 dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len,
233 DMA_TO_DEVICE);
234 if (dma_mapping_error(dev->dev, dma_addr)) {
235 dev_err(dev->dev, "dma map failed\n");
236 return;
237 }
238 dma->buf_mapped = true;
239 at91_twi_irq_restore(dev);
240 sg_dma_len(&dma->sg) = dev->buf_len;
241 sg_dma_address(&dma->sg) = dma_addr;
242
243 txdesc = dmaengine_prep_slave_sg(chan_tx, &dma->sg, 1, DMA_MEM_TO_DEV,
244 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
245 if (!txdesc) {
246 dev_err(dev->dev, "dma prep slave sg failed\n");
247 goto error;
248 }
249
250 txdesc->callback = at91_twi_write_data_dma_callback;
251 txdesc->callback_param = dev;
252
253 dma->xfer_in_progress = true;
254 dmaengine_submit(txdesc);
255 dma_async_issue_pending(chan_tx);
256
257 return;
258
259error:
260 at91_twi_dma_cleanup(dev);
261}
262
263static void at91_twi_read_next_byte(struct at91_twi_dev *dev)
264{
265 if (dev->buf_len <= 0)
266 return;
267
268 *dev->buf = at91_twi_read(dev, AT91_TWI_RHR) & 0xff;
269 --dev->buf_len;
270
271
272 if (unlikely(dev->msg->flags & I2C_M_RECV_LEN)) {
273 dev->msg->flags &= ~I2C_M_RECV_LEN;
274 dev->buf_len += *dev->buf;
275 dev->msg->len = dev->buf_len + 1;
276 dev_dbg(dev->dev, "received block length %d\n", dev->buf_len);
277 }
278
279
280 if (dev->buf_len == 1)
281 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
282
283 dev_dbg(dev->dev, "read 0x%x, to go %d\n", *dev->buf, dev->buf_len);
284
285 ++dev->buf;
286}
287
288static void at91_twi_read_data_dma_callback(void *data)
289{
290 struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
291
292 dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg),
293 dev->buf_len, DMA_DEV_TO_MEM);
294
295
296 dev->buf += dev->buf_len - 2;
297 dev->buf_len = 2;
298 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_RXRDY);
299}
300
301static void at91_twi_read_data_dma(struct at91_twi_dev *dev)
302{
303 dma_addr_t dma_addr;
304 struct dma_async_tx_descriptor *rxdesc;
305 struct at91_twi_dma *dma = &dev->dma;
306 struct dma_chan *chan_rx = dma->chan_rx;
307
308 dma->direction = DMA_FROM_DEVICE;
309
310
311 at91_twi_irq_save(dev);
312 dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len - 2,
313 DMA_FROM_DEVICE);
314 if (dma_mapping_error(dev->dev, dma_addr)) {
315 dev_err(dev->dev, "dma map failed\n");
316 return;
317 }
318 dma->buf_mapped = true;
319 at91_twi_irq_restore(dev);
320 dma->sg.dma_address = dma_addr;
321 sg_dma_len(&dma->sg) = dev->buf_len - 2;
322
323 rxdesc = dmaengine_prep_slave_sg(chan_rx, &dma->sg, 1, DMA_DEV_TO_MEM,
324 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
325 if (!rxdesc) {
326 dev_err(dev->dev, "dma prep slave sg failed\n");
327 goto error;
328 }
329
330 rxdesc->callback = at91_twi_read_data_dma_callback;
331 rxdesc->callback_param = dev;
332
333 dma->xfer_in_progress = true;
334 dmaengine_submit(rxdesc);
335 dma_async_issue_pending(dma->chan_rx);
336
337 return;
338
339error:
340 at91_twi_dma_cleanup(dev);
341}
342
343static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id)
344{
345 struct at91_twi_dev *dev = dev_id;
346 const unsigned status = at91_twi_read(dev, AT91_TWI_SR);
347 const unsigned irqstatus = status & at91_twi_read(dev, AT91_TWI_IMR);
348
349 if (!irqstatus)
350 return IRQ_NONE;
351 else if (irqstatus & AT91_TWI_RXRDY)
352 at91_twi_read_next_byte(dev);
353 else if (irqstatus & AT91_TWI_TXRDY)
354 at91_twi_write_next_byte(dev);
355
356
357 dev->transfer_status |= status;
358
359 if (irqstatus & AT91_TWI_TXCOMP) {
360 at91_disable_twi_interrupts(dev);
361 complete(&dev->cmd_complete);
362 }
363
364 return IRQ_HANDLED;
365}
366
367static int at91_do_twi_transfer(struct at91_twi_dev *dev)
368{
369 int ret;
370 bool has_unre_flag = dev->pdata->has_unre_flag;
371
372 dev_dbg(dev->dev, "transfer: %s %d bytes.\n",
373 (dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len);
374
375 INIT_COMPLETION(dev->cmd_complete);
376 dev->transfer_status = 0;
377
378 if (!dev->buf_len) {
379 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_QUICK);
380 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
381 } else if (dev->msg->flags & I2C_M_RD) {
382 unsigned start_flags = AT91_TWI_START;
383
384 if (at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_RXRDY) {
385 dev_err(dev->dev, "RXRDY still set!");
386 at91_twi_read(dev, AT91_TWI_RHR);
387 }
388
389
390 if (dev->buf_len <= 1 && !(dev->msg->flags & I2C_M_RECV_LEN))
391 start_flags |= AT91_TWI_STOP;
392 at91_twi_write(dev, AT91_TWI_CR, start_flags);
393
394
395
396
397
398
399
400
401 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
402 at91_twi_read_data_dma(dev);
403
404
405
406
407
408
409 at91_twi_write(dev, AT91_TWI_IER,
410 AT91_TWI_TXCOMP);
411 } else
412 at91_twi_write(dev, AT91_TWI_IER,
413 AT91_TWI_TXCOMP | AT91_TWI_RXRDY);
414 } else {
415 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
416 at91_twi_write_data_dma(dev);
417 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
418 } else {
419 at91_twi_write_next_byte(dev);
420 at91_twi_write(dev, AT91_TWI_IER,
421 AT91_TWI_TXCOMP | AT91_TWI_TXRDY);
422 }
423 }
424
425 ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
426 dev->adapter.timeout);
427 if (ret == 0) {
428 dev_err(dev->dev, "controller timed out\n");
429 at91_init_twi_bus(dev);
430 ret = -ETIMEDOUT;
431 goto error;
432 }
433 if (dev->transfer_status & AT91_TWI_NACK) {
434 dev_dbg(dev->dev, "received nack\n");
435 ret = -EREMOTEIO;
436 goto error;
437 }
438 if (dev->transfer_status & AT91_TWI_OVRE) {
439 dev_err(dev->dev, "overrun while reading\n");
440 ret = -EIO;
441 goto error;
442 }
443 if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) {
444 dev_err(dev->dev, "underrun while writing\n");
445 ret = -EIO;
446 goto error;
447 }
448 dev_dbg(dev->dev, "transfer complete\n");
449
450 return 0;
451
452error:
453 at91_twi_dma_cleanup(dev);
454 return ret;
455}
456
457static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
458{
459 struct at91_twi_dev *dev = i2c_get_adapdata(adap);
460 int ret;
461 unsigned int_addr_flag = 0;
462 struct i2c_msg *m_start = msg;
463
464 dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num);
465
466
467
468
469
470 if (num > 2) {
471 dev_err(dev->dev,
472 "cannot handle more than two concatenated messages.\n");
473 return 0;
474 } else if (num == 2) {
475 int internal_address = 0;
476 int i;
477
478 if (msg->flags & I2C_M_RD) {
479 dev_err(dev->dev, "first transfer must be write.\n");
480 return -EINVAL;
481 }
482 if (msg->len > 3) {
483 dev_err(dev->dev, "first message size must be <= 3.\n");
484 return -EINVAL;
485 }
486
487
488 m_start = &msg[1];
489 for (i = 0; i < msg->len; ++i) {
490 const unsigned addr = msg->buf[msg->len - 1 - i];
491
492 internal_address |= addr << (8 * i);
493 int_addr_flag += AT91_TWI_IADRSZ_1;
494 }
495 at91_twi_write(dev, AT91_TWI_IADR, internal_address);
496 }
497
498 at91_twi_write(dev, AT91_TWI_MMR, (m_start->addr << 16) | int_addr_flag
499 | ((m_start->flags & I2C_M_RD) ? AT91_TWI_MREAD : 0));
500
501 dev->buf_len = m_start->len;
502 dev->buf = m_start->buf;
503 dev->msg = m_start;
504
505 ret = at91_do_twi_transfer(dev);
506
507 return (ret < 0) ? ret : num;
508}
509
510static u32 at91_twi_func(struct i2c_adapter *adapter)
511{
512 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
513 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
514}
515
516static struct i2c_algorithm at91_twi_algorithm = {
517 .master_xfer = at91_twi_xfer,
518 .functionality = at91_twi_func,
519};
520
521static struct at91_twi_pdata at91rm9200_config = {
522 .clk_max_div = 5,
523 .clk_offset = 3,
524 .has_unre_flag = true,
525 .has_dma_support = false,
526};
527
528static struct at91_twi_pdata at91sam9261_config = {
529 .clk_max_div = 5,
530 .clk_offset = 4,
531 .has_unre_flag = false,
532 .has_dma_support = false,
533};
534
535static struct at91_twi_pdata at91sam9260_config = {
536 .clk_max_div = 7,
537 .clk_offset = 4,
538 .has_unre_flag = false,
539 .has_dma_support = false,
540};
541
542static struct at91_twi_pdata at91sam9g20_config = {
543 .clk_max_div = 7,
544 .clk_offset = 4,
545 .has_unre_flag = false,
546 .has_dma_support = false,
547};
548
549static struct at91_twi_pdata at91sam9g10_config = {
550 .clk_max_div = 7,
551 .clk_offset = 4,
552 .has_unre_flag = false,
553 .has_dma_support = false,
554};
555
556static const struct platform_device_id at91_twi_devtypes[] = {
557 {
558 .name = "i2c-at91rm9200",
559 .driver_data = (unsigned long) &at91rm9200_config,
560 }, {
561 .name = "i2c-at91sam9261",
562 .driver_data = (unsigned long) &at91sam9261_config,
563 }, {
564 .name = "i2c-at91sam9260",
565 .driver_data = (unsigned long) &at91sam9260_config,
566 }, {
567 .name = "i2c-at91sam9g20",
568 .driver_data = (unsigned long) &at91sam9g20_config,
569 }, {
570 .name = "i2c-at91sam9g10",
571 .driver_data = (unsigned long) &at91sam9g10_config,
572 }, {
573
574 }
575};
576
577#if defined(CONFIG_OF)
578static struct at91_twi_pdata at91sam9x5_config = {
579 .clk_max_div = 7,
580 .clk_offset = 4,
581 .has_unre_flag = false,
582 .has_dma_support = true,
583};
584
585static const struct of_device_id atmel_twi_dt_ids[] = {
586 {
587 .compatible = "atmel,at91rm9200-i2c",
588 .data = &at91rm9200_config,
589 } , {
590 .compatible = "atmel,at91sam9260-i2c",
591 .data = &at91sam9260_config,
592 } , {
593 .compatible = "atmel,at91sam9g20-i2c",
594 .data = &at91sam9g20_config,
595 } , {
596 .compatible = "atmel,at91sam9g10-i2c",
597 .data = &at91sam9g10_config,
598 }, {
599 .compatible = "atmel,at91sam9x5-i2c",
600 .data = &at91sam9x5_config,
601 }, {
602
603 }
604};
605MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids);
606#else
607#define atmel_twi_dt_ids NULL
608#endif
609
610static bool filter(struct dma_chan *chan, void *slave)
611{
612 struct at_dma_slave *sl = slave;
613
614 if (sl->dma_dev == chan->device->dev) {
615 chan->private = sl;
616 return true;
617 } else {
618 return false;
619 }
620}
621
622static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr)
623{
624 int ret = 0;
625 struct at_dma_slave *sdata;
626 struct dma_slave_config slave_config;
627 struct at91_twi_dma *dma = &dev->dma;
628
629 sdata = &dev->pdata->dma_slave;
630
631 memset(&slave_config, 0, sizeof(slave_config));
632 slave_config.src_addr = (dma_addr_t)phy_addr + AT91_TWI_RHR;
633 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
634 slave_config.src_maxburst = 1;
635 slave_config.dst_addr = (dma_addr_t)phy_addr + AT91_TWI_THR;
636 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
637 slave_config.dst_maxburst = 1;
638 slave_config.device_fc = false;
639
640 if (sdata && sdata->dma_dev) {
641 dma_cap_mask_t mask;
642
643 dma_cap_zero(mask);
644 dma_cap_set(DMA_SLAVE, mask);
645 dma->chan_tx = dma_request_channel(mask, filter, sdata);
646 if (!dma->chan_tx) {
647 dev_err(dev->dev, "no DMA channel available for tx\n");
648 ret = -EBUSY;
649 goto error;
650 }
651 dma->chan_rx = dma_request_channel(mask, filter, sdata);
652 if (!dma->chan_rx) {
653 dev_err(dev->dev, "no DMA channel available for rx\n");
654 ret = -EBUSY;
655 goto error;
656 }
657 } else {
658 ret = -EINVAL;
659 goto error;
660 }
661
662 slave_config.direction = DMA_MEM_TO_DEV;
663 if (dmaengine_slave_config(dma->chan_tx, &slave_config)) {
664 dev_err(dev->dev, "failed to configure tx channel\n");
665 ret = -EINVAL;
666 goto error;
667 }
668
669 slave_config.direction = DMA_DEV_TO_MEM;
670 if (dmaengine_slave_config(dma->chan_rx, &slave_config)) {
671 dev_err(dev->dev, "failed to configure rx channel\n");
672 ret = -EINVAL;
673 goto error;
674 }
675
676 sg_init_table(&dma->sg, 1);
677 dma->buf_mapped = false;
678 dma->xfer_in_progress = false;
679
680 dev_info(dev->dev, "using %s (tx) and %s (rx) for DMA transfers\n",
681 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
682
683 return ret;
684
685error:
686 dev_info(dev->dev, "can't use DMA\n");
687 if (dma->chan_rx)
688 dma_release_channel(dma->chan_rx);
689 if (dma->chan_tx)
690 dma_release_channel(dma->chan_tx);
691 return ret;
692}
693
694static struct at91_twi_pdata *at91_twi_get_driver_data(
695 struct platform_device *pdev)
696{
697 if (pdev->dev.of_node) {
698 const struct of_device_id *match;
699 match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node);
700 if (!match)
701 return NULL;
702 return (struct at91_twi_pdata *)match->data;
703 }
704 return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data;
705}
706
707static int at91_twi_probe(struct platform_device *pdev)
708{
709 struct at91_twi_dev *dev;
710 struct resource *mem;
711 int rc;
712 u32 phy_addr;
713
714 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
715 if (!dev)
716 return -ENOMEM;
717 init_completion(&dev->cmd_complete);
718 dev->dev = &pdev->dev;
719
720 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
721 if (!mem)
722 return -ENODEV;
723 phy_addr = mem->start;
724
725 dev->pdata = at91_twi_get_driver_data(pdev);
726 if (!dev->pdata)
727 return -ENODEV;
728
729 dev->base = devm_ioremap_resource(&pdev->dev, mem);
730 if (IS_ERR(dev->base))
731 return PTR_ERR(dev->base);
732
733 dev->irq = platform_get_irq(pdev, 0);
734 if (dev->irq < 0)
735 return dev->irq;
736
737 rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt, 0,
738 dev_name(dev->dev), dev);
739 if (rc) {
740 dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc);
741 return rc;
742 }
743
744 platform_set_drvdata(pdev, dev);
745
746 dev->clk = devm_clk_get(dev->dev, NULL);
747 if (IS_ERR(dev->clk)) {
748 dev_err(dev->dev, "no clock defined\n");
749 return -ENODEV;
750 }
751 clk_prepare_enable(dev->clk);
752
753 if (dev->pdata->has_dma_support) {
754 if (at91_twi_configure_dma(dev, phy_addr) == 0)
755 dev->use_dma = true;
756 }
757
758 at91_calc_twi_clock(dev, TWI_CLK_HZ);
759 at91_init_twi_bus(dev);
760
761 snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91");
762 i2c_set_adapdata(&dev->adapter, dev);
763 dev->adapter.owner = THIS_MODULE;
764 dev->adapter.class = I2C_CLASS_HWMON;
765 dev->adapter.algo = &at91_twi_algorithm;
766 dev->adapter.dev.parent = dev->dev;
767 dev->adapter.nr = pdev->id;
768 dev->adapter.timeout = AT91_I2C_TIMEOUT;
769 dev->adapter.dev.of_node = pdev->dev.of_node;
770
771 rc = i2c_add_numbered_adapter(&dev->adapter);
772 if (rc) {
773 dev_err(dev->dev, "Adapter %s registration failed\n",
774 dev->adapter.name);
775 clk_disable_unprepare(dev->clk);
776 return rc;
777 }
778
779 of_i2c_register_devices(&dev->adapter);
780
781 dev_info(dev->dev, "AT91 i2c bus driver.\n");
782 return 0;
783}
784
785static int at91_twi_remove(struct platform_device *pdev)
786{
787 struct at91_twi_dev *dev = platform_get_drvdata(pdev);
788 int rc;
789
790 rc = i2c_del_adapter(&dev->adapter);
791 clk_disable_unprepare(dev->clk);
792
793 return rc;
794}
795
796#ifdef CONFIG_PM
797
798static int at91_twi_runtime_suspend(struct device *dev)
799{
800 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
801
802 clk_disable(twi_dev->clk);
803
804 return 0;
805}
806
807static int at91_twi_runtime_resume(struct device *dev)
808{
809 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
810
811 return clk_enable(twi_dev->clk);
812}
813
814static const struct dev_pm_ops at91_twi_pm = {
815 .runtime_suspend = at91_twi_runtime_suspend,
816 .runtime_resume = at91_twi_runtime_resume,
817};
818
819#define at91_twi_pm_ops (&at91_twi_pm)
820#else
821#define at91_twi_pm_ops NULL
822#endif
823
824static struct platform_driver at91_twi_driver = {
825 .probe = at91_twi_probe,
826 .remove = at91_twi_remove,
827 .id_table = at91_twi_devtypes,
828 .driver = {
829 .name = "at91_i2c",
830 .owner = THIS_MODULE,
831 .of_match_table = atmel_twi_dt_ids,
832 .pm = at91_twi_pm_ops,
833 },
834};
835
836static int __init at91_twi_init(void)
837{
838 return platform_driver_register(&at91_twi_driver);
839}
840
841static void __exit at91_twi_exit(void)
842{
843 platform_driver_unregister(&at91_twi_driver);
844}
845
846subsys_initcall(at91_twi_init);
847module_exit(at91_twi_exit);
848
849MODULE_AUTHOR("Nikolaus Voss <n.voss@weinmann.de>");
850MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91");
851MODULE_LICENSE("GPL");
852MODULE_ALIAS("platform:at91_i2c");
853
