linux/drivers/edac/ppc4xx_edac.c
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   1/*
   2 * Copyright (c) 2008 Nuovation System Designs, LLC
   3 *   Grant Erickson <gerickson@nuovations.com>
   4 *
   5 * This program is free software; you can redistribute it and/or
   6 * modify it under the terms of the GNU General Public License as
   7 * published by the Free Software Foundation; version 2 of the
   8 * License.
   9 *
  10 */
  11
  12#include <linux/edac.h>
  13#include <linux/interrupt.h>
  14#include <linux/irq.h>
  15#include <linux/kernel.h>
  16#include <linux/mm.h>
  17#include <linux/module.h>
  18#include <linux/of_device.h>
  19#include <linux/of_platform.h>
  20#include <linux/types.h>
  21
  22#include <asm/dcr.h>
  23
  24#include "edac_core.h"
  25#include "ppc4xx_edac.h"
  26
  27/*
  28 * This file implements a driver for monitoring and handling events
  29 * associated with the IMB DDR2 ECC controller found in the AMCC/IBM
  30 * 405EX[r], 440SP, 440SPe, 460EX, 460GT and 460SX.
  31 *
  32 * As realized in the 405EX[r], this controller features:
  33 *
  34 *   - Support for registered- and non-registered DDR1 and DDR2 memory.
  35 *   - 32-bit or 16-bit memory interface with optional ECC.
  36 *
  37 *     o ECC support includes:
  38 *
  39 *       - 4-bit SEC/DED
  40 *       - Aligned-nibble error detect
  41 *       - Bypass mode
  42 *
  43 *   - Two (2) memory banks/ranks.
  44 *   - Up to 1 GiB per bank/rank in 32-bit mode and up to 512 MiB per
  45 *     bank/rank in 16-bit mode.
  46 *
  47 * As realized in the 440SP and 440SPe, this controller changes/adds:
  48 *
  49 *   - 64-bit or 32-bit memory interface with optional ECC.
  50 *
  51 *     o ECC support includes:
  52 *
  53 *       - 8-bit SEC/DED
  54 *       - Aligned-nibble error detect
  55 *       - Bypass mode
  56 *
  57 *   - Up to 4 GiB per bank/rank in 64-bit mode and up to 2 GiB
  58 *     per bank/rank in 32-bit mode.
  59 *
  60 * As realized in the 460EX and 460GT, this controller changes/adds:
  61 *
  62 *   - 64-bit or 32-bit memory interface with optional ECC.
  63 *
  64 *     o ECC support includes:
  65 *
  66 *       - 8-bit SEC/DED
  67 *       - Aligned-nibble error detect
  68 *       - Bypass mode
  69 *
  70 *   - Four (4) memory banks/ranks.
  71 *   - Up to 16 GiB per bank/rank in 64-bit mode and up to 8 GiB
  72 *     per bank/rank in 32-bit mode.
  73 *
  74 * At present, this driver has ONLY been tested against the controller
  75 * realization in the 405EX[r] on the AMCC Kilauea and Haleakala
  76 * boards (256 MiB w/o ECC memory soldered onto the board) and a
  77 * proprietary board based on those designs (128 MiB ECC memory, also
  78 * soldered onto the board).
  79 *
  80 * Dynamic feature detection and handling needs to be added for the
  81 * other realizations of this controller listed above.
  82 *
  83 * Eventually, this driver will likely be adapted to the above variant
  84 * realizations of this controller as well as broken apart to handle
  85 * the other known ECC-capable controllers prevalent in other 4xx
  86 * processors:
  87 *
  88 *   - IBM SDRAM (405GP, 405CR and 405EP) "ibm,sdram-4xx"
  89 *   - IBM DDR1 (440GP, 440GX, 440EP and 440GR) "ibm,sdram-4xx-ddr"
  90 *   - Denali DDR1/DDR2 (440EPX and 440GRX) "denali,sdram-4xx-ddr2"
  91 *
  92 * For this controller, unfortunately, correctable errors report
  93 * nothing more than the beat/cycle and byte/lane the correction
  94 * occurred on and the check bit group that covered the error.
  95 *
  96 * In contrast, uncorrectable errors also report the failing address,
  97 * the bus master and the transaction direction (i.e. read or write)
  98 *
  99 * Regardless of whether the error is a CE or a UE, we report the
 100 * following pieces of information in the driver-unique message to the
 101 * EDAC subsystem:
 102 *
 103 *   - Device tree path
 104 *   - Bank(s)
 105 *   - Check bit error group
 106 *   - Beat(s)/lane(s)
 107 */
 108
 109/* Preprocessor Definitions */
 110
 111#define EDAC_OPSTATE_INT_STR            "interrupt"
 112#define EDAC_OPSTATE_POLL_STR           "polled"
 113#define EDAC_OPSTATE_UNKNOWN_STR        "unknown"
 114
 115#define PPC4XX_EDAC_MODULE_NAME         "ppc4xx_edac"
 116#define PPC4XX_EDAC_MODULE_REVISION     "v1.0.0"
 117
 118#define PPC4XX_EDAC_MESSAGE_SIZE        256
 119
 120/*
 121 * Kernel logging without an EDAC instance
 122 */
 123#define ppc4xx_edac_printk(level, fmt, arg...) \
 124        edac_printk(level, "PPC4xx MC", fmt, ##arg)
 125
 126/*
 127 * Kernel logging with an EDAC instance
 128 */
 129#define ppc4xx_edac_mc_printk(level, mci, fmt, arg...) \
 130        edac_mc_chipset_printk(mci, level, "PPC4xx", fmt, ##arg)
 131
 132/*
 133 * Macros to convert bank configuration size enumerations into MiB and
 134 * page values.
 135 */
 136#define SDRAM_MBCF_SZ_MiB_MIN           4
 137#define SDRAM_MBCF_SZ_TO_MiB(n)         (SDRAM_MBCF_SZ_MiB_MIN \
 138                                         << (SDRAM_MBCF_SZ_DECODE(n)))
 139#define SDRAM_MBCF_SZ_TO_PAGES(n)       (SDRAM_MBCF_SZ_MiB_MIN \
 140                                         << (20 - PAGE_SHIFT + \
 141                                             SDRAM_MBCF_SZ_DECODE(n)))
 142
 143/*
 144 * The ibm,sdram-4xx-ddr2 Device Control Registers (DCRs) are
 145 * indirectly accessed and have a base and length defined by the
 146 * device tree. The base can be anything; however, we expect the
 147 * length to be precisely two registers, the first for the address
 148 * window and the second for the data window.
 149 */
 150#define SDRAM_DCR_RESOURCE_LEN          2
 151#define SDRAM_DCR_ADDR_OFFSET           0
 152#define SDRAM_DCR_DATA_OFFSET           1
 153
 154/*
 155 * Device tree interrupt indices
 156 */
 157#define INTMAP_ECCDED_INDEX             0       /* Double-bit Error Detect */
 158#define INTMAP_ECCSEC_INDEX             1       /* Single-bit Error Correct */
 159
 160/* Type Definitions */
 161
 162/*
 163 * PPC4xx SDRAM memory controller private instance data
 164 */
 165struct ppc4xx_edac_pdata {
 166        dcr_host_t dcr_host;    /* Indirect DCR address/data window mapping */
 167        struct {
 168                int sec;        /* Single-bit correctable error IRQ assigned */
 169                int ded;        /* Double-bit detectable error IRQ assigned */
 170        } irqs;
 171};
 172
 173/*
 174 * Various status data gathered and manipulated when checking and
 175 * reporting ECC status.
 176 */
 177struct ppc4xx_ecc_status {
 178        u32 ecces;
 179        u32 besr;
 180        u32 bearh;
 181        u32 bearl;
 182        u32 wmirq;
 183};
 184
 185/* Function Prototypes */
 186
 187static int ppc4xx_edac_probe(struct platform_device *device);
 188static int ppc4xx_edac_remove(struct platform_device *device);
 189
 190/* Global Variables */
 191
 192/*
 193 * Device tree node type and compatible tuples this driver can match
 194 * on.
 195 */
 196static struct of_device_id ppc4xx_edac_match[] = {
 197        {
 198                .compatible     = "ibm,sdram-4xx-ddr2"
 199        },
 200        { }
 201};
 202
 203static struct platform_driver ppc4xx_edac_driver = {
 204        .probe                  = ppc4xx_edac_probe,
 205        .remove                 = ppc4xx_edac_remove,
 206        .driver = {
 207                .name = PPC4XX_EDAC_MODULE_NAME,
 208                .of_match_table = ppc4xx_edac_match,
 209        },
 210};
 211
 212/*
 213 * TODO: The row and channel parameters likely need to be dynamically
 214 * set based on the aforementioned variant controller realizations.
 215 */
 216static const unsigned ppc4xx_edac_nr_csrows = 2;
 217static const unsigned ppc4xx_edac_nr_chans = 1;
 218
 219/*
 220 * Strings associated with PLB master IDs capable of being posted in
 221 * SDRAM_BESR or SDRAM_WMIRQ on uncorrectable ECC errors.
 222 */
 223static const char * const ppc4xx_plb_masters[9] = {
 224        [SDRAM_PLB_M0ID_ICU]    = "ICU",
 225        [SDRAM_PLB_M0ID_PCIE0]  = "PCI-E 0",
 226        [SDRAM_PLB_M0ID_PCIE1]  = "PCI-E 1",
 227        [SDRAM_PLB_M0ID_DMA]    = "DMA",
 228        [SDRAM_PLB_M0ID_DCU]    = "DCU",
 229        [SDRAM_PLB_M0ID_OPB]    = "OPB",
 230        [SDRAM_PLB_M0ID_MAL]    = "MAL",
 231        [SDRAM_PLB_M0ID_SEC]    = "SEC",
 232        [SDRAM_PLB_M0ID_AHB]    = "AHB"
 233};
 234
 235/**
 236 * mfsdram - read and return controller register data
 237 * @dcr_host: A pointer to the DCR mapping.
 238 * @idcr_n: The indirect DCR register to read.
 239 *
 240 * This routine reads and returns the data associated with the
 241 * controller's specified indirect DCR register.
 242 *
 243 * Returns the read data.
 244 */
 245static inline u32
 246mfsdram(const dcr_host_t *dcr_host, unsigned int idcr_n)
 247{
 248        return __mfdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET,
 249                        dcr_host->base + SDRAM_DCR_DATA_OFFSET,
 250                        idcr_n);
 251}
 252
 253/**
 254 * mtsdram - write controller register data
 255 * @dcr_host: A pointer to the DCR mapping.
 256 * @idcr_n: The indirect DCR register to write.
 257 * @value: The data to write.
 258 *
 259 * This routine writes the provided data to the controller's specified
 260 * indirect DCR register.
 261 */
 262static inline void
 263mtsdram(const dcr_host_t *dcr_host, unsigned int idcr_n, u32 value)
 264{
 265        return __mtdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET,
 266                        dcr_host->base + SDRAM_DCR_DATA_OFFSET,
 267                        idcr_n,
 268                        value);
 269}
 270
 271/**
 272 * ppc4xx_edac_check_bank_error - check a bank for an ECC bank error
 273 * @status: A pointer to the ECC status structure to check for an
 274 *          ECC bank error.
 275 * @bank: The bank to check for an ECC error.
 276 *
 277 * This routine determines whether the specified bank has an ECC
 278 * error.
 279 *
 280 * Returns true if the specified bank has an ECC error; otherwise,
 281 * false.
 282 */
 283static bool
 284ppc4xx_edac_check_bank_error(const struct ppc4xx_ecc_status *status,
 285                             unsigned int bank)
 286{
 287        switch (bank) {
 288        case 0:
 289                return status->ecces & SDRAM_ECCES_BK0ER;
 290        case 1:
 291                return status->ecces & SDRAM_ECCES_BK1ER;
 292        default:
 293                return false;
 294        }
 295}
 296
 297/**
 298 * ppc4xx_edac_generate_bank_message - generate interpretted bank status message
 299 * @mci: A pointer to the EDAC memory controller instance associated
 300 *       with the bank message being generated.
 301 * @status: A pointer to the ECC status structure to generate the
 302 *          message from.
 303 * @buffer: A pointer to the buffer in which to generate the
 304 *          message.
 305 * @size: The size, in bytes, of space available in buffer.
 306 *
 307 * This routine generates to the provided buffer the portion of the
 308 * driver-unique report message associated with the ECCESS[BKNER]
 309 * field of the specified ECC status.
 310 *
 311 * Returns the number of characters generated on success; otherwise, <
 312 * 0 on error.
 313 */
 314static int
 315ppc4xx_edac_generate_bank_message(const struct mem_ctl_info *mci,
 316                                  const struct ppc4xx_ecc_status *status,
 317                                  char *buffer,
 318                                  size_t size)
 319{
 320        int n, total = 0;
 321        unsigned int row, rows;
 322
 323        n = snprintf(buffer, size, "%s: Banks: ", mci->dev_name);
 324
 325        if (n < 0 || n >= size)
 326                goto fail;
 327
 328        buffer += n;
 329        size -= n;
 330        total += n;
 331
 332        for (rows = 0, row = 0; row < mci->nr_csrows; row++) {
 333                if (ppc4xx_edac_check_bank_error(status, row)) {
 334                        n = snprintf(buffer, size, "%s%u",
 335                                        (rows++ ? ", " : ""), row);
 336
 337                        if (n < 0 || n >= size)
 338                                goto fail;
 339
 340                        buffer += n;
 341                        size -= n;
 342                        total += n;
 343                }
 344        }
 345
 346        n = snprintf(buffer, size, "%s; ", rows ? "" : "None");
 347
 348        if (n < 0 || n >= size)
 349                goto fail;
 350
 351        buffer += n;
 352        size -= n;
 353        total += n;
 354
 355 fail:
 356        return total;
 357}
 358
 359/**
 360 * ppc4xx_edac_generate_checkbit_message - generate interpretted checkbit message
 361 * @mci: A pointer to the EDAC memory controller instance associated
 362 *       with the checkbit message being generated.
 363 * @status: A pointer to the ECC status structure to generate the
 364 *          message from.
 365 * @buffer: A pointer to the buffer in which to generate the
 366 *          message.
 367 * @size: The size, in bytes, of space available in buffer.
 368 *
 369 * This routine generates to the provided buffer the portion of the
 370 * driver-unique report message associated with the ECCESS[CKBER]
 371 * field of the specified ECC status.
 372 *
 373 * Returns the number of characters generated on success; otherwise, <
 374 * 0 on error.
 375 */
 376static int
 377ppc4xx_edac_generate_checkbit_message(const struct mem_ctl_info *mci,
 378                                      const struct ppc4xx_ecc_status *status,
 379                                      char *buffer,
 380                                      size_t size)
 381{
 382        const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
 383        const char *ckber = NULL;
 384
 385        switch (status->ecces & SDRAM_ECCES_CKBER_MASK) {
 386        case SDRAM_ECCES_CKBER_NONE:
 387                ckber = "None";
 388                break;
 389        case SDRAM_ECCES_CKBER_32_ECC_0_3:
 390                ckber = "ECC0:3";
 391                break;
 392        case SDRAM_ECCES_CKBER_32_ECC_4_8:
 393                switch (mfsdram(&pdata->dcr_host, SDRAM_MCOPT1) &
 394                        SDRAM_MCOPT1_WDTH_MASK) {
 395                case SDRAM_MCOPT1_WDTH_16:
 396                        ckber = "ECC0:3";
 397                        break;
 398                case SDRAM_MCOPT1_WDTH_32:
 399                        ckber = "ECC4:8";
 400                        break;
 401                default:
 402                        ckber = "Unknown";
 403                        break;
 404                }
 405                break;
 406        case SDRAM_ECCES_CKBER_32_ECC_0_8:
 407                ckber = "ECC0:8";
 408                break;
 409        default:
 410                ckber = "Unknown";
 411                break;
 412        }
 413
 414        return snprintf(buffer, size, "Checkbit Error: %s", ckber);
 415}
 416
 417/**
 418 * ppc4xx_edac_generate_lane_message - generate interpretted byte lane message
 419 * @mci: A pointer to the EDAC memory controller instance associated
 420 *       with the byte lane message being generated.
 421 * @status: A pointer to the ECC status structure to generate the
 422 *          message from.
 423 * @buffer: A pointer to the buffer in which to generate the
 424 *          message.
 425 * @size: The size, in bytes, of space available in buffer.
 426 *
 427 * This routine generates to the provided buffer the portion of the
 428 * driver-unique report message associated with the ECCESS[BNCE]
 429 * field of the specified ECC status.
 430 *
 431 * Returns the number of characters generated on success; otherwise, <
 432 * 0 on error.
 433 */
 434static int
 435ppc4xx_edac_generate_lane_message(const struct mem_ctl_info *mci,
 436                                  const struct ppc4xx_ecc_status *status,
 437                                  char *buffer,
 438                                  size_t size)
 439{
 440        int n, total = 0;
 441        unsigned int lane, lanes;
 442        const unsigned int first_lane = 0;
 443        const unsigned int lane_count = 16;
 444
 445        n = snprintf(buffer, size, "; Byte Lane Errors: ");
 446
 447        if (n < 0 || n >= size)
 448                goto fail;
 449
 450        buffer += n;
 451        size -= n;
 452        total += n;
 453
 454        for (lanes = 0, lane = first_lane; lane < lane_count; lane++) {
 455                if ((status->ecces & SDRAM_ECCES_BNCE_ENCODE(lane)) != 0) {
 456                        n = snprintf(buffer, size,
 457                                     "%s%u",
 458                                     (lanes++ ? ", " : ""), lane);
 459
 460                        if (n < 0 || n >= size)
 461                                goto fail;
 462
 463                        buffer += n;
 464                        size -= n;
 465                        total += n;
 466                }
 467        }
 468
 469        n = snprintf(buffer, size, "%s; ", lanes ? "" : "None");
 470
 471        if (n < 0 || n >= size)
 472                goto fail;
 473
 474        buffer += n;
 475        size -= n;
 476        total += n;
 477
 478 fail:
 479        return total;
 480}
 481
 482/**
 483 * ppc4xx_edac_generate_ecc_message - generate interpretted ECC status message
 484 * @mci: A pointer to the EDAC memory controller instance associated
 485 *       with the ECCES message being generated.
 486 * @status: A pointer to the ECC status structure to generate the
 487 *          message from.
 488 * @buffer: A pointer to the buffer in which to generate the
 489 *          message.
 490 * @size: The size, in bytes, of space available in buffer.
 491 *
 492 * This routine generates to the provided buffer the portion of the
 493 * driver-unique report message associated with the ECCESS register of
 494 * the specified ECC status.
 495 *
 496 * Returns the number of characters generated on success; otherwise, <
 497 * 0 on error.
 498 */
 499static int
 500ppc4xx_edac_generate_ecc_message(const struct mem_ctl_info *mci,
 501                                 const struct ppc4xx_ecc_status *status,
 502                                 char *buffer,
 503                                 size_t size)
 504{
 505        int n, total = 0;
 506
 507        n = ppc4xx_edac_generate_bank_message(mci, status, buffer, size);
 508
 509        if (n < 0 || n >= size)
 510                goto fail;
 511
 512        buffer += n;
 513        size -= n;
 514        total += n;
 515
 516        n = ppc4xx_edac_generate_checkbit_message(mci, status, buffer, size);
 517
 518        if (n < 0 || n >= size)
 519                goto fail;
 520
 521        buffer += n;
 522        size -= n;
 523        total += n;
 524
 525        n = ppc4xx_edac_generate_lane_message(mci, status, buffer, size);
 526
 527        if (n < 0 || n >= size)
 528                goto fail;
 529
 530        buffer += n;
 531        size -= n;
 532        total += n;
 533
 534 fail:
 535        return total;
 536}
 537
 538/**
 539 * ppc4xx_edac_generate_plb_message - generate interpretted PLB status message
 540 * @mci: A pointer to the EDAC memory controller instance associated
 541 *       with the PLB message being generated.
 542 * @status: A pointer to the ECC status structure to generate the
 543 *          message from.
 544 * @buffer: A pointer to the buffer in which to generate the
 545 *          message.
 546 * @size: The size, in bytes, of space available in buffer.
 547 *
 548 * This routine generates to the provided buffer the portion of the
 549 * driver-unique report message associated with the PLB-related BESR
 550 * and/or WMIRQ registers of the specified ECC status.
 551 *
 552 * Returns the number of characters generated on success; otherwise, <
 553 * 0 on error.
 554 */
 555static int
 556ppc4xx_edac_generate_plb_message(const struct mem_ctl_info *mci,
 557                                 const struct ppc4xx_ecc_status *status,
 558                                 char *buffer,
 559                                 size_t size)
 560{
 561        unsigned int master;
 562        bool read;
 563
 564        if ((status->besr & SDRAM_BESR_MASK) == 0)
 565                return 0;
 566
 567        if ((status->besr & SDRAM_BESR_M0ET_MASK) == SDRAM_BESR_M0ET_NONE)
 568                return 0;
 569
 570        read = ((status->besr & SDRAM_BESR_M0RW_MASK) == SDRAM_BESR_M0RW_READ);
 571
 572        master = SDRAM_BESR_M0ID_DECODE(status->besr);
 573
 574        return snprintf(buffer, size,
 575                        "%s error w/ PLB master %u \"%s\"; ",
 576                        (read ? "Read" : "Write"),
 577                        master,
 578                        (((master >= SDRAM_PLB_M0ID_FIRST) &&
 579                          (master <= SDRAM_PLB_M0ID_LAST)) ?
 580                         ppc4xx_plb_masters[master] : "UNKNOWN"));
 581}
 582
 583/**
 584 * ppc4xx_edac_generate_message - generate interpretted status message
 585 * @mci: A pointer to the EDAC memory controller instance associated
 586 *       with the driver-unique message being generated.
 587 * @status: A pointer to the ECC status structure to generate the
 588 *          message from.
 589 * @buffer: A pointer to the buffer in which to generate the
 590 *          message.
 591 * @size: The size, in bytes, of space available in buffer.
 592 *
 593 * This routine generates to the provided buffer the driver-unique
 594 * EDAC report message from the specified ECC status.
 595 */
 596static void
 597ppc4xx_edac_generate_message(const struct mem_ctl_info *mci,
 598                             const struct ppc4xx_ecc_status *status,
 599                             char *buffer,
 600                             size_t size)
 601{
 602        int n;
 603
 604        if (buffer == NULL || size == 0)
 605                return;
 606
 607        n = ppc4xx_edac_generate_ecc_message(mci, status, buffer, size);
 608
 609        if (n < 0 || n >= size)
 610                return;
 611
 612        buffer += n;
 613        size -= n;
 614
 615        ppc4xx_edac_generate_plb_message(mci, status, buffer, size);
 616}
 617
 618#ifdef DEBUG
 619/**
 620 * ppc4xx_ecc_dump_status - dump controller ECC status registers
 621 * @mci: A pointer to the EDAC memory controller instance
 622 *       associated with the status being dumped.
 623 * @status: A pointer to the ECC status structure to generate the
 624 *          dump from.
 625 *
 626 * This routine dumps to the kernel log buffer the raw and
 627 * interpretted specified ECC status.
 628 */
 629static void
 630ppc4xx_ecc_dump_status(const struct mem_ctl_info *mci,
 631                       const struct ppc4xx_ecc_status *status)
 632{
 633        char message[PPC4XX_EDAC_MESSAGE_SIZE];
 634
 635        ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
 636
 637        ppc4xx_edac_mc_printk(KERN_INFO, mci,
 638                              "\n"
 639                              "\tECCES: 0x%08x\n"
 640                              "\tWMIRQ: 0x%08x\n"
 641                              "\tBESR:  0x%08x\n"
 642                              "\tBEAR:  0x%08x%08x\n"
 643                              "\t%s\n",
 644                              status->ecces,
 645                              status->wmirq,
 646                              status->besr,
 647                              status->bearh,
 648                              status->bearl,
 649                              message);
 650}
 651#endif /* DEBUG */
 652
 653/**
 654 * ppc4xx_ecc_get_status - get controller ECC status
 655 * @mci: A pointer to the EDAC memory controller instance
 656 *       associated with the status being retrieved.
 657 * @status: A pointer to the ECC status structure to populate the
 658 *          ECC status with.
 659 *
 660 * This routine reads and masks, as appropriate, all the relevant
 661 * status registers that deal with ibm,sdram-4xx-ddr2 ECC errors.
 662 * While we read all of them, for correctable errors, we only expect
 663 * to deal with ECCES. For uncorrectable errors, we expect to deal
 664 * with all of them.
 665 */
 666static void
 667ppc4xx_ecc_get_status(const struct mem_ctl_info *mci,
 668                      struct ppc4xx_ecc_status *status)
 669{
 670        const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
 671        const dcr_host_t *dcr_host = &pdata->dcr_host;
 672
 673        status->ecces = mfsdram(dcr_host, SDRAM_ECCES) & SDRAM_ECCES_MASK;
 674        status->wmirq = mfsdram(dcr_host, SDRAM_WMIRQ) & SDRAM_WMIRQ_MASK;
 675        status->besr  = mfsdram(dcr_host, SDRAM_BESR)  & SDRAM_BESR_MASK;
 676        status->bearl = mfsdram(dcr_host, SDRAM_BEARL);
 677        status->bearh = mfsdram(dcr_host, SDRAM_BEARH);
 678}
 679
 680/**
 681 * ppc4xx_ecc_clear_status - clear controller ECC status
 682 * @mci: A pointer to the EDAC memory controller instance
 683 *       associated with the status being cleared.
 684 * @status: A pointer to the ECC status structure containing the
 685 *          values to write to clear the ECC status.
 686 *
 687 * This routine clears--by writing the masked (as appropriate) status
 688 * values back to--the status registers that deal with
 689 * ibm,sdram-4xx-ddr2 ECC errors.
 690 */
 691static void
 692ppc4xx_ecc_clear_status(const struct mem_ctl_info *mci,
 693                        const struct ppc4xx_ecc_status *status)
 694{
 695        const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
 696        const dcr_host_t *dcr_host = &pdata->dcr_host;
 697
 698        mtsdram(dcr_host, SDRAM_ECCES,  status->ecces & SDRAM_ECCES_MASK);
 699        mtsdram(dcr_host, SDRAM_WMIRQ,  status->wmirq & SDRAM_WMIRQ_MASK);
 700        mtsdram(dcr_host, SDRAM_BESR,   status->besr & SDRAM_BESR_MASK);
 701        mtsdram(dcr_host, SDRAM_BEARL,  0);
 702        mtsdram(dcr_host, SDRAM_BEARH,  0);
 703}
 704
 705/**
 706 * ppc4xx_edac_handle_ce - handle controller correctable ECC error (CE)
 707 * @mci: A pointer to the EDAC memory controller instance
 708 *       associated with the correctable error being handled and reported.
 709 * @status: A pointer to the ECC status structure associated with
 710 *          the correctable error being handled and reported.
 711 *
 712 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
 713 * correctable error. Per the aforementioned discussion, there's not
 714 * enough status available to use the full EDAC correctable error
 715 * interface, so we just pass driver-unique message to the "no info"
 716 * interface.
 717 */
 718static void
 719ppc4xx_edac_handle_ce(struct mem_ctl_info *mci,
 720                      const struct ppc4xx_ecc_status *status)
 721{
 722        int row;
 723        char message[PPC4XX_EDAC_MESSAGE_SIZE];
 724
 725        ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
 726
 727        for (row = 0; row < mci->nr_csrows; row++)
 728                if (ppc4xx_edac_check_bank_error(status, row))
 729                        edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
 730                                             0, 0, 0,
 731                                             row, 0, -1,
 732                                             message, "");
 733}
 734
 735/**
 736 * ppc4xx_edac_handle_ue - handle controller uncorrectable ECC error (UE)
 737 * @mci: A pointer to the EDAC memory controller instance
 738 *       associated with the uncorrectable error being handled and
 739 *       reported.
 740 * @status: A pointer to the ECC status structure associated with
 741 *          the uncorrectable error being handled and reported.
 742 *
 743 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
 744 * uncorrectable error.
 745 */
 746static void
 747ppc4xx_edac_handle_ue(struct mem_ctl_info *mci,
 748                      const struct ppc4xx_ecc_status *status)
 749{
 750        const u64 bear = ((u64)status->bearh << 32 | status->bearl);
 751        const unsigned long page = bear >> PAGE_SHIFT;
 752        const unsigned long offset = bear & ~PAGE_MASK;
 753        int row;
 754        char message[PPC4XX_EDAC_MESSAGE_SIZE];
 755
 756        ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
 757
 758        for (row = 0; row < mci->nr_csrows; row++)
 759                if (ppc4xx_edac_check_bank_error(status, row))
 760                        edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
 761                                             page, offset, 0,
 762                                             row, 0, -1,
 763                                             message, "");
 764}
 765
 766/**
 767 * ppc4xx_edac_check - check controller for ECC errors
 768 * @mci: A pointer to the EDAC memory controller instance
 769 *       associated with the ibm,sdram-4xx-ddr2 controller being
 770 *       checked.
 771 *
 772 * This routine is used to check and post ECC errors and is called by
 773 * both the EDAC polling thread and this driver's CE and UE interrupt
 774 * handler.
 775 */
 776static void
 777ppc4xx_edac_check(struct mem_ctl_info *mci)
 778{
 779#ifdef DEBUG
 780        static unsigned int count;
 781#endif
 782        struct ppc4xx_ecc_status status;
 783
 784        ppc4xx_ecc_get_status(mci, &status);
 785
 786#ifdef DEBUG
 787        if (count++ % 30 == 0)
 788                ppc4xx_ecc_dump_status(mci, &status);
 789#endif
 790
 791        if (status.ecces & SDRAM_ECCES_UE)
 792                ppc4xx_edac_handle_ue(mci, &status);
 793
 794        if (status.ecces & SDRAM_ECCES_CE)
 795                ppc4xx_edac_handle_ce(mci, &status);
 796
 797        ppc4xx_ecc_clear_status(mci, &status);
 798}
 799
 800/**
 801 * ppc4xx_edac_isr - SEC (CE) and DED (UE) interrupt service routine
 802 * @irq:    The virtual interrupt number being serviced.
 803 * @dev_id: A pointer to the EDAC memory controller instance
 804 *          associated with the interrupt being handled.
 805 *
 806 * This routine implements the interrupt handler for both correctable
 807 * (CE) and uncorrectable (UE) ECC errors for the ibm,sdram-4xx-ddr2
 808 * controller. It simply calls through to the same routine used during
 809 * polling to check, report and clear the ECC status.
 810 *
 811 * Unconditionally returns IRQ_HANDLED.
 812 */
 813static irqreturn_t
 814ppc4xx_edac_isr(int irq, void *dev_id)
 815{
 816        struct mem_ctl_info *mci = dev_id;
 817
 818        ppc4xx_edac_check(mci);
 819
 820        return IRQ_HANDLED;
 821}
 822
 823/**
 824 * ppc4xx_edac_get_dtype - return the controller memory width
 825 * @mcopt1: The 32-bit Memory Controller Option 1 register value
 826 *          currently set for the controller, from which the width
 827 *          is derived.
 828 *
 829 * This routine returns the EDAC device type width appropriate for the
 830 * current controller configuration.
 831 *
 832 * TODO: This needs to be conditioned dynamically through feature
 833 * flags or some such when other controller variants are supported as
 834 * the 405EX[r] is 16-/32-bit and the others are 32-/64-bit with the
 835 * 16- and 64-bit field definition/value/enumeration (b1) overloaded
 836 * among them.
 837 *
 838 * Returns a device type width enumeration.
 839 */
 840static enum dev_type ppc4xx_edac_get_dtype(u32 mcopt1)
 841{
 842        switch (mcopt1 & SDRAM_MCOPT1_WDTH_MASK) {
 843        case SDRAM_MCOPT1_WDTH_16:
 844                return DEV_X2;
 845        case SDRAM_MCOPT1_WDTH_32:
 846                return DEV_X4;
 847        default:
 848                return DEV_UNKNOWN;
 849        }
 850}
 851
 852/**
 853 * ppc4xx_edac_get_mtype - return controller memory type
 854 * @mcopt1: The 32-bit Memory Controller Option 1 register value
 855 *          currently set for the controller, from which the memory type
 856 *          is derived.
 857 *
 858 * This routine returns the EDAC memory type appropriate for the
 859 * current controller configuration.
 860 *
 861 * Returns a memory type enumeration.
 862 */
 863static enum mem_type ppc4xx_edac_get_mtype(u32 mcopt1)
 864{
 865        bool rden = ((mcopt1 & SDRAM_MCOPT1_RDEN_MASK) == SDRAM_MCOPT1_RDEN);
 866
 867        switch (mcopt1 & SDRAM_MCOPT1_DDR_TYPE_MASK) {
 868        case SDRAM_MCOPT1_DDR2_TYPE:
 869                return rden ? MEM_RDDR2 : MEM_DDR2;
 870        case SDRAM_MCOPT1_DDR1_TYPE:
 871                return rden ? MEM_RDDR : MEM_DDR;
 872        default:
 873                return MEM_UNKNOWN;
 874        }
 875}
 876
 877/**
 878 * ppc4xx_edac_init_csrows - initialize driver instance rows
 879 * @mci: A pointer to the EDAC memory controller instance
 880 *       associated with the ibm,sdram-4xx-ddr2 controller for which
 881 *       the csrows (i.e. banks/ranks) are being initialized.
 882 * @mcopt1: The 32-bit Memory Controller Option 1 register value
 883 *          currently set for the controller, from which bank width
 884 *          and memory typ information is derived.
 885 *
 886 * This routine initializes the virtual "chip select rows" associated
 887 * with the EDAC memory controller instance. An ibm,sdram-4xx-ddr2
 888 * controller bank/rank is mapped to a row.
 889 *
 890 * Returns 0 if OK; otherwise, -EINVAL if the memory bank size
 891 * configuration cannot be determined.
 892 */
 893static int ppc4xx_edac_init_csrows(struct mem_ctl_info *mci, u32 mcopt1)
 894{
 895        const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
 896        int status = 0;
 897        enum mem_type mtype;
 898        enum dev_type dtype;
 899        enum edac_type edac_mode;
 900        int row, j;
 901        u32 mbxcf, size, nr_pages;
 902
 903        /* Establish the memory type and width */
 904
 905        mtype = ppc4xx_edac_get_mtype(mcopt1);
 906        dtype = ppc4xx_edac_get_dtype(mcopt1);
 907
 908        /* Establish EDAC mode */
 909
 910        if (mci->edac_cap & EDAC_FLAG_SECDED)
 911                edac_mode = EDAC_SECDED;
 912        else if (mci->edac_cap & EDAC_FLAG_EC)
 913                edac_mode = EDAC_EC;
 914        else
 915                edac_mode = EDAC_NONE;
 916
 917        /*
 918         * Initialize each chip select row structure which correspond
 919         * 1:1 with a controller bank/rank.
 920         */
 921
 922        for (row = 0; row < mci->nr_csrows; row++) {
 923                struct csrow_info *csi = &mci->csrows[row];
 924
 925                /*
 926                 * Get the configuration settings for this
 927                 * row/bank/rank and skip disabled banks.
 928                 */
 929
 930                mbxcf = mfsdram(&pdata->dcr_host, SDRAM_MBXCF(row));
 931
 932                if ((mbxcf & SDRAM_MBCF_BE_MASK) != SDRAM_MBCF_BE_ENABLE)
 933                        continue;
 934
 935                /* Map the bank configuration size setting to pages. */
 936
 937                size = mbxcf & SDRAM_MBCF_SZ_MASK;
 938
 939                switch (size) {
 940                case SDRAM_MBCF_SZ_4MB:
 941                case SDRAM_MBCF_SZ_8MB:
 942                case SDRAM_MBCF_SZ_16MB:
 943                case SDRAM_MBCF_SZ_32MB:
 944                case SDRAM_MBCF_SZ_64MB:
 945                case SDRAM_MBCF_SZ_128MB:
 946                case SDRAM_MBCF_SZ_256MB:
 947                case SDRAM_MBCF_SZ_512MB:
 948                case SDRAM_MBCF_SZ_1GB:
 949                case SDRAM_MBCF_SZ_2GB:
 950                case SDRAM_MBCF_SZ_4GB:
 951                case SDRAM_MBCF_SZ_8GB:
 952                        nr_pages = SDRAM_MBCF_SZ_TO_PAGES(size);
 953                        break;
 954                default:
 955                        ppc4xx_edac_mc_printk(KERN_ERR, mci,
 956                                              "Unrecognized memory bank %d "
 957                                              "size 0x%08x\n",
 958                                              row, SDRAM_MBCF_SZ_DECODE(size));
 959                        status = -EINVAL;
 960                        goto done;
 961                }
 962
 963                /*
 964                 * It's unclear exactly what grain should be set to
 965                 * here. The SDRAM_ECCES register allows resolution of
 966                 * an error down to a nibble which would potentially
 967                 * argue for a grain of '1' byte, even though we only
 968                 * know the associated address for uncorrectable
 969                 * errors. This value is not used at present for
 970                 * anything other than error reporting so getting it
 971                 * wrong should be of little consequence. Other
 972                 * possible values would be the PLB width (16), the
 973                 * page size (PAGE_SIZE) or the memory width (2 or 4).
 974                 */
 975                for (j = 0; j < csi->nr_channels; j++) {
 976                        struct dimm_info *dimm = csi->channels[j]->dimm;
 977
 978                        dimm->nr_pages  = nr_pages / csi->nr_channels;
 979                        dimm->grain     = 1;
 980
 981                        dimm->mtype     = mtype;
 982                        dimm->dtype     = dtype;
 983
 984                        dimm->edac_mode = edac_mode;
 985                }
 986        }
 987
 988 done:
 989        return status;
 990}
 991
 992/**
 993 * ppc4xx_edac_mc_init - initialize driver instance
 994 * @mci: A pointer to the EDAC memory controller instance being
 995 *       initialized.
 996 * @op: A pointer to the OpenFirmware device tree node associated
 997 *      with the controller this EDAC instance is bound to.
 998 * @dcr_host: A pointer to the DCR data containing the DCR mapping
 999 *            for this controller instance.
1000 * @mcopt1: The 32-bit Memory Controller Option 1 register value
1001 *          currently set for the controller, from which ECC capabilities
1002 *          and scrub mode are derived.
1003 *
1004 * This routine performs initialization of the EDAC memory controller
1005 * instance and related driver-private data associated with the
1006 * ibm,sdram-4xx-ddr2 memory controller the instance is bound to.
1007 *
1008 * Returns 0 if OK; otherwise, < 0 on error.
1009 */
1010static int ppc4xx_edac_mc_init(struct mem_ctl_info *mci,
1011                               struct platform_device *op,
1012                               const dcr_host_t *dcr_host, u32 mcopt1)
1013{
1014        int status = 0;
1015        const u32 memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK);
1016        struct ppc4xx_edac_pdata *pdata = NULL;
1017        const struct device_node *np = op->dev.of_node;
1018
1019        if (of_match_device(ppc4xx_edac_match, &op->dev) == NULL)
1020                return -EINVAL;
1021
1022        /* Initial driver pointers and private data */
1023
1024        mci->pdev               = &op->dev;
1025
1026        dev_set_drvdata(mci->pdev, mci);
1027
1028        pdata                   = mci->pvt_info;
1029
1030        pdata->dcr_host         = *dcr_host;
1031        pdata->irqs.sec         = NO_IRQ;
1032        pdata->irqs.ded         = NO_IRQ;
1033
1034        /* Initialize controller capabilities and configuration */
1035
1036        mci->mtype_cap          = (MEM_FLAG_DDR | MEM_FLAG_RDDR |
1037                                   MEM_FLAG_DDR2 | MEM_FLAG_RDDR2);
1038
1039        mci->edac_ctl_cap       = (EDAC_FLAG_NONE |
1040                                   EDAC_FLAG_EC |
1041                                   EDAC_FLAG_SECDED);
1042
1043        mci->scrub_cap          = SCRUB_NONE;
1044        mci->scrub_mode         = SCRUB_NONE;
1045
1046        /*
1047         * Update the actual capabilites based on the MCOPT1[MCHK]
1048         * settings. Scrubbing is only useful if reporting is enabled.
1049         */
1050
1051        switch (memcheck) {
1052        case SDRAM_MCOPT1_MCHK_CHK:
1053                mci->edac_cap   = EDAC_FLAG_EC;
1054                break;
1055        case SDRAM_MCOPT1_MCHK_CHK_REP:
1056                mci->edac_cap   = (EDAC_FLAG_EC | EDAC_FLAG_SECDED);
1057                mci->scrub_mode = SCRUB_SW_SRC;
1058                break;
1059        default:
1060                mci->edac_cap   = EDAC_FLAG_NONE;
1061                break;
1062        }
1063
1064        /* Initialize strings */
1065
1066        mci->mod_name           = PPC4XX_EDAC_MODULE_NAME;
1067        mci->mod_ver            = PPC4XX_EDAC_MODULE_REVISION;
1068        mci->ctl_name           = ppc4xx_edac_match->compatible,
1069        mci->dev_name           = np->full_name;
1070
1071        /* Initialize callbacks */
1072
1073        mci->edac_check         = ppc4xx_edac_check;
1074        mci->ctl_page_to_phys   = NULL;
1075
1076        /* Initialize chip select rows */
1077
1078        status = ppc4xx_edac_init_csrows(mci, mcopt1);
1079
1080        if (status)
1081                ppc4xx_edac_mc_printk(KERN_ERR, mci,
1082                                      "Failed to initialize rows!\n");
1083
1084        return status;
1085}
1086
1087/**
1088 * ppc4xx_edac_register_irq - setup and register controller interrupts
1089 * @op: A pointer to the OpenFirmware device tree node associated
1090 *      with the controller this EDAC instance is bound to.
1091 * @mci: A pointer to the EDAC memory controller instance
1092 *       associated with the ibm,sdram-4xx-ddr2 controller for which
1093 *       interrupts are being registered.
1094 *
1095 * This routine parses the correctable (CE) and uncorrectable error (UE)
1096 * interrupts from the device tree node and maps and assigns them to
1097 * the associated EDAC memory controller instance.
1098 *
1099 * Returns 0 if OK; otherwise, -ENODEV if the interrupts could not be
1100 * mapped and assigned.
1101 */
1102static int ppc4xx_edac_register_irq(struct platform_device *op,
1103                                    struct mem_ctl_info *mci)
1104{
1105        int status = 0;
1106        int ded_irq, sec_irq;
1107        struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
1108        struct device_node *np = op->dev.of_node;
1109
1110        ded_irq = irq_of_parse_and_map(np, INTMAP_ECCDED_INDEX);
1111        sec_irq = irq_of_parse_and_map(np, INTMAP_ECCSEC_INDEX);
1112
1113        if (ded_irq == NO_IRQ || sec_irq == NO_IRQ) {
1114                ppc4xx_edac_mc_printk(KERN_ERR, mci,
1115                                      "Unable to map interrupts.\n");
1116                status = -ENODEV;
1117                goto fail;
1118        }
1119
1120        status = request_irq(ded_irq,
1121                             ppc4xx_edac_isr,
1122                             0,
1123                             "[EDAC] MC ECCDED",
1124                             mci);
1125
1126        if (status < 0) {
1127                ppc4xx_edac_mc_printk(KERN_ERR, mci,
1128                                      "Unable to request irq %d for ECC DED",
1129                                      ded_irq);
1130                status = -ENODEV;
1131                goto fail1;
1132        }
1133
1134        status = request_irq(sec_irq,
1135                             ppc4xx_edac_isr,
1136                             0,
1137                             "[EDAC] MC ECCSEC",
1138                             mci);
1139
1140        if (status < 0) {
1141                ppc4xx_edac_mc_printk(KERN_ERR, mci,
1142                                      "Unable to request irq %d for ECC SEC",
1143                                      sec_irq);
1144                status = -ENODEV;
1145                goto fail2;
1146        }
1147
1148        ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCDED irq is %d\n", ded_irq);
1149        ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCSEC irq is %d\n", sec_irq);
1150
1151        pdata->irqs.ded = ded_irq;
1152        pdata->irqs.sec = sec_irq;
1153
1154        return 0;
1155
1156 fail2:
1157        free_irq(sec_irq, mci);
1158
1159 fail1:
1160        free_irq(ded_irq, mci);
1161
1162 fail:
1163        return status;
1164}
1165
1166/**
1167 * ppc4xx_edac_map_dcrs - locate and map controller registers
1168 * @np: A pointer to the device tree node containing the DCR
1169 *      resources to map.
1170 * @dcr_host: A pointer to the DCR data to populate with the
1171 *            DCR mapping.
1172 *
1173 * This routine attempts to locate in the device tree and map the DCR
1174 * register resources associated with the controller's indirect DCR
1175 * address and data windows.
1176 *
1177 * Returns 0 if the DCRs were successfully mapped; otherwise, < 0 on
1178 * error.
1179 */
1180static int ppc4xx_edac_map_dcrs(const struct device_node *np,
1181                                dcr_host_t *dcr_host)
1182{
1183        unsigned int dcr_base, dcr_len;
1184
1185        if (np == NULL || dcr_host == NULL)
1186                return -EINVAL;
1187
1188        /* Get the DCR resource extent and sanity check the values. */
1189
1190        dcr_base = dcr_resource_start(np, 0);
1191        dcr_len = dcr_resource_len(np, 0);
1192
1193        if (dcr_base == 0 || dcr_len == 0) {
1194                ppc4xx_edac_printk(KERN_ERR,
1195                                   "Failed to obtain DCR property.\n");
1196                return -ENODEV;
1197        }
1198
1199        if (dcr_len != SDRAM_DCR_RESOURCE_LEN) {
1200                ppc4xx_edac_printk(KERN_ERR,
1201                                   "Unexpected DCR length %d, expected %d.\n",
1202                                   dcr_len, SDRAM_DCR_RESOURCE_LEN);
1203                return -ENODEV;
1204        }
1205
1206        /*  Attempt to map the DCR extent. */
1207
1208        *dcr_host = dcr_map(np, dcr_base, dcr_len);
1209
1210        if (!DCR_MAP_OK(*dcr_host)) {
1211                ppc4xx_edac_printk(KERN_INFO, "Failed to map DCRs.\n");
1212                    return -ENODEV;
1213        }
1214
1215        return 0;
1216}
1217
1218/**
1219 * ppc4xx_edac_probe - check controller and bind driver
1220 * @op: A pointer to the OpenFirmware device tree node associated
1221 *      with the controller being probed for driver binding.
1222 *
1223 * This routine probes a specific ibm,sdram-4xx-ddr2 controller
1224 * instance for binding with the driver.
1225 *
1226 * Returns 0 if the controller instance was successfully bound to the
1227 * driver; otherwise, < 0 on error.
1228 */
1229static int ppc4xx_edac_probe(struct platform_device *op)
1230{
1231        int status = 0;
1232        u32 mcopt1, memcheck;
1233        dcr_host_t dcr_host;
1234        const struct device_node *np = op->dev.of_node;
1235        struct mem_ctl_info *mci = NULL;
1236        struct edac_mc_layer layers[2];
1237        static int ppc4xx_edac_instance;
1238
1239        /*
1240         * At this point, we only support the controller realized on
1241         * the AMCC PPC 405EX[r]. Reject anything else.
1242         */
1243
1244        if (!of_device_is_compatible(np, "ibm,sdram-405ex") &&
1245            !of_device_is_compatible(np, "ibm,sdram-405exr")) {
1246                ppc4xx_edac_printk(KERN_NOTICE,
1247                                   "Only the PPC405EX[r] is supported.\n");
1248                return -ENODEV;
1249        }
1250
1251        /*
1252         * Next, get the DCR property and attempt to map it so that we
1253         * can probe the controller.
1254         */
1255
1256        status = ppc4xx_edac_map_dcrs(np, &dcr_host);
1257
1258        if (status)
1259                return status;
1260
1261        /*
1262         * First determine whether ECC is enabled at all. If not,
1263         * there is no useful checking or monitoring that can be done
1264         * for this controller.
1265         */
1266
1267        mcopt1 = mfsdram(&dcr_host, SDRAM_MCOPT1);
1268        memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK);
1269
1270        if (memcheck == SDRAM_MCOPT1_MCHK_NON) {
1271                ppc4xx_edac_printk(KERN_INFO, "%s: No ECC memory detected or "
1272                                   "ECC is disabled.\n", np->full_name);
1273                status = -ENODEV;
1274                goto done;
1275        }
1276
1277        /*
1278         * At this point, we know ECC is enabled, allocate an EDAC
1279         * controller instance and perform the appropriate
1280         * initialization.
1281         */
1282        layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
1283        layers[0].size = ppc4xx_edac_nr_csrows;
1284        layers[0].is_virt_csrow = true;
1285        layers[1].type = EDAC_MC_LAYER_CHANNEL;
1286        layers[1].size = ppc4xx_edac_nr_chans;
1287        layers[1].is_virt_csrow = false;
1288        mci = edac_mc_alloc(ppc4xx_edac_instance, ARRAY_SIZE(layers), layers,
1289                            sizeof(struct ppc4xx_edac_pdata));
1290        if (mci == NULL) {
1291                ppc4xx_edac_printk(KERN_ERR, "%s: "
1292                                   "Failed to allocate EDAC MC instance!\n",
1293                                   np->full_name);
1294                status = -ENOMEM;
1295                goto done;
1296        }
1297
1298        status = ppc4xx_edac_mc_init(mci, op, &dcr_host, mcopt1);
1299
1300        if (status) {
1301                ppc4xx_edac_mc_printk(KERN_ERR, mci,
1302                                      "Failed to initialize instance!\n");
1303                goto fail;
1304        }
1305
1306        /*
1307         * We have a valid, initialized EDAC instance bound to the
1308         * controller. Attempt to register it with the EDAC subsystem
1309         * and, if necessary, register interrupts.
1310         */
1311
1312        if (edac_mc_add_mc(mci)) {
1313                ppc4xx_edac_mc_printk(KERN_ERR, mci,
1314                                      "Failed to add instance!\n");
1315                status = -ENODEV;
1316                goto fail;
1317        }
1318
1319        if (edac_op_state == EDAC_OPSTATE_INT) {
1320                status = ppc4xx_edac_register_irq(op, mci);
1321
1322                if (status)
1323                        goto fail1;
1324        }
1325
1326        ppc4xx_edac_instance++;
1327
1328        return 0;
1329
1330 fail1:
1331        edac_mc_del_mc(mci->pdev);
1332
1333 fail:
1334        edac_mc_free(mci);
1335
1336 done:
1337        return status;
1338}
1339
1340/**
1341 * ppc4xx_edac_remove - unbind driver from controller
1342 * @op: A pointer to the OpenFirmware device tree node associated
1343 *      with the controller this EDAC instance is to be unbound/removed
1344 *      from.
1345 *
1346 * This routine unbinds the EDAC memory controller instance associated
1347 * with the specified ibm,sdram-4xx-ddr2 controller described by the
1348 * OpenFirmware device tree node passed as a parameter.
1349 *
1350 * Unconditionally returns 0.
1351 */
1352static int
1353ppc4xx_edac_remove(struct platform_device *op)
1354{
1355        struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
1356        struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
1357
1358        if (edac_op_state == EDAC_OPSTATE_INT) {
1359                free_irq(pdata->irqs.sec, mci);
1360                free_irq(pdata->irqs.ded, mci);
1361        }
1362
1363        dcr_unmap(pdata->dcr_host, SDRAM_DCR_RESOURCE_LEN);
1364
1365        edac_mc_del_mc(mci->pdev);
1366        edac_mc_free(mci);
1367
1368        return 0;
1369}
1370
1371/**
1372 * ppc4xx_edac_opstate_init - initialize EDAC reporting method
1373 *
1374 * This routine ensures that the EDAC memory controller reporting
1375 * method is mapped to a sane value as the EDAC core defines the value
1376 * to EDAC_OPSTATE_INVAL by default. We don't call the global
1377 * opstate_init as that defaults to polling and we want interrupt as
1378 * the default.
1379 */
1380static inline void __init
1381ppc4xx_edac_opstate_init(void)
1382{
1383        switch (edac_op_state) {
1384        case EDAC_OPSTATE_POLL:
1385        case EDAC_OPSTATE_INT:
1386                break;
1387        default:
1388                edac_op_state = EDAC_OPSTATE_INT;
1389                break;
1390        }
1391
1392        ppc4xx_edac_printk(KERN_INFO, "Reporting type: %s\n",
1393                           ((edac_op_state == EDAC_OPSTATE_POLL) ?
1394                            EDAC_OPSTATE_POLL_STR :
1395                            ((edac_op_state == EDAC_OPSTATE_INT) ?
1396                             EDAC_OPSTATE_INT_STR :
1397                             EDAC_OPSTATE_UNKNOWN_STR)));
1398}
1399
1400/**
1401 * ppc4xx_edac_init - driver/module insertion entry point
1402 *
1403 * This routine is the driver/module insertion entry point. It
1404 * initializes the EDAC memory controller reporting state and
1405 * registers the driver as an OpenFirmware device tree platform
1406 * driver.
1407 */
1408static int __init
1409ppc4xx_edac_init(void)
1410{
1411        ppc4xx_edac_printk(KERN_INFO, PPC4XX_EDAC_MODULE_REVISION "\n");
1412
1413        ppc4xx_edac_opstate_init();
1414
1415        return platform_driver_register(&ppc4xx_edac_driver);
1416}
1417
1418/**
1419 * ppc4xx_edac_exit - driver/module removal entry point
1420 *
1421 * This routine is the driver/module removal entry point. It
1422 * unregisters the driver as an OpenFirmware device tree platform
1423 * driver.
1424 */
1425static void __exit
1426ppc4xx_edac_exit(void)
1427{
1428        platform_driver_unregister(&ppc4xx_edac_driver);
1429}
1430
1431module_init(ppc4xx_edac_init);
1432module_exit(ppc4xx_edac_exit);
1433
1434MODULE_LICENSE("GPL v2");
1435MODULE_AUTHOR("Grant Erickson <gerickson@nuovations.com>");
1436MODULE_DESCRIPTION("EDAC MC Driver for the PPC4xx IBM DDR2 Memory Controller");
1437module_param(edac_op_state, int, 0444);
1438MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting State: "
1439                 "0=" EDAC_OPSTATE_POLL_STR ", 2=" EDAC_OPSTATE_INT_STR);
1440
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