linux/drivers/crypto/omap-sham.c
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   1/*
   2 * Cryptographic API.
   3 *
   4 * Support for OMAP SHA1/MD5 HW acceleration.
   5 *
   6 * Copyright (c) 2010 Nokia Corporation
   7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   8 * Copyright (c) 2011 Texas Instruments Incorporated
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License version 2 as published
  12 * by the Free Software Foundation.
  13 *
  14 * Some ideas are from old omap-sha1-md5.c driver.
  15 */
  16
  17#define pr_fmt(fmt) "%s: " fmt, __func__
  18
  19#include <linux/err.h>
  20#include <linux/device.h>
  21#include <linux/module.h>
  22#include <linux/init.h>
  23#include <linux/errno.h>
  24#include <linux/interrupt.h>
  25#include <linux/kernel.h>
  26#include <linux/irq.h>
  27#include <linux/io.h>
  28#include <linux/platform_device.h>
  29#include <linux/scatterlist.h>
  30#include <linux/dma-mapping.h>
  31#include <linux/dmaengine.h>
  32#include <linux/omap-dma.h>
  33#include <linux/pm_runtime.h>
  34#include <linux/of.h>
  35#include <linux/of_device.h>
  36#include <linux/of_address.h>
  37#include <linux/of_irq.h>
  38#include <linux/delay.h>
  39#include <linux/crypto.h>
  40#include <linux/cryptohash.h>
  41#include <crypto/scatterwalk.h>
  42#include <crypto/algapi.h>
  43#include <crypto/sha.h>
  44#include <crypto/hash.h>
  45#include <crypto/internal/hash.h>
  46
  47#define MD5_DIGEST_SIZE                 16
  48
  49#define SHA_REG_IDIGEST(dd, x)          ((dd)->pdata->idigest_ofs + ((x)*0x04))
  50#define SHA_REG_DIN(dd, x)              ((dd)->pdata->din_ofs + ((x) * 0x04))
  51#define SHA_REG_DIGCNT(dd)              ((dd)->pdata->digcnt_ofs)
  52
  53#define SHA_REG_ODIGEST(dd, x)          ((dd)->pdata->odigest_ofs + (x * 0x04))
  54
  55#define SHA_REG_CTRL                    0x18
  56#define SHA_REG_CTRL_LENGTH             (0xFFFFFFFF << 5)
  57#define SHA_REG_CTRL_CLOSE_HASH         (1 << 4)
  58#define SHA_REG_CTRL_ALGO_CONST         (1 << 3)
  59#define SHA_REG_CTRL_ALGO               (1 << 2)
  60#define SHA_REG_CTRL_INPUT_READY        (1 << 1)
  61#define SHA_REG_CTRL_OUTPUT_READY       (1 << 0)
  62
  63#define SHA_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  64
  65#define SHA_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  66#define SHA_REG_MASK_DMA_EN             (1 << 3)
  67#define SHA_REG_MASK_IT_EN              (1 << 2)
  68#define SHA_REG_MASK_SOFTRESET          (1 << 1)
  69#define SHA_REG_AUTOIDLE                (1 << 0)
  70
  71#define SHA_REG_SYSSTATUS(dd)           ((dd)->pdata->sysstatus_ofs)
  72#define SHA_REG_SYSSTATUS_RESETDONE     (1 << 0)
  73
  74#define SHA_REG_MODE(dd)                ((dd)->pdata->mode_ofs)
  75#define SHA_REG_MODE_HMAC_OUTER_HASH    (1 << 7)
  76#define SHA_REG_MODE_HMAC_KEY_PROC      (1 << 5)
  77#define SHA_REG_MODE_CLOSE_HASH         (1 << 4)
  78#define SHA_REG_MODE_ALGO_CONSTANT      (1 << 3)
  79
  80#define SHA_REG_MODE_ALGO_MASK          (7 << 0)
  81#define SHA_REG_MODE_ALGO_MD5_128       (0 << 1)
  82#define SHA_REG_MODE_ALGO_SHA1_160      (1 << 1)
  83#define SHA_REG_MODE_ALGO_SHA2_224      (2 << 1)
  84#define SHA_REG_MODE_ALGO_SHA2_256      (3 << 1)
  85#define SHA_REG_MODE_ALGO_SHA2_384      (1 << 0)
  86#define SHA_REG_MODE_ALGO_SHA2_512      (3 << 0)
  87
  88#define SHA_REG_LENGTH(dd)              ((dd)->pdata->length_ofs)
  89
  90#define SHA_REG_IRQSTATUS               0x118
  91#define SHA_REG_IRQSTATUS_CTX_RDY       (1 << 3)
  92#define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
  93#define SHA_REG_IRQSTATUS_INPUT_RDY     (1 << 1)
  94#define SHA_REG_IRQSTATUS_OUTPUT_RDY    (1 << 0)
  95
  96#define SHA_REG_IRQENA                  0x11C
  97#define SHA_REG_IRQENA_CTX_RDY          (1 << 3)
  98#define SHA_REG_IRQENA_PARTHASH_RDY     (1 << 2)
  99#define SHA_REG_IRQENA_INPUT_RDY        (1 << 1)
 100#define SHA_REG_IRQENA_OUTPUT_RDY       (1 << 0)
 101
 102#define DEFAULT_TIMEOUT_INTERVAL        HZ
 103
 104/* mostly device flags */
 105#define FLAGS_BUSY              0
 106#define FLAGS_FINAL             1
 107#define FLAGS_DMA_ACTIVE        2
 108#define FLAGS_OUTPUT_READY      3
 109#define FLAGS_INIT              4
 110#define FLAGS_CPU               5
 111#define FLAGS_DMA_READY         6
 112#define FLAGS_AUTO_XOR          7
 113#define FLAGS_BE32_SHA1         8
 114/* context flags */
 115#define FLAGS_FINUP             16
 116#define FLAGS_SG                17
 117
 118#define FLAGS_MODE_SHIFT        18
 119#define FLAGS_MODE_MASK         (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
 120#define FLAGS_MODE_MD5          (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
 121#define FLAGS_MODE_SHA1         (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
 122#define FLAGS_MODE_SHA224       (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
 123#define FLAGS_MODE_SHA256       (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
 124#define FLAGS_MODE_SHA384       (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
 125#define FLAGS_MODE_SHA512       (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
 126
 127#define FLAGS_HMAC              21
 128#define FLAGS_ERROR             22
 129
 130#define OP_UPDATE               1
 131#define OP_FINAL                2
 132
 133#define OMAP_ALIGN_MASK         (sizeof(u32)-1)
 134#define OMAP_ALIGNED            __attribute__((aligned(sizeof(u32))))
 135
 136#define BUFLEN                  PAGE_SIZE
 137
 138struct omap_sham_dev;
 139
 140struct omap_sham_reqctx {
 141        struct omap_sham_dev    *dd;
 142        unsigned long           flags;
 143        unsigned long           op;
 144
 145        u8                      digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
 146        size_t                  digcnt;
 147        size_t                  bufcnt;
 148        size_t                  buflen;
 149        dma_addr_t              dma_addr;
 150
 151        /* walk state */
 152        struct scatterlist      *sg;
 153        struct scatterlist      sgl;
 154        unsigned int            offset; /* offset in current sg */
 155        unsigned int            total;  /* total request */
 156
 157        u8                      buffer[0] OMAP_ALIGNED;
 158};
 159
 160struct omap_sham_hmac_ctx {
 161        struct crypto_shash     *shash;
 162        u8                      ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 163        u8                      opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 164};
 165
 166struct omap_sham_ctx {
 167        struct omap_sham_dev    *dd;
 168
 169        unsigned long           flags;
 170
 171        /* fallback stuff */
 172        struct crypto_shash     *fallback;
 173
 174        struct omap_sham_hmac_ctx base[0];
 175};
 176
 177#define OMAP_SHAM_QUEUE_LENGTH  1
 178
 179struct omap_sham_algs_info {
 180        struct ahash_alg        *algs_list;
 181        unsigned int            size;
 182        unsigned int            registered;
 183};
 184
 185struct omap_sham_pdata {
 186        struct omap_sham_algs_info      *algs_info;
 187        unsigned int    algs_info_size;
 188        unsigned long   flags;
 189        int             digest_size;
 190
 191        void            (*copy_hash)(struct ahash_request *req, int out);
 192        void            (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
 193                                      int final, int dma);
 194        void            (*trigger)(struct omap_sham_dev *dd, size_t length);
 195        int             (*poll_irq)(struct omap_sham_dev *dd);
 196        irqreturn_t     (*intr_hdlr)(int irq, void *dev_id);
 197
 198        u32             odigest_ofs;
 199        u32             idigest_ofs;
 200        u32             din_ofs;
 201        u32             digcnt_ofs;
 202        u32             rev_ofs;
 203        u32             mask_ofs;
 204        u32             sysstatus_ofs;
 205        u32             mode_ofs;
 206        u32             length_ofs;
 207
 208        u32             major_mask;
 209        u32             major_shift;
 210        u32             minor_mask;
 211        u32             minor_shift;
 212};
 213
 214struct omap_sham_dev {
 215        struct list_head        list;
 216        unsigned long           phys_base;
 217        struct device           *dev;
 218        void __iomem            *io_base;
 219        int                     irq;
 220        spinlock_t              lock;
 221        int                     err;
 222        unsigned int            dma;
 223        struct dma_chan         *dma_lch;
 224        struct tasklet_struct   done_task;
 225        u8                      polling_mode;
 226
 227        unsigned long           flags;
 228        struct crypto_queue     queue;
 229        struct ahash_request    *req;
 230
 231        const struct omap_sham_pdata    *pdata;
 232};
 233
 234struct omap_sham_drv {
 235        struct list_head        dev_list;
 236        spinlock_t              lock;
 237        unsigned long           flags;
 238};
 239
 240static struct omap_sham_drv sham = {
 241        .dev_list = LIST_HEAD_INIT(sham.dev_list),
 242        .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
 243};
 244
 245static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
 246{
 247        return __raw_readl(dd->io_base + offset);
 248}
 249
 250static inline void omap_sham_write(struct omap_sham_dev *dd,
 251                                        u32 offset, u32 value)
 252{
 253        __raw_writel(value, dd->io_base + offset);
 254}
 255
 256static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
 257                                        u32 value, u32 mask)
 258{
 259        u32 val;
 260
 261        val = omap_sham_read(dd, address);
 262        val &= ~mask;
 263        val |= value;
 264        omap_sham_write(dd, address, val);
 265}
 266
 267static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
 268{
 269        unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
 270
 271        while (!(omap_sham_read(dd, offset) & bit)) {
 272                if (time_is_before_jiffies(timeout))
 273                        return -ETIMEDOUT;
 274        }
 275
 276        return 0;
 277}
 278
 279static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
 280{
 281        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 282        struct omap_sham_dev *dd = ctx->dd;
 283        u32 *hash = (u32 *)ctx->digest;
 284        int i;
 285
 286        for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 287                if (out)
 288                        hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
 289                else
 290                        omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
 291        }
 292}
 293
 294static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
 295{
 296        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 297        struct omap_sham_dev *dd = ctx->dd;
 298        int i;
 299
 300        if (ctx->flags & BIT(FLAGS_HMAC)) {
 301                struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 302                struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 303                struct omap_sham_hmac_ctx *bctx = tctx->base;
 304                u32 *opad = (u32 *)bctx->opad;
 305
 306                for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 307                        if (out)
 308                                opad[i] = omap_sham_read(dd,
 309                                                SHA_REG_ODIGEST(dd, i));
 310                        else
 311                                omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
 312                                                opad[i]);
 313                }
 314        }
 315
 316        omap_sham_copy_hash_omap2(req, out);
 317}
 318
 319static void omap_sham_copy_ready_hash(struct ahash_request *req)
 320{
 321        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 322        u32 *in = (u32 *)ctx->digest;
 323        u32 *hash = (u32 *)req->result;
 324        int i, d, big_endian = 0;
 325
 326        if (!hash)
 327                return;
 328
 329        switch (ctx->flags & FLAGS_MODE_MASK) {
 330        case FLAGS_MODE_MD5:
 331                d = MD5_DIGEST_SIZE / sizeof(u32);
 332                break;
 333        case FLAGS_MODE_SHA1:
 334                /* OMAP2 SHA1 is big endian */
 335                if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
 336                        big_endian = 1;
 337                d = SHA1_DIGEST_SIZE / sizeof(u32);
 338                break;
 339        case FLAGS_MODE_SHA224:
 340                d = SHA224_DIGEST_SIZE / sizeof(u32);
 341                break;
 342        case FLAGS_MODE_SHA256:
 343                d = SHA256_DIGEST_SIZE / sizeof(u32);
 344                break;
 345        case FLAGS_MODE_SHA384:
 346                d = SHA384_DIGEST_SIZE / sizeof(u32);
 347                break;
 348        case FLAGS_MODE_SHA512:
 349                d = SHA512_DIGEST_SIZE / sizeof(u32);
 350                break;
 351        default:
 352                d = 0;
 353        }
 354
 355        if (big_endian)
 356                for (i = 0; i < d; i++)
 357                        hash[i] = be32_to_cpu(in[i]);
 358        else
 359                for (i = 0; i < d; i++)
 360                        hash[i] = le32_to_cpu(in[i]);
 361}
 362
 363static int omap_sham_hw_init(struct omap_sham_dev *dd)
 364{
 365        pm_runtime_get_sync(dd->dev);
 366
 367        if (!test_bit(FLAGS_INIT, &dd->flags)) {
 368                set_bit(FLAGS_INIT, &dd->flags);
 369                dd->err = 0;
 370        }
 371
 372        return 0;
 373}
 374
 375static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
 376                                 int final, int dma)
 377{
 378        struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 379        u32 val = length << 5, mask;
 380
 381        if (likely(ctx->digcnt))
 382                omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
 383
 384        omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 385                SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
 386                SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 387        /*
 388         * Setting ALGO_CONST only for the first iteration
 389         * and CLOSE_HASH only for the last one.
 390         */
 391        if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
 392                val |= SHA_REG_CTRL_ALGO;
 393        if (!ctx->digcnt)
 394                val |= SHA_REG_CTRL_ALGO_CONST;
 395        if (final)
 396                val |= SHA_REG_CTRL_CLOSE_HASH;
 397
 398        mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
 399                        SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
 400
 401        omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
 402}
 403
 404static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
 405{
 406}
 407
 408static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
 409{
 410        return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
 411}
 412
 413static int get_block_size(struct omap_sham_reqctx *ctx)
 414{
 415        int d;
 416
 417        switch (ctx->flags & FLAGS_MODE_MASK) {
 418        case FLAGS_MODE_MD5:
 419        case FLAGS_MODE_SHA1:
 420                d = SHA1_BLOCK_SIZE;
 421                break;
 422        case FLAGS_MODE_SHA224:
 423        case FLAGS_MODE_SHA256:
 424                d = SHA256_BLOCK_SIZE;
 425                break;
 426        case FLAGS_MODE_SHA384:
 427        case FLAGS_MODE_SHA512:
 428                d = SHA512_BLOCK_SIZE;
 429                break;
 430        default:
 431                d = 0;
 432        }
 433
 434        return d;
 435}
 436
 437static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
 438                                    u32 *value, int count)
 439{
 440        for (; count--; value++, offset += 4)
 441                omap_sham_write(dd, offset, *value);
 442}
 443
 444static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
 445                                 int final, int dma)
 446{
 447        struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 448        u32 val, mask;
 449
 450        /*
 451         * Setting ALGO_CONST only for the first iteration and
 452         * CLOSE_HASH only for the last one. Note that flags mode bits
 453         * correspond to algorithm encoding in mode register.
 454         */
 455        val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
 456        if (!ctx->digcnt) {
 457                struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 458                struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 459                struct omap_sham_hmac_ctx *bctx = tctx->base;
 460                int bs, nr_dr;
 461
 462                val |= SHA_REG_MODE_ALGO_CONSTANT;
 463
 464                if (ctx->flags & BIT(FLAGS_HMAC)) {
 465                        bs = get_block_size(ctx);
 466                        nr_dr = bs / (2 * sizeof(u32));
 467                        val |= SHA_REG_MODE_HMAC_KEY_PROC;
 468                        omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
 469                                          (u32 *)bctx->ipad, nr_dr);
 470                        omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
 471                                          (u32 *)bctx->ipad + nr_dr, nr_dr);
 472                        ctx->digcnt += bs;
 473                }
 474        }
 475
 476        if (final) {
 477                val |= SHA_REG_MODE_CLOSE_HASH;
 478
 479                if (ctx->flags & BIT(FLAGS_HMAC))
 480                        val |= SHA_REG_MODE_HMAC_OUTER_HASH;
 481        }
 482
 483        mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
 484               SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
 485               SHA_REG_MODE_HMAC_KEY_PROC;
 486
 487        dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
 488        omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
 489        omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
 490        omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 491                             SHA_REG_MASK_IT_EN |
 492                                     (dma ? SHA_REG_MASK_DMA_EN : 0),
 493                             SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 494}
 495
 496static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
 497{
 498        omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
 499}
 500
 501static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
 502{
 503        return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
 504                              SHA_REG_IRQSTATUS_INPUT_RDY);
 505}
 506
 507static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
 508                              size_t length, int final)
 509{
 510        struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 511        int count, len32, bs32, offset = 0;
 512        const u32 *buffer = (const u32 *)buf;
 513
 514        dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
 515                                                ctx->digcnt, length, final);
 516
 517        dd->pdata->write_ctrl(dd, length, final, 0);
 518        dd->pdata->trigger(dd, length);
 519
 520        /* should be non-zero before next lines to disable clocks later */
 521        ctx->digcnt += length;
 522
 523        if (final)
 524                set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 525
 526        set_bit(FLAGS_CPU, &dd->flags);
 527
 528        len32 = DIV_ROUND_UP(length, sizeof(u32));
 529        bs32 = get_block_size(ctx) / sizeof(u32);
 530
 531        while (len32) {
 532                if (dd->pdata->poll_irq(dd))
 533                        return -ETIMEDOUT;
 534
 535                for (count = 0; count < min(len32, bs32); count++, offset++)
 536                        omap_sham_write(dd, SHA_REG_DIN(dd, count),
 537                                        buffer[offset]);
 538                len32 -= min(len32, bs32);
 539        }
 540
 541        return -EINPROGRESS;
 542}
 543
 544static void omap_sham_dma_callback(void *param)
 545{
 546        struct omap_sham_dev *dd = param;
 547
 548        set_bit(FLAGS_DMA_READY, &dd->flags);
 549        tasklet_schedule(&dd->done_task);
 550}
 551
 552static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
 553                              size_t length, int final, int is_sg)
 554{
 555        struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 556        struct dma_async_tx_descriptor *tx;
 557        struct dma_slave_config cfg;
 558        int len32, ret, dma_min = get_block_size(ctx);
 559
 560        dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
 561                                                ctx->digcnt, length, final);
 562
 563        memset(&cfg, 0, sizeof(cfg));
 564
 565        cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
 566        cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 567        cfg.dst_maxburst = dma_min / DMA_SLAVE_BUSWIDTH_4_BYTES;
 568
 569        ret = dmaengine_slave_config(dd->dma_lch, &cfg);
 570        if (ret) {
 571                pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
 572                return ret;
 573        }
 574
 575        len32 = DIV_ROUND_UP(length, dma_min) * dma_min;
 576
 577        if (is_sg) {
 578                /*
 579                 * The SG entry passed in may not have the 'length' member
 580                 * set correctly so use a local SG entry (sgl) with the
 581                 * proper value for 'length' instead.  If this is not done,
 582                 * the dmaengine may try to DMA the incorrect amount of data.
 583                 */
 584                sg_init_table(&ctx->sgl, 1);
 585                ctx->sgl.page_link = ctx->sg->page_link;
 586                ctx->sgl.offset = ctx->sg->offset;
 587                sg_dma_len(&ctx->sgl) = len32;
 588                sg_dma_address(&ctx->sgl) = sg_dma_address(ctx->sg);
 589
 590                tx = dmaengine_prep_slave_sg(dd->dma_lch, &ctx->sgl, 1,
 591                        DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 592        } else {
 593                tx = dmaengine_prep_slave_single(dd->dma_lch, dma_addr, len32,
 594                        DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 595        }
 596
 597        if (!tx) {
 598                dev_err(dd->dev, "prep_slave_sg/single() failed\n");
 599                return -EINVAL;
 600        }
 601
 602        tx->callback = omap_sham_dma_callback;
 603        tx->callback_param = dd;
 604
 605        dd->pdata->write_ctrl(dd, length, final, 1);
 606
 607        ctx->digcnt += length;
 608
 609        if (final)
 610                set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 611
 612        set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 613
 614        dmaengine_submit(tx);
 615        dma_async_issue_pending(dd->dma_lch);
 616
 617        dd->pdata->trigger(dd, length);
 618
 619        return -EINPROGRESS;
 620}
 621
 622static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx,
 623                                const u8 *data, size_t length)
 624{
 625        size_t count = min(length, ctx->buflen - ctx->bufcnt);
 626
 627        count = min(count, ctx->total);
 628        if (count <= 0)
 629                return 0;
 630        memcpy(ctx->buffer + ctx->bufcnt, data, count);
 631        ctx->bufcnt += count;
 632
 633        return count;
 634}
 635
 636static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx)
 637{
 638        size_t count;
 639        const u8 *vaddr;
 640
 641        while (ctx->sg) {
 642                vaddr = kmap_atomic(sg_page(ctx->sg));
 643
 644                count = omap_sham_append_buffer(ctx,
 645                                vaddr + ctx->offset,
 646                                ctx->sg->length - ctx->offset);
 647
 648                kunmap_atomic((void *)vaddr);
 649
 650                if (!count)
 651                        break;
 652                ctx->offset += count;
 653                ctx->total -= count;
 654                if (ctx->offset == ctx->sg->length) {
 655                        ctx->sg = sg_next(ctx->sg);
 656                        if (ctx->sg)
 657                                ctx->offset = 0;
 658                        else
 659                                ctx->total = 0;
 660                }
 661        }
 662
 663        return 0;
 664}
 665
 666static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
 667                                        struct omap_sham_reqctx *ctx,
 668                                        size_t length, int final)
 669{
 670        int ret;
 671
 672        ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen,
 673                                       DMA_TO_DEVICE);
 674        if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
 675                dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen);
 676                return -EINVAL;
 677        }
 678
 679        ctx->flags &= ~BIT(FLAGS_SG);
 680
 681        ret = omap_sham_xmit_dma(dd, ctx->dma_addr, length, final, 0);
 682        if (ret != -EINPROGRESS)
 683                dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
 684                                 DMA_TO_DEVICE);
 685
 686        return ret;
 687}
 688
 689static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
 690{
 691        struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 692        unsigned int final;
 693        size_t count;
 694
 695        omap_sham_append_sg(ctx);
 696
 697        final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 698
 699        dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n",
 700                                         ctx->bufcnt, ctx->digcnt, final);
 701
 702        if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
 703                count = ctx->bufcnt;
 704                ctx->bufcnt = 0;
 705                return omap_sham_xmit_dma_map(dd, ctx, count, final);
 706        }
 707
 708        return 0;
 709}
 710
 711/* Start address alignment */
 712#define SG_AA(sg)       (IS_ALIGNED(sg->offset, sizeof(u32)))
 713/* SHA1 block size alignment */
 714#define SG_SA(sg, bs)   (IS_ALIGNED(sg->length, bs))
 715
 716static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
 717{
 718        struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 719        unsigned int length, final, tail;
 720        struct scatterlist *sg;
 721        int ret, bs;
 722
 723        if (!ctx->total)
 724                return 0;
 725
 726        if (ctx->bufcnt || ctx->offset)
 727                return omap_sham_update_dma_slow(dd);
 728
 729        /*
 730         * Don't use the sg interface when the transfer size is less
 731         * than the number of elements in a DMA frame.  Otherwise,
 732         * the dmaengine infrastructure will calculate that it needs
 733         * to transfer 0 frames which ultimately fails.
 734         */
 735        if (ctx->total < get_block_size(ctx))
 736                return omap_sham_update_dma_slow(dd);
 737
 738        dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n",
 739                        ctx->digcnt, ctx->bufcnt, ctx->total);
 740
 741        sg = ctx->sg;
 742        bs = get_block_size(ctx);
 743
 744        if (!SG_AA(sg))
 745                return omap_sham_update_dma_slow(dd);
 746
 747        if (!sg_is_last(sg) && !SG_SA(sg, bs))
 748                /* size is not BLOCK_SIZE aligned */
 749                return omap_sham_update_dma_slow(dd);
 750
 751        length = min(ctx->total, sg->length);
 752
 753        if (sg_is_last(sg)) {
 754                if (!(ctx->flags & BIT(FLAGS_FINUP))) {
 755                        /* not last sg must be BLOCK_SIZE aligned */
 756                        tail = length & (bs - 1);
 757                        /* without finup() we need one block to close hash */
 758                        if (!tail)
 759                                tail = bs;
 760                        length -= tail;
 761                }
 762        }
 763
 764        if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
 765                dev_err(dd->dev, "dma_map_sg  error\n");
 766                return -EINVAL;
 767        }
 768
 769        ctx->flags |= BIT(FLAGS_SG);
 770
 771        ctx->total -= length;
 772        ctx->offset = length; /* offset where to start slow */
 773
 774        final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 775
 776        ret = omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final, 1);
 777        if (ret != -EINPROGRESS)
 778                dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
 779
 780        return ret;
 781}
 782
 783static int omap_sham_update_cpu(struct omap_sham_dev *dd)
 784{
 785        struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 786        int bufcnt, final;
 787
 788        if (!ctx->total)
 789                return 0;
 790
 791        omap_sham_append_sg(ctx);
 792
 793        final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 794
 795        dev_dbg(dd->dev, "cpu: bufcnt: %u, digcnt: %d, final: %d\n",
 796                ctx->bufcnt, ctx->digcnt, final);
 797
 798        if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
 799                bufcnt = ctx->bufcnt;
 800                ctx->bufcnt = 0;
 801                return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, final);
 802        }
 803
 804        return 0;
 805}
 806
 807static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
 808{
 809        struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 810
 811        dmaengine_terminate_all(dd->dma_lch);
 812
 813        if (ctx->flags & BIT(FLAGS_SG)) {
 814                dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
 815                if (ctx->sg->length == ctx->offset) {
 816                        ctx->sg = sg_next(ctx->sg);
 817                        if (ctx->sg)
 818                                ctx->offset = 0;
 819                }
 820        } else {
 821                dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
 822                                 DMA_TO_DEVICE);
 823        }
 824
 825        return 0;
 826}
 827
 828static int omap_sham_init(struct ahash_request *req)
 829{
 830        struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 831        struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 832        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 833        struct omap_sham_dev *dd = NULL, *tmp;
 834        int bs = 0;
 835
 836        spin_lock_bh(&sham.lock);
 837        if (!tctx->dd) {
 838                list_for_each_entry(tmp, &sham.dev_list, list) {
 839                        dd = tmp;
 840                        break;
 841                }
 842                tctx->dd = dd;
 843        } else {
 844                dd = tctx->dd;
 845        }
 846        spin_unlock_bh(&sham.lock);
 847
 848        ctx->dd = dd;
 849
 850        ctx->flags = 0;
 851
 852        dev_dbg(dd->dev, "init: digest size: %d\n",
 853                crypto_ahash_digestsize(tfm));
 854
 855        switch (crypto_ahash_digestsize(tfm)) {
 856        case MD5_DIGEST_SIZE:
 857                ctx->flags |= FLAGS_MODE_MD5;
 858                bs = SHA1_BLOCK_SIZE;
 859                break;
 860        case SHA1_DIGEST_SIZE:
 861                ctx->flags |= FLAGS_MODE_SHA1;
 862                bs = SHA1_BLOCK_SIZE;
 863                break;
 864        case SHA224_DIGEST_SIZE:
 865                ctx->flags |= FLAGS_MODE_SHA224;
 866                bs = SHA224_BLOCK_SIZE;
 867                break;
 868        case SHA256_DIGEST_SIZE:
 869                ctx->flags |= FLAGS_MODE_SHA256;
 870                bs = SHA256_BLOCK_SIZE;
 871                break;
 872        case SHA384_DIGEST_SIZE:
 873                ctx->flags |= FLAGS_MODE_SHA384;
 874                bs = SHA384_BLOCK_SIZE;
 875                break;
 876        case SHA512_DIGEST_SIZE:
 877                ctx->flags |= FLAGS_MODE_SHA512;
 878                bs = SHA512_BLOCK_SIZE;
 879                break;
 880        }
 881
 882        ctx->bufcnt = 0;
 883        ctx->digcnt = 0;
 884        ctx->buflen = BUFLEN;
 885
 886        if (tctx->flags & BIT(FLAGS_HMAC)) {
 887                if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
 888                        struct omap_sham_hmac_ctx *bctx = tctx->base;
 889
 890                        memcpy(ctx->buffer, bctx->ipad, bs);
 891                        ctx->bufcnt = bs;
 892                }
 893
 894                ctx->flags |= BIT(FLAGS_HMAC);
 895        }
 896
 897        return 0;
 898
 899}
 900
 901static int omap_sham_update_req(struct omap_sham_dev *dd)
 902{
 903        struct ahash_request *req = dd->req;
 904        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 905        int err;
 906
 907        dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
 908                 ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
 909
 910        if (ctx->flags & BIT(FLAGS_CPU))
 911                err = omap_sham_update_cpu(dd);
 912        else
 913                err = omap_sham_update_dma_start(dd);
 914
 915        /* wait for dma completion before can take more data */
 916        dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
 917
 918        return err;
 919}
 920
 921static int omap_sham_final_req(struct omap_sham_dev *dd)
 922{
 923        struct ahash_request *req = dd->req;
 924        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 925        int err = 0, use_dma = 1;
 926
 927        if ((ctx->bufcnt <= get_block_size(ctx)) || dd->polling_mode)
 928                /*
 929                 * faster to handle last block with cpu or
 930                 * use cpu when dma is not present.
 931                 */
 932                use_dma = 0;
 933
 934        if (use_dma)
 935                err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1);
 936        else
 937                err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1);
 938
 939        ctx->bufcnt = 0;
 940
 941        dev_dbg(dd->dev, "final_req: err: %d\n", err);
 942
 943        return err;
 944}
 945
 946static int omap_sham_finish_hmac(struct ahash_request *req)
 947{
 948        struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
 949        struct omap_sham_hmac_ctx *bctx = tctx->base;
 950        int bs = crypto_shash_blocksize(bctx->shash);
 951        int ds = crypto_shash_digestsize(bctx->shash);
 952        SHASH_DESC_ON_STACK(shash, bctx->shash);
 953
 954        shash->tfm = bctx->shash;
 955        shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
 956
 957        return crypto_shash_init(shash) ?:
 958               crypto_shash_update(shash, bctx->opad, bs) ?:
 959               crypto_shash_finup(shash, req->result, ds, req->result);
 960}
 961
 962static int omap_sham_finish(struct ahash_request *req)
 963{
 964        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 965        struct omap_sham_dev *dd = ctx->dd;
 966        int err = 0;
 967
 968        if (ctx->digcnt) {
 969                omap_sham_copy_ready_hash(req);
 970                if ((ctx->flags & BIT(FLAGS_HMAC)) &&
 971                                !test_bit(FLAGS_AUTO_XOR, &dd->flags))
 972                        err = omap_sham_finish_hmac(req);
 973        }
 974
 975        dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
 976
 977        return err;
 978}
 979
 980static void omap_sham_finish_req(struct ahash_request *req, int err)
 981{
 982        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 983        struct omap_sham_dev *dd = ctx->dd;
 984
 985        if (!err) {
 986                dd->pdata->copy_hash(req, 1);
 987                if (test_bit(FLAGS_FINAL, &dd->flags))
 988                        err = omap_sham_finish(req);
 989        } else {
 990                ctx->flags |= BIT(FLAGS_ERROR);
 991        }
 992
 993        /* atomic operation is not needed here */
 994        dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
 995                        BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
 996
 997        pm_runtime_put(dd->dev);
 998
 999        if (req->base.complete)
1000                req->base.complete(&req->base, err);
1001
1002        /* handle new request */
1003        tasklet_schedule(&dd->done_task);
1004}
1005
1006static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1007                                  struct ahash_request *req)
1008{
1009        struct crypto_async_request *async_req, *backlog;
1010        struct omap_sham_reqctx *ctx;
1011        unsigned long flags;
1012        int err = 0, ret = 0;
1013
1014        spin_lock_irqsave(&dd->lock, flags);
1015        if (req)
1016                ret = ahash_enqueue_request(&dd->queue, req);
1017        if (test_bit(FLAGS_BUSY, &dd->flags)) {
1018                spin_unlock_irqrestore(&dd->lock, flags);
1019                return ret;
1020        }
1021        backlog = crypto_get_backlog(&dd->queue);
1022        async_req = crypto_dequeue_request(&dd->queue);
1023        if (async_req)
1024                set_bit(FLAGS_BUSY, &dd->flags);
1025        spin_unlock_irqrestore(&dd->lock, flags);
1026
1027        if (!async_req)
1028                return ret;
1029
1030        if (backlog)
1031                backlog->complete(backlog, -EINPROGRESS);
1032
1033        req = ahash_request_cast(async_req);
1034        dd->req = req;
1035        ctx = ahash_request_ctx(req);
1036
1037        dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1038                                                ctx->op, req->nbytes);
1039
1040        err = omap_sham_hw_init(dd);
1041        if (err)
1042                goto err1;
1043
1044        if (ctx->digcnt)
1045                /* request has changed - restore hash */
1046                dd->pdata->copy_hash(req, 0);
1047
1048        if (ctx->op == OP_UPDATE) {
1049                err = omap_sham_update_req(dd);
1050                if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1051                        /* no final() after finup() */
1052                        err = omap_sham_final_req(dd);
1053        } else if (ctx->op == OP_FINAL) {
1054                err = omap_sham_final_req(dd);
1055        }
1056err1:
1057        if (err != -EINPROGRESS)
1058                /* done_task will not finish it, so do it here */
1059                omap_sham_finish_req(req, err);
1060
1061        dev_dbg(dd->dev, "exit, err: %d\n", err);
1062
1063        return ret;
1064}
1065
1066static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1067{
1068        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1069        struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1070        struct omap_sham_dev *dd = tctx->dd;
1071
1072        ctx->op = op;
1073
1074        return omap_sham_handle_queue(dd, req);
1075}
1076
1077static int omap_sham_update(struct ahash_request *req)
1078{
1079        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1080        struct omap_sham_dev *dd = ctx->dd;
1081        int bs = get_block_size(ctx);
1082
1083        if (!req->nbytes)
1084                return 0;
1085
1086        ctx->total = req->nbytes;
1087        ctx->sg = req->src;
1088        ctx->offset = 0;
1089
1090        if (ctx->flags & BIT(FLAGS_FINUP)) {
1091                if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 9) {
1092                        /*
1093                        * OMAP HW accel works only with buffers >= 9
1094                        * will switch to bypass in final()
1095                        * final has the same request and data
1096                        */
1097                        omap_sham_append_sg(ctx);
1098                        return 0;
1099                } else if ((ctx->bufcnt + ctx->total <= bs) ||
1100                           dd->polling_mode) {
1101                        /*
1102                         * faster to use CPU for short transfers or
1103                         * use cpu when dma is not present.
1104                         */
1105                        ctx->flags |= BIT(FLAGS_CPU);
1106                }
1107        } else if (ctx->bufcnt + ctx->total < ctx->buflen) {
1108                omap_sham_append_sg(ctx);
1109                return 0;
1110        }
1111
1112        if (dd->polling_mode)
1113                ctx->flags |= BIT(FLAGS_CPU);
1114
1115        return omap_sham_enqueue(req, OP_UPDATE);
1116}
1117
1118static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1119                                  const u8 *data, unsigned int len, u8 *out)
1120{
1121        SHASH_DESC_ON_STACK(shash, tfm);
1122
1123        shash->tfm = tfm;
1124        shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
1125
1126        return crypto_shash_digest(shash, data, len, out);
1127}
1128
1129static int omap_sham_final_shash(struct ahash_request *req)
1130{
1131        struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1132        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1133
1134        return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1135                                      ctx->buffer, ctx->bufcnt, req->result);
1136}
1137
1138static int omap_sham_final(struct ahash_request *req)
1139{
1140        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1141
1142        ctx->flags |= BIT(FLAGS_FINUP);
1143
1144        if (ctx->flags & BIT(FLAGS_ERROR))
1145                return 0; /* uncompleted hash is not needed */
1146
1147        /* OMAP HW accel works only with buffers >= 9 */
1148        /* HMAC is always >= 9 because ipad == block size */
1149        if ((ctx->digcnt + ctx->bufcnt) < 9)
1150                return omap_sham_final_shash(req);
1151        else if (ctx->bufcnt)
1152                return omap_sham_enqueue(req, OP_FINAL);
1153
1154        /* copy ready hash (+ finalize hmac) */
1155        return omap_sham_finish(req);
1156}
1157
1158static int omap_sham_finup(struct ahash_request *req)
1159{
1160        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1161        int err1, err2;
1162
1163        ctx->flags |= BIT(FLAGS_FINUP);
1164
1165        err1 = omap_sham_update(req);
1166        if (err1 == -EINPROGRESS || err1 == -EBUSY)
1167                return err1;
1168        /*
1169         * final() has to be always called to cleanup resources
1170         * even if udpate() failed, except EINPROGRESS
1171         */
1172        err2 = omap_sham_final(req);
1173
1174        return err1 ?: err2;
1175}
1176
1177static int omap_sham_digest(struct ahash_request *req)
1178{
1179        return omap_sham_init(req) ?: omap_sham_finup(req);
1180}
1181
1182static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1183                      unsigned int keylen)
1184{
1185        struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1186        struct omap_sham_hmac_ctx *bctx = tctx->base;
1187        int bs = crypto_shash_blocksize(bctx->shash);
1188        int ds = crypto_shash_digestsize(bctx->shash);
1189        struct omap_sham_dev *dd = NULL, *tmp;
1190        int err, i;
1191
1192        spin_lock_bh(&sham.lock);
1193        if (!tctx->dd) {
1194                list_for_each_entry(tmp, &sham.dev_list, list) {
1195                        dd = tmp;
1196                        break;
1197                }
1198                tctx->dd = dd;
1199        } else {
1200                dd = tctx->dd;
1201        }
1202        spin_unlock_bh(&sham.lock);
1203
1204        err = crypto_shash_setkey(tctx->fallback, key, keylen);
1205        if (err)
1206                return err;
1207
1208        if (keylen > bs) {
1209                err = omap_sham_shash_digest(bctx->shash,
1210                                crypto_shash_get_flags(bctx->shash),
1211                                key, keylen, bctx->ipad);
1212                if (err)
1213                        return err;
1214                keylen = ds;
1215        } else {
1216                memcpy(bctx->ipad, key, keylen);
1217        }
1218
1219        memset(bctx->ipad + keylen, 0, bs - keylen);
1220
1221        if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
1222                memcpy(bctx->opad, bctx->ipad, bs);
1223
1224                for (i = 0; i < bs; i++) {
1225                        bctx->ipad[i] ^= 0x36;
1226                        bctx->opad[i] ^= 0x5c;
1227                }
1228        }
1229
1230        return err;
1231}
1232
1233static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1234{
1235        struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1236        const char *alg_name = crypto_tfm_alg_name(tfm);
1237
1238        /* Allocate a fallback and abort if it failed. */
1239        tctx->fallback = crypto_alloc_shash(alg_name, 0,
1240                                            CRYPTO_ALG_NEED_FALLBACK);
1241        if (IS_ERR(tctx->fallback)) {
1242                pr_err("omap-sham: fallback driver '%s' "
1243                                "could not be loaded.\n", alg_name);
1244                return PTR_ERR(tctx->fallback);
1245        }
1246
1247        crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1248                                 sizeof(struct omap_sham_reqctx) + BUFLEN);
1249
1250        if (alg_base) {
1251                struct omap_sham_hmac_ctx *bctx = tctx->base;
1252                tctx->flags |= BIT(FLAGS_HMAC);
1253                bctx->shash = crypto_alloc_shash(alg_base, 0,
1254                                                CRYPTO_ALG_NEED_FALLBACK);
1255                if (IS_ERR(bctx->shash)) {
1256                        pr_err("omap-sham: base driver '%s' "
1257                                        "could not be loaded.\n", alg_base);
1258                        crypto_free_shash(tctx->fallback);
1259                        return PTR_ERR(bctx->shash);
1260                }
1261
1262        }
1263
1264        return 0;
1265}
1266
1267static int omap_sham_cra_init(struct crypto_tfm *tfm)
1268{
1269        return omap_sham_cra_init_alg(tfm, NULL);
1270}
1271
1272static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1273{
1274        return omap_sham_cra_init_alg(tfm, "sha1");
1275}
1276
1277static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1278{
1279        return omap_sham_cra_init_alg(tfm, "sha224");
1280}
1281
1282static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1283{
1284        return omap_sham_cra_init_alg(tfm, "sha256");
1285}
1286
1287static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1288{
1289        return omap_sham_cra_init_alg(tfm, "md5");
1290}
1291
1292static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1293{
1294        return omap_sham_cra_init_alg(tfm, "sha384");
1295}
1296
1297static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1298{
1299        return omap_sham_cra_init_alg(tfm, "sha512");
1300}
1301
1302static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1303{
1304        struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1305
1306        crypto_free_shash(tctx->fallback);
1307        tctx->fallback = NULL;
1308
1309        if (tctx->flags & BIT(FLAGS_HMAC)) {
1310                struct omap_sham_hmac_ctx *bctx = tctx->base;
1311                crypto_free_shash(bctx->shash);
1312        }
1313}
1314
1315static struct ahash_alg algs_sha1_md5[] = {
1316{
1317        .init           = omap_sham_init,
1318        .update         = omap_sham_update,
1319        .final          = omap_sham_final,
1320        .finup          = omap_sham_finup,
1321        .digest         = omap_sham_digest,
1322        .halg.digestsize        = SHA1_DIGEST_SIZE,
1323        .halg.base      = {
1324                .cra_name               = "sha1",
1325                .cra_driver_name        = "omap-sha1",
1326                .cra_priority           = 100,
1327                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1328                                                CRYPTO_ALG_KERN_DRIVER_ONLY |
1329                                                CRYPTO_ALG_ASYNC |
1330                                                CRYPTO_ALG_NEED_FALLBACK,
1331                .cra_blocksize          = SHA1_BLOCK_SIZE,
1332                .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1333                .cra_alignmask          = 0,
1334                .cra_module             = THIS_MODULE,
1335                .cra_init               = omap_sham_cra_init,
1336                .cra_exit               = omap_sham_cra_exit,
1337        }
1338},
1339{
1340        .init           = omap_sham_init,
1341        .update         = omap_sham_update,
1342        .final          = omap_sham_final,
1343        .finup          = omap_sham_finup,
1344        .digest         = omap_sham_digest,
1345        .halg.digestsize        = MD5_DIGEST_SIZE,
1346        .halg.base      = {
1347                .cra_name               = "md5",
1348                .cra_driver_name        = "omap-md5",
1349                .cra_priority           = 100,
1350                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1351                                                CRYPTO_ALG_KERN_DRIVER_ONLY |
1352                                                CRYPTO_ALG_ASYNC |
1353                                                CRYPTO_ALG_NEED_FALLBACK,
1354                .cra_blocksize          = SHA1_BLOCK_SIZE,
1355                .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1356                .cra_alignmask          = OMAP_ALIGN_MASK,
1357                .cra_module             = THIS_MODULE,
1358                .cra_init               = omap_sham_cra_init,
1359                .cra_exit               = omap_sham_cra_exit,
1360        }
1361},
1362{
1363        .init           = omap_sham_init,
1364        .update         = omap_sham_update,
1365        .final          = omap_sham_final,
1366        .finup          = omap_sham_finup,
1367        .digest         = omap_sham_digest,
1368        .setkey         = omap_sham_setkey,
1369        .halg.digestsize        = SHA1_DIGEST_SIZE,
1370        .halg.base      = {
1371                .cra_name               = "hmac(sha1)",
1372                .cra_driver_name        = "omap-hmac-sha1",
1373                .cra_priority           = 100,
1374                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1375                                                CRYPTO_ALG_KERN_DRIVER_ONLY |
1376                                                CRYPTO_ALG_ASYNC |
1377                                                CRYPTO_ALG_NEED_FALLBACK,
1378                .cra_blocksize          = SHA1_BLOCK_SIZE,
1379                .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1380                                        sizeof(struct omap_sham_hmac_ctx),
1381                .cra_alignmask          = OMAP_ALIGN_MASK,
1382                .cra_module             = THIS_MODULE,
1383                .cra_init               = omap_sham_cra_sha1_init,
1384                .cra_exit               = omap_sham_cra_exit,
1385        }
1386},
1387{
1388        .init           = omap_sham_init,
1389        .update         = omap_sham_update,
1390        .final          = omap_sham_final,
1391        .finup          = omap_sham_finup,
1392        .digest         = omap_sham_digest,
1393        .setkey         = omap_sham_setkey,
1394        .halg.digestsize        = MD5_DIGEST_SIZE,
1395        .halg.base      = {
1396                .cra_name               = "hmac(md5)",
1397                .cra_driver_name        = "omap-hmac-md5",
1398                .cra_priority           = 100,
1399                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1400                                                CRYPTO_ALG_KERN_DRIVER_ONLY |
1401                                                CRYPTO_ALG_ASYNC |
1402                                                CRYPTO_ALG_NEED_FALLBACK,
1403                .cra_blocksize          = SHA1_BLOCK_SIZE,
1404                .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1405                                        sizeof(struct omap_sham_hmac_ctx),
1406                .cra_alignmask          = OMAP_ALIGN_MASK,
1407                .cra_module             = THIS_MODULE,
1408                .cra_init               = omap_sham_cra_md5_init,
1409                .cra_exit               = omap_sham_cra_exit,
1410        }
1411}
1412};
1413
1414/* OMAP4 has some algs in addition to what OMAP2 has */
1415static struct ahash_alg algs_sha224_sha256[] = {
1416{
1417        .init           = omap_sham_init,
1418        .update         = omap_sham_update,
1419        .final          = omap_sham_final,
1420        .finup          = omap_sham_finup,
1421        .digest         = omap_sham_digest,
1422        .halg.digestsize        = SHA224_DIGEST_SIZE,
1423        .halg.base      = {
1424                .cra_name               = "sha224",
1425                .cra_driver_name        = "omap-sha224",
1426                .cra_priority           = 100,
1427                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1428                                                CRYPTO_ALG_ASYNC |
1429                                                CRYPTO_ALG_NEED_FALLBACK,
1430                .cra_blocksize          = SHA224_BLOCK_SIZE,
1431                .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1432                .cra_alignmask          = 0,
1433                .cra_module             = THIS_MODULE,
1434                .cra_init               = omap_sham_cra_init,
1435                .cra_exit               = omap_sham_cra_exit,
1436        }
1437},
1438{
1439        .init           = omap_sham_init,
1440        .update         = omap_sham_update,
1441        .final          = omap_sham_final,
1442        .finup          = omap_sham_finup,
1443        .digest         = omap_sham_digest,
1444        .halg.digestsize        = SHA256_DIGEST_SIZE,
1445        .halg.base      = {
1446                .cra_name               = "sha256",
1447                .cra_driver_name        = "omap-sha256",
1448                .cra_priority           = 100,
1449                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1450                                                CRYPTO_ALG_ASYNC |
1451                                                CRYPTO_ALG_NEED_FALLBACK,
1452                .cra_blocksize          = SHA256_BLOCK_SIZE,
1453                .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1454                .cra_alignmask          = 0,
1455                .cra_module             = THIS_MODULE,
1456                .cra_init               = omap_sham_cra_init,
1457                .cra_exit               = omap_sham_cra_exit,
1458        }
1459},
1460{
1461        .init           = omap_sham_init,
1462        .update         = omap_sham_update,
1463        .final          = omap_sham_final,
1464        .finup          = omap_sham_finup,
1465        .digest         = omap_sham_digest,
1466        .setkey         = omap_sham_setkey,
1467        .halg.digestsize        = SHA224_DIGEST_SIZE,
1468        .halg.base      = {
1469                .cra_name               = "hmac(sha224)",
1470                .cra_driver_name        = "omap-hmac-sha224",
1471                .cra_priority           = 100,
1472                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1473                                                CRYPTO_ALG_ASYNC |
1474                                                CRYPTO_ALG_NEED_FALLBACK,
1475                .cra_blocksize          = SHA224_BLOCK_SIZE,
1476                .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1477                                        sizeof(struct omap_sham_hmac_ctx),
1478                .cra_alignmask          = OMAP_ALIGN_MASK,
1479                .cra_module             = THIS_MODULE,
1480                .cra_init               = omap_sham_cra_sha224_init,
1481                .cra_exit               = omap_sham_cra_exit,
1482        }
1483},
1484{
1485        .init           = omap_sham_init,
1486        .update         = omap_sham_update,
1487        .final          = omap_sham_final,
1488        .finup          = omap_sham_finup,
1489        .digest         = omap_sham_digest,
1490        .setkey         = omap_sham_setkey,
1491        .halg.digestsize        = SHA256_DIGEST_SIZE,
1492        .halg.base      = {
1493                .cra_name               = "hmac(sha256)",
1494                .cra_driver_name        = "omap-hmac-sha256",
1495                .cra_priority           = 100,
1496                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1497                                                CRYPTO_ALG_ASYNC |
1498                                                CRYPTO_ALG_NEED_FALLBACK,
1499                .cra_blocksize          = SHA256_BLOCK_SIZE,
1500                .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1501                                        sizeof(struct omap_sham_hmac_ctx),
1502                .cra_alignmask          = OMAP_ALIGN_MASK,
1503                .cra_module             = THIS_MODULE,
1504                .cra_init               = omap_sham_cra_sha256_init,
1505                .cra_exit               = omap_sham_cra_exit,
1506        }
1507},
1508};
1509
1510static struct ahash_alg algs_sha384_sha512[] = {
1511{
1512        .init           = omap_sham_init,
1513        .update         = omap_sham_update,
1514        .final          = omap_sham_final,
1515        .finup          = omap_sham_finup,
1516        .digest         = omap_sham_digest,
1517        .halg.digestsize        = SHA384_DIGEST_SIZE,
1518        .halg.base      = {
1519                .cra_name               = "sha384",
1520                .cra_driver_name        = "omap-sha384",
1521                .cra_priority           = 100,
1522                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1523                                                CRYPTO_ALG_ASYNC |
1524                                                CRYPTO_ALG_NEED_FALLBACK,
1525                .cra_blocksize          = SHA384_BLOCK_SIZE,
1526                .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1527                .cra_alignmask          = 0,
1528                .cra_module             = THIS_MODULE,
1529                .cra_init               = omap_sham_cra_init,
1530                .cra_exit               = omap_sham_cra_exit,
1531        }
1532},
1533{
1534        .init           = omap_sham_init,
1535        .update         = omap_sham_update,
1536        .final          = omap_sham_final,
1537        .finup          = omap_sham_finup,
1538        .digest         = omap_sham_digest,
1539        .halg.digestsize        = SHA512_DIGEST_SIZE,
1540        .halg.base      = {
1541                .cra_name               = "sha512",
1542                .cra_driver_name        = "omap-sha512",
1543                .cra_priority           = 100,
1544                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1545                                                CRYPTO_ALG_ASYNC |
1546                                                CRYPTO_ALG_NEED_FALLBACK,
1547                .cra_blocksize          = SHA512_BLOCK_SIZE,
1548                .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1549                .cra_alignmask          = 0,
1550                .cra_module             = THIS_MODULE,
1551                .cra_init               = omap_sham_cra_init,
1552                .cra_exit               = omap_sham_cra_exit,
1553        }
1554},
1555{
1556        .init           = omap_sham_init,
1557        .update         = omap_sham_update,
1558        .final          = omap_sham_final,
1559        .finup          = omap_sham_finup,
1560        .digest         = omap_sham_digest,
1561        .setkey         = omap_sham_setkey,
1562        .halg.digestsize        = SHA384_DIGEST_SIZE,
1563        .halg.base      = {
1564                .cra_name               = "hmac(sha384)",
1565                .cra_driver_name        = "omap-hmac-sha384",
1566                .cra_priority           = 100,
1567                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1568                                                CRYPTO_ALG_ASYNC |
1569                                                CRYPTO_ALG_NEED_FALLBACK,
1570                .cra_blocksize          = SHA384_BLOCK_SIZE,
1571                .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1572                                        sizeof(struct omap_sham_hmac_ctx),
1573                .cra_alignmask          = OMAP_ALIGN_MASK,
1574                .cra_module             = THIS_MODULE,
1575                .cra_init               = omap_sham_cra_sha384_init,
1576                .cra_exit               = omap_sham_cra_exit,
1577        }
1578},
1579{
1580        .init           = omap_sham_init,
1581        .update         = omap_sham_update,
1582        .final          = omap_sham_final,
1583        .finup          = omap_sham_finup,
1584        .digest         = omap_sham_digest,
1585        .setkey         = omap_sham_setkey,
1586        .halg.digestsize        = SHA512_DIGEST_SIZE,
1587        .halg.base      = {
1588                .cra_name               = "hmac(sha512)",
1589                .cra_driver_name        = "omap-hmac-sha512",
1590                .cra_priority           = 100,
1591                .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1592                                                CRYPTO_ALG_ASYNC |
1593                                                CRYPTO_ALG_NEED_FALLBACK,
1594                .cra_blocksize          = SHA512_BLOCK_SIZE,
1595                .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1596                                        sizeof(struct omap_sham_hmac_ctx),
1597                .cra_alignmask          = OMAP_ALIGN_MASK,
1598                .cra_module             = THIS_MODULE,
1599                .cra_init               = omap_sham_cra_sha512_init,
1600                .cra_exit               = omap_sham_cra_exit,
1601        }
1602},
1603};
1604
1605static void omap_sham_done_task(unsigned long data)
1606{
1607        struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1608        int err = 0;
1609
1610        if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1611                omap_sham_handle_queue(dd, NULL);
1612                return;
1613        }
1614
1615        if (test_bit(FLAGS_CPU, &dd->flags)) {
1616                if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1617                        /* hash or semi-hash ready */
1618                        err = omap_sham_update_cpu(dd);
1619                        if (err != -EINPROGRESS)
1620                                goto finish;
1621                }
1622        } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1623                if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1624                        omap_sham_update_dma_stop(dd);
1625                        if (dd->err) {
1626                                err = dd->err;
1627                                goto finish;
1628                        }
1629                }
1630                if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1631                        /* hash or semi-hash ready */
1632                        clear_bit(FLAGS_DMA_READY, &dd->flags);
1633                        err = omap_sham_update_dma_start(dd);
1634                        if (err != -EINPROGRESS)
1635                                goto finish;
1636                }
1637        }
1638
1639        return;
1640
1641finish:
1642        dev_dbg(dd->dev, "update done: err: %d\n", err);
1643        /* finish curent request */
1644        omap_sham_finish_req(dd->req, err);
1645}
1646
1647static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1648{
1649        if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1650                dev_warn(dd->dev, "Interrupt when no active requests.\n");
1651        } else {
1652                set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1653                tasklet_schedule(&dd->done_task);
1654        }
1655
1656        return IRQ_HANDLED;
1657}
1658
1659static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1660{
1661        struct omap_sham_dev *dd = dev_id;
1662
1663        if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1664                /* final -> allow device to go to power-saving mode */
1665                omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1666
1667        omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1668                                 SHA_REG_CTRL_OUTPUT_READY);
1669        omap_sham_read(dd, SHA_REG_CTRL);
1670
1671        return omap_sham_irq_common(dd);
1672}
1673
1674static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1675{
1676        struct omap_sham_dev *dd = dev_id;
1677
1678        omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1679
1680        return omap_sham_irq_common(dd);
1681}
1682
1683static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1684        {
1685                .algs_list      = algs_sha1_md5,
1686                .size           = ARRAY_SIZE(algs_sha1_md5),
1687        },
1688};
1689
1690static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1691        .algs_info      = omap_sham_algs_info_omap2,
1692        .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1693        .flags          = BIT(FLAGS_BE32_SHA1),
1694        .digest_size    = SHA1_DIGEST_SIZE,
1695        .copy_hash      = omap_sham_copy_hash_omap2,
1696        .write_ctrl     = omap_sham_write_ctrl_omap2,
1697        .trigger        = omap_sham_trigger_omap2,
1698        .poll_irq       = omap_sham_poll_irq_omap2,
1699        .intr_hdlr      = omap_sham_irq_omap2,
1700        .idigest_ofs    = 0x00,
1701        .din_ofs        = 0x1c,
1702        .digcnt_ofs     = 0x14,
1703        .rev_ofs        = 0x5c,
1704        .mask_ofs       = 0x60,
1705        .sysstatus_ofs  = 0x64,
1706        .major_mask     = 0xf0,
1707        .major_shift    = 4,
1708        .minor_mask     = 0x0f,
1709        .minor_shift    = 0,
1710};
1711
1712#ifdef CONFIG_OF
1713static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1714        {
1715                .algs_list      = algs_sha1_md5,
1716                .size           = ARRAY_SIZE(algs_sha1_md5),
1717        },
1718        {
1719                .algs_list      = algs_sha224_sha256,
1720                .size           = ARRAY_SIZE(algs_sha224_sha256),
1721        },
1722};
1723
1724static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1725        .algs_info      = omap_sham_algs_info_omap4,
1726        .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1727        .flags          = BIT(FLAGS_AUTO_XOR),
1728        .digest_size    = SHA256_DIGEST_SIZE,
1729        .copy_hash      = omap_sham_copy_hash_omap4,
1730        .write_ctrl     = omap_sham_write_ctrl_omap4,
1731        .trigger        = omap_sham_trigger_omap4,
1732        .poll_irq       = omap_sham_poll_irq_omap4,
1733        .intr_hdlr      = omap_sham_irq_omap4,
1734        .idigest_ofs    = 0x020,
1735        .odigest_ofs    = 0x0,
1736        .din_ofs        = 0x080,
1737        .digcnt_ofs     = 0x040,
1738        .rev_ofs        = 0x100,
1739        .mask_ofs       = 0x110,
1740        .sysstatus_ofs  = 0x114,
1741        .mode_ofs       = 0x44,
1742        .length_ofs     = 0x48,
1743        .major_mask     = 0x0700,
1744        .major_shift    = 8,
1745        .minor_mask     = 0x003f,
1746        .minor_shift    = 0,
1747};
1748
1749static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1750        {
1751                .algs_list      = algs_sha1_md5,
1752                .size           = ARRAY_SIZE(algs_sha1_md5),
1753        },
1754        {
1755                .algs_list      = algs_sha224_sha256,
1756                .size           = ARRAY_SIZE(algs_sha224_sha256),
1757        },
1758        {
1759                .algs_list      = algs_sha384_sha512,
1760                .size           = ARRAY_SIZE(algs_sha384_sha512),
1761        },
1762};
1763
1764static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1765        .algs_info      = omap_sham_algs_info_omap5,
1766        .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1767        .flags          = BIT(FLAGS_AUTO_XOR),
1768        .digest_size    = SHA512_DIGEST_SIZE,
1769        .copy_hash      = omap_sham_copy_hash_omap4,
1770        .write_ctrl     = omap_sham_write_ctrl_omap4,
1771        .trigger        = omap_sham_trigger_omap4,
1772        .poll_irq       = omap_sham_poll_irq_omap4,
1773        .intr_hdlr      = omap_sham_irq_omap4,
1774        .idigest_ofs    = 0x240,
1775        .odigest_ofs    = 0x200,
1776        .din_ofs        = 0x080,
1777        .digcnt_ofs     = 0x280,
1778        .rev_ofs        = 0x100,
1779        .mask_ofs       = 0x110,
1780        .sysstatus_ofs  = 0x114,
1781        .mode_ofs       = 0x284,
1782        .length_ofs     = 0x288,
1783        .major_mask     = 0x0700,
1784        .major_shift    = 8,
1785        .minor_mask     = 0x003f,
1786        .minor_shift    = 0,
1787};
1788
1789static const struct of_device_id omap_sham_of_match[] = {
1790        {
1791                .compatible     = "ti,omap2-sham",
1792                .data           = &omap_sham_pdata_omap2,
1793        },
1794        {
1795                .compatible     = "ti,omap4-sham",
1796                .data           = &omap_sham_pdata_omap4,
1797        },
1798        {
1799                .compatible     = "ti,omap5-sham",
1800                .data           = &omap_sham_pdata_omap5,
1801        },
1802        {},
1803};
1804MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1805
1806static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1807                struct device *dev, struct resource *res)
1808{
1809        struct device_node *node = dev->of_node;
1810        const struct of_device_id *match;
1811        int err = 0;
1812
1813        match = of_match_device(of_match_ptr(omap_sham_of_match), dev);
1814        if (!match) {
1815                dev_err(dev, "no compatible OF match\n");
1816                err = -EINVAL;
1817                goto err;
1818        }
1819
1820        err = of_address_to_resource(node, 0, res);
1821        if (err < 0) {
1822                dev_err(dev, "can't translate OF node address\n");
1823                err = -EINVAL;
1824                goto err;
1825        }
1826
1827        dd->irq = irq_of_parse_and_map(node, 0);
1828        if (!dd->irq) {
1829                dev_err(dev, "can't translate OF irq value\n");
1830                err = -EINVAL;
1831                goto err;
1832        }
1833
1834        dd->dma = -1; /* Dummy value that's unused */
1835        dd->pdata = match->data;
1836
1837err:
1838        return err;
1839}
1840#else
1841static const struct of_device_id omap_sham_of_match[] = {
1842        {},
1843};
1844
1845static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1846                struct device *dev, struct resource *res)
1847{
1848        return -EINVAL;
1849}
1850#endif
1851
1852static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1853                struct platform_device *pdev, struct resource *res)
1854{
1855        struct device *dev = &pdev->dev;
1856        struct resource *r;
1857        int err = 0;
1858
1859        /* Get the base address */
1860        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1861        if (!r) {
1862                dev_err(dev, "no MEM resource info\n");
1863                err = -ENODEV;
1864                goto err;
1865        }
1866        memcpy(res, r, sizeof(*res));
1867
1868        /* Get the IRQ */
1869        dd->irq = platform_get_irq(pdev, 0);
1870        if (dd->irq < 0) {
1871                dev_err(dev, "no IRQ resource info\n");
1872                err = dd->irq;
1873                goto err;
1874        }
1875
1876        /* Get the DMA */
1877        r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1878        if (!r) {
1879                dev_err(dev, "no DMA resource info\n");
1880                err = -ENODEV;
1881                goto err;
1882        }
1883        dd->dma = r->start;
1884
1885        /* Only OMAP2/3 can be non-DT */
1886        dd->pdata = &omap_sham_pdata_omap2;
1887
1888err:
1889        return err;
1890}
1891
1892static int omap_sham_probe(struct platform_device *pdev)
1893{
1894        struct omap_sham_dev *dd;
1895        struct device *dev = &pdev->dev;
1896        struct resource res;
1897        dma_cap_mask_t mask;
1898        int err, i, j;
1899        u32 rev;
1900
1901        dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
1902        if (dd == NULL) {
1903                dev_err(dev, "unable to alloc data struct.\n");
1904                err = -ENOMEM;
1905                goto data_err;
1906        }
1907        dd->dev = dev;
1908        platform_set_drvdata(pdev, dd);
1909
1910        INIT_LIST_HEAD(&dd->list);
1911        spin_lock_init(&dd->lock);
1912        tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
1913        crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
1914
1915        err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
1916                               omap_sham_get_res_pdev(dd, pdev, &res);
1917        if (err)
1918                goto data_err;
1919
1920        dd->io_base = devm_ioremap_resource(dev, &res);
1921        if (IS_ERR(dd->io_base)) {
1922                err = PTR_ERR(dd->io_base);
1923                goto data_err;
1924        }
1925        dd->phys_base = res.start;
1926
1927        err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
1928                               IRQF_TRIGGER_NONE, dev_name(dev), dd);
1929        if (err) {
1930                dev_err(dev, "unable to request irq %d, err = %d\n",
1931                        dd->irq, err);
1932                goto data_err;
1933        }
1934
1935        dma_cap_zero(mask);
1936        dma_cap_set(DMA_SLAVE, mask);
1937
1938        dd->dma_lch = dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
1939                                                       &dd->dma, dev, "rx");
1940        if (!dd->dma_lch) {
1941                dd->polling_mode = 1;
1942                dev_dbg(dev, "using polling mode instead of dma\n");
1943        }
1944
1945        dd->flags |= dd->pdata->flags;
1946
1947        pm_runtime_enable(dev);
1948        pm_runtime_get_sync(dev);
1949        rev = omap_sham_read(dd, SHA_REG_REV(dd));
1950        pm_runtime_put_sync(&pdev->dev);
1951
1952        dev_info(dev, "hw accel on OMAP rev %u.%u\n",
1953                (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
1954                (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1955
1956        spin_lock(&sham.lock);
1957        list_add_tail(&dd->list, &sham.dev_list);
1958        spin_unlock(&sham.lock);
1959
1960        for (i = 0; i < dd->pdata->algs_info_size; i++) {
1961                for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1962                        err = crypto_register_ahash(
1963                                        &dd->pdata->algs_info[i].algs_list[j]);
1964                        if (err)
1965                                goto err_algs;
1966
1967                        dd->pdata->algs_info[i].registered++;
1968                }
1969        }
1970
1971        return 0;
1972
1973err_algs:
1974        for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1975                for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1976                        crypto_unregister_ahash(
1977                                        &dd->pdata->algs_info[i].algs_list[j]);
1978        pm_runtime_disable(dev);
1979        if (dd->dma_lch)
1980                dma_release_channel(dd->dma_lch);
1981data_err:
1982        dev_err(dev, "initialization failed.\n");
1983
1984        return err;
1985}
1986
1987static int omap_sham_remove(struct platform_device *pdev)
1988{
1989        static struct omap_sham_dev *dd;
1990        int i, j;
1991
1992        dd = platform_get_drvdata(pdev);
1993        if (!dd)
1994                return -ENODEV;
1995        spin_lock(&sham.lock);
1996        list_del(&dd->list);
1997        spin_unlock(&sham.lock);
1998        for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1999                for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2000                        crypto_unregister_ahash(
2001                                        &dd->pdata->algs_info[i].algs_list[j]);
2002        tasklet_kill(&dd->done_task);
2003        pm_runtime_disable(&pdev->dev);
2004
2005        if (dd->dma_lch)
2006                dma_release_channel(dd->dma_lch);
2007
2008        return 0;
2009}
2010
2011#ifdef CONFIG_PM_SLEEP
2012static int omap_sham_suspend(struct device *dev)
2013{
2014        pm_runtime_put_sync(dev);
2015        return 0;
2016}
2017
2018static int omap_sham_resume(struct device *dev)
2019{
2020        pm_runtime_get_sync(dev);
2021        return 0;
2022}
2023#endif
2024
2025static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2026
2027static struct platform_driver omap_sham_driver = {
2028        .probe  = omap_sham_probe,
2029        .remove = omap_sham_remove,
2030        .driver = {
2031                .name   = "omap-sham",
2032                .pm     = &omap_sham_pm_ops,
2033                .of_match_table = omap_sham_of_match,
2034        },
2035};
2036
2037module_platform_driver(omap_sham_driver);
2038
2039MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2040MODULE_LICENSE("GPL v2");
2041MODULE_AUTHOR("Dmitry Kasatkin");
2042MODULE_ALIAS("platform:omap-sham");
2043
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