linux/drivers/crypto/omap-aes.c
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   1/*
   2 * Cryptographic API.
   3 *
   4 * Support for OMAP AES HW acceleration.
   5 *
   6 * Copyright (c) 2010 Nokia Corporation
   7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   8 * Copyright (c) 2011 Texas Instruments Incorporated
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License version 2 as published
  12 * by the Free Software Foundation.
  13 *
  14 */
  15
  16#define pr_fmt(fmt) "%20s: " fmt, __func__
  17#define prn(num) pr_debug(#num "=%d\n", num)
  18#define prx(num) pr_debug(#num "=%x\n", num)
  19
  20#include <linux/err.h>
  21#include <linux/module.h>
  22#include <linux/init.h>
  23#include <linux/errno.h>
  24#include <linux/kernel.h>
  25#include <linux/platform_device.h>
  26#include <linux/scatterlist.h>
  27#include <linux/dma-mapping.h>
  28#include <linux/dmaengine.h>
  29#include <linux/omap-dma.h>
  30#include <linux/pm_runtime.h>
  31#include <linux/of.h>
  32#include <linux/of_device.h>
  33#include <linux/of_address.h>
  34#include <linux/io.h>
  35#include <linux/crypto.h>
  36#include <linux/interrupt.h>
  37#include <crypto/scatterwalk.h>
  38#include <crypto/aes.h>
  39
  40#define DST_MAXBURST                    4
  41#define DMA_MIN                         (DST_MAXBURST * sizeof(u32))
  42
  43#define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
  44
  45/* OMAP TRM gives bitfields as start:end, where start is the higher bit
  46   number. For example 7:0 */
  47#define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  48#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  49
  50#define AES_REG_KEY(dd, x)              ((dd)->pdata->key_ofs - \
  51                                                ((x ^ 0x01) * 0x04))
  52#define AES_REG_IV(dd, x)               ((dd)->pdata->iv_ofs + ((x) * 0x04))
  53
  54#define AES_REG_CTRL(dd)                ((dd)->pdata->ctrl_ofs)
  55#define AES_REG_CTRL_CTR_WIDTH_MASK     (3 << 7)
  56#define AES_REG_CTRL_CTR_WIDTH_32               (0 << 7)
  57#define AES_REG_CTRL_CTR_WIDTH_64               (1 << 7)
  58#define AES_REG_CTRL_CTR_WIDTH_96               (2 << 7)
  59#define AES_REG_CTRL_CTR_WIDTH_128              (3 << 7)
  60#define AES_REG_CTRL_CTR                (1 << 6)
  61#define AES_REG_CTRL_CBC                (1 << 5)
  62#define AES_REG_CTRL_KEY_SIZE           (3 << 3)
  63#define AES_REG_CTRL_DIRECTION          (1 << 2)
  64#define AES_REG_CTRL_INPUT_READY        (1 << 1)
  65#define AES_REG_CTRL_OUTPUT_READY       (1 << 0)
  66
  67#define AES_REG_DATA_N(dd, x)           ((dd)->pdata->data_ofs + ((x) * 0x04))
  68
  69#define AES_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  70
  71#define AES_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  72#define AES_REG_MASK_SIDLE              (1 << 6)
  73#define AES_REG_MASK_START              (1 << 5)
  74#define AES_REG_MASK_DMA_OUT_EN         (1 << 3)
  75#define AES_REG_MASK_DMA_IN_EN          (1 << 2)
  76#define AES_REG_MASK_SOFTRESET          (1 << 1)
  77#define AES_REG_AUTOIDLE                (1 << 0)
  78
  79#define AES_REG_LENGTH_N(x)             (0x54 + ((x) * 0x04))
  80
  81#define AES_REG_IRQ_STATUS(dd)         ((dd)->pdata->irq_status_ofs)
  82#define AES_REG_IRQ_ENABLE(dd)         ((dd)->pdata->irq_enable_ofs)
  83#define AES_REG_IRQ_DATA_IN            BIT(1)
  84#define AES_REG_IRQ_DATA_OUT           BIT(2)
  85#define DEFAULT_TIMEOUT         (5*HZ)
  86
  87#define FLAGS_MODE_MASK         0x000f
  88#define FLAGS_ENCRYPT           BIT(0)
  89#define FLAGS_CBC               BIT(1)
  90#define FLAGS_GIV               BIT(2)
  91#define FLAGS_CTR               BIT(3)
  92
  93#define FLAGS_INIT              BIT(4)
  94#define FLAGS_FAST              BIT(5)
  95#define FLAGS_BUSY              BIT(6)
  96
  97#define AES_BLOCK_WORDS         (AES_BLOCK_SIZE >> 2)
  98
  99struct omap_aes_ctx {
 100        struct omap_aes_dev *dd;
 101
 102        int             keylen;
 103        u32             key[AES_KEYSIZE_256 / sizeof(u32)];
 104        unsigned long   flags;
 105};
 106
 107struct omap_aes_reqctx {
 108        unsigned long mode;
 109};
 110
 111#define OMAP_AES_QUEUE_LENGTH   1
 112#define OMAP_AES_CACHE_SIZE     0
 113
 114struct omap_aes_algs_info {
 115        struct crypto_alg       *algs_list;
 116        unsigned int            size;
 117        unsigned int            registered;
 118};
 119
 120struct omap_aes_pdata {
 121        struct omap_aes_algs_info       *algs_info;
 122        unsigned int    algs_info_size;
 123
 124        void            (*trigger)(struct omap_aes_dev *dd, int length);
 125
 126        u32             key_ofs;
 127        u32             iv_ofs;
 128        u32             ctrl_ofs;
 129        u32             data_ofs;
 130        u32             rev_ofs;
 131        u32             mask_ofs;
 132        u32             irq_enable_ofs;
 133        u32             irq_status_ofs;
 134
 135        u32             dma_enable_in;
 136        u32             dma_enable_out;
 137        u32             dma_start;
 138
 139        u32             major_mask;
 140        u32             major_shift;
 141        u32             minor_mask;
 142        u32             minor_shift;
 143};
 144
 145struct omap_aes_dev {
 146        struct list_head        list;
 147        unsigned long           phys_base;
 148        void __iomem            *io_base;
 149        struct omap_aes_ctx     *ctx;
 150        struct device           *dev;
 151        unsigned long           flags;
 152        int                     err;
 153
 154        spinlock_t              lock;
 155        struct crypto_queue     queue;
 156
 157        struct tasklet_struct   done_task;
 158        struct tasklet_struct   queue_task;
 159
 160        struct ablkcipher_request       *req;
 161
 162        /*
 163         * total is used by PIO mode for book keeping so introduce
 164         * variable total_save as need it to calc page_order
 165         */
 166        size_t                          total;
 167        size_t                          total_save;
 168
 169        struct scatterlist              *in_sg;
 170        struct scatterlist              *out_sg;
 171
 172        /* Buffers for copying for unaligned cases */
 173        struct scatterlist              in_sgl;
 174        struct scatterlist              out_sgl;
 175        struct scatterlist              *orig_out;
 176        int                             sgs_copied;
 177
 178        struct scatter_walk             in_walk;
 179        struct scatter_walk             out_walk;
 180        int                     dma_in;
 181        struct dma_chan         *dma_lch_in;
 182        int                     dma_out;
 183        struct dma_chan         *dma_lch_out;
 184        int                     in_sg_len;
 185        int                     out_sg_len;
 186        int                     pio_only;
 187        const struct omap_aes_pdata     *pdata;
 188};
 189
 190/* keep registered devices data here */
 191static LIST_HEAD(dev_list);
 192static DEFINE_SPINLOCK(list_lock);
 193
 194#ifdef DEBUG
 195#define omap_aes_read(dd, offset)                               \
 196({                                                              \
 197        int _read_ret;                                          \
 198        _read_ret = __raw_readl(dd->io_base + offset);          \
 199        pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n",       \
 200                 offset, _read_ret);                            \
 201        _read_ret;                                              \
 202})
 203#else
 204static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
 205{
 206        return __raw_readl(dd->io_base + offset);
 207}
 208#endif
 209
 210#ifdef DEBUG
 211#define omap_aes_write(dd, offset, value)                               \
 212        do {                                                            \
 213                pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
 214                         offset, value);                                \
 215                __raw_writel(value, dd->io_base + offset);              \
 216        } while (0)
 217#else
 218static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
 219                                  u32 value)
 220{
 221        __raw_writel(value, dd->io_base + offset);
 222}
 223#endif
 224
 225static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
 226                                        u32 value, u32 mask)
 227{
 228        u32 val;
 229
 230        val = omap_aes_read(dd, offset);
 231        val &= ~mask;
 232        val |= value;
 233        omap_aes_write(dd, offset, val);
 234}
 235
 236static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
 237                                        u32 *value, int count)
 238{
 239        for (; count--; value++, offset += 4)
 240                omap_aes_write(dd, offset, *value);
 241}
 242
 243static int omap_aes_hw_init(struct omap_aes_dev *dd)
 244{
 245        if (!(dd->flags & FLAGS_INIT)) {
 246                dd->flags |= FLAGS_INIT;
 247                dd->err = 0;
 248        }
 249
 250        return 0;
 251}
 252
 253static int omap_aes_write_ctrl(struct omap_aes_dev *dd)
 254{
 255        unsigned int key32;
 256        int i, err;
 257        u32 val, mask = 0;
 258
 259        err = omap_aes_hw_init(dd);
 260        if (err)
 261                return err;
 262
 263        key32 = dd->ctx->keylen / sizeof(u32);
 264
 265        /* it seems a key should always be set even if it has not changed */
 266        for (i = 0; i < key32; i++) {
 267                omap_aes_write(dd, AES_REG_KEY(dd, i),
 268                        __le32_to_cpu(dd->ctx->key[i]));
 269        }
 270
 271        if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info)
 272                omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4);
 273
 274        val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
 275        if (dd->flags & FLAGS_CBC)
 276                val |= AES_REG_CTRL_CBC;
 277        if (dd->flags & FLAGS_CTR) {
 278                val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128;
 279                mask = AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_MASK;
 280        }
 281        if (dd->flags & FLAGS_ENCRYPT)
 282                val |= AES_REG_CTRL_DIRECTION;
 283
 284        mask |= AES_REG_CTRL_CBC | AES_REG_CTRL_DIRECTION |
 285                        AES_REG_CTRL_KEY_SIZE;
 286
 287        omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, mask);
 288
 289        return 0;
 290}
 291
 292static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
 293{
 294        u32 mask, val;
 295
 296        val = dd->pdata->dma_start;
 297
 298        if (dd->dma_lch_out != NULL)
 299                val |= dd->pdata->dma_enable_out;
 300        if (dd->dma_lch_in != NULL)
 301                val |= dd->pdata->dma_enable_in;
 302
 303        mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
 304               dd->pdata->dma_start;
 305
 306        omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
 307
 308}
 309
 310static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
 311{
 312        omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
 313        omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
 314
 315        omap_aes_dma_trigger_omap2(dd, length);
 316}
 317
 318static void omap_aes_dma_stop(struct omap_aes_dev *dd)
 319{
 320        u32 mask;
 321
 322        mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
 323               dd->pdata->dma_start;
 324
 325        omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
 326}
 327
 328static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx)
 329{
 330        struct omap_aes_dev *dd = NULL, *tmp;
 331
 332        spin_lock_bh(&list_lock);
 333        if (!ctx->dd) {
 334                list_for_each_entry(tmp, &dev_list, list) {
 335                        /* FIXME: take fist available aes core */
 336                        dd = tmp;
 337                        break;
 338                }
 339                ctx->dd = dd;
 340        } else {
 341                /* already found before */
 342                dd = ctx->dd;
 343        }
 344        spin_unlock_bh(&list_lock);
 345
 346        return dd;
 347}
 348
 349static void omap_aes_dma_out_callback(void *data)
 350{
 351        struct omap_aes_dev *dd = data;
 352
 353        /* dma_lch_out - completed */
 354        tasklet_schedule(&dd->done_task);
 355}
 356
 357static int omap_aes_dma_init(struct omap_aes_dev *dd)
 358{
 359        int err = -ENOMEM;
 360        dma_cap_mask_t mask;
 361
 362        dd->dma_lch_out = NULL;
 363        dd->dma_lch_in = NULL;
 364
 365        dma_cap_zero(mask);
 366        dma_cap_set(DMA_SLAVE, mask);
 367
 368        dd->dma_lch_in = dma_request_slave_channel_compat(mask,
 369                                                          omap_dma_filter_fn,
 370                                                          &dd->dma_in,
 371                                                          dd->dev, "rx");
 372        if (!dd->dma_lch_in) {
 373                dev_err(dd->dev, "Unable to request in DMA channel\n");
 374                goto err_dma_in;
 375        }
 376
 377        dd->dma_lch_out = dma_request_slave_channel_compat(mask,
 378                                                           omap_dma_filter_fn,
 379                                                           &dd->dma_out,
 380                                                           dd->dev, "tx");
 381        if (!dd->dma_lch_out) {
 382                dev_err(dd->dev, "Unable to request out DMA channel\n");
 383                goto err_dma_out;
 384        }
 385
 386        return 0;
 387
 388err_dma_out:
 389        dma_release_channel(dd->dma_lch_in);
 390err_dma_in:
 391        if (err)
 392                pr_err("error: %d\n", err);
 393        return err;
 394}
 395
 396static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
 397{
 398        dma_release_channel(dd->dma_lch_out);
 399        dma_release_channel(dd->dma_lch_in);
 400}
 401
 402static void sg_copy_buf(void *buf, struct scatterlist *sg,
 403                              unsigned int start, unsigned int nbytes, int out)
 404{
 405        struct scatter_walk walk;
 406
 407        if (!nbytes)
 408                return;
 409
 410        scatterwalk_start(&walk, sg);
 411        scatterwalk_advance(&walk, start);
 412        scatterwalk_copychunks(buf, &walk, nbytes, out);
 413        scatterwalk_done(&walk, out, 0);
 414}
 415
 416static int omap_aes_crypt_dma(struct crypto_tfm *tfm,
 417                struct scatterlist *in_sg, struct scatterlist *out_sg,
 418                int in_sg_len, int out_sg_len)
 419{
 420        struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
 421        struct omap_aes_dev *dd = ctx->dd;
 422        struct dma_async_tx_descriptor *tx_in, *tx_out;
 423        struct dma_slave_config cfg;
 424        int ret;
 425
 426        if (dd->pio_only) {
 427                scatterwalk_start(&dd->in_walk, dd->in_sg);
 428                scatterwalk_start(&dd->out_walk, dd->out_sg);
 429
 430                /* Enable DATAIN interrupt and let it take
 431                   care of the rest */
 432                omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
 433                return 0;
 434        }
 435
 436        dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
 437
 438        memset(&cfg, 0, sizeof(cfg));
 439
 440        cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
 441        cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
 442        cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 443        cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 444        cfg.src_maxburst = DST_MAXBURST;
 445        cfg.dst_maxburst = DST_MAXBURST;
 446
 447        /* IN */
 448        ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
 449        if (ret) {
 450                dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
 451                        ret);
 452                return ret;
 453        }
 454
 455        tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
 456                                        DMA_MEM_TO_DEV,
 457                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 458        if (!tx_in) {
 459                dev_err(dd->dev, "IN prep_slave_sg() failed\n");
 460                return -EINVAL;
 461        }
 462
 463        /* No callback necessary */
 464        tx_in->callback_param = dd;
 465
 466        /* OUT */
 467        ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
 468        if (ret) {
 469                dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
 470                        ret);
 471                return ret;
 472        }
 473
 474        tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
 475                                        DMA_DEV_TO_MEM,
 476                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 477        if (!tx_out) {
 478                dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
 479                return -EINVAL;
 480        }
 481
 482        tx_out->callback = omap_aes_dma_out_callback;
 483        tx_out->callback_param = dd;
 484
 485        dmaengine_submit(tx_in);
 486        dmaengine_submit(tx_out);
 487
 488        dma_async_issue_pending(dd->dma_lch_in);
 489        dma_async_issue_pending(dd->dma_lch_out);
 490
 491        /* start DMA */
 492        dd->pdata->trigger(dd, dd->total);
 493
 494        return 0;
 495}
 496
 497static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
 498{
 499        struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
 500                                        crypto_ablkcipher_reqtfm(dd->req));
 501        int err;
 502
 503        pr_debug("total: %d\n", dd->total);
 504
 505        if (!dd->pio_only) {
 506                err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
 507                                 DMA_TO_DEVICE);
 508                if (!err) {
 509                        dev_err(dd->dev, "dma_map_sg() error\n");
 510                        return -EINVAL;
 511                }
 512
 513                err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 514                                 DMA_FROM_DEVICE);
 515                if (!err) {
 516                        dev_err(dd->dev, "dma_map_sg() error\n");
 517                        return -EINVAL;
 518                }
 519        }
 520
 521        err = omap_aes_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
 522                                 dd->out_sg_len);
 523        if (err && !dd->pio_only) {
 524                dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
 525                dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 526                             DMA_FROM_DEVICE);
 527        }
 528
 529        return err;
 530}
 531
 532static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
 533{
 534        struct ablkcipher_request *req = dd->req;
 535
 536        pr_debug("err: %d\n", err);
 537
 538        dd->flags &= ~FLAGS_BUSY;
 539
 540        req->base.complete(&req->base, err);
 541}
 542
 543static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
 544{
 545        int err = 0;
 546
 547        pr_debug("total: %d\n", dd->total);
 548
 549        omap_aes_dma_stop(dd);
 550
 551        dmaengine_terminate_all(dd->dma_lch_in);
 552        dmaengine_terminate_all(dd->dma_lch_out);
 553
 554        return err;
 555}
 556
 557static int omap_aes_check_aligned(struct scatterlist *sg)
 558{
 559        while (sg) {
 560                if (!IS_ALIGNED(sg->offset, 4))
 561                        return -1;
 562                if (!IS_ALIGNED(sg->length, AES_BLOCK_SIZE))
 563                        return -1;
 564                sg = sg_next(sg);
 565        }
 566        return 0;
 567}
 568
 569static int omap_aes_copy_sgs(struct omap_aes_dev *dd)
 570{
 571        void *buf_in, *buf_out;
 572        int pages;
 573
 574        pages = get_order(dd->total);
 575
 576        buf_in = (void *)__get_free_pages(GFP_ATOMIC, pages);
 577        buf_out = (void *)__get_free_pages(GFP_ATOMIC, pages);
 578
 579        if (!buf_in || !buf_out) {
 580                pr_err("Couldn't allocated pages for unaligned cases.\n");
 581                return -1;
 582        }
 583
 584        dd->orig_out = dd->out_sg;
 585
 586        sg_copy_buf(buf_in, dd->in_sg, 0, dd->total, 0);
 587
 588        sg_init_table(&dd->in_sgl, 1);
 589        sg_set_buf(&dd->in_sgl, buf_in, dd->total);
 590        dd->in_sg = &dd->in_sgl;
 591
 592        sg_init_table(&dd->out_sgl, 1);
 593        sg_set_buf(&dd->out_sgl, buf_out, dd->total);
 594        dd->out_sg = &dd->out_sgl;
 595
 596        return 0;
 597}
 598
 599static int omap_aes_handle_queue(struct omap_aes_dev *dd,
 600                               struct ablkcipher_request *req)
 601{
 602        struct crypto_async_request *async_req, *backlog;
 603        struct omap_aes_ctx *ctx;
 604        struct omap_aes_reqctx *rctx;
 605        unsigned long flags;
 606        int err, ret = 0;
 607
 608        spin_lock_irqsave(&dd->lock, flags);
 609        if (req)
 610                ret = ablkcipher_enqueue_request(&dd->queue, req);
 611        if (dd->flags & FLAGS_BUSY) {
 612                spin_unlock_irqrestore(&dd->lock, flags);
 613                return ret;
 614        }
 615        backlog = crypto_get_backlog(&dd->queue);
 616        async_req = crypto_dequeue_request(&dd->queue);
 617        if (async_req)
 618                dd->flags |= FLAGS_BUSY;
 619        spin_unlock_irqrestore(&dd->lock, flags);
 620
 621        if (!async_req)
 622                return ret;
 623
 624        if (backlog)
 625                backlog->complete(backlog, -EINPROGRESS);
 626
 627        req = ablkcipher_request_cast(async_req);
 628
 629        /* assign new request to device */
 630        dd->req = req;
 631        dd->total = req->nbytes;
 632        dd->total_save = req->nbytes;
 633        dd->in_sg = req->src;
 634        dd->out_sg = req->dst;
 635
 636        if (omap_aes_check_aligned(dd->in_sg) ||
 637            omap_aes_check_aligned(dd->out_sg)) {
 638                if (omap_aes_copy_sgs(dd))
 639                        pr_err("Failed to copy SGs for unaligned cases\n");
 640                dd->sgs_copied = 1;
 641        } else {
 642                dd->sgs_copied = 0;
 643        }
 644
 645        dd->in_sg_len = scatterwalk_bytes_sglen(dd->in_sg, dd->total);
 646        dd->out_sg_len = scatterwalk_bytes_sglen(dd->out_sg, dd->total);
 647        BUG_ON(dd->in_sg_len < 0 || dd->out_sg_len < 0);
 648
 649        rctx = ablkcipher_request_ctx(req);
 650        ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
 651        rctx->mode &= FLAGS_MODE_MASK;
 652        dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
 653
 654        dd->ctx = ctx;
 655        ctx->dd = dd;
 656
 657        err = omap_aes_write_ctrl(dd);
 658        if (!err)
 659                err = omap_aes_crypt_dma_start(dd);
 660        if (err) {
 661                /* aes_task will not finish it, so do it here */
 662                omap_aes_finish_req(dd, err);
 663                tasklet_schedule(&dd->queue_task);
 664        }
 665
 666        return ret; /* return ret, which is enqueue return value */
 667}
 668
 669static void omap_aes_done_task(unsigned long data)
 670{
 671        struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
 672        void *buf_in, *buf_out;
 673        int pages;
 674
 675        pr_debug("enter done_task\n");
 676
 677        if (!dd->pio_only) {
 678                dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
 679                                       DMA_FROM_DEVICE);
 680                dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
 681                dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 682                             DMA_FROM_DEVICE);
 683                omap_aes_crypt_dma_stop(dd);
 684        }
 685
 686        if (dd->sgs_copied) {
 687                buf_in = sg_virt(&dd->in_sgl);
 688                buf_out = sg_virt(&dd->out_sgl);
 689
 690                sg_copy_buf(buf_out, dd->orig_out, 0, dd->total_save, 1);
 691
 692                pages = get_order(dd->total_save);
 693                free_pages((unsigned long)buf_in, pages);
 694                free_pages((unsigned long)buf_out, pages);
 695        }
 696
 697        omap_aes_finish_req(dd, 0);
 698        omap_aes_handle_queue(dd, NULL);
 699
 700        pr_debug("exit\n");
 701}
 702
 703static void omap_aes_queue_task(unsigned long data)
 704{
 705        struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
 706
 707        omap_aes_handle_queue(dd, NULL);
 708}
 709
 710static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
 711{
 712        struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
 713                        crypto_ablkcipher_reqtfm(req));
 714        struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
 715        struct omap_aes_dev *dd;
 716
 717        pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
 718                  !!(mode & FLAGS_ENCRYPT),
 719                  !!(mode & FLAGS_CBC));
 720
 721        if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) {
 722                pr_err("request size is not exact amount of AES blocks\n");
 723                return -EINVAL;
 724        }
 725
 726        dd = omap_aes_find_dev(ctx);
 727        if (!dd)
 728                return -ENODEV;
 729
 730        rctx->mode = mode;
 731
 732        return omap_aes_handle_queue(dd, req);
 733}
 734
 735/* ********************** ALG API ************************************ */
 736
 737static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
 738                           unsigned int keylen)
 739{
 740        struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
 741
 742        if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
 743                   keylen != AES_KEYSIZE_256)
 744                return -EINVAL;
 745
 746        pr_debug("enter, keylen: %d\n", keylen);
 747
 748        memcpy(ctx->key, key, keylen);
 749        ctx->keylen = keylen;
 750
 751        return 0;
 752}
 753
 754static int omap_aes_ecb_encrypt(struct ablkcipher_request *req)
 755{
 756        return omap_aes_crypt(req, FLAGS_ENCRYPT);
 757}
 758
 759static int omap_aes_ecb_decrypt(struct ablkcipher_request *req)
 760{
 761        return omap_aes_crypt(req, 0);
 762}
 763
 764static int omap_aes_cbc_encrypt(struct ablkcipher_request *req)
 765{
 766        return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
 767}
 768
 769static int omap_aes_cbc_decrypt(struct ablkcipher_request *req)
 770{
 771        return omap_aes_crypt(req, FLAGS_CBC);
 772}
 773
 774static int omap_aes_ctr_encrypt(struct ablkcipher_request *req)
 775{
 776        return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
 777}
 778
 779static int omap_aes_ctr_decrypt(struct ablkcipher_request *req)
 780{
 781        return omap_aes_crypt(req, FLAGS_CTR);
 782}
 783
 784static int omap_aes_cra_init(struct crypto_tfm *tfm)
 785{
 786        struct omap_aes_dev *dd = NULL;
 787        int err;
 788
 789        /* Find AES device, currently picks the first device */
 790        spin_lock_bh(&list_lock);
 791        list_for_each_entry(dd, &dev_list, list) {
 792                break;
 793        }
 794        spin_unlock_bh(&list_lock);
 795
 796        err = pm_runtime_get_sync(dd->dev);
 797        if (err < 0) {
 798                dev_err(dd->dev, "%s: failed to get_sync(%d)\n",
 799                        __func__, err);
 800                return err;
 801        }
 802
 803        tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx);
 804
 805        return 0;
 806}
 807
 808static void omap_aes_cra_exit(struct crypto_tfm *tfm)
 809{
 810        struct omap_aes_dev *dd = NULL;
 811
 812        /* Find AES device, currently picks the first device */
 813        spin_lock_bh(&list_lock);
 814        list_for_each_entry(dd, &dev_list, list) {
 815                break;
 816        }
 817        spin_unlock_bh(&list_lock);
 818
 819        pm_runtime_put_sync(dd->dev);
 820}
 821
 822/* ********************** ALGS ************************************ */
 823
 824static struct crypto_alg algs_ecb_cbc[] = {
 825{
 826        .cra_name               = "ecb(aes)",
 827        .cra_driver_name        = "ecb-aes-omap",
 828        .cra_priority           = 100,
 829        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
 830                                  CRYPTO_ALG_KERN_DRIVER_ONLY |
 831                                  CRYPTO_ALG_ASYNC,
 832        .cra_blocksize          = AES_BLOCK_SIZE,
 833        .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 834        .cra_alignmask          = 0,
 835        .cra_type               = &crypto_ablkcipher_type,
 836        .cra_module             = THIS_MODULE,
 837        .cra_init               = omap_aes_cra_init,
 838        .cra_exit               = omap_aes_cra_exit,
 839        .cra_u.ablkcipher = {
 840                .min_keysize    = AES_MIN_KEY_SIZE,
 841                .max_keysize    = AES_MAX_KEY_SIZE,
 842                .setkey         = omap_aes_setkey,
 843                .encrypt        = omap_aes_ecb_encrypt,
 844                .decrypt        = omap_aes_ecb_decrypt,
 845        }
 846},
 847{
 848        .cra_name               = "cbc(aes)",
 849        .cra_driver_name        = "cbc-aes-omap",
 850        .cra_priority           = 100,
 851        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
 852                                  CRYPTO_ALG_KERN_DRIVER_ONLY |
 853                                  CRYPTO_ALG_ASYNC,
 854        .cra_blocksize          = AES_BLOCK_SIZE,
 855        .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 856        .cra_alignmask          = 0,
 857        .cra_type               = &crypto_ablkcipher_type,
 858        .cra_module             = THIS_MODULE,
 859        .cra_init               = omap_aes_cra_init,
 860        .cra_exit               = omap_aes_cra_exit,
 861        .cra_u.ablkcipher = {
 862                .min_keysize    = AES_MIN_KEY_SIZE,
 863                .max_keysize    = AES_MAX_KEY_SIZE,
 864                .ivsize         = AES_BLOCK_SIZE,
 865                .setkey         = omap_aes_setkey,
 866                .encrypt        = omap_aes_cbc_encrypt,
 867                .decrypt        = omap_aes_cbc_decrypt,
 868        }
 869}
 870};
 871
 872static struct crypto_alg algs_ctr[] = {
 873{
 874        .cra_name               = "ctr(aes)",
 875        .cra_driver_name        = "ctr-aes-omap",
 876        .cra_priority           = 100,
 877        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
 878                                  CRYPTO_ALG_KERN_DRIVER_ONLY |
 879                                  CRYPTO_ALG_ASYNC,
 880        .cra_blocksize          = AES_BLOCK_SIZE,
 881        .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 882        .cra_alignmask          = 0,
 883        .cra_type               = &crypto_ablkcipher_type,
 884        .cra_module             = THIS_MODULE,
 885        .cra_init               = omap_aes_cra_init,
 886        .cra_exit               = omap_aes_cra_exit,
 887        .cra_u.ablkcipher = {
 888                .min_keysize    = AES_MIN_KEY_SIZE,
 889                .max_keysize    = AES_MAX_KEY_SIZE,
 890                .geniv          = "eseqiv",
 891                .ivsize         = AES_BLOCK_SIZE,
 892                .setkey         = omap_aes_setkey,
 893                .encrypt        = omap_aes_ctr_encrypt,
 894                .decrypt        = omap_aes_ctr_decrypt,
 895        }
 896} ,
 897};
 898
 899static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
 900        {
 901                .algs_list      = algs_ecb_cbc,
 902                .size           = ARRAY_SIZE(algs_ecb_cbc),
 903        },
 904};
 905
 906static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
 907        .algs_info      = omap_aes_algs_info_ecb_cbc,
 908        .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
 909        .trigger        = omap_aes_dma_trigger_omap2,
 910        .key_ofs        = 0x1c,
 911        .iv_ofs         = 0x20,
 912        .ctrl_ofs       = 0x30,
 913        .data_ofs       = 0x34,
 914        .rev_ofs        = 0x44,
 915        .mask_ofs       = 0x48,
 916        .dma_enable_in  = BIT(2),
 917        .dma_enable_out = BIT(3),
 918        .dma_start      = BIT(5),
 919        .major_mask     = 0xf0,
 920        .major_shift    = 4,
 921        .minor_mask     = 0x0f,
 922        .minor_shift    = 0,
 923};
 924
 925#ifdef CONFIG_OF
 926static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
 927        {
 928                .algs_list      = algs_ecb_cbc,
 929                .size           = ARRAY_SIZE(algs_ecb_cbc),
 930        },
 931        {
 932                .algs_list      = algs_ctr,
 933                .size           = ARRAY_SIZE(algs_ctr),
 934        },
 935};
 936
 937static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
 938        .algs_info      = omap_aes_algs_info_ecb_cbc_ctr,
 939        .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
 940        .trigger        = omap_aes_dma_trigger_omap2,
 941        .key_ofs        = 0x1c,
 942        .iv_ofs         = 0x20,
 943        .ctrl_ofs       = 0x30,
 944        .data_ofs       = 0x34,
 945        .rev_ofs        = 0x44,
 946        .mask_ofs       = 0x48,
 947        .dma_enable_in  = BIT(2),
 948        .dma_enable_out = BIT(3),
 949        .dma_start      = BIT(5),
 950        .major_mask     = 0xf0,
 951        .major_shift    = 4,
 952        .minor_mask     = 0x0f,
 953        .minor_shift    = 0,
 954};
 955
 956static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
 957        .algs_info      = omap_aes_algs_info_ecb_cbc_ctr,
 958        .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
 959        .trigger        = omap_aes_dma_trigger_omap4,
 960        .key_ofs        = 0x3c,
 961        .iv_ofs         = 0x40,
 962        .ctrl_ofs       = 0x50,
 963        .data_ofs       = 0x60,
 964        .rev_ofs        = 0x80,
 965        .mask_ofs       = 0x84,
 966        .irq_status_ofs = 0x8c,
 967        .irq_enable_ofs = 0x90,
 968        .dma_enable_in  = BIT(5),
 969        .dma_enable_out = BIT(6),
 970        .major_mask     = 0x0700,
 971        .major_shift    = 8,
 972        .minor_mask     = 0x003f,
 973        .minor_shift    = 0,
 974};
 975
 976static irqreturn_t omap_aes_irq(int irq, void *dev_id)
 977{
 978        struct omap_aes_dev *dd = dev_id;
 979        u32 status, i;
 980        u32 *src, *dst;
 981
 982        status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd));
 983        if (status & AES_REG_IRQ_DATA_IN) {
 984                omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
 985
 986                BUG_ON(!dd->in_sg);
 987
 988                BUG_ON(_calc_walked(in) > dd->in_sg->length);
 989
 990                src = sg_virt(dd->in_sg) + _calc_walked(in);
 991
 992                for (i = 0; i < AES_BLOCK_WORDS; i++) {
 993                        omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src);
 994
 995                        scatterwalk_advance(&dd->in_walk, 4);
 996                        if (dd->in_sg->length == _calc_walked(in)) {
 997                                dd->in_sg = scatterwalk_sg_next(dd->in_sg);
 998                                if (dd->in_sg) {
 999                                        scatterwalk_start(&dd->in_walk,
1000                                                          dd->in_sg);
1001                                        src = sg_virt(dd->in_sg) +
1002                                              _calc_walked(in);
1003                                }
1004                        } else {
1005                                src++;
1006                        }
1007                }
1008
1009                /* Clear IRQ status */
1010                status &= ~AES_REG_IRQ_DATA_IN;
1011                omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
1012
1013                /* Enable DATA_OUT interrupt */
1014                omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4);
1015
1016        } else if (status & AES_REG_IRQ_DATA_OUT) {
1017                omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
1018
1019                BUG_ON(!dd->out_sg);
1020
1021                BUG_ON(_calc_walked(out) > dd->out_sg->length);
1022
1023                dst = sg_virt(dd->out_sg) + _calc_walked(out);
1024
1025                for (i = 0; i < AES_BLOCK_WORDS; i++) {
1026                        *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i));
1027                        scatterwalk_advance(&dd->out_walk, 4);
1028                        if (dd->out_sg->length == _calc_walked(out)) {
1029                                dd->out_sg = scatterwalk_sg_next(dd->out_sg);
1030                                if (dd->out_sg) {
1031                                        scatterwalk_start(&dd->out_walk,
1032                                                          dd->out_sg);
1033                                        dst = sg_virt(dd->out_sg) +
1034                                              _calc_walked(out);
1035                                }
1036                        } else {
1037                                dst++;
1038                        }
1039                }
1040
1041                dd->total -= AES_BLOCK_SIZE;
1042
1043                BUG_ON(dd->total < 0);
1044
1045                /* Clear IRQ status */
1046                status &= ~AES_REG_IRQ_DATA_OUT;
1047                omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
1048
1049                if (!dd->total)
1050                        /* All bytes read! */
1051                        tasklet_schedule(&dd->done_task);
1052                else
1053                        /* Enable DATA_IN interrupt for next block */
1054                        omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
1055        }
1056
1057        return IRQ_HANDLED;
1058}
1059
1060static const struct of_device_id omap_aes_of_match[] = {
1061        {
1062                .compatible     = "ti,omap2-aes",
1063                .data           = &omap_aes_pdata_omap2,
1064        },
1065        {
1066                .compatible     = "ti,omap3-aes",
1067                .data           = &omap_aes_pdata_omap3,
1068        },
1069        {
1070                .compatible     = "ti,omap4-aes",
1071                .data           = &omap_aes_pdata_omap4,
1072        },
1073        {},
1074};
1075MODULE_DEVICE_TABLE(of, omap_aes_of_match);
1076
1077static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1078                struct device *dev, struct resource *res)
1079{
1080        struct device_node *node = dev->of_node;
1081        const struct of_device_id *match;
1082        int err = 0;
1083
1084        match = of_match_device(of_match_ptr(omap_aes_of_match), dev);
1085        if (!match) {
1086                dev_err(dev, "no compatible OF match\n");
1087                err = -EINVAL;
1088                goto err;
1089        }
1090
1091        err = of_address_to_resource(node, 0, res);
1092        if (err < 0) {
1093                dev_err(dev, "can't translate OF node address\n");
1094                err = -EINVAL;
1095                goto err;
1096        }
1097
1098        dd->dma_out = -1; /* Dummy value that's unused */
1099        dd->dma_in = -1; /* Dummy value that's unused */
1100
1101        dd->pdata = match->data;
1102
1103err:
1104        return err;
1105}
1106#else
1107static const struct of_device_id omap_aes_of_match[] = {
1108        {},
1109};
1110
1111static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1112                struct device *dev, struct resource *res)
1113{
1114        return -EINVAL;
1115}
1116#endif
1117
1118static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
1119                struct platform_device *pdev, struct resource *res)
1120{
1121        struct device *dev = &pdev->dev;
1122        struct resource *r;
1123        int err = 0;
1124
1125        /* Get the base address */
1126        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1127        if (!r) {
1128                dev_err(dev, "no MEM resource info\n");
1129                err = -ENODEV;
1130                goto err;
1131        }
1132        memcpy(res, r, sizeof(*res));
1133
1134        /* Get the DMA out channel */
1135        r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1136        if (!r) {
1137                dev_err(dev, "no DMA out resource info\n");
1138                err = -ENODEV;
1139                goto err;
1140        }
1141        dd->dma_out = r->start;
1142
1143        /* Get the DMA in channel */
1144        r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1145        if (!r) {
1146                dev_err(dev, "no DMA in resource info\n");
1147                err = -ENODEV;
1148                goto err;
1149        }
1150        dd->dma_in = r->start;
1151
1152        /* Only OMAP2/3 can be non-DT */
1153        dd->pdata = &omap_aes_pdata_omap2;
1154
1155err:
1156        return err;
1157}
1158
1159static int omap_aes_probe(struct platform_device *pdev)
1160{
1161        struct device *dev = &pdev->dev;
1162        struct omap_aes_dev *dd;
1163        struct crypto_alg *algp;
1164        struct resource res;
1165        int err = -ENOMEM, i, j, irq = -1;
1166        u32 reg;
1167
1168        dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL);
1169        if (dd == NULL) {
1170                dev_err(dev, "unable to alloc data struct.\n");
1171                goto err_data;
1172        }
1173        dd->dev = dev;
1174        platform_set_drvdata(pdev, dd);
1175
1176        spin_lock_init(&dd->lock);
1177        crypto_init_queue(&dd->queue, OMAP_AES_QUEUE_LENGTH);
1178
1179        err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
1180                               omap_aes_get_res_pdev(dd, pdev, &res);
1181        if (err)
1182                goto err_res;
1183
1184        dd->io_base = devm_ioremap_resource(dev, &res);
1185        if (IS_ERR(dd->io_base)) {
1186                err = PTR_ERR(dd->io_base);
1187                goto err_res;
1188        }
1189        dd->phys_base = res.start;
1190
1191        pm_runtime_enable(dev);
1192        err = pm_runtime_get_sync(dev);
1193        if (err < 0) {
1194                dev_err(dev, "%s: failed to get_sync(%d)\n",
1195                        __func__, err);
1196                goto err_res;
1197        }
1198
1199        omap_aes_dma_stop(dd);
1200
1201        reg = omap_aes_read(dd, AES_REG_REV(dd));
1202
1203        pm_runtime_put_sync(dev);
1204
1205        dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
1206                 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1207                 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1208
1209        tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
1210        tasklet_init(&dd->queue_task, omap_aes_queue_task, (unsigned long)dd);
1211
1212        err = omap_aes_dma_init(dd);
1213        if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) {
1214                dd->pio_only = 1;
1215
1216                irq = platform_get_irq(pdev, 0);
1217                if (irq < 0) {
1218                        dev_err(dev, "can't get IRQ resource\n");
1219                        goto err_irq;
1220                }
1221
1222                err = devm_request_irq(dev, irq, omap_aes_irq, 0,
1223                                dev_name(dev), dd);
1224                if (err) {
1225                        dev_err(dev, "Unable to grab omap-aes IRQ\n");
1226                        goto err_irq;
1227                }
1228        }
1229
1230
1231        INIT_LIST_HEAD(&dd->list);
1232        spin_lock(&list_lock);
1233        list_add_tail(&dd->list, &dev_list);
1234        spin_unlock(&list_lock);
1235
1236        for (i = 0; i < dd->pdata->algs_info_size; i++) {
1237                for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1238                        algp = &dd->pdata->algs_info[i].algs_list[j];
1239
1240                        pr_debug("reg alg: %s\n", algp->cra_name);
1241                        INIT_LIST_HEAD(&algp->cra_list);
1242
1243                        err = crypto_register_alg(algp);
1244                        if (err)
1245                                goto err_algs;
1246
1247                        dd->pdata->algs_info[i].registered++;
1248                }
1249        }
1250
1251        return 0;
1252err_algs:
1253        for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1254                for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1255                        crypto_unregister_alg(
1256                                        &dd->pdata->algs_info[i].algs_list[j]);
1257        if (!dd->pio_only)
1258                omap_aes_dma_cleanup(dd);
1259err_irq:
1260        tasklet_kill(&dd->done_task);
1261        tasklet_kill(&dd->queue_task);
1262        pm_runtime_disable(dev);
1263err_res:
1264        dd = NULL;
1265err_data:
1266        dev_err(dev, "initialization failed.\n");
1267        return err;
1268}
1269
1270static int omap_aes_remove(struct platform_device *pdev)
1271{
1272        struct omap_aes_dev *dd = platform_get_drvdata(pdev);
1273        int i, j;
1274
1275        if (!dd)
1276                return -ENODEV;
1277
1278        spin_lock(&list_lock);
1279        list_del(&dd->list);
1280        spin_unlock(&list_lock);
1281
1282        for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1283                for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1284                        crypto_unregister_alg(
1285                                        &dd->pdata->algs_info[i].algs_list[j]);
1286
1287        tasklet_kill(&dd->done_task);
1288        tasklet_kill(&dd->queue_task);
1289        omap_aes_dma_cleanup(dd);
1290        pm_runtime_disable(dd->dev);
1291        dd = NULL;
1292
1293        return 0;
1294}
1295
1296#ifdef CONFIG_PM_SLEEP
1297static int omap_aes_suspend(struct device *dev)
1298{
1299        pm_runtime_put_sync(dev);
1300        return 0;
1301}
1302
1303static int omap_aes_resume(struct device *dev)
1304{
1305        pm_runtime_get_sync(dev);
1306        return 0;
1307}
1308#endif
1309
1310static const struct dev_pm_ops omap_aes_pm_ops = {
1311        SET_SYSTEM_SLEEP_PM_OPS(omap_aes_suspend, omap_aes_resume)
1312};
1313
1314static struct platform_driver omap_aes_driver = {
1315        .probe  = omap_aes_probe,
1316        .remove = omap_aes_remove,
1317        .driver = {
1318                .name   = "omap-aes",
1319                .owner  = THIS_MODULE,
1320                .pm     = &omap_aes_pm_ops,
1321                .of_match_table = omap_aes_of_match,
1322        },
1323};
1324
1325module_platform_driver(omap_aes_driver);
1326
1327MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
1328MODULE_LICENSE("GPL v2");
1329MODULE_AUTHOR("Dmitry Kasatkin");
1330
1331
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