linux/drivers/clk/ux500/u8500_of_clk.c
<<
n> 2" /spa3.1 2" /form.1 2" a n> 2" href="../linux+von v/drivers/clk/ux500/u8500_of_clk.c">n> 2" img src="../.static/gfx/right.png" alt=">>">n> /spa3.1n> spa3 class="lxr_search">n> n> 2" input typ4.1hidden" nam4.1navtarget" v3.14.1">n> 2" input typ4.1text" nam4.1search" id.1search">n> 2" butt typ4.1submit">Search spa3 class="lxr_prefs".1 2" a href="+prefs?return=drivers/clk/ux500/u8500_of_clk.c"n> 2" onclick="return ajax_prefs();">n> 2"Prefs1 2" /a>n> /spa3.1 2" " /div.1 2" " form ac="v3="ajax+*" method="post" onsubmit="return false;">n> input typ4.1hidden" nam4.1ajax_lookup" id.1ajax_lookup" v3.14.1">n 2" " /form.1n 2" " div class="headingbott m">1 div id.1file_contents".
" "1
/a>
spa3 class="comment">/*
/spa3.1" "2
/a>
spa3 class="comment"> * Clock defini="v3s for u8500 platform.
/spa3.1" "3
/a>
spa3 class="comment"> *
/spa3.1" "4
/a>
spa3 class="comment"> * Copyright (C) 2012 ST-Ericss
  SA
/spa3.1" "5
/a>
spa3 class="comment"> * Author: Ulf Hanss
  <ulf.hanss
 @linaro.org>
/spa3.1" "6
/a>
spa3 class="comment"> *
/spa3.1" "7
/a>
spa3 class="comment"> * License terms: GNU General Public License (GPL) vers>
  2
/spa3.1" "8
/a>
spa3 class="comment"> */
/spa3.1" "9
/a>n"  vala>#include <linux/of.hala>>n" 11ala>#include <linux/of_address.hala>>n" 12ala>#include <linux/clk-provider.hala>>n" 13ala>#include <linux/mfd/dbx500-prcmu.hala>>n" 14ala>#include "clk.hala>"n" 15
/a>n" 16
/a>#define"
a href="+code=PRCC_NUM_PERIPH_CLUSTERS" class="sref">PRCC_NUM_PERIPH_CLUSTERS
/a> 6n" 17
/a>#define"
a href="+code=PRCC_PERIPHS_PER_CLUSTER" class="sref">PRCC_PERIPHS_PER_CLUSTER
/a> 32n" 18
/a>n" 19
/a>static struct"
a href="+code=clk" class="sref">clk
/a> *
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_NUM_CLKS" class="sref">PRCMU_NUM_CLKS
/a>];n" 20
/a>static struct"
a href="+code=clk" class="sref">clk
/a> *
a href="+code=prcc_pclk" class="sref">prcc_pclk
/a>[(
a href="+code=PRCC_NUM_PERIPH_CLUSTERS" class="sref">PRCC_NUM_PERIPH_CLUSTERS
/a> + 1) * 
a href="+code=PRCC_PERIPHS_PER_CLUSTER" class="sref">PRCC_PERIPHS_PER_CLUSTER
/a>];n" 21
/a>static struct"
a href="+code=clk" class="sref">clk
/a> *
a href="+code=prcc_kclk" class="sref">prcc_kclk
/a>[(
a href="+code=PRCC_NUM_PERIPH_CLUSTERS" class="sref">PRCC_NUM_PERIPH_CLUSTERS
/a> + 1) * 
a href="+code=PRCC_PERIPHS_PER_CLUSTER" class="sref">PRCC_PERIPHS_PER_CLUSTER
/a>];n" 22
/a>n" 23
/a>#define"
a href="+code=PRCC_SHOW" class="sref">PRCC_SHOW
/a>(
a href="+code=clk" class="sref">clk
/a>,"
a href="+code=base" class="sref">base
/a>,"
a href="+code=bit" class="sref">bit
/a>) \n" 24ala>        
a href="+code=clk" class="sref">clk
/a>[(
a href="+code=base" class="sref">base
/a> * 
a href="+code=PRCC_PERIPHS_PER_CLUSTER" class="sref">PRCC_PERIPHS_PER_CLUSTER
/a>) + 
a href="+code=bit" class="sref">bit
/a>]n" 25
/a>#define"
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>,"
a href="+code=base" class="sref">base
/a>,"
a href="+code=bit" class="sref">bit
/a>) \n" 26ala>        
a href="+code=prcc_pclk" class="sref">prcc_pclk
/a>[(
a href="+code=base" class="sref">base
/a> * 
a href="+code=PRCC_PERIPHS_PER_CLUSTER" class="sref">PRCC_PERIPHS_PER_CLUSTER
/a>) + 
a href="+code=bit" class="sref">bit
/a>] = 
a href="+code=clk" class="sref">clk
/a>n" 27
/a>#define"
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>,"
a href="+code=base" class="sref">base
/a>,"
a href="+code=bit" class="sref">bit
/a>)        \n" 28ala>        
a href="+code=prcc_kclk" class="sref">prcc_kclk
/a>[(
a href="+code=base" class="sref">base
/a> * 
a href="+code=PRCC_PERIPHS_PER_CLUSTER" class="sref">PRCC_PERIPHS_PER_CLUSTER
/a>) + 
a href="+code=bit" class="sref">bit
/a>] = 
a href="+code=clk" class="sref">clk
/a>n" 29
/a>n" 30
/a>static struct"
a href="+code=clk" class="sref">clk
/a> *
a href="+code=ux500_twocell_get" class="sref">ux500_twocell_get
/a>(struct"
a href="+code=of_phandle_args" class="sref">of_phandle_args
/a> *
a href="+code=clkspec" class="sref">clkspec
/a>,n" 31ala>                                     void *
a href="+code=data" class="sref">data
/a>)n" 32
/a>{n" 33ala>        struct"
a href="+code=clk" class="sref">clk
/a> **
a href="+code=clk_data" class="sref">clk_data
/a> = 
a href="+code=data" class="sref">data
/a>;n" 34ala>        unsigned int"
a href="+code=base" class="sref">base
/a>,"
a href="+code=bit" class="sref">bit
/a>;n" 35
/a>n" 36ala>        if (
a href="+code=clkspec" class="sref">clkspec
/a>->
a href="+code=args_count" class="sref">args_countala> != 2)n" 37ala>                return "
a href="+code=ERR_PTR" class="sref">ERR_PTR
/a>(-
a href="+code=EINVAL" class="sref">EINVAL
/a>);n" 38
/a>n" 39ala>        
a href="+code=base" class="sref">base
/a> = 
a href="+code=clkspec" class="sref">clkspec
/a>->
a href="+code=args" class="sref">args
/a>[0];n" 40ala>        
a href="+code=bit" class="sref">bit
/a> = 
a href="+code=clkspec" class="sref">clkspec
/a>->
a href="+code=args" class="sref">args
/a>[1];n" 41
/a>n" 42ala>        if (
a href="+code=base" class="sref">base
/a> != 1 && 
a href="+code=base" class="sref">base
/a> != 2 && 
a href="+code=base" class="sref">base
/a> != 3 && 
a href="+code=base" class="sref">base
/a> != 5 && 
a href="+code=base" class="sref">base
/a> != 6) {n" 43ala>                
a href="+code=pr_err" class="sref">pr_err
/a>(
spa3 class="string">"%s: invalid PRCC base %d\n"__func__
/a>,"
a href="+code=base" class="sref">base
/a>);n" 44ala>                return 
a href="+code=ERR_PTR" class="sref">ERR_PTR
/a>(-
a href="+code=EINVAL" class="sref">EINVAL
/a>);n" 45ala>        }n" 46
/a>n" 47ala>        return 
a href="+code=PRCC_SHOW" class="sref">PRCC_SHOW
/a>(
a href="+code=clk_data" class="sref">clk_data
/a>,"
a href="+code=base" class="sref">base
/a>,"
a href="+code=bit" class="sref">bit
/a>);n" 48
/a>}n" 49
/a>n" 50
/a>
spa3 class="comment">/* CLKRST4 is missing making it hard to index things */
/spa3.1" 51
/a>enum 
a href="+code=clkrst_index" class="sref">clkrst_indexala> {n" 52ala>        
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a> = 0,n" 53ala>        
a href="+code=CLKRST2_INDEX" class="sref">CLKRST2_INDEX
/a>,n" 54ala>        
a href="+code=CLKRST3_INDEX" class="sref">CLKRST3_INDEX
/a>,n" 55ala>        
a href="+code=CLKRST5_INDEX" class="sref">CLKRST5_INDEX
/a>,n" 56ala>        
a href="+code=CLKRST6_INDEX" class="sref">CLKRST6_INDEX
/a>,n" 57ala>        
a href="+code=CLKRST_MAX" class="sref">CLKRST_MAX
/a>,n" 58
/a>};n" 59
/a>n" 60
/a>static void 
a href="+code=u8500_clk_ini=" class="sref">u8500_clk_ini=
/a>(struct"
a href="+code=device_node" class="sref">device_node
/a> *
a href="+code=np" class="sref">np
/a>)n" 61
/a>{n" 62ala>        struct"
a href="+code=prcmu_fw_vers>
 " class="sref">prcmu_fw_vers>
 
/a> *
a href="+code=fw_vers>
 " class="sref">fw_vers>
 
/a>;n" 63ala>        struct"
a href="+code=device_node" class="sref">device_node
/a> *
a href="+code=child" class="sref">child
/a> = 
a href="+code=NULL" class="sref">NULL
/a>;n" 64ala>        const char *
a href="+code=sgaclk_parent" class="sref">sgaclk_parent
/a> = 
a href="+code=NULL" class="sref">NULL
/a>;n" 65ala>        struct"
a href="+code=clk" class="sref">clk
/a> *
a href="+code=clk" class="sref">clk
/a>,"*
a href="+code=rtc_clk" class="sref">rtc_clk
/a>,"*
a href="+code=twd_clk" class="sref">twd_clk
/a>;n" 66ala>        
a href="+code=u32" class="sref">u32
/a>"
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST_MAX" class="sref">CLKRST_MAX
/a>];n" 67ala>        int"
a href="+code=i" class="sref">i
/a>;n" 68
/a>n" 69ala>        for (
a href="+code=i" class="sref">i
/a> = 0; 
a href="+code=i" class="sref">i
/a> < 
a href="+code=ARRAY_SIZE" class="sref">ARRAY_SIZE
/a>(
a href="+code=bases" class="sref">bases
/a>); 
a href="+code=i" class="sref">i
/a>++) {n" 70ala>                struct"
a href="+code=resource" class="sref">resource
/a>"
a href="+code=r" class="sref">r
/a>;n" 71
/a>n" 72ala>                if (
a href="+code=of_address_to_resource" class="sref">of_address_to_resource
/a>(
a href="+code=np" class="sref">np
/a>,"
a href="+code=i" class="sref">i
/a>, &
a href="+code=r" class="sref">r
/a>))n" 73ala>                        
spa3 class="comment">/* Not much choice but to continue */
/spa3.1" 74ala>                        
a href="+code=pr_err" class="sref">pr_err
/a>(
spa3 class="string">"failed to get CLKRST %d base address\n"" 75ala>                               
a href="+code=i" class="sref">i
/a> + 1);n" 76ala>                
a href="+code=bases" class="sref">bases
/a>[
a href="+code=i" class="sref">i
/a>] = 
a href="+code=r" class="sref">r
/a>.
a href="+code=start" class="sref">start
/a>;n" 77ala>        }n" 78
/a>n" 79ala>        
spa3 class="comment">/* Clock sources */
/spa3.1" 80ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"soc0_pll"NULL
/a>,"
a href="+code=PRCMU_PLLSOC0" class="sref">PRCMU_PLLSOC0
/a>,n" 81ala>                                
a href="+code=CLK_IGNORE_UNUSED" class="sref">CLK_IGNORE_UNUSED
/a>);n" 82ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_PLLSOC0" class="sref">PRCMU_PLLSOC0
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n" 83
/a>n" 84ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"soc1_pll"NULL
/a>,"
a href="+code=PRCMU_PLLSOC1" class="sref">PRCMU_PLLSOC1
/a>,n" 85ala>                                
a href="+code=CLK_IGNORE_UNUSED" class="sref">CLK_IGNORE_UNUSED
/a>);n" 86ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_PLLSOC1" class="sref">PRCMU_PLLSOC1
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n" 87
/a>n" 88ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"ddr_pll"NULL
/a>,"
a href="+code=PRCMU_PLLDDR" class="sref">PRCMU_PLLDDR
/a>,n" 89ala>                                
a href="+code=CLK_IGNORE_UNUSED" class="sref">CLK_IGNORE_UNUSED
/a>);n" 90ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_PLLDDR" class="sref">PRCMU_PLLDDR
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n" 91
/a>n" 92ala>        
spa3 class="comment">/* FIXME: Add sys, ulp and int"clocks here. */
/spa3.1" 93
/a>n" 94ala>        
a href="+code=rtc_clk" class="sref">rtc_clk
/a> = 
a href="+code=clk_register_fixed_rate" class="sref">clk_register_fixed_rate
/a>(
a href="+code=NULL" class="sref">NULL
/a>,"
spa3 class="string">"rtc32k""NULL"" 95ala>                                
a href="+code=CLK_IGNORE_UNUSED" class="sref">CLK_IGNORE_UNUSED
/a>,1" 96ala>                                32768);n" 97
/a>n" 98ala>        
spa3 class="comment">/* PRCMU"clocks */
/spa3.1" 99ala>        
a href="+code=fw_vers>
 " class="sref">fw_vers>
 
/a> = 
a href="+code=prcmu_get_fw_vers>
 " class="sref">prcmu_get_fw_vers>
 
/a>();n"100ala>        if (
a href="+code=fw_vers>
 " class="sref">fw_vers>
 
/a> != 
a href="+code=NULL" class="sref">NULL
/a>) {n"101ala>                switch (
a href="+code=fw_vers>
 " class="sref">fw_vers>
 
/a>->
a href="+code=project" class="sref">project
/a>) {n"102ala>                case 
a href="+code=PRCMU_FW_PROJECT_U8500_C2" class="sref">PRCMU_FW_PROJECT_U8500_C2ala>:n"103ala>                case 
a href="+code=PRCMU_FW_PROJECT_U8520" class="sref">PRCMU_FW_PROJECT_U8520ala>:n"104ala>                case 
a href="+code=PRCMU_FW_PROJECT_U8420" class="sref">PRCMU_FW_PROJECT_U8420ala>:n"105ala>                        
a href="+code=sgaclk_parent" class="sref">sgaclk_parent
/a> = 
spa3 class="string">"soc0_pll""106ala>                        break;n"107ala>                default:n"108ala>                        break;n"109ala>                }n"110ala>        }n"111
/a>n"112ala>        if (
a href="+code=sgaclk_parent" class="sref">sgaclk_parent
/a>)n"113ala>                
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"sgclk"sgaclk_parent
/a>,1"114ala>                                        
a href="+code=PRCMU_SGACLK" class="sref">PRCMU_SGACLK
/a>,"0);n"115ala>        elsen"116ala>                
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"sgclk"NULL
/a>,"
a href="+code=PRCMU_SGACLK" class="sref">PRCMU_SGACLK
/a>,"0);n"117ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_SGACLK" class="sref">PRCMU_SGACLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"118
/a>n"119ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"uartclk"NULL
/a>,"
a href="+code=PRCMU_UARTCLK" class="sref">PRCMU_UARTCLK
/a>,"0);n"120ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_UARTCLK" class="sref">PRCMU_UARTCLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"121
/a>n"122ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"msp02clk"NULL
/a>,"
a href="+code=PRCMU_MSP02CLK" class="sref">PRCMU_MSP02CLK
/a>,"0);n"123ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_MSP02CLK" class="sref">PRCMU_MSP02CLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"124ala>n"125ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"msp1clk"NULL
/a>,"
a href="+code=PRCMU_MSP1CLK" class="sref">PRCMU_MSP1CLK
/a>,"0);n"126ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_MSP1CLK" class="sref">PRCMU_MSP1CLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"127
/a>n"128ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"i2cclk"NULL
/a>,"
a href="+code=PRCMU_I2CCLK" class="sref">PRCMU_I2CCLK
/a>,"0);n"129ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_I2CCLK" class="sref">PRCMU_I2CCLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"130
/a>n"131ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"slimclk"NULL
/a>,"
a href="+code=PRCMU_SLIMCLK" class="sref">PRCMU_SLIMCLK
/a>,"0);n"132ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_SLIMCLK" class="sref">PRCMU_SLIMCLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"133
/a>n"134ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"per1clk"NULL
/a>,"
a href="+code=PRCMU_PER1CLK" class="sref">PRCMU_PER1CLK
/a>,"0);n"135ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_PER1CLK" class="sref">PRCMU_PER1CLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"136
/a>n"137ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"per2clk"NULL
/a>,"
a href="+code=PRCMU_PER2CLK" class="sref">PRCMU_PER2CLK
/a>,"0);n"138ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_PER2CLK" class="sref">PRCMU_PER2CLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"139
/a>n"140ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"per3clk"NULL
/a>,"
a href="+code=PRCMU_PER3CLK" class="sref">PRCMU_PER3CLK
/a>,"0);n"141ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_PER3CLK" class="sref">PRCMU_PER3CLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"142
/a>n"143ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"per5clk"NULL
/a>,"
a href="+code=PRCMU_PER5CLK" class="sref">PRCMU_PER5CLK
/a>,"0);n"144ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_PER5CLK" class="sref">PRCMU_PER5CLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"145
/a>n"146ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"per6clk"NULL
/a>,"
a href="+code=PRCMU_PER6CLK" class="sref">PRCMU_PER6CLK
/a>,"0);n"147ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_PER6CLK" class="sref">PRCMU_PER6CLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"148
/a>n"149ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"per7clk"NULL
/a>,"
a href="+code=PRCMU_PER7CLK" class="sref">PRCMU_PER7CLK
/a>,"0);n"150ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_PER7CLK" class="sref">PRCMU_PER7CLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"151
/a>n"152ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_scalable" class="sref">clk_reg_prcmu_scalable
/a>(
spa3 class="string">"lcdclk"NULL
/a>,"
a href="+code=PRCMU_LCDCLK" class="sref">PRCMU_LCDCLK
/a>,"0,1"153ala>                                
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATEala>);n"154ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_LCDCLK" class="sref">PRCMU_LCDCLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"155
/a>n"156ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_opp_gate" class="sref">clk_reg_prcmu_opp_gate
/a>(
spa3 class="string">"bmlclk"NULL
/a>,"
a href="+code=PRCMU_BMLCLK" class="sref">PRCMU_BMLCLK
/a>,"0);n"157ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_BMLCLK" class="sref">PRCMU_BMLCLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"158
/a>n"159ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_scalable" class="sref">clk_reg_prcmu_scalable
/a>(
spa3 class="string">"hsitxclk"NULL
/a>,"
a href="+code=PRCMU_HSITXCLK" class="sref">PRCMU_HSITXCLK
/a>,"0,1"160ala>                                
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATEala>);n"161ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_HSITXCLK" class="sref">PRCMU_HSITXCLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"162
/a>n"163ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_scalable" class="sref">clk_reg_prcmu_scalable
/a>(
spa3 class="string">"hsirxclk"NULL
/a>,"
a href="+code=PRCMU_HSIRXCLK" class="sref">PRCMU_HSIRXCLK
/a>,"0,1"164ala>                                
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATEala>);n"165ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_HSIRXCLK" class="sref">PRCMU_HSIRXCLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"166
/a>n"167ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_scalable" class="sref">clk_reg_prcmu_scalable
/a>(
spa3 class="string">"hdmiclk"NULL
/a>,"
a href="+code=PRCMU_HDMICLK" class="sref">PRCMU_HDMICLK
/a>,"0,1"168ala>                                
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATEala>);n"169ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_HDMICLK" class="sref">PRCMU_HDMICLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"170
/a>n"171ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"apeatclk"NULL
/a>,"
a href="+code=PRCMU_APEATCLK" class="sref">PRCMU_APEATCLK
/a>,"0);n"172ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_APEATCLK" class="sref">PRCMU_APEATCLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"173
/a>n"174ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_scalable" class="sref">clk_reg_prcmu_scalable
/a>(
spa3 class="string">"apetraceclk"NULL
/a>,"
a href="+code=PRCMU_APETRACECLK" class="sref">PRCMU_APETRACECLK
/a>,"0,1"175ala>                                
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATEala>);n"176ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_APETRACECLK" class="sref">PRCMU_APETRACECLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"177
/a>n"178ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"mcdeclk"NULL
/a>,"
a href="+code=PRCMU_MCDECLK" class="sref">PRCMU_MCDECLK
/a>,"0);n"179ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_MCDECLK" class="sref">PRCMU_MCDECLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"180
/a>n"181ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_opp_gate" class="sref">clk_reg_prcmu_opp_gate
/a>(
spa3 class="string">"ipi2cclk"NULL
/a>,"
a href="+code=PRCMU_IPI2CCLK" class="sref">PRCMU_IPI2CCLK
/a>,"0);n"182ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_IPI2CCLK" class="sref">PRCMU_IPI2CCLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"183
/a>n"184ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"dsialtclk"NULL
/a>,"
a href="+code=PRCMU_DSIALTCLK" class="sref">PRCMU_DSIALTCLK
/a>,"0);n"185ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_DSIALTCLK" class="sref">PRCMU_DSIALTCLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"186
/a>n"187ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"dmaclk"NULL
/a>,"
a href="+code=PRCMU_DMACLK" class="sref">PRCMU_DMACLK
/a>,"0);n"188ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_DMACLK" class="sref">PRCMU_DMACLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"189
/a>n"190ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"b2r2clk"NULL
/a>,"
a href="+code=PRCMU_B2R2CLK" class="sref">PRCMU_B2R2CLK
/a>,"0);n"191ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_B2R2CLK" class="sref">PRCMU_B2R2CLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"192
/a>n"193ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_scalable" class="sref">clk_reg_prcmu_scalable
/a>(
spa3 class="string">"tvclk"NULL
/a>,"
a href="+code=PRCMU_TVCLK" class="sref">PRCMU_TVCLK
/a>,"0,1"194ala>                                
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATEala>);n"195ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_TVCLK" class="sref">PRCMU_TVCLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"196
/a>n"197ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"sspclk"NULL
/a>,"
a href="+code=PRCMU_SSPCLK" class="sref">PRCMU_SSPCLK
/a>,"0);n"198ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_SSPCLK" class="sref">PRCMU_SSPCLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"199
/a>n"200ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"rngclk"NULL
/a>,"
a href="+code=PRCMU_RNGCLK" class="sref">PRCMU_RNGCLK
/a>,"0);n"201ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_RNGCLK" class="sref">PRCMU_RNGCLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"202
/a>n"203ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"uiccclk"NULL
/a>,"
a href="+code=PRCMU_UICCCLK" class="sref">PRCMU_UICCCLK
/a>,"0);n"204ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_UICCCLK" class="sref">PRCMU_UICCCLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"205
/a>n"206ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_gate" class="sref">clk_reg_prcmu_gate
/a>(
spa3 class="string">"timclk"NULL
/a>,"
a href="+code=PRCMU_TIMCLK" class="sref">PRCMU_TIMCLK
/a>,"0);n"207ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_TIMCLK" class="sref">PRCMU_TIMCLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"208
/a>n"209ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_opp_volt_scalable" class="sref">clk_reg_prcmu_opp_volt_scalable
/a>(
spa3 class="string">"sdmmcclk"NULL
/a>,"
a href="+code=PRCMU_SDMMCCLK" class="sref">PRCMU_SDMMCCLK
/a>,n"210ala>                                        100000000,"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATEala>);n"211ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_SDMMCCLK" class="sref">PRCMU_SDMMCCLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"212
/a>n"213ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_scalable" class="sref">clk_reg_prcmu_scalable
/a>(
spa3 class="string">"dsi_pll""hdmiclk""214ala>                                
a href="+code=PRCMU_PLLDSI" class="sref">PRCMU_PLLDSI
/a>,"0,"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATEala>);n"215ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_PLLDSI" class="sref">PRCMU_PLLDSI
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"216
/a>n"217ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_scalable" class="sref">clk_reg_prcmu_scalable
/a>(
spa3 class="string">"dsi0clk""dsi_pll""218ala>                                
a href="+code=PRCMU_DSI0CLK" class="sref">PRCMU_DSI0CLK
/a>,"0,"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATEala>);n"219ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_DSI0CLK" class="sref">PRCMU_DSI0CLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"220
/a>n"221ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_scalable" class="sref">clk_reg_prcmu_scalable
/a>(
spa3 class="string">"dsi1clk""dsi_pll""222ala>                                
a href="+code=PRCMU_DSI1CLK" class="sref">PRCMU_DSI1CLK
/a>,"0,"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATEala>);n"223ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_DSI1CLK" class="sref">PRCMU_DSI1CLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"224ala>n"225ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_scalable" class="sref">clk_reg_prcmu_scalable
/a>(
spa3 class="string">"dsi0escclk""tvclk""226ala>                                
a href="+code=PRCMU_DSI0ESCCLK" class="sref">PRCMU_DSI0ESCCLK
/a>,"0,"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATEala>);n"227ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_DSI0ESCCLK" class="sref">PRCMU_DSI0ESCCLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"228
/a>n"229ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_scalable" class="sref">clk_reg_prcmu_scalable
/a>(
spa3 class="string">"dsi1escclk""tvclk""230ala>                                
a href="+code=PRCMU_DSI1ESCCLK" class="sref">PRCMU_DSI1ESCCLK
/a>,"0,"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATEala>);n"231ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_DSI1ESCCLK" class="sref">PRCMU_DSI1ESCCLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"232
/a>n"233ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_scalable" class="sref">clk_reg_prcmu_scalable
/a>(
spa3 class="string">"dsi2escclk""tvclk""234ala>                                
a href="+code=PRCMU_DSI2ESCCLK" class="sref">PRCMU_DSI2ESCCLK
/a>,"0,"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATEala>);n"235ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_DSI2ESCCLK" class="sref">PRCMU_DSI2ESCCLK
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"236
/a>n"237ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcmu_scalable_rate" class="sref">clk_reg_prcmu_scalable_rate
/a>(
spa3 class="string">"armss"NULL
/a>,n"238ala>                                
a href="+code=PRCMU_ARMSS" class="sref">PRCMU_ARMSS
/a>,"0,"
a href="+code=CLK_IGNORE_UNUSED" class="sref">CLK_IGNORE_UNUSEDala>);n"239ala>        
a href="+code=prcmu_clk" class="sref">prcmu_clk
/a>[
a href="+code=PRCMU_ARMSS" class="sref">PRCMU_ARMSS
/a>] = 
a href="+code=clk" class="sref">clk
/a>;n"240
/a>n"241ala>        
a href="+code=twd_clk" class="sref">twd_clk
/a> = 
a href="+code=clk_register_fixed_factor" class="sref">clk_register_fixed_factor
/a>(
a href="+code=NULL" class="sref">NULL
/a>,"
spa3 class="string">"smp_twd""armss""242ala>                                
a href="+code=CLK_IGNORE_UNUSED" class="sref">CLK_IGNORE_UNUSEDala>, 1, 2);n"243
/a>n"244ala>        
spa3 class="comment">/*"245
/a>
spa3 class="comment">         * FIXME: Add special handled PRCMU clocks here:"246ala>
spa3 class="comment">         * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl."247ala>
spa3 class="comment">         * 2. ab9540_clkout1yuv, see clkout0yuv"248
/a>
spa3 class="comment">         */"249
/a>n"250ala>        
spa3 class="comment">/* PRCC P-clocks */"251ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p1_pclk0""per1clk"bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>],n"252ala>                                
a href="+code=BIT" class="sref">BIT
/a>(0),"0);n"253ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1, 0);n"254ala>n"255ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p1_pclk1""per1clk"bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>],n"256ala>                                
a href="+code=BIT" class="sref">BIT
/a>(1),"0);n"257ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1, 1);n"258
/a>n"259ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p1_pclk2""per1clk"bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>],n"260ala>                                
a href="+code=BIT" class="sref">BIT
/a>(2),"0);n"261ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1, 2);n"262
/a>n"263ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p1_pclk3""per1clk"bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>],n"264ala>                                
a href="+code=BIT" class="sref">BIT
/a>(3),"0);n"265ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1, 3);n"266
/a>n"267ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p1_pclk4""per1clk"bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>],n"268ala>                                
a href="+code=BIT" class="sref">BIT
/a>(4),"0);n"269ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1, 4);n"270
/a>n"271ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p1_pclk5""per1clk"bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>],n"272ala>                                
a href="+code=BIT" class="sref">BIT
/a>(5),"0);n"273ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1, 5);n"274ala>n"275ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p1_pclk6""per1clk"bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>],n"276ala>                                
a href="+code=BIT" class="sref">BIT
/a>(6),"0);n"277ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1, 6);n"278
/a>n"279ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p1_pclk7""per1clk"bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>],n"280ala>                                
a href="+code=BIT" class="sref">BIT
/a>(7),"0);n"281ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1, 7);n"282
/a>n"283ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p1_pclk8""per1clk"bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>],n"284ala>                                
a href="+code=BIT" class="sref">BIT
/a>(8),"0);n"285ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1, 8);n"286
/a>n"287ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p1_pclk9""per1clk"bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>],n"288ala>                                
a href="+code=BIT" class="sref">BIT
/a>(9),"0);n"289ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1, 9);n"290
/a>n"291ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p1_pclk10""per1clk"bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>],n"292ala>                                
a href="+code=BIT" class="sref">BIT
/a>(10),"0);n"293ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1, 10);n"294ala>n"295ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p1_pclk11""per1clk"bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>],n"296ala>                                
a href="+code=BIT" class="sref">BIT
/a>(11),"0);n"297ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1, 11);n"298
/a>n"299ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p2_pclk0""per2clk"bases
/a>[
a href="+code=CLKRST2_INDEX" class="sref">CLKRST2_INDEX
/a>],n"300ala>                                
a href="+code=BIT" class="sref">BIT
/a>(0),"0);n"301ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 2,"0);n"302
/a>n"303ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p2_pclk1""per2clk"bases
/a>[
a href="+code=CLKRST2_INDEX" class="sref">CLKRST2_INDEX
/a>],n"304ala>                                
a href="+code=BIT" class="sref">BIT
/a>(1),"0);n"305ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 2, 1);n"306
/a>n"307ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p2_pclk2""per2clk"bases
/a>[
a href="+code=CLKRST2_INDEX" class="sref">CLKRST2_INDEX
/a>],n"308ala>                                
a href="+code=BIT" class="sref">BIT
/a>(2),"0);n"309ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 2, 2);n"310
/a>n"311ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p2_pclk3""per2clk"bases
/a>[
a href="+code=CLKRST2_INDEX" class="sref">CLKRST2_INDEX
/a>],n"312ala>                                
a href="+code=BIT" class="sref">BIT
/a>(3),"0);n"313ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 2, 3);n"314ala>n"315ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p2_pclk4""per2clk"bases
/a>[
a href="+code=CLKRST2_INDEX" class="sref">CLKRST2_INDEX
/a>],n"316ala>                                
a href="+code=BIT" class="sref">BIT
/a>(4),"0);n"317ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 2, 4);n"318
/a>n"319ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p2_pclk5""per2clk"bases
/a>[
a href="+code=CLKRST2_INDEX" class="sref">CLKRST2_INDEX
/a>],n"320ala>                                
a href="+code=BIT" class="sref">BIT
/a>(5),"0);n"321ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 2, 5);n"322
/a>n"323ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p2_pclk6""per2clk"bases
/a>[
a href="+code=CLKRST2_INDEX" class="sref">CLKRST2_INDEX
/a>],n"324ala>                                
a href="+code=BIT" class="sref">BIT
/a>(6),"0);n"325ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 2, 6);n"326
/a>n"327ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p2_pclk7""per2clk"bases
/a>[
a href="+code=CLKRST2_INDEX" class="sref">CLKRST2_INDEX
/a>],n"328ala>                                
a href="+code=BIT" class="sref">BIT
/a>(7),"0);n"329ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 2, 7);n"330
/a>n"331ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p2_pclk8""per2clk"bases
/a>[
a href="+code=CLKRST2_INDEX" class="sref">CLKRST2_INDEX
/a>],n"332ala>                                
a href="+code=BIT" class="sref">BIT
/a>(8),"0);n"333ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 2, 8);n"334ala>n"335ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p2_pclk9""per2clk"bases
/a>[
a href="+code=CLKRST2_INDEX" class="sref">CLKRST2_INDEX
/a>],n"336ala>                                
a href="+code=BIT" class="sref">BIT
/a>(9),"0);n"337ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 2, 9);n"338
/a>n"339ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p2_pclk10""per2clk"bases
/a>[
a href="+code=CLKRST2_INDEX" class="sref">CLKRST2_INDEX
/a>],n"340ala>                                
a href="+code=BIT" class="sref">BIT
/a>(10),"0);n"341ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 2, 10);n"342
/a>n"343ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p2_pclk11""per2clk"bases
/a>[
a href="+code=CLKRST2_INDEX" class="sref">CLKRST2_INDEX
/a>],n"344ala>                                
a href="+code=BIT" class="sref">BIT
/a>(11),"0);n"345ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 2, 11);n"346
/a>n"347ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p2_pclk12""per2clk"bases
/a>[
a href="+code=CLKRST2_INDEX" class="sref">CLKRST2_INDEX
/a>],n"348ala>                                
a href="+code=BIT" class="sref">BIT
/a>(12),"0);n"349ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 2, 12);n"350
/a>n"351ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p3_pclk0""per3clk"bases
/a>[
a href="+code=CLKRST3_INDEX" class="sref">CLKRST3_INDEX
/a>],n"352ala>                                
a href="+code=BIT" class="sref">BIT
/a>(0),"0);n"353ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 3,"0);n"354ala>n"355ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p3_pclk1""per3clk"bases
/a>[
a href="+code=CLKRST3_INDEX" class="sref">CLKRST3_INDEX
/a>],n"356ala>                                
a href="+code=BIT" class="sref">BIT
/a>(1),"0);n"357ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 3, 1);n"358
/a>n"359ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p3_pclk2""per3clk"bases
/a>[
a href="+code=CLKRST3_INDEX" class="sref">CLKRST3_INDEX
/a>],n"360ala>                                
a href="+code=BIT" class="sref">BIT
/a>(2),"0);n"361ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 3, 2);n"362
/a>n"363ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p3_pclk3""per3clk"bases
/a>[
a href="+code=CLKRST3_INDEX" class="sref">CLKRST3_INDEX
/a>],n"364ala>                                
a href="+code=BIT" class="sref">BIT
/a>(3),"0);n"365ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 3, 3);n"366
/a>n"367ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p3_pclk4""per3clk"bases
/a>[
a href="+code=CLKRST3_INDEX" class="sref">CLKRST3_INDEX
/a>],n"368ala>                                
a href="+code=BIT" class="sref">BIT
/a>(4),"0);n"369ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 3, 4);n"370
/a>n"371ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p3_pclk5""per3clk"bases
/a>[
a href="+code=CLKRST3_INDEX" class="sref">CLKRST3_INDEX
/a>],n"372ala>                                
a href="+code=BIT" class="sref">BIT
/a>(5),"0);n"373ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 3, 5);n"374ala>n"375ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p3_pclk6""per3clk"bases
/a>[
a href="+code=CLKRST3_INDEX" class="sref">CLKRST3_INDEX
/a>],n"376ala>                                
a href="+code=BIT" class="sref">BIT
/a>(6),"0);n"377ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 3, 6);n"378
/a>n"379ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p3_pclk7""per3clk"bases
/a>[
a href="+code=CLKRST3_INDEX" class="sref">CLKRST3_INDEX
/a>],n"380ala>                                
a href="+code=BIT" class="sref">BIT
/a>(7),"0);n"381ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 3, 7);n"382
/a>n"383ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p3_pclk8""per3clk"bases
/a>[
a href="+code=CLKRST3_INDEX" class="sref">CLKRST3_INDEX
/a>],n"384ala>                                
a href="+code=BIT" class="sref">BIT
/a>(8),"0);n"385ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 3, 8);n"386
/a>n"387ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p5_pclk0""per5clk"bases
/a>[
a href="+code=CLKRST5_INDEX" class="sref">CLKRST5_INDEX
/a>],n"388ala>                                
a href="+code=BIT" class="sref">BIT
/a>(0),"0);n"389ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 5,"0);n"390
/a>n"391ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p5_pclk1""per5clk"bases
/a>[
a href="+code=CLKRST5_INDEX" class="sref">CLKRST5_INDEX
/a>],n"392ala>                                
a href="+code=BIT" class="sref">BIT
/a>(1),"0);n"393ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 5, 1);n"394ala>n"395ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p6_pclk0""per6clk"bases
/a>[
a href="+code=CLKRST6_INDEX" class="sref">CLKRST6_INDEX
/a>],n"396ala>                                
a href="+code=BIT" class="sref">BIT
/a>(0),"0);n"397ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 6,"0);n"398
/a>n"399ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p6_pclk1""per6clk"bases
/a>[
a href="+code=CLKRST6_INDEX" class="sref">CLKRST6_INDEX
/a>],n"400ala>                                
a href="+code=BIT" class="sref">BIT
/a>(1),"0);n"401ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 6, 1);n"402
/a>n"403ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p6_pclk2""per6clk"bases
/a>[
a href="+code=CLKRST6_INDEX" class="sref">CLKRST6_INDEX
/a>],n"404ala>                                
a href="+code=BIT" class="sref">BIT
/a>(2),"0);n"405ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 6, 2);n"406
/a>n"407ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p6_pclk3""per6clk"bases
/a>[
a href="+code=CLKRST6_INDEX" class="sref">CLKRST6_INDEX
/a>],n"408ala>                                
a href="+code=BIT" class="sref">BIT
/a>(3),"0);n"409ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 6, 3);n"410
/a>n"411ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p6_pclk4""per6clk"bases
/a>[
a href="+code=CLKRST6_INDEX" class="sref">CLKRST6_INDEX
/a>],n"412ala>                                
a href="+code=BIT" class="sref">BIT
/a>(4),"0);n"413ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 6, 4);n"414ala>n"415ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p6_pclk5""per6clk"bases
/a>[
a href="+code=CLKRST6_INDEX" class="sref">CLKRST6_INDEX
/a>],n"416ala>                                
a href="+code=BIT" class="sref">BIT
/a>(5),"0);n"417ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 6, 5);n"418
/a>n"419ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p6_pclk6""per6clk"bases
/a>[
a href="+code=CLKRST6_INDEX" class="sref">CLKRST6_INDEX
/a>],n"420ala>                                
a href="+code=BIT" class="sref">BIT
/a>(6),"0);n"421ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 6, 6);n"422
/a>n"423ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_pclk" class="sref">clk_reg_prcc_pclk
/a>(
spa3 class="string">"p6_pclk7""per6clk"bases
/a>[
a href="+code=CLKRST6_INDEX" class="sref">CLKRST6_INDEX
/a>],n"424ala>                                
a href="+code=BIT" class="sref">BIT
/a>(7),"0);n"425ala>        
a href="+code=PRCC_PCLK_STORE" class="sref">PRCC_PCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 6, 7);n"426
/a>n"427ala>        
spa3 class="comment">/* PRCC K-clocks"428ala>
spa3 class="comment">         *"429ala>
spa3 class="comment">         * FIXME: Some drivers requires PERPIH[n| to be automatically enabled"430
/a>
spa3 class="comment">         * by enabling just the K-clock, even if it is not a valid parent to"431ala>
spa3 class="comment">         * the K-clock. Until drivers get fixed we might need some kind of"432ala>
spa3 class="comment">         * "parent muxed join"."433ala>
spa3 class="comment">         */"434ala>n"435ala>        
spa3 class="comment">/* Periph1 */"436ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p1_uart0_kclk""uartclk""437ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(0),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"438ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1,"0);n"439ala>n"440ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p1_uart1_kclk""uartclk""441ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(1),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"442ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1,"1);n"443ala>n"444ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p1_i2c1_kclk""i2cclk""445ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(2),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"446ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1,"2);n"447ala>n"448ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p1_msp0_kclk""msp02clk""449ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(3),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"450ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1,"3);n"451ala>n"452ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p1_msp1_kclk""msp1clk""453ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(4),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"454ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1,"4);n"455ala>n"456ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p1_sdi0_kclk""sdmmcclk""457ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(5),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"458ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1,"5);n"459ala>n"460ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p1_i2c2_kclk""i2cclk""461ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(6),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"462ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1,"6);n"463ala>n"464ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p1_slimbus0_kclk""slimclk""465ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(8),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"466ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1,"8);n"467ala>n"468ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p1_i2c4_kclk""i2cclk""469ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(9),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"470ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1,"9);n"471ala>n"472ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p1_msp3_kclk""msp1clk""473ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST1_INDEX" class="sref">CLKRST1_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(10),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"474ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 1,"10);n"475ala>n"476ala>        
spa3 class="comment">/* Periph2 */"477ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p2_i2c3_kclk""i2cclk""478ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST2_INDEX" class="sref">CLKRST2_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(0),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"479ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 2,"0);n"480
/a>n"481ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p2_sdi4_kclk""sdmmcclk""482ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST2_INDEX" class="sref">CLKRST2_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(2),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"483ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 2,"2);n"484ala>n"485ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p2_msp2_kclk""msp02clk""486ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST2_INDEX" class="sref">CLKRST2_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(3),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"487ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 2,"3);n"488
/a>n"489ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p2_sdi1_kclk""sdmmcclk""490ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST2_INDEX" class="sref">CLKRST2_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(4),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"491ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 2,"4);n"492
/a>n"493ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p2_sdi3_kclk""sdmmcclk""494ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST2_INDEX" class="sref">CLKRST2_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(5),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"495ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 2,"5);n"496
/a>n"497ala>        
spa3 class="comment">/* Note that rate is received from parent. */"498ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p2_ssirx_kclk""hsirxclk""499ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST2_INDEX" class="sref">CLKRST2_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(6),n"500ala>                        
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>|
a href="+code=CLK_SET_RATE_PARENT" class="sref">CLK_SET_RATE_PARENT
/a>);n"501ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 2,"6);n"502
/a>n"503ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p2_ssitx_kclk""hsitxclk""504ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST2_INDEX" class="sref">CLKRST2_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(7),n"505ala>                        
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>|
a href="+code=CLK_SET_RATE_PARENT" class="sref">CLK_SET_RATE_PARENT
/a>);n"506ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 2, 7);n"507ala>n"508ala>        
spa3 class="comment">/* Periph3 */"509ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p3_ssp0_kclk""sspclk""510ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST3_INDEX" class="sref">CLKRST3_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(1),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"511ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 3,"1);n"512
/a>n"513ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p3_ssp1_kclk""sspclk""514ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST3_INDEX" class="sref">CLKRST3_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(2),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"515ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 3,"2);n"516
/a>n"517ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p3_i2c0_kclk""i2cclk""518ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST3_INDEX" class="sref">CLKRST3_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(3),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"519ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 3,"3);n"520
/a>n"521ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p3_sdi2_kclk""sdmmcclk""522ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST3_INDEX" class="sref">CLKRST3_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(4),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"523ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 3,"4);n"524ala>n"525ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p3_ske_kclk""rtc32k""526ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST3_INDEX" class="sref">CLKRST3_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(5),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"527ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 3,"5);n"528
/a>n"529ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p3_uart2_kclk""uartclk""530ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST3_INDEX" class="sref">CLKRST3_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(6),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"531ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 3,"6);n"532
/a>n"533ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p3_sdi5_kclk""sdmmcclk""534ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST3_INDEX" class="sref">CLKRST3_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(7),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"535ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 3,"7);n"536
/a>n"537ala>        
spa3 class="comment">/* Periph6 */"538ala>        
a href="+code=clk" class="sref">clk
/a> = 
a href="+code=clk_reg_prcc_kclk" class="sref">clk_reg_prcc_kclk
/a>(
spa3 class="string">"p3_rng_kclk""rngclk""539ala>                        
a href="+code=bases" class="sref">bases
/a>[
a href="+code=CLKRST6_INDEX" class="sref">CLKRST6_INDEX
/a>], 
a href="+code=BIT" class="sref">BIT
/a>(0),"
a href="+code=CLK_SET_RATE_GATE" class="sref">CLK_SET_RATE_GATE
/a>);n"540ala>        
a href="+code=PRCC_KCLK_STORE" class="sref">PRCC_KCLK_STORE
/a>(
a href="+code=clk" class="sref">clk
/a>, 6,"0);n"541ala>n"542ala>        
a href="+code=for_each_child_of_node" class="sref">for_each_child_of_node
/a>(
a href="+code=np" class="sref">np
/a>, 
a href="+code=child" class="sref">child
/a>) {n"543ala>                static struct 
a href="+code=clk_onecell_data" class="sref">clk_onecell_dataala> 
a href="+code=clk_data" class="sref">clk_dataala>;n"544ala>n"545ala>                if (!
a href="+code=of_node_cmp" class="sref">of_node_cmp
/a>(
a href="+code=child" class="sref">child
/a>->nam4
/a>, 
spa3 class="string">"prcmu-clock""546ala>                        
a href="+code=clk_data" class="sref">clk_dataala>.
a href="+code=clks" class="sref">clks
/a> = 
a href="+code=prcmu_clk" class="sref">prcmu_clkala>;n"547ala>                        
a href="+code=clk_data" class="sref">clk_dataala>.
a href="+code=clk_num" class="sref">clk_num
/a> = 
a href="+code=ARRAY_SIZE" class="sref">ARRAY_SIZE
/a>(
a href="+code=prcmu_clk" class="sref">prcmu_clkala>);n"548ala>                        
a href="+code=of_clk_add_provider" class="sref">of_clk_add_provider
/a>(
a href="+code=child" class="sref">child
/a>, 
a href="+code=of_clk_src_onecell_get" class="sref">of_clk_src_onecell_get
/a>, &clk_dataala>);n"549ala>                }n"550ala>                if (!
a href="+code=of_node_cmp" class="sref">of_node_cmp
/a>(
a href="+code=child" class="sref">child
/a>->nam4
/a>, 
spa3 class="string">"prcc-periph-clock""551ala>                        
a href="+code=of_clk_add_provider" class="sref">of_clk_add_provider
/a>(
a href="+code=child" class="sref">child
/a>, 
a href="+code=ux500_twocell_get" class="sref">ux500_twocell_get
/a>, 
a href="+code=prcc_pclk" class="sref">prcc_pclk
/a>);n"552
/a>n"553ala>                if (!
a href="+code=of_node_cmp" class="sref">of_node_cmp
/a>(
a href="+code=child" class="sref">child
/a>->nam4
/a>, 
spa3 class="string">"prcc-kernel-clock""554ala>                        
a href="+code=of_clk_add_provider" class="sref">of_clk_add_provider
/a>(
a href="+code=child" class="sref">child
/a>, 
a href="+code=ux500_twocell_get" class="sref">ux500_twocell_get
/a>, 
a href="+code=prcc_kclk" class="sref">prcc_kclk
/a>);n"555ala>n"556ala>                if (!
a href="+code=of_node_cmp" class="sref">of_node_cmp
/a>(
a href="+code=child" class="sref">child
/a>->nam4
/a>, 
spa3 class="string">"rtc32k-clock""557ala>                        
a href="+code=of_clk_add_provider" class="sref">of_clk_add_provider
/a>(
a href="+code=child" class="sref">child
/a>, 
a href="+code=of_clk_src_simple_get" class="sref">of_clk_src_simple_get
/a>, 
a href="+code=rtc_clk" class="sref">rtc_clk
/a>);n"558
/a>n"559ala>                if (!
a href="+code=of_node_cmp" class="sref">of_node_cmp
/a>(
a href="+code=child" class="sref">child
/a>->nam4
/a>, 
spa3 class="string">"smp-twd-clock""560ala>                        
a href="+code=of_clk_add_provider" class="sref">of_clk_add_provider
/a>(
a href="+code=child" class="sref">child
/a>, 
a href="+code=of_clk_src_simple_get" class="sref">of_clk_src_simple_get
/a>, 
a href="+code=twd_clk" class="sref">twd_clk
/a>);n"561ala>        }n"562ala>}n"563ala>
a href="+code=CLK_OF_DECLARE" class="sref">CLK_OF_DECLARE
/a>(
a href="+code=u8500_clks" class="sref">u8500_clks
/a>, 
spa3 class="string">"stericsson,u8500-clks"u8500_clk_init
/a>);n"564ala>
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