linux/drivers/clk/ux500/u8500_of_clk.c
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   1/*
   2 * Clock definitions for u8500 platform.
   3 *
   4 * Copyright (C) 2012 ST-Ericsson SA
   5 * Author: Ulf Hansson <ulf.hansson@linaro.org>
   6 *
   7 * License terms: GNU General Public License (GPL) version 2
   8 */
   9
  10#include <linux/of.h>
  11#include <linux/of_address.h>
  12#include <linux/clk-provider.h>
  13#include <linux/mfd/dbx500-prcmu.h>
  14#include <linux/platform_data/clk-ux500.h>
  15#include "clk.h"
  16
  17#define PRCC_NUM_PERIPH_CLUSTERS 6
  18#define PRCC_PERIPHS_PER_CLUSTER 32
  19
  20static struct clk *prcmu_clk[PRCMU_NUM_CLKS];
  21static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
  22static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
  23
  24#define PRCC_SHOW(clk, base, bit) \
  25        clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
  26#define PRCC_PCLK_STORE(clk, base, bit) \
  27        prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
  28#define PRCC_KCLK_STORE(clk, base, bit)        \
  29        prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
  30
  31static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec,
  32                                     void *data)
  33{
  34        struct clk **clk_data = data;
  35        unsigned int base, bit;
  36
  37        if (clkspec->args_count != 2)
  38                return  ERR_PTR(-EINVAL);
  39
  40        base = clkspec->args[0];
  41        bit = clkspec->args[1];
  42
  43        if (base != 1 && base != 2 && base != 3 && base != 5 && base != 6) {
  44                pr_err("%s: invalid PRCC base %d\n", __func__, base);
  45                return ERR_PTR(-EINVAL);
  46        }
  47
  48        return PRCC_SHOW(clk_data, base, bit);
  49}
  50
  51static const struct of_device_id u8500_clk_of_match[] = {
  52        { .compatible = "stericsson,u8500-clks", },
  53        { },
  54};
  55
  56/* CLKRST4 is missing making it hard to index things */
  57enum clkrst_index {
  58        CLKRST1_INDEX = 0,
  59        CLKRST2_INDEX,
  60        CLKRST3_INDEX,
  61        CLKRST5_INDEX,
  62        CLKRST6_INDEX,
  63        CLKRST_MAX,
  64};
  65
  66void u8500_clk_init(void)
  67{
  68        struct prcmu_fw_version *fw_version;
  69        struct device_node *np = NULL;
  70        struct device_node *child = NULL;
  71        const char *sgaclk_parent = NULL;
  72        struct clk *clk, *rtc_clk, *twd_clk;
  73        u32 bases[CLKRST_MAX];
  74        int i;
  75
  76        if (of_have_populated_dt())
  77                np = of_find_matching_node(NULL, u8500_clk_of_match);
  78        if (!np) {
  79                pr_err("Either DT or U8500 Clock node not found\n");
  80                return;
  81        }
  82        for (i = 0; i < ARRAY_SIZE(bases); i++) {
  83                struct resource r;
  84
  85                if (of_address_to_resource(np, i, &r))
  86                        /* Not much choice but to continue */
  87                        pr_err("failed to get CLKRST %d base address\n",
  88                               i + 1);
  89                bases[i] = r.start;
  90        }
  91
  92        /* Clock sources */
  93        clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
  94                                CLK_IGNORE_UNUSED);
  95        prcmu_clk[PRCMU_PLLSOC0] = clk;
  96
  97        clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
  98                                CLK_IGNORE_UNUSED);
  99        prcmu_clk[PRCMU_PLLSOC1] = clk;
 100
 101        clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
 102                                CLK_IGNORE_UNUSED);
 103        prcmu_clk[PRCMU_PLLDDR] = clk;
 104
 105        /* FIXME: Add sys, ulp and int clocks here. */
 106
 107        rtc_clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
 108                                CLK_IGNORE_UNUSED,
 109                                32768);
 110
 111        /* PRCMU clocks */
 112        fw_version = prcmu_get_fw_version();
 113        if (fw_version != NULL) {
 114                switch (fw_version->project) {
 115                case PRCMU_FW_PROJECT_U8500_C2:
 116                case PRCMU_FW_PROJECT_U8520:
 117                case PRCMU_FW_PROJECT_U8420:
 118                        sgaclk_parent = "soc0_pll";
 119                        break;
 120                default:
 121                        break;
 122                }
 123        }
 124
 125        if (sgaclk_parent)
 126                clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
 127                                        PRCMU_SGACLK, 0);
 128        else
 129                clk = clk_reg_prcmu_gate("sgclk", NULL, PRCMU_SGACLK, 0);
 130        prcmu_clk[PRCMU_SGACLK] = clk;
 131
 132        clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, 0);
 133        prcmu_clk[PRCMU_UARTCLK] = clk;
 134
 135        clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, 0);
 136        prcmu_clk[PRCMU_MSP02CLK] = clk;
 137
 138        clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, 0);
 139        prcmu_clk[PRCMU_MSP1CLK] = clk;
 140
 141        clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, 0);
 142        prcmu_clk[PRCMU_I2CCLK] = clk;
 143
 144        clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, 0);
 145        prcmu_clk[PRCMU_SLIMCLK] = clk;
 146
 147        clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, 0);
 148        prcmu_clk[PRCMU_PER1CLK] = clk;
 149
 150        clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, 0);
 151        prcmu_clk[PRCMU_PER2CLK] = clk;
 152
 153        clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, 0);
 154        prcmu_clk[PRCMU_PER3CLK] = clk;
 155
 156        clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, 0);
 157        prcmu_clk[PRCMU_PER5CLK] = clk;
 158
 159        clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, 0);
 160        prcmu_clk[PRCMU_PER6CLK] = clk;
 161
 162        clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, 0);
 163        prcmu_clk[PRCMU_PER7CLK] = clk;
 164
 165        clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
 166                                CLK_SET_RATE_GATE);
 167        prcmu_clk[PRCMU_LCDCLK] = clk;
 168
 169        clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, 0);
 170        prcmu_clk[PRCMU_BMLCLK] = clk;
 171
 172        clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
 173                                CLK_SET_RATE_GATE);
 174        prcmu_clk[PRCMU_HSITXCLK] = clk;
 175
 176        clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
 177                                CLK_SET_RATE_GATE);
 178        prcmu_clk[PRCMU_HSIRXCLK] = clk;
 179
 180        clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
 181                                CLK_SET_RATE_GATE);
 182        prcmu_clk[PRCMU_HDMICLK] = clk;
 183
 184        clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, 0);
 185        prcmu_clk[PRCMU_APEATCLK] = clk;
 186
 187        clk = clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0,
 188                                CLK_SET_RATE_GATE);
 189        prcmu_clk[PRCMU_APETRACECLK] = clk;
 190
 191        clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, 0);
 192        prcmu_clk[PRCMU_MCDECLK] = clk;
 193
 194        clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, 0);
 195        prcmu_clk[PRCMU_IPI2CCLK] = clk;
 196
 197        clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, 0);
 198        prcmu_clk[PRCMU_DSIALTCLK] = clk;
 199
 200        clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, 0);
 201        prcmu_clk[PRCMU_DMACLK] = clk;
 202
 203        clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, 0);
 204        prcmu_clk[PRCMU_B2R2CLK] = clk;
 205
 206        clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
 207                                CLK_SET_RATE_GATE);
 208        prcmu_clk[PRCMU_TVCLK] = clk;
 209
 210        clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, 0);
 211        prcmu_clk[PRCMU_SSPCLK] = clk;
 212
 213        clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, 0);
 214        prcmu_clk[PRCMU_RNGCLK] = clk;
 215
 216        clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, 0);
 217        prcmu_clk[PRCMU_UICCCLK] = clk;
 218
 219        clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0);
 220        prcmu_clk[PRCMU_TIMCLK] = clk;
 221
 222        clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
 223                                        100000000, CLK_SET_RATE_GATE);
 224        prcmu_clk[PRCMU_SDMMCCLK] = clk;
 225
 226        clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
 227                                PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
 228        prcmu_clk[PRCMU_PLLDSI] = clk;
 229
 230        clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
 231                                PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
 232        prcmu_clk[PRCMU_DSI0CLK] = clk;
 233
 234        clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
 235                                PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
 236        prcmu_clk[PRCMU_DSI1CLK] = clk;
 237
 238        clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
 239                                PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
 240        prcmu_clk[PRCMU_DSI0ESCCLK] = clk;
 241
 242        clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
 243                                PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
 244        prcmu_clk[PRCMU_DSI1ESCCLK] = clk;
 245
 246        clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
 247                                PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
 248        prcmu_clk[PRCMU_DSI2ESCCLK] = clk;
 249
 250        clk = clk_reg_prcmu_scalable_rate("armss", NULL,
 251                                PRCMU_ARMSS, 0, CLK_IGNORE_UNUSED);
 252        prcmu_clk[PRCMU_ARMSS] = clk;
 253
 254        twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
 255                                CLK_IGNORE_UNUSED, 1, 2);
 256
 257        /*
 258         * FIXME: Add special handled PRCMU clocks here:
 259         * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
 260         * 2. ab9540_clkout1yuv, see clkout0yuv
 261         */
 262
 263        /* PRCC P-clocks */
 264        clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX],
 265                                BIT(0), 0);
 266        PRCC_PCLK_STORE(clk, 1, 0);
 267
 268        clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX],
 269                                BIT(1), 0);
 270        PRCC_PCLK_STORE(clk, 1, 1);
 271
 272        clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX],
 273                                BIT(2), 0);
 274        PRCC_PCLK_STORE(clk, 1, 2);
 275
 276        clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX],
 277                                BIT(3), 0);
 278        PRCC_PCLK_STORE(clk, 1, 3);
 279
 280        clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX],
 281                                BIT(4), 0);
 282        PRCC_PCLK_STORE(clk, 1, 4);
 283
 284        clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX],
 285                                BIT(5), 0);
 286        PRCC_PCLK_STORE(clk, 1, 5);
 287
 288        clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX],
 289                                BIT(6), 0);
 290        PRCC_PCLK_STORE(clk, 1, 6);
 291
 292        clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX],
 293                                BIT(7), 0);
 294        PRCC_PCLK_STORE(clk, 1, 7);
 295
 296        clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX],
 297                                BIT(8), 0);
 298        PRCC_PCLK_STORE(clk, 1, 8);
 299
 300        clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX],
 301                                BIT(9), 0);
 302        PRCC_PCLK_STORE(clk, 1, 9);
 303
 304        clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX],
 305                                BIT(10), 0);
 306        PRCC_PCLK_STORE(clk, 1, 10);
 307
 308        clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX],
 309                                BIT(11), 0);
 310        PRCC_PCLK_STORE(clk, 1, 11);
 311
 312        clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX],
 313                                BIT(0), 0);
 314        PRCC_PCLK_STORE(clk, 2, 0);
 315
 316        clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX],
 317                                BIT(1), 0);
 318        PRCC_PCLK_STORE(clk, 2, 1);
 319
 320        clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX],
 321                                BIT(2), 0);
 322        PRCC_PCLK_STORE(clk, 2, 2);
 323
 324        clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX],
 325                                BIT(3), 0);
 326        PRCC_PCLK_STORE(clk, 2, 3);
 327
 328        clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX],
 329                                BIT(4), 0);
 330        PRCC_PCLK_STORE(clk, 2, 4);
 331
 332        clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX],
 333                                BIT(5), 0);
 334        PRCC_PCLK_STORE(clk, 2, 5);
 335
 336        clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX],
 337                                BIT(6), 0);
 338        PRCC_PCLK_STORE(clk, 2, 6);
 339
 340        clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX],
 341                                BIT(7), 0);
 342        PRCC_PCLK_STORE(clk, 2, 7);
 343
 344        clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX],
 345                                BIT(8), 0);
 346        PRCC_PCLK_STORE(clk, 2, 8);
 347
 348        clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX],
 349                                BIT(9), 0);
 350        PRCC_PCLK_STORE(clk, 2, 9);
 351
 352        clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX],
 353                                BIT(10), 0);
 354        PRCC_PCLK_STORE(clk, 2, 10);
 355
 356        clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX],
 357                                BIT(11), 0);
 358        PRCC_PCLK_STORE(clk, 2, 11);
 359
 360        clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX],
 361                                BIT(12), 0);
 362        PRCC_PCLK_STORE(clk, 2, 12);
 363
 364        clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX],
 365                                BIT(0), 0);
 366        PRCC_PCLK_STORE(clk, 3, 0);
 367
 368        clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX],
 369                                BIT(1), 0);
 370        PRCC_PCLK_STORE(clk, 3, 1);
 371
 372        clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX],
 373                                BIT(2), 0);
 374        PRCC_PCLK_STORE(clk, 3, 2);
 375
 376        clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX],
 377                                BIT(3), 0);
 378        PRCC_PCLK_STORE(clk, 3, 3);
 379
 380        clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX],
 381                                BIT(4), 0);
 382        PRCC_PCLK_STORE(clk, 3, 4);
 383
 384        clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX],
 385                                BIT(5), 0);
 386        PRCC_PCLK_STORE(clk, 3, 5);
 387
 388        clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX],
 389                                BIT(6), 0);
 390        PRCC_PCLK_STORE(clk, 3, 6);
 391
 392        clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX],
 393                                BIT(7), 0);
 394        PRCC_PCLK_STORE(clk, 3, 7);
 395
 396        clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX],
 397                                BIT(8), 0);
 398        PRCC_PCLK_STORE(clk, 3, 8);
 399
 400        clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX],
 401                                BIT(0), 0);
 402        PRCC_PCLK_STORE(clk, 5, 0);
 403
 404        clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX],
 405                                BIT(1), 0);
 406        PRCC_PCLK_STORE(clk, 5, 1);
 407
 408        clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX],
 409                                BIT(0), 0);
 410        PRCC_PCLK_STORE(clk, 6, 0);
 411
 412        clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX],
 413                                BIT(1), 0);
 414        PRCC_PCLK_STORE(clk, 6, 1);
 415
 416        clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX],
 417                                BIT(2), 0);
 418        PRCC_PCLK_STORE(clk, 6, 2);
 419
 420        clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX],
 421                                BIT(3), 0);
 422        PRCC_PCLK_STORE(clk, 6, 3);
 423
 424        clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX],
 425                                BIT(4), 0);
 426        PRCC_PCLK_STORE(clk, 6, 4);
 427
 428        clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX],
 429                                BIT(5), 0);
 430        PRCC_PCLK_STORE(clk, 6, 5);
 431
 432        clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX],
 433                                BIT(6), 0);
 434        PRCC_PCLK_STORE(clk, 6, 6);
 435
 436        clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX],
 437                                BIT(7), 0);
 438        PRCC_PCLK_STORE(clk, 6, 7);
 439
 440        /* PRCC K-clocks
 441         *
 442         * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
 443         * by enabling just the K-clock, even if it is not a valid parent to
 444         * the K-clock. Until drivers get fixed we might need some kind of
 445         * "parent muxed join".
 446         */
 447
 448        /* Periph1 */
 449        clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
 450                        bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE);
 451        PRCC_KCLK_STORE(clk, 1, 0);
 452
 453        clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
 454                        bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE);
 455        PRCC_KCLK_STORE(clk, 1, 1);
 456
 457        clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
 458                        bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE);
 459        PRCC_KCLK_STORE(clk, 1, 2);
 460
 461        clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
 462                        bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE);
 463        PRCC_KCLK_STORE(clk, 1, 3);
 464
 465        clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
 466                        bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE);
 467        PRCC_KCLK_STORE(clk, 1, 4);
 468
 469        clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
 470                        bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE);
 471        PRCC_KCLK_STORE(clk, 1, 5);
 472
 473        clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
 474                        bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE);
 475        PRCC_KCLK_STORE(clk, 1, 6);
 476
 477        clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
 478                        bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE);
 479        PRCC_KCLK_STORE(clk, 1, 8);
 480
 481        clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
 482                        bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE);
 483        PRCC_KCLK_STORE(clk, 1, 9);
 484
 485        clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
 486                        bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE);
 487        PRCC_KCLK_STORE(clk, 1, 10);
 488
 489        /* Periph2 */
 490        clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
 491                        bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE);
 492        PRCC_KCLK_STORE(clk, 2, 0);
 493
 494        clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
 495                        bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE);
 496        PRCC_KCLK_STORE(clk, 2, 2);
 497
 498        clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
 499                        bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE);
 500        PRCC_KCLK_STORE(clk, 2, 3);
 501
 502        clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
 503                        bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE);
 504        PRCC_KCLK_STORE(clk, 2, 4);
 505
 506        clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
 507                        bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE);
 508        PRCC_KCLK_STORE(clk, 2, 5);
 509
 510        /* Note that rate is received from parent. */
 511        clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
 512                        bases[CLKRST2_INDEX], BIT(6),
 513                        CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
 514        PRCC_KCLK_STORE(clk, 2, 6);
 515
 516        clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
 517                        bases[CLKRST2_INDEX], BIT(7),
 518                        CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
 519        PRCC_KCLK_STORE(clk, 2, 7);
 520
 521        /* Periph3 */
 522        clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
 523                        bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE);
 524        PRCC_KCLK_STORE(clk, 3, 1);
 525
 526        clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
 527                        bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE);
 528        PRCC_KCLK_STORE(clk, 3, 2);
 529
 530        clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
 531                        bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE);
 532        PRCC_KCLK_STORE(clk, 3, 3);
 533
 534        clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
 535                        bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE);
 536        PRCC_KCLK_STORE(clk, 3, 4);
 537
 538        clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
 539                        bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE);
 540        PRCC_KCLK_STORE(clk, 3, 5);
 541
 542        clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
 543                        bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE);
 544        PRCC_KCLK_STORE(clk, 3, 6);
 545
 546        clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
 547                        bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE);
 548        PRCC_KCLK_STORE(clk, 3, 7);
 549
 550        /* Periph6 */
 551        clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
 552                        bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE);
 553        PRCC_KCLK_STORE(clk, 6, 0);
 554
 555        for_each_child_of_node(np, child) {
 556                static struct clk_onecell_data clk_data;
 557
 558                if (!of_node_cmp(child->name, "prcmu-clock")) {
 559                        clk_data.clks = prcmu_clk;
 560                        clk_data.clk_num = ARRAY_SIZE(prcmu_clk);
 561                        of_clk_add_provider(child, of_clk_src_onecell_get, &clk_data);
 562                }
 563                if (!of_node_cmp(child->name, "prcc-periph-clock"))
 564                        of_clk_add_provider(child, ux500_twocell_get, prcc_pclk);
 565
 566                if (!of_node_cmp(child->name, "prcc-kernel-clock"))
 567                        of_clk_add_provider(child, ux500_twocell_get, prcc_kclk);
 568
 569                if (!of_node_cmp(child->name, "rtc32k-clock"))
 570                        of_clk_add_provider(child, of_clk_src_simple_get, rtc_clk);
 571
 572                if (!of_node_cmp(child->name, "smp-twd-clock"))
 573                        of_clk_add_provider(child, of_clk_src_simple_get, twd_clk);
 574        }
 575}
 576
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