linux/drivers/clk/samsung/clk-exynos-audss.c
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   1/*
   2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   3 * Author: Padmavathi Venna <padma.v@samsung.com>
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License version 2 as
   7 * published by the Free Software Foundation.
   8 *
   9 * Common Clock Framework support for Audio Subsystem Clock Controller.
  10*/
  11
  12#include <linux/slab.h>
  13#include <linux/io.h>
  14#include <linux/clk.h>
  15#include <linux/clk-provider.h>
  16#include <linux/of_address.h>
  17#include <linux/of_device.h>
  18#include <linux/syscore_ops.h>
  19#include <linux/module.h>
  20#include <linux/platform_device.h>
  21
  22#include <dt-bindings/clock/exynos-audss-clk.h>
  23
  24static DEFINE_SPINLOCK(lock);
  25static struct clk **clk_table;
  26static void __iomem *reg_base;
  27static struct clk_onecell_data clk_data;
  28/*
  29 * On Exynos5420 this will be a clock which has to be enabled before any
  30 * access to audss registers. Typically a child of EPLL.
  31 *
  32 * On other platforms this will be -ENODEV.
  33 */
  34static struct clk *epll;
  35
  36#define ASS_CLK_SRC 0x0
  37#define ASS_CLK_DIV 0x4
  38#define ASS_CLK_GATE 0x8
  39
  40#ifdef CONFIG_PM_SLEEP
  41static unsigned long reg_save[][2] = {
  42        { ASS_CLK_SRC,  0 },
  43        { ASS_CLK_DIV,  0 },
  44        { ASS_CLK_GATE, 0 },
  45};
  46
  47static int exynos_audss_clk_suspend(void)
  48{
  49        int i;
  50
  51        for (i = 0; i < ARRAY_SIZE(reg_save); i++)
  52                reg_save[i][1] = readl(reg_base + reg_save[i][0]);
  53
  54        return 0;
  55}
  56
  57static void exynos_audss_clk_resume(void)
  58{
  59        int i;
  60
  61        for (i = 0; i < ARRAY_SIZE(reg_save); i++)
  62                writel(reg_save[i][1], reg_base + reg_save[i][0]);
  63}
  64
  65static struct syscore_ops exynos_audss_clk_syscore_ops = {
  66        .suspend        = exynos_audss_clk_suspend,
  67        .resume         = exynos_audss_clk_resume,
  68};
  69#endif /* CONFIG_PM_SLEEP */
  70
  71struct exynos_audss_clk_drvdata {
  72        unsigned int has_adma_clk:1;
  73        unsigned int has_mst_clk:1;
  74        unsigned int enable_epll:1;
  75        unsigned int num_clks;
  76};
  77
  78static const struct exynos_audss_clk_drvdata exynos4210_drvdata = {
  79        .num_clks       = EXYNOS_AUDSS_MAX_CLKS - 1,
  80};
  81
  82static const struct exynos_audss_clk_drvdata exynos5410_drvdata = {
  83        .num_clks       = EXYNOS_AUDSS_MAX_CLKS - 1,
  84        .has_mst_clk    = 1,
  85};
  86
  87static const struct exynos_audss_clk_drvdata exynos5420_drvdata = {
  88        .num_clks       = EXYNOS_AUDSS_MAX_CLKS,
  89        .has_adma_clk   = 1,
  90        .enable_epll    = 1,
  91};
  92
  93static const struct of_device_id exynos_audss_clk_of_match[] = {
  94        {
  95                .compatible     = "samsung,exynos4210-audss-clock",
  96                .data           = &exynos4210_drvdata,
  97        }, {
  98                .compatible     = "samsung,exynos5250-audss-clock",
  99                .data           = &exynos4210_drvdata,
 100        }, {
 101                .compatible     = "samsung,exynos5410-audss-clock",
 102                .data           = &exynos5410_drvdata,
 103        }, {
 104                .compatible     = "samsung,exynos5420-audss-clock",
 105                .data           = &exynos5420_drvdata,
 106        },
 107        { },
 108};
 109MODULE_DEVICE_TABLE(of, exynos_audss_clk_of_match);
 110
 111static void exynos_audss_clk_teardown(void)
 112{
 113        int i;
 114
 115        for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
 116                if (!IS_ERR(clk_table[i]))
 117                        clk_unregister_mux(clk_table[i]);
 118        }
 119
 120        for (; i < EXYNOS_SRP_CLK; i++) {
 121                if (!IS_ERR(clk_table[i]))
 122                        clk_unregister_divider(clk_table[i]);
 123        }
 124
 125        for (; i < clk_data.clk_num; i++) {
 126                if (!IS_ERR(clk_table[i]))
 127                        clk_unregister_gate(clk_table[i]);
 128        }
 129}
 130
 131/* register exynos_audss clocks */
 132static int exynos_audss_clk_probe(struct platform_device *pdev)
 133{
 134        const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
 135        const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
 136        const char *sclk_pcm_p = "sclk_pcm0";
 137        struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
 138        const struct exynos_audss_clk_drvdata *variant;
 139        struct resource *res;
 140        int i, ret = 0;
 141
 142        variant = of_device_get_match_data(&pdev->dev);
 143        if (!variant)
 144                return -EINVAL;
 145
 146        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 147        reg_base = devm_ioremap_resource(&pdev->dev, res);
 148        if (IS_ERR(reg_base)) {
 149                dev_err(&pdev->dev, "failed to map audss registers\n");
 150                return PTR_ERR(reg_base);
 151        }
 152
 153        epll = ERR_PTR(-ENODEV);
 154
 155        clk_table = devm_kzalloc(&pdev->dev,
 156                                sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
 157                                GFP_KERNEL);
 158        if (!clk_table)
 159                return -ENOMEM;
 160
 161        clk_data.clks = clk_table;
 162        clk_data.clk_num = variant->num_clks;
 163
 164        pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
 165        pll_in = devm_clk_get(&pdev->dev, "pll_in");
 166        if (!IS_ERR(pll_ref))
 167                mout_audss_p[0] = __clk_get_name(pll_ref);
 168        if (!IS_ERR(pll_in)) {
 169                mout_audss_p[1] = __clk_get_name(pll_in);
 170
 171                if (variant->enable_epll) {
 172                        epll = pll_in;
 173
 174                        ret = clk_prepare_enable(epll);
 175                        if (ret) {
 176                                dev_err(&pdev->dev,
 177                                        "failed to prepare the epll clock\n");
 178                                return ret;
 179                        }
 180                }
 181        }
 182        clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
 183                                mout_audss_p, ARRAY_SIZE(mout_audss_p),
 184                                CLK_SET_RATE_NO_REPARENT,
 185                                reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
 186
 187        cdclk = devm_clk_get(&pdev->dev, "cdclk");
 188        sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio");
 189        if (!IS_ERR(cdclk))
 190                mout_i2s_p[1] = __clk_get_name(cdclk);
 191        if (!IS_ERR(sclk_audio))
 192                mout_i2s_p[2] = __clk_get_name(sclk_audio);
 193        clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
 194                                mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
 195                                CLK_SET_RATE_NO_REPARENT,
 196                                reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
 197
 198        clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
 199                                "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
 200                                0, &lock);
 201
 202        clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
 203                                "dout_aud_bus", "dout_srp", 0,
 204                                reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
 205
 206        clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
 207                                "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
 208                                &lock);
 209
 210        clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
 211                                "dout_srp", CLK_SET_RATE_PARENT,
 212                                reg_base + ASS_CLK_GATE, 0, 0, &lock);
 213
 214        clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
 215                                "dout_aud_bus", CLK_SET_RATE_PARENT,
 216                                reg_base + ASS_CLK_GATE, 2, 0, &lock);
 217
 218        clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
 219                                "dout_i2s", CLK_SET_RATE_PARENT,
 220                                reg_base + ASS_CLK_GATE, 3, 0, &lock);
 221
 222        clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
 223                                 "sclk_pcm", CLK_SET_RATE_PARENT,
 224                                reg_base + ASS_CLK_GATE, 4, 0, &lock);
 225
 226        sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in");
 227        if (!IS_ERR(sclk_pcm_in))
 228                sclk_pcm_p = __clk_get_name(sclk_pcm_in);
 229        clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
 230                                sclk_pcm_p, CLK_SET_RATE_PARENT,
 231                                reg_base + ASS_CLK_GATE, 5, 0, &lock);
 232
 233        if (variant->has_adma_clk) {
 234                clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
 235                                "dout_srp", CLK_SET_RATE_PARENT,
 236                                reg_base + ASS_CLK_GATE, 9, 0, &lock);
 237        }
 238
 239        for (i = 0; i < clk_data.clk_num; i++) {
 240                if (IS_ERR(clk_table[i])) {
 241                        dev_err(&pdev->dev, "failed to register clock %d\n", i);
 242                        ret = PTR_ERR(clk_table[i]);
 243                        goto unregister;
 244                }
 245        }
 246
 247        ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
 248                                        &clk_data);
 249        if (ret) {
 250                dev_err(&pdev->dev, "failed to add clock provider\n");
 251                goto unregister;
 252        }
 253
 254#ifdef CONFIG_PM_SLEEP
 255        register_syscore_ops(&exynos_audss_clk_syscore_ops);
 256#endif
 257        return 0;
 258
 259unregister:
 260        exynos_audss_clk_teardown();
 261
 262        if (!IS_ERR(epll))
 263                clk_disable_unprepare(epll);
 264
 265        return ret;
 266}
 267
 268static int exynos_audss_clk_remove(struct platform_device *pdev)
 269{
 270#ifdef CONFIG_PM_SLEEP
 271        unregister_syscore_ops(&exynos_audss_clk_syscore_ops);
 272#endif
 273
 274        of_clk_del_provider(pdev->dev.of_node);
 275
 276        exynos_audss_clk_teardown();
 277
 278        if (!IS_ERR(epll))
 279                clk_disable_unprepare(epll);
 280
 281        return 0;
 282}
 283
 284static struct platform_driver exynos_audss_clk_driver = {
 285        .driver = {
 286                .name = "exynos-audss-clk",
 287                .of_match_table = exynos_audss_clk_of_match,
 288        },
 289        .probe = exynos_audss_clk_probe,
 290        .remove = exynos_audss_clk_remove,
 291};
 292
 293module_platform_driver(exynos_audss_clk_driver);
 294
 295MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
 296MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
 297MODULE_LICENSE("GPL v2");
 298MODULE_ALIAS("platform:exynos-audss-clk");
 299
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