LXR linux/drivers/ata/pata

   1/*
   2 * Libata driver for the highpoint 372N and 302N UDMA66 ATA controllers.
   3 *
   4 * This driver is heavily based upon:
   5 *
   6 * linux/drivers/ide/pci/hpt366.c               Version 0.36    April 25, 2003
   7 *
   8 * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   9 * Portions Copyright (C) 2001          Sun Microsystems, Inc.
  10 * Portions Copyright (C) 2003          Red Hat Inc
  11 * Portions Copyright (C) 2005-2007     MontaVista Software, Inc.
  12 *
  13 *
  14 * TODO
  15 *      Work out best PLL policy
  16 */
  17
  18#include <linux/kernel.h>
  19#include <linux/module.h>
  20#include <linux/pci.h>
  21#include <linux/init.h>
  22#include <linux/blkdev.h>
  23#include <linux/delay.h>
  24#include <scsi/scsi_host.h>
  25#include <linux/libata.h>
  26
  27#define DRV_NAME        "pata_hpt3x2n"
  28#define DRV_VERSION     "0.3.4"
  29
  30enum {
  31        HPT_PCI_FAST    =       (1 << 31),
  32        PCI66           =       (1 << 1),
  33        USE_DPLL        =       (1 << 0)
  34};
  35
  36struct hpt_clock {
  37        u8      xfer_speed;
  38        u32     timing;
  39};
  40
  41struct hpt_chip {
  42        const char *name;
  43        struct hpt_clock *clocks[3];
  44};
  45
  46/* key for bus clock timings
  47 * bit
  48 * 0:3    data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
  49 *        DMA. cycles = value + 1
  50 * 4:8    data_low_time. active time of DIOW_/DIOR_ for PIO and MW
  51 *        DMA. cycles = value + 1
  52 * 9:12   cmd_high_time. inactive time of DIOW_/DIOR_ during task file
  53 *        register access.
  54 * 13:17  cmd_low_time. active time of DIOW_/DIOR_ during task file
  55 *        register access.
  56 * 18:21  udma_cycle_time. clock freq and clock cycles for UDMA xfer.
  57 *        during task file register access.
  58 * 22:24  pre_high_time. time to initialize 1st cycle for PIO and MW DMA
  59 *        xfer.
  60 * 25:27  cmd_pre_high_time. time to initialize 1st PIO cycle for task
  61 *        register access.
  62 * 28     UDMA enable
  63 * 29     DMA enable
  64 * 30     PIO_MST enable. if set, the chip is in bus master mode during
  65 *        PIO.
  66 * 31     FIFO enable.
  67 */
  68
  69/* 66MHz DPLL clocks */
  70
  71static struct hpt_clock hpt3x2n_clocks[] = {
  72        {       XFER_UDMA_7,    0x1c869c62      },
  73        {       XFER_UDMA_6,    0x1c869c62      },
  74        {       XFER_UDMA_5,    0x1c8a9c62      },
  75        {       XFER_UDMA_4,    0x1c8a9c62      },
  76        {       XFER_UDMA_3,    0x1c8e9c62      },
  77        {       XFER_UDMA_2,    0x1c929c62      },
  78        {       XFER_UDMA_1,    0x1c9a9c62      },
  79        {       XFER_UDMA_0,    0x1c829c62      },
  80
  81        {       XFER_MW_DMA_2,  0x2c829c62      },
  82        {       XFER_MW_DMA_1,  0x2c829c66      },
  83        {       XFER_MW_DMA_0,  0x2c829d2c      },
  84
  85        {       XFER_PIO_4,     0x0c829c62      },
  86        {       XFER_PIO_3,     0x0c829c84      },
  87        {       XFER_PIO_2,     0x0c829ca6      },
  88        {       XFER_PIO_1,     0x0d029d26      },
  89        {       XFER_PIO_0,     0x0d029d5e      },
  90        {       0,              0x0d029d5e      }
  91};
  92
  93/**
  94 *      hpt3x2n_find_mode       -       reset the hpt3x2n bus
  95 *      @ap: ATA port
  96 *      @speed: transfer mode
  97 *
  98 *      Return the 32bit register programming information for this channel
  99 *      that matches the speed provided. For the moment the clocks table
 100 *      is hard coded but easy to change. This will be needed if we use
 101 *      different DPLLs
 102 */
 103
 104static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
 105{
 106        struct hpt_clock *clocks = hpt3x2n_clocks;
 107
 108        while(clocks->xfer_speed) {
 109                if (clocks->xfer_speed == speed)
 110                        return clocks->timing;
 111                clocks++;
 112        }
 113        BUG();
 114        return 0xffffffffU;     /* silence compiler warning */
 115}
 116
 117/**
 118 *      hpt3x2n_cable_detect    -       Detect the cable type
 119 *      @ap: ATA port to detect on
 120 *
 121 *      Return the cable type attached to this port
 122 */
 123
 124static int hpt3x2n_cable_detect(struct ata_port *ap)
 125{
 126        u8 scr2, ata66;
 127        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 128
 129        pci_read_config_byte(pdev, 0x5B, &scr2);
 130        pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
 131        /* Cable register now active */
 132        pci_read_config_byte(pdev, 0x5A, &ata66);
 133        /* Restore state */
 134        pci_write_config_byte(pdev, 0x5B, scr2);
 135
 136        if (ata66 & (1 << ap->port_no))
 137                return ATA_CBL_PATA40;
 138        else
 139                return ATA_CBL_PATA80;
 140}
 141
 142/**
 143 *      hpt3x2n_pre_reset       -       reset the hpt3x2n bus
 144 *      @link: ATA link to reset
 145 *      @deadline: deadline jiffies for the operation
 146 *
 147 *      Perform the initial reset handling for the 3x2n series controllers.
 148 *      Reset the hardware and state machine,
 149 */
 150
 151static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline)
 152{
 153        struct ata_port *ap = link->ap;
 154        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 155        /* Reset the state machine */
 156        pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
 157        udelay(100);
 158
 159        return ata_sff_prereset(link, deadline);
 160}
 161
 162/**
 163 *      hpt3x2n_set_piomode             -       PIO setup
 164 *      @ap: ATA interface
 165 *      @adev: device on the interface
 166 *
 167 *      Perform PIO mode setup.
 168 */
 169
 170static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
 171{
 172        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 173        u32 addr1, addr2;
 174        u32 reg;
 175        u32 mode;
 176        u8 fast;
 177
 178        addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
 179        addr2 = 0x51 + 4 * ap->port_no;
 180
 181        /* Fast interrupt prediction disable, hold off interrupt disable */
 182        pci_read_config_byte(pdev, addr2, &fast);
 183        fast &= ~0x07;
 184        pci_write_config_byte(pdev, addr2, fast);
 185
 186        pci_read_config_dword(pdev, addr1, &reg);
 187        mode = hpt3x2n_find_mode(ap, adev->pio_mode);
 188        mode &= ~0x8000000;     /* No FIFO in PIO */
 189        mode &= ~0x30070000;    /* Leave config bits alone */
 190        reg &= 0x30070000;      /* Strip timing bits */
 191        pci_write_config_dword(pdev, addr1, reg | mode);
 192}
 193
 194/**
 195 *      hpt3x2n_set_dmamode             -       DMA timing setup
 196 *      @ap: ATA interface
 197 *      @adev: Device being configured
 198 *
 199 *      Set up the channel for MWDMA or UDMA modes. Much the same as with
 200 *      PIO, load the mode number and then set MWDMA or UDMA flag.
 201 */
 202
 203static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 204{
 205        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 206        u32 addr1, addr2;
 207        u32 reg;
 208        u32 mode;
 209        u8 fast;
 210
 211        addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
 212        addr2 = 0x51 + 4 * ap->port_no;
 213
 214        /* Fast interrupt prediction disable, hold off interrupt disable */
 215        pci_read_config_byte(pdev, addr2, &fast);
 216        fast &= ~0x07;
 217        pci_write_config_byte(pdev, addr2, fast);
 218
 219        pci_read_config_dword(pdev, addr1, &reg);
 220        mode = hpt3x2n_find_mode(ap, adev->dma_mode);
 221        mode |= 0x8000000;      /* FIFO in MWDMA or UDMA */
 222        mode &= ~0xC0000000;    /* Leave config bits alone */
 223        reg &= 0xC0000000;      /* Strip timing bits */
 224        pci_write_config_dword(pdev, addr1, reg | mode);
 225}
 226
 227/**
 228 *      hpt3x2n_bmdma_end               -       DMA engine stop
 229 *      @qc: ATA command
 230 *
 231 *      Clean up after the HPT3x2n and later DMA engine
 232 */
 233
 234static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
 235{
 236        struct ata_port *ap = qc->ap;
 237        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 238        int mscreg = 0x50 + 2 * ap->port_no;
 239        u8 bwsr_stat, msc_stat;
 240
 241        pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
 242        pci_read_config_byte(pdev, mscreg, &msc_stat);
 243        if (bwsr_stat & (1 << ap->port_no))
 244                pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
 245        ata_bmdma_stop(qc);
 246}
 247
 248/**
 249 *      hpt3x2n_set_clock       -       clock control
 250 *      @ap: ATA port
 251 *      @source: 0x21 or 0x23 for PLL or PCI sourced clock
 252 *
 253 *      Switch the ATA bus clock between the PLL and PCI clock sources
 254 *      while correctly isolating the bus and resetting internal logic
 255 *
 256 *      We must use the DPLL for
 257 *      -       writing
 258 *      -       second channel UDMA7 (SATA ports) or higher
 259 *      -       66MHz PCI
 260 *
 261 *      or we will underclock the device and get reduced performance.
 262 */
 263
 264static void hpt3x2n_set_clock(struct ata_port *ap, int source)
 265{
 266        void __iomem *bmdma = ap->ioaddr.bmdma_addr;
 267
 268        /* Tristate the bus */
 269        iowrite8(0x80, bmdma+0x73);
 270        iowrite8(0x80, bmdma+0x77);
 271
 272        /* Switch clock and reset channels */
 273        iowrite8(source, bmdma+0x7B);
 274        iowrite8(0xC0, bmdma+0x79);
 275
 276        /* Reset state machines */
 277        iowrite8(0x37, bmdma+0x70);
 278        iowrite8(0x37, bmdma+0x74);
 279
 280        /* Complete reset */
 281        iowrite8(0x00, bmdma+0x79);
 282
 283        /* Reconnect channels to bus */
 284        iowrite8(0x00, bmdma+0x73);
 285        iowrite8(0x00, bmdma+0x77);
 286}
 287
 288/* Check if our partner interface is busy */
 289
 290static int hpt3x2n_pair_idle(struct ata_port *ap)
 291{
 292        struct ata_host *host = ap->host;
 293        struct ata_port *pair = host->ports[ap->port_no ^ 1];
 294
 295        if (pair->hsm_task_state == HSM_ST_IDLE)
 296                return 1;
 297        return 0;
 298}
 299
 300static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
 301{
 302        long flags = (long)ap->host->private_data;
 303        /* See if we should use the DPLL */
 304        if (writing)
 305                return USE_DPLL;        /* Needed for write */
 306        if (flags & PCI66)
 307                return USE_DPLL;        /* Needed at 66Mhz */
 308        return 0;
 309}
 310
 311static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc)
 312{
 313        struct ata_taskfile *tf = &qc->tf;
 314        struct ata_port *ap = qc->ap;
 315        int flags = (long)ap->host->private_data;
 316
 317        if (hpt3x2n_pair_idle(ap)) {
 318                int dpll = hpt3x2n_use_dpll(ap, (tf->flags & ATA_TFLAG_WRITE));
 319                if ((flags & USE_DPLL) != dpll) {
 320                        if (dpll == 1)
 321                                hpt3x2n_set_clock(ap, 0x21);
 322                        else
 323                                hpt3x2n_set_clock(ap, 0x23);
 324                }
 325        }
 326        return ata_sff_qc_issue(qc);
 327}
 328
 329static struct scsi_host_template hpt3x2n_sht = {
 330        ATA_BMDMA_SHT(DRV_NAME),
 331};
 332
 333/*
 334 *      Configuration for HPT3x2n.
 335 */
 336
 337static struct ata_port_operations hpt3x2n_port_ops = {
 338        .inherits       = &ata_bmdma_port_ops,
 339
 340        .bmdma_stop     = hpt3x2n_bmdma_stop,
 341        .qc_issue       = hpt3x2n_qc_issue,
 342
 343        .cable_detect   = hpt3x2n_cable_detect,
 344        .set_piomode    = hpt3x2n_set_piomode,
 345        .set_dmamode    = hpt3x2n_set_dmamode,
 346        .prereset       = hpt3x2n_pre_reset,
 347};
 348
 349/**
 350 *      hpt3xn_calibrate_dpll           -       Calibrate the DPLL loop
 351 *      @dev: PCI device
 352 *
 353 *      Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
 354 *      succeeds
 355 */
 356
 357static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
 358{
 359        u8 reg5b;
 360        u32 reg5c;
 361        int tries;
 362
 363        for(tries = 0; tries < 0x5000; tries++) {
 364                udelay(50);
 365                pci_read_config_byte(dev, 0x5b, &reg5b);
 366                if (reg5b & 0x80) {
 367                        /* See if it stays set */
 368                        for(tries = 0; tries < 0x1000; tries ++) {
 369                                pci_read_config_byte(dev, 0x5b, &reg5b);
 370                                /* Failed ? */
 371                                if ((reg5b & 0x80) == 0)
 372                                        return 0;
 373                        }
 374                        /* Turn off tuning, we have the DPLL set */
 375                        pci_read_config_dword(dev, 0x5c, &reg5c);
 376                        pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
 377                        return 1;
 378                }
 379        }
 380        /* Never went stable */
 381        return 0;
 382}
 383
 384static int hpt3x2n_pci_clock(struct pci_dev *pdev)
 385{
 386        unsigned long freq;
 387        u32 fcnt;
 388        unsigned long iobase = pci_resource_start(pdev, 4);
 389
 390        fcnt = inl(iobase + 0x90);      /* Not PCI readable for some chips */
 391        if ((fcnt >> 12) != 0xABCDE) {
 392                printk(KERN_WARNING "hpt3xn: BIOS clock data not set.\n");
 393                return 33;      /* Not BIOS set */
 394        }
 395        fcnt &= 0x1FF;
 396
 397        freq = (fcnt * 77) / 192;
 398
 399        /* Clamp to bands */
 400        if (freq < 40)
 401                return 33;
 402        if (freq < 45)
 403                return 40;
 404        if (freq < 55)
 405                return 50;
 406        return 66;
 407}
 408
 409/**
 410 *      hpt3x2n_init_one                -       Initialise an HPT37X/302
 411 *      @dev: PCI device
 412 *      @id: Entry in match table
 413 *
 414 *      Initialise an HPT3x2n device. There are some interesting complications
 415 *      here. Firstly the chip may report 366 and be one of several variants.
 416 *      Secondly all the timings depend on the clock for the chip which we must
 417 *      detect and look up
 418 *
 419 *      This is the known chip mappings. It may be missing a couple of later
 420 *      releases.
 421 *
 422 *      Chip version            PCI             Rev     Notes
 423 *      HPT372                  4 (HPT366)      5       Other driver
 424 *      HPT372N                 4 (HPT366)      6       UDMA133
 425 *      HPT372                  5 (HPT372)      1       Other driver
 426 *      HPT372N                 5 (HPT372)      2       UDMA133
 427 *      HPT302                  6 (HPT302)      *       Other driver
 428 *      HPT302N                 6 (HPT302)      > 1     UDMA133
 429 *      HPT371                  7 (HPT371)      *       Other driver
 430 *      HPT371N                 7 (HPT371)      > 1     UDMA133
 431 *      HPT374                  8 (HPT374)      *       Other driver
 432 *      HPT372N                 9 (HPT372N)     *       UDMA133
 433 *
 434 *      (1) UDMA133 support depends on the bus clock
 435 *
 436 *      To pin down             HPT371N
 437 */
 438
 439static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 440{
 441        /* HPT372N and friends - UDMA133 */
 442        static const struct ata_port_info info = {
 443                .flags = ATA_FLAG_SLAVE_POSS,
 444                .pio_mask = ATA_PIO4,
 445                .mwdma_mask = ATA_MWDMA2,
 446                .udma_mask = ATA_UDMA6,
 447                .port_ops = &hpt3x2n_port_ops
 448        };
 449        const struct ata_port_info *ppi[] = { &info, NULL };
 450
 451        u8 irqmask;
 452        u32 class_rev;
 453
 454        unsigned int pci_mhz;
 455        unsigned int f_low, f_high;
 456        int adjust;
 457        unsigned long iobase = pci_resource_start(dev, 4);
 458        void *hpriv = NULL;
 459        int rc;
 460
 461        rc = pcim_enable_device(dev);
 462        if (rc)
 463                return rc;
 464
 465        pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 466        class_rev &= 0xFF;
 467
 468        switch(dev->device) {
 469                case PCI_DEVICE_ID_TTI_HPT366:
 470                        if (class_rev < 6)
 471                                return -ENODEV;
 472                        break;
 473                case PCI_DEVICE_ID_TTI_HPT371:
 474                        if (class_rev < 2)
 475                                return -ENODEV;
 476                        /* 371N if rev > 1 */
 477                        break;
 478                case PCI_DEVICE_ID_TTI_HPT372:
 479                        /* 372N if rev >= 2*/
 480                        if (class_rev < 2)
 481                                return -ENODEV;
 482                        break;
 483                case PCI_DEVICE_ID_TTI_HPT302:
 484                        if (class_rev < 2)
 485                                return -ENODEV;
 486                        break;
 487                case PCI_DEVICE_ID_TTI_HPT372N:
 488                        break;
 489                default:
 490                        printk(KERN_ERR "pata_hpt3x2n: PCI table is bogus please report (%d).\n", dev->device);
 491                        return -ENODEV;
 492        }
 493
 494        /* Ok so this is a chip we support */
 495
 496        pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
 497        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
 498        pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
 499        pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
 500
 501        pci_read_config_byte(dev, 0x5A, &irqmask);
 502        irqmask &= ~0x10;
 503        pci_write_config_byte(dev, 0x5a, irqmask);
 504
 505        /*
 506         * HPT371 chips physically have only one channel, the secondary one,
 507         * but the primary channel registers do exist!  Go figure...
 508         * So,  we manually disable the non-existing channel here
 509         * (if the BIOS hasn't done this already).
 510         */
 511        if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
 512                u8 mcr1;
 513                pci_read_config_byte(dev, 0x50, &mcr1);
 514                mcr1 &= ~0x04;
 515                pci_write_config_byte(dev, 0x50, mcr1);
 516        }
 517
 518        /* Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
 519           50 for UDMA100. Right now we always use 66 */
 520
 521        pci_mhz = hpt3x2n_pci_clock(dev);
 522
 523        f_low = (pci_mhz * 48) / 66;    /* PCI Mhz for 66Mhz DPLL */
 524        f_high = f_low + 2;             /* Tolerance */
 525
 526        pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
 527        /* PLL clock */
 528        pci_write_config_byte(dev, 0x5B, 0x21);
 529
 530        /* Unlike the 37x we don't try jiggling the frequency */
 531        for(adjust = 0; adjust < 8; adjust++) {
 532                if (hpt3xn_calibrate_dpll(dev))
 533                        break;
 534                pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
 535        }
 536        if (adjust == 8) {
 537                printk(KERN_ERR "pata_hpt3x2n: DPLL did not stabilize!\n");
 538                return -ENODEV;
 539        }
 540
 541        printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using 66MHz DPLL.\n",
 542               pci_mhz);
 543        /* Set our private data up. We only need a few flags so we use
 544           it directly */
 545        if (pci_mhz > 60) {
 546                hpriv = (void *)PCI66;
 547                /*
 548                 * On  HPT371N, if ATA clock is 66 MHz we must set bit 2 in
 549                 * the MISC. register to stretch the UltraDMA Tss timing.
 550                 * NOTE: This register is only writeable via I/O space.
 551                 */
 552                if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
 553                        outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
 554        }
 555
 556        /* Now kick off ATA set up */
 557        return ata_pci_sff_init_one(dev, ppi, &hpt3x2n_sht, hpriv);
 558}
 559
 560static const struct pci_device_id hpt3x2n[] = {
 561        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
 562        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
 563        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
 564        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
 565        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), },
 566
 567        { },
 568};
 569
 570static struct pci_driver hpt3x2n_pci_driver = {
 571        .name           = DRV_NAME,
 572        .id_table       = hpt3x2n,
 573        .probe          = hpt3x2n_init_one,
 574        .remove         = ata_pci_remove_one
 575};
 576
 577static int __init hpt3x2n_init(void)
 578{
 579        return pci_register_driver(&hpt3x2n_pci_driver);
 580}
 581
 582static void __exit hpt3x2n_exit(void)
 583{
 584        pci_unregister_driver(&hpt3x2n_pci_driver);
 585}
 586
 587MODULE_AUTHOR("Alan Cox");
 588MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3x2n/30x");
 589MODULE_LICENSE("GPL");
 590MODULE_DEVICE_TABLE(pci, hpt3x2n);
 591MODULE_VERSION(DRV_VERSION);
 592
 593module_init(hpt3x2n_init);
 594module_exit(hpt3x2n_exit);
 595