LXR linux/drivers/ata/pata

   1/*
   2 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
   3 *
   4 * This driver is heavily based upon:
   5 *
   6 * linux/drivers/ide/pci/hpt366.c               Version 0.36    April 25, 2003
   7 *
   8 * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   9 * Portions Copyright (C) 2001          Sun Microsystems, Inc.
  10 * Portions Copyright (C) 2003          Red Hat Inc
  11 *
  12 *
  13 * TODO
  14 *      Maybe PLL mode
  15 *      Look into engine reset on timeout errors. Should not be
  16 *              required.
  17 */
  18
  19
  20#include <linux/kernel.h>
  21#include <linux/module.h>
  22#include <linux/pci.h>
  23#include <linux/init.h>
  24#include <linux/blkdev.h>
  25#include <linux/delay.h>
  26#include <scsi/scsi_host.h>
  27#include <linux/libata.h>
  28
  29#define DRV_NAME        "pata_hpt366"
  30#define DRV_VERSION     "0.6.7"
  31
  32struct hpt_clock {
  33        u8      xfer_mode;
  34        u32     timing;
  35};
  36
  37/* key for bus clock timings
  38 * bit
  39 * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
  40 *        cycles = value + 1
  41 * 4:7    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
  42 *        cycles = value + 1
  43 * 8:11   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
  44 *        register access.
  45 * 12:15  cmd_low_time. Active time of DIOW_/DIOR_ during task file
  46 *        register access.
  47 * 16:18  udma_cycle_time. Clock cycles for UDMA xfer?
  48 * 19:21  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
  49 * 22:24  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
  50 *        register access.
  51 * 28     UDMA enable.
  52 * 29     DMA  enable.
  53 * 30     PIO_MST enable. If set, the chip is in bus master mode during
  54 *        PIO xfer.
  55 * 31     FIFO enable.
  56 */
  57
  58static const struct hpt_clock hpt366_40[] = {
  59        {       XFER_UDMA_4,    0x900fd943      },
  60        {       XFER_UDMA_3,    0x900ad943      },
  61        {       XFER_UDMA_2,    0x900bd943      },
  62        {       XFER_UDMA_1,    0x9008d943      },
  63        {       XFER_UDMA_0,    0x9008d943      },
  64
  65        {       XFER_MW_DMA_2,  0xa008d943      },
  66        {       XFER_MW_DMA_1,  0xa010d955      },
  67        {       XFER_MW_DMA_0,  0xa010d9fc      },
  68
  69        {       XFER_PIO_4,     0xc008d963      },
  70        {       XFER_PIO_3,     0xc010d974      },
  71        {       XFER_PIO_2,     0xc010d997      },
  72        {       XFER_PIO_1,     0xc010d9c7      },
  73        {       XFER_PIO_0,     0xc018d9d9      },
  74        {       0,              0x0120d9d9      }
  75};
  76
  77static const struct hpt_clock hpt366_33[] = {
  78        {       XFER_UDMA_4,    0x90c9a731      },
  79        {       XFER_UDMA_3,    0x90cfa731      },
  80        {       XFER_UDMA_2,    0x90caa731      },
  81        {       XFER_UDMA_1,    0x90cba731      },
  82        {       XFER_UDMA_0,    0x90c8a731      },
  83
  84        {       XFER_MW_DMA_2,  0xa0c8a731      },
  85        {       XFER_MW_DMA_1,  0xa0c8a732      },      /* 0xa0c8a733 */
  86        {       XFER_MW_DMA_0,  0xa0c8a797      },
  87
  88        {       XFER_PIO_4,     0xc0c8a731      },
  89        {       XFER_PIO_3,     0xc0c8a742      },
  90        {       XFER_PIO_2,     0xc0d0a753      },
  91        {       XFER_PIO_1,     0xc0d0a7a3      },      /* 0xc0d0a793 */
  92        {       XFER_PIO_0,     0xc0d0a7aa      },      /* 0xc0d0a7a7 */
  93        {       0,              0x0120a7a7      }
  94};
  95
  96static const struct hpt_clock hpt366_25[] = {
  97        {       XFER_UDMA_4,    0x90c98521      },
  98        {       XFER_UDMA_3,    0x90cf8521      },
  99        {       XFER_UDMA_2,    0x90cf8521      },
 100        {       XFER_UDMA_1,    0x90cb8521      },
 101        {       XFER_UDMA_0,    0x90cb8521      },
 102
 103        {       XFER_MW_DMA_2,  0xa0ca8521      },
 104        {       XFER_MW_DMA_1,  0xa0ca8532      },
 105        {       XFER_MW_DMA_0,  0xa0ca8575      },
 106
 107        {       XFER_PIO_4,     0xc0ca8521      },
 108        {       XFER_PIO_3,     0xc0ca8532      },
 109        {       XFER_PIO_2,     0xc0ca8542      },
 110        {       XFER_PIO_1,     0xc0d08572      },
 111        {       XFER_PIO_0,     0xc0d08585      },
 112        {       0,              0x01208585      }
 113};
 114
 115static const char *bad_ata33[] = {
 116        "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
 117        "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
 118        "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
 119        "Maxtor 90510D4",
 120        "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
 121        "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
 122        "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
 123        NULL
 124};
 125
 126static const char *bad_ata66_4[] = {
 127        "IBM-DTLA-307075",
 128        "IBM-DTLA-307060",
 129        "IBM-DTLA-307045",
 130        "IBM-DTLA-307030",
 131        "IBM-DTLA-307020",
 132        "IBM-DTLA-307015",
 133        "IBM-DTLA-305040",
 134        "IBM-DTLA-305030",
 135        "IBM-DTLA-305020",
 136        "IC35L010AVER07-0",
 137        "IC35L020AVER07-0",
 138        "IC35L030AVER07-0",
 139        "IC35L040AVER07-0",
 140        "IC35L060AVER07-0",
 141        "WDC AC310200R",
 142        NULL
 143};
 144
 145static const char *bad_ata66_3[] = {
 146        "WDC AC310200R",
 147        NULL
 148};
 149
 150static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
 151{
 152        unsigned char model_num[ATA_ID_PROD_LEN + 1];
 153        int i = 0;
 154
 155        ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
 156
 157        while (list[i] != NULL) {
 158                if (!strcmp(list[i], model_num)) {
 159                        printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
 160                                modestr, list[i]);
 161                        return 1;
 162                }
 163                i++;
 164        }
 165        return 0;
 166}
 167
 168/**
 169 *      hpt366_filter   -       mode selection filter
 170 *      @adev: ATA device
 171 *
 172 *      Block UDMA on devices that cause trouble with this controller.
 173 */
 174
 175static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
 176{
 177        if (adev->class == ATA_DEV_ATA) {
 178                if (hpt_dma_blacklisted(adev, "UDMA",  bad_ata33))
 179                        mask &= ~ATA_MASK_UDMA;
 180                if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
 181                        mask &= ~(0xF8 << ATA_SHIFT_UDMA);
 182                if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
 183                        mask &= ~(0xF0 << ATA_SHIFT_UDMA);
 184        } else if (adev->class == ATA_DEV_ATAPI)
 185                mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
 186
 187        return ata_bmdma_mode_filter(adev, mask);
 188}
 189
 190static int hpt36x_cable_detect(struct ata_port *ap)
 191{
 192        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 193        u8 ata66;
 194
 195        /*
 196         * Each channel of pata_hpt366 occupies separate PCI function
 197         * as the primary channel and bit1 indicates the cable type.
 198         */
 199        pci_read_config_byte(pdev, 0x5A, &ata66);
 200        if (ata66 & 2)
 201                return ATA_CBL_PATA40;
 202        return ATA_CBL_PATA80;
 203}
 204
 205static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev,
 206                            u8 mode)
 207{
 208        struct hpt_clock *clocks = ap->host->private_data;
 209        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 210        u32 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
 211        u32 addr2 = 0x51 + 4 * ap->port_no;
 212        u32 mask, reg;
 213        u8 fast;
 214
 215        /* Fast interrupt prediction disable, hold off interrupt disable */
 216        pci_read_config_byte(pdev, addr2, &fast);
 217        if (fast & 0x80) {
 218                fast &= ~0x80;
 219                pci_write_config_byte(pdev, addr2, fast);
 220        }
 221
 222        /* determine timing mask and find matching clock entry */
 223        if (mode < XFER_MW_DMA_0)
 224                mask = 0xc1f8ffff;
 225        else if (mode < XFER_UDMA_0)
 226                mask = 0x303800ff;
 227        else
 228                mask = 0x30070000;
 229
 230        while (clocks->xfer_mode) {
 231                if (clocks->xfer_mode == mode)
 232                        break;
 233                clocks++;
 234        }
 235        if (!clocks->xfer_mode)
 236                BUG();
 237
 238        /*
 239         * Combine new mode bits with old config bits and disable
 240         * on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
 241         * problems handling I/O errors later.
 242         */
 243        pci_read_config_dword(pdev, addr1, &reg);
 244        reg = ((reg & ~mask) | (clocks->timing & mask)) & ~0xc0000000;
 245        pci_write_config_dword(pdev, addr1, reg);
 246}
 247
 248/**
 249 *      hpt366_set_piomode              -       PIO setup
 250 *      @ap: ATA interface
 251 *      @adev: device on the interface
 252 *
 253 *      Perform PIO mode setup.
 254 */
 255
 256static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
 257{
 258        hpt366_set_mode(ap, adev, adev->pio_mode);
 259}
 260
 261/**
 262 *      hpt366_set_dmamode              -       DMA timing setup
 263 *      @ap: ATA interface
 264 *      @adev: Device being configured
 265 *
 266 *      Set up the channel for MWDMA or UDMA modes. Much the same as with
 267 *      PIO, load the mode number and then set MWDMA or UDMA flag.
 268 */
 269
 270static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 271{
 272        hpt366_set_mode(ap, adev, adev->dma_mode);
 273}
 274
 275static struct scsi_host_template hpt36x_sht = {
 276        ATA_BMDMA_SHT(DRV_NAME),
 277};
 278
 279/*
 280 *      Configuration for HPT366/68
 281 */
 282
 283static struct ata_port_operations hpt366_port_ops = {
 284        .inherits       = &ata_bmdma_port_ops,
 285        .cable_detect   = hpt36x_cable_detect,
 286        .mode_filter    = hpt366_filter,
 287        .set_piomode    = hpt366_set_piomode,
 288        .set_dmamode    = hpt366_set_dmamode,
 289};
 290
 291/**
 292 *      hpt36x_init_chipset     -       common chip setup
 293 *      @dev: PCI device
 294 *
 295 *      Perform the chip setup work that must be done at both init and
 296 *      resume time
 297 */
 298
 299static void hpt36x_init_chipset(struct pci_dev *dev)
 300{
 301        u8 drive_fast;
 302        pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
 303        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
 304        pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
 305        pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
 306
 307        pci_read_config_byte(dev, 0x51, &drive_fast);
 308        if (drive_fast & 0x80)
 309                pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
 310}
 311
 312/**
 313 *      hpt36x_init_one         -       Initialise an HPT366/368
 314 *      @dev: PCI device
 315 *      @id: Entry in match table
 316 *
 317 *      Initialise an HPT36x device. There are some interesting complications
 318 *      here. Firstly the chip may report 366 and be one of several variants.
 319 *      Secondly all the timings depend on the clock for the chip which we must
 320 *      detect and look up
 321 *
 322 *      This is the known chip mappings. It may be missing a couple of later
 323 *      releases.
 324 *
 325 *      Chip version            PCI             Rev     Notes
 326 *      HPT366                  4 (HPT366)      0       UDMA66
 327 *      HPT366                  4 (HPT366)      1       UDMA66
 328 *      HPT368                  4 (HPT366)      2       UDMA66
 329 *      HPT37x/30x              4 (HPT366)      3+      Other driver
 330 *
 331 */
 332
 333static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 334{
 335        static const struct ata_port_info info_hpt366 = {
 336                .flags = ATA_FLAG_SLAVE_POSS,
 337                .pio_mask = ATA_PIO4,
 338                .mwdma_mask = ATA_MWDMA2,
 339                .udma_mask = ATA_UDMA4,
 340                .port_ops = &hpt366_port_ops
 341        };
 342        const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
 343
 344        void *hpriv = NULL;
 345        u32 reg1;
 346        int rc;
 347
 348        rc = pcim_enable_device(dev);
 349        if (rc)
 350                return rc;
 351
 352        /* May be a later chip in disguise. Check */
 353        /* Newer chips are not in the HPT36x driver. Ignore them */
 354        if (dev->revision > 2)
 355                return -ENODEV;
 356
 357        hpt36x_init_chipset(dev);
 358
 359        pci_read_config_dword(dev, 0x40,  &reg1);
 360
 361        /* PCI clocking determines the ATA timing values to use */
 362        /* info_hpt366 is safe against re-entry so we can scribble on it */
 363        switch((reg1 & 0x700) >> 8) {
 364                case 9:
 365                        hpriv = &hpt366_40;
 366                        break;
 367                case 5:
 368                        hpriv = &hpt366_25;
 369                        break;
 370                default:
 371                        hpriv = &hpt366_33;
 372                        break;
 373        }
 374        /* Now kick off ATA set up */
 375        return ata_pci_sff_init_one(dev, ppi, &hpt36x_sht, hpriv);
 376}
 377
 378#ifdef CONFIG_PM
 379static int hpt36x_reinit_one(struct pci_dev *dev)
 380{
 381        struct ata_host *host = dev_get_drvdata(&dev->dev);
 382        int rc;
 383
 384        rc = ata_pci_device_do_resume(dev);
 385        if (rc)
 386                return rc;
 387        hpt36x_init_chipset(dev);
 388        ata_host_resume(host);
 389        return 0;
 390}
 391#endif
 392
 393static const struct pci_device_id hpt36x[] = {
 394        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
 395        { },
 396};
 397
 398static struct pci_driver hpt36x_pci_driver = {
 399        .name           = DRV_NAME,
 400        .id_table       = hpt36x,
 401        .probe          = hpt36x_init_one,
 402        .remove         = ata_pci_remove_one,
 403#ifdef CONFIG_PM
 404        .suspend        = ata_pci_device_suspend,
 405        .resume         = hpt36x_reinit_one,
 406#endif
 407};
 408
 409static int __init hpt36x_init(void)
 410{
 411        return pci_register_driver(&hpt36x_pci_driver);
 412}
 413
 414static void __exit hpt36x_exit(void)
 415{
 416        pci_unregister_driver(&hpt36x_pci_driver);
 417}
 418
 419MODULE_AUTHOR("Alan Cox");
 420MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
 421MODULE_LICENSE("GPL");
 422MODULE_DEVICE_TABLE(pci, hpt36x);
 423MODULE_VERSION(DRV_VERSION);
 424
 425module_init(hpt36x_init);
 426module_exit(hpt36x_exit);
 427