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86#include <linux/kernel.h>
87#include <linux/module.h>
88#include <linux/pci.h>
89#include <linux/init.h>
90#include <linux/blkdev.h>
91#include <linux/delay.h>
92#include <linux/device.h>
93#include <linux/gfp.h>
94#include <scsi/scsi_host.h>
95#include <linux/libata.h>
96#include <linux/dmi.h>
97
98#define DRV_NAME "ata_piix"
99#define DRV_VERSION "2.13"
100
101enum {
102 PIIX_IOCFG = 0x54,
103 ICH5_PMR = 0x90,
104 ICH5_PCS = 0x92,
105 PIIX_SIDPR_BAR = 5,
106 PIIX_SIDPR_LEN = 16,
107 PIIX_SIDPR_IDX = 0,
108 PIIX_SIDPR_DATA = 4,
109
110 PIIX_FLAG_CHECKINTR = (1 << 28),
111 PIIX_FLAG_SIDPR = (1 << 29),
112
113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
115
116 PIIX_FLAG_PIO16 = (1 << 30),
117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
121
122 P0 = 0,
123 P1 = 1,
124 P2 = 2,
125 P3 = 3,
126 IDE = -1,
127 NA = -2,
128 RV = -3,
129
130 PIIX_AHCI_DEVICE = 6,
131
132
133 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
134};
135
136enum piix_controller_ids {
137
138 piix_pata_mwdma,
139 piix_pata_33,
140 ich_pata_33,
141 ich_pata_66,
142 ich_pata_100,
143 ich_pata_100_nomwdma1,
144 ich5_sata,
145 ich6_sata,
146 ich6m_sata,
147 ich8_sata,
148 ich8_2port_sata,
149 ich8m_apple_sata,
150 tolapai_sata,
151 piix_pata_vmw,
152 ich8_sata_snb,
153 ich8_2port_sata_snb,
154};
155
156struct piix_map_db {
157 const u32 mask;
158 const u16 port_enable;
159 const int map[][4];
160};
161
162struct piix_host_priv {
163 const int *map;
164 u32 saved_iocfg;
165 void __iomem *sidpr;
166};
167
168static unsigned int in_module_init = 1;
169
170static const struct pci_device_id piix_pci_tbl[] = {
171
172 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
173
174 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
175
176
177 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
178
179 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
180
181 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
182
183 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
184
185 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
186
187 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
188
189 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
190
191 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
192
193 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
194
195 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
196
197 { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
198
199 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
200 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201
202 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203
204 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
205
206 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207
208 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
209
210 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
211 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
212
213 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
214
215
216
217
218 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
219
220 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
221
222 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
223
224 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
225
226 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
227
228 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
229
230
231 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
232 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
233
234 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
235
236 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
237
238 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
239
240 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
241
242 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
243
244 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
245 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
246 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
247
248 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
249
250 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
251
252 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
253
254 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
255
256 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
257
258 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
259
260 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
261
262 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
263
264 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
265
266 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
267
268 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
269
270 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
271
272 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
273
274 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
275
276 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
277
278 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
279
280 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
281
282 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
283
284 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
285
286 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
287
288 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
289
290 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
291
292 { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
293
294 { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
295
296 { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
297
298 { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
299
300 { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
301
302 { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
303
304 { 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
305
306 { 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
307
308 { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
309
310 { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
311
312 { 0x8086, 0x9c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
313
314 { 0x8086, 0x9c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
315
316 { 0x8086, 0x9c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
317
318 { 0x8086, 0x9c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
319
320 { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
321
322 { 0x8086, 0x1f20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
323
324 { 0x8086, 0x1f21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
325
326 { 0x8086, 0x1f30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
327
328 { 0x8086, 0x1f31, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
329
330 { 0x8086, 0x8d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
331
332 { 0x8086, 0x8d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
333
334 { 0x8086, 0x8d60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
335
336 { 0x8086, 0x8d68, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
337
338 { }
339};
340
341static const struct piix_map_db ich5_map_db = {
342 .mask = 0x7,
343 .port_enable = 0x3,
344 .map = {
345
346 { P0, NA, P1, NA },
347 { P1, NA, P0, NA },
348 { RV, RV, RV, RV },
349 { RV, RV, RV, RV },
350 { P0, P1, IDE, IDE },
351 { P1, P0, IDE, IDE },
352 { IDE, IDE, P0, P1 },
353 { IDE, IDE, P1, P0 },
354 },
355};
356
357static const struct piix_map_db ich6_map_db = {
358 .mask = 0x3,
359 .port_enable = 0xf,
360 .map = {
361
362 { P0, P2, P1, P3 },
363 { IDE, IDE, P1, P3 },
364 { P0, P2, IDE, IDE },
365 { RV, RV, RV, RV },
366 },
367};
368
369static const struct piix_map_db ich6m_map_db = {
370 .mask = 0x3,
371 .port_enable = 0x5,
372
373
374
375
376
377 .map = {
378
379 { P0, P2, NA, NA },
380 { IDE, IDE, P1, P3 },
381 { P0, P2, IDE, IDE },
382 { RV, RV, RV, RV },
383 },
384};
385
386static const struct piix_map_db ich8_map_db = {
387 .mask = 0x3,
388 .port_enable = 0xf,
389 .map = {
390
391 { P0, P2, P1, P3 },
392 { RV, RV, RV, RV },
393 { P0, P2, IDE, IDE },
394 { RV, RV, RV, RV },
395 },
396};
397
398static const struct piix_map_db ich8_2port_map_db = {
399 .mask = 0x3,
400 .port_enable = 0x3,
401 .map = {
402
403 { P0, NA, P1, NA },
404 { RV, RV, RV, RV },
405 { RV, RV, RV, RV },
406 { RV, RV, RV, RV },
407 },
408};
409
410static const struct piix_map_db ich8m_apple_map_db = {
411 .mask = 0x3,
412 .port_enable = 0x1,
413 .map = {
414
415 { P0, NA, NA, NA },
416 { RV, RV, RV, RV },
417 { P0, P2, IDE, IDE },
418 { RV, RV, RV, RV },
419 },
420};
421
422static const struct piix_map_db tolapai_map_db = {
423 .mask = 0x3,
424 .port_enable = 0x3,
425 .map = {
426
427 { P0, NA, P1, NA },
428 { RV, RV, RV, RV },
429 { RV, RV, RV, RV },
430 { RV, RV, RV, RV },
431 },
432};
433
434static const struct piix_map_db *piix_map_db_table[] = {
435 [ich5_sata] = &ich5_map_db,
436 [ich6_sata] = &ich6_map_db,
437 [ich6m_sata] = &ich6m_map_db,
438 [ich8_sata] = &ich8_map_db,
439 [ich8_2port_sata] = &ich8_2port_map_db,
440 [ich8m_apple_sata] = &ich8m_apple_map_db,
441 [tolapai_sata] = &tolapai_map_db,
442 [ich8_sata_snb] = &ich8_map_db,
443 [ich8_2port_sata_snb] = &ich8_2port_map_db,
444};
445
446static struct pci_bits piix_enable_bits[] = {
447 { 0x41U, 1U, 0x80UL, 0x80UL },
448 { 0x43U, 1U, 0x80UL, 0x80UL },
449};
450
451MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
452MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
453MODULE_LICENSE("GPL");
454MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
455MODULE_VERSION(DRV_VERSION);
456
457struct ich_laptop {
458 u16 device;
459 u16 subvendor;
460 u16 subdevice;
461};
462
463
464
465
466
467static const struct ich_laptop ich_laptop[] = {
468
469 { 0x27DF, 0x0005, 0x0280 },
470 { 0x27DF, 0x1025, 0x0102 },
471 { 0x27DF, 0x1025, 0x0110 },
472 { 0x27DF, 0x1028, 0x02b0 },
473 { 0x27DF, 0x1043, 0x1267 },
474 { 0x27DF, 0x103C, 0x30A1 },
475 { 0x27DF, 0x103C, 0x361a },
476 { 0x27DF, 0x1071, 0xD221 },
477 { 0x27DF, 0x152D, 0x0778 },
478 { 0x24CA, 0x1025, 0x0061 },
479 { 0x24CA, 0x1025, 0x003d },
480 { 0x266F, 0x1025, 0x0066 },
481 { 0x2653, 0x1043, 0x82D8 },
482 { 0x27df, 0x104d, 0x900e },
483
484 { 0, }
485};
486
487static int piix_port_start(struct ata_port *ap)
488{
489 if (!(ap->flags & PIIX_FLAG_PIO16))
490 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
491
492 return ata_bmdma_port_start(ap);
493}
494
495
496
497
498
499
500
501
502
503
504
505
506static int ich_pata_cable_detect(struct ata_port *ap)
507{
508 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
509 struct piix_host_priv *hpriv = ap->host->private_data;
510 const struct ich_laptop *lap = &ich_laptop[0];
511 u8 mask;
512
513
514 while (lap->device) {
515 if (lap->device == pdev->device &&
516 lap->subvendor == pdev->subsystem_vendor &&
517 lap->subdevice == pdev->subsystem_device)
518 return ATA_CBL_PATA40_SHORT;
519
520 lap++;
521 }
522
523
524 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
525 if ((hpriv->saved_iocfg & mask) == 0)
526 return ATA_CBL_PATA40;
527 return ATA_CBL_PATA80;
528}
529
530
531
532
533
534
535
536
537
538static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
539{
540 struct ata_port *ap = link->ap;
541 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
542
543 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
544 return -ENOENT;
545 return ata_sff_prereset(link, deadline);
546}
547
548static DEFINE_SPINLOCK(piix_lock);
549
550static void piix_set_timings(struct ata_port *ap, struct ata_device *adev,
551 u8 pio)
552{
553 struct pci_dev *dev = to_pci_dev(ap->host->dev);
554 unsigned long flags;
555 unsigned int is_slave = (adev->devno != 0);
556 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
557 unsigned int slave_port = 0x44;
558 u16 master_data;
559 u8 slave_data;
560 u8 udma_enable;
561 int control = 0;
562
563
564
565
566
567
568 static const
569 u8 timings[][2] = { { 0, 0 },
570 { 0, 0 },
571 { 1, 0 },
572 { 2, 1 },
573 { 2, 3 }, };
574
575 if (pio >= 2)
576 control |= 1;
577 if (ata_pio_need_iordy(adev))
578 control |= 2;
579
580 if (adev->class == ATA_DEV_ATA)
581 control |= 4;
582
583
584
585
586 if (adev->pio_mode < XFER_PIO_0 + pio)
587
588 control |= 8;
589
590 spin_lock_irqsave(&piix_lock, flags);
591
592
593
594
595
596 pci_read_config_word(dev, master_port, &master_data);
597 if (is_slave) {
598
599 master_data &= 0xff0f;
600
601 master_data |= (control << 4);
602 pci_read_config_byte(dev, slave_port, &slave_data);
603 slave_data &= (ap->port_no ? 0x0f : 0xf0);
604
605 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
606 << (ap->port_no ? 4 : 0);
607 } else {
608
609 master_data &= 0xccf0;
610
611 master_data |= control;
612
613 master_data |=
614 (timings[pio][0] << 12) |
615 (timings[pio][1] << 8);
616 }
617
618
619 master_data |= 0x4000;
620 pci_write_config_word(dev, master_port, master_data);
621 if (is_slave)
622 pci_write_config_byte(dev, slave_port, slave_data);
623
624
625
626
627 if (ap->udma_mask) {
628 pci_read_config_byte(dev, 0x48, &udma_enable);
629 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
630 pci_write_config_byte(dev, 0x48, udma_enable);
631 }
632
633 spin_unlock_irqrestore(&piix_lock, flags);
634}
635
636
637
638
639
640
641
642
643
644
645
646
647static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
648{
649 piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0);
650}
651
652
653
654
655
656
657
658
659
660
661
662
663
664static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
665{
666 struct pci_dev *dev = to_pci_dev(ap->host->dev);
667 unsigned long flags;
668 u8 speed = adev->dma_mode;
669 int devid = adev->devno + 2 * ap->port_no;
670 u8 udma_enable = 0;
671
672 if (speed >= XFER_UDMA_0) {
673 unsigned int udma = speed - XFER_UDMA_0;
674 u16 udma_timing;
675 u16 ideconf;
676 int u_clock, u_speed;
677
678 spin_lock_irqsave(&piix_lock, flags);
679
680 pci_read_config_byte(dev, 0x48, &udma_enable);
681
682
683
684
685
686
687
688
689 u_speed = min(2 - (udma & 1), udma);
690 if (udma == 5)
691 u_clock = 0x1000;
692 else if (udma > 2)
693 u_clock = 1;
694 else
695 u_clock = 0;
696
697 udma_enable |= (1 << devid);
698
699
700 pci_read_config_word(dev, 0x4A, &udma_timing);
701 udma_timing &= ~(3 << (4 * devid));
702 udma_timing |= u_speed << (4 * devid);
703 pci_write_config_word(dev, 0x4A, udma_timing);
704
705 if (isich) {
706
707 pci_read_config_word(dev, 0x54, &ideconf);
708 ideconf &= ~(0x1001 << devid);
709 ideconf |= u_clock << devid;
710
711
712 pci_write_config_word(dev, 0x54, ideconf);
713 }
714
715 pci_write_config_byte(dev, 0x48, udma_enable);
716
717 spin_unlock_irqrestore(&piix_lock, flags);
718 } else {
719
720 unsigned int mwdma = speed - XFER_MW_DMA_0;
721 const unsigned int needed_pio[3] = {
722 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
723 };
724 int pio = needed_pio[mwdma] - XFER_PIO_0;
725
726
727 piix_set_timings(ap, adev, pio);
728 }
729}
730
731
732
733
734
735
736
737
738
739
740
741
742static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
743{
744 do_pata_set_dmamode(ap, adev, 0);
745}
746
747
748
749
750
751
752
753
754
755
756
757
758static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
759{
760 do_pata_set_dmamode(ap, adev, 1);
761}
762
763
764
765
766
767
768
769
770
771static const int piix_sidx_map[] = {
772 [SCR_STATUS] = 0,
773 [SCR_ERROR] = 2,
774 [SCR_CONTROL] = 1,
775};
776
777static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
778{
779 struct ata_port *ap = link->ap;
780 struct piix_host_priv *hpriv = ap->host->private_data;
781
782 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
783 hpriv->sidpr + PIIX_SIDPR_IDX);
784}
785
786static int piix_sidpr_scr_read(struct ata_link *link,
787 unsigned int reg, u32 *val)
788{
789 struct piix_host_priv *hpriv = link->ap->host->private_data;
790
791 if (reg >= ARRAY_SIZE(piix_sidx_map))
792 return -EINVAL;
793
794 piix_sidpr_sel(link, reg);
795 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
796 return 0;
797}
798
799static int piix_sidpr_scr_write(struct ata_link *link,
800 unsigned int reg, u32 val)
801{
802 struct piix_host_priv *hpriv = link->ap->host->private_data;
803
804 if (reg >= ARRAY_SIZE(piix_sidx_map))
805 return -EINVAL;
806
807 piix_sidpr_sel(link, reg);
808 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
809 return 0;
810}
811
812static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
813 unsigned hints)
814{
815 return sata_link_scr_lpm(link, policy, false);
816}
817
818static bool piix_irq_check(struct ata_port *ap)
819{
820 if (unlikely(!ap->ioaddr.bmdma_addr))
821 return false;
822
823 return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
824}
825
826#ifdef CONFIG_PM
827static int piix_broken_suspend(void)
828{
829 static const struct dmi_system_id sysids[] = {
830 {
831 .ident = "TECRA M3",
832 .matches = {
833 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
834 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
835 },
836 },
837 {
838 .ident = "TECRA M3",
839 .matches = {
840 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
841 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
842 },
843 },
844 {
845 .ident = "TECRA M4",
846 .matches = {
847 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
848 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
849 },
850 },
851 {
852 .ident = "TECRA M4",
853 .matches = {
854 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
855 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
856 },
857 },
858 {
859 .ident = "TECRA M5",
860 .matches = {
861 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
862 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
863 },
864 },
865 {
866 .ident = "TECRA M6",
867 .matches = {
868 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
869 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
870 },
871 },
872 {
873 .ident = "TECRA M7",
874 .matches = {
875 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
876 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
877 },
878 },
879 {
880 .ident = "TECRA A8",
881 .matches = {
882 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
883 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
884 },
885 },
886 {
887 .ident = "Satellite R20",
888 .matches = {
889 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
890 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
891 },
892 },
893 {
894 .ident = "Satellite R25",
895 .matches = {
896 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
897 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
898 },
899 },
900 {
901 .ident = "Satellite U200",
902 .matches = {
903 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
904 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
905 },
906 },
907 {
908 .ident = "Satellite U200",
909 .matches = {
910 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
911 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
912 },
913 },
914 {
915 .ident = "Satellite Pro U200",
916 .matches = {
917 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
918 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
919 },
920 },
921 {
922 .ident = "Satellite U205",
923 .matches = {
924 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
925 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
926 },
927 },
928 {
929 .ident = "SATELLITE U205",
930 .matches = {
931 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
932 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
933 },
934 },
935 {
936 .ident = "Satellite Pro A120",
937 .matches = {
938 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
939 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite Pro A120"),
940 },
941 },
942 {
943 .ident = "Portege M500",
944 .matches = {
945 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
946 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
947 },
948 },
949 {
950 .ident = "VGN-BX297XP",
951 .matches = {
952 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
953 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
954 },
955 },
956
957 { }
958 };
959 static const char *oemstrs[] = {
960 "Tecra M3,",
961 };
962 int i;
963
964 if (dmi_check_system(sysids))
965 return 1;
966
967 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
968 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
969 return 1;
970
971
972
973
974
975
976
977 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
978 dmi_match(DMI_PRODUCT_NAME, "000000") &&
979 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
980 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
981 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
982 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
983 dmi_match(DMI_BOARD_VERSION, "Version A0"))
984 return 1;
985
986 return 0;
987}
988
989static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
990{
991 struct ata_host *host = dev_get_drvdata(&pdev->dev);
992 unsigned long flags;
993 int rc = 0;
994
995 rc = ata_host_suspend(host, mesg);
996 if (rc)
997 return rc;
998
999
1000
1001
1002
1003
1004 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1005 pci_save_state(pdev);
1006
1007
1008
1009
1010
1011 if (pdev->current_state == PCI_D0)
1012 pdev->current_state = PCI_UNKNOWN;
1013
1014
1015 spin_lock_irqsave(&host->lock, flags);
1016 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1017 spin_unlock_irqrestore(&host->lock, flags);
1018 } else
1019 ata_pci_device_do_suspend(pdev, mesg);
1020
1021 return 0;
1022}
1023
1024static int piix_pci_device_resume(struct pci_dev *pdev)
1025{
1026 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1027 unsigned long flags;
1028 int rc;
1029
1030 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1031 spin_lock_irqsave(&host->lock, flags);
1032 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1033 spin_unlock_irqrestore(&host->lock, flags);
1034
1035 pci_set_power_state(pdev, PCI_D0);
1036 pci_restore_state(pdev);
1037
1038
1039
1040
1041
1042 rc = pci_reenable_device(pdev);
1043 if (rc)
1044 dev_err(&pdev->dev,
1045 "failed to enable device after resume (%d)\n",
1046 rc);
1047 } else
1048 rc = ata_pci_device_do_resume(pdev);
1049
1050 if (rc == 0)
1051 ata_host_resume(host);
1052
1053 return rc;
1054}
1055#endif
1056
1057static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1058{
1059 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1060}
1061
1062static struct scsi_host_template piix_sht = {
1063 ATA_BMDMA_SHT(DRV_NAME),
1064};
1065
1066static struct ata_port_operations piix_sata_ops = {
1067 .inherits = &ata_bmdma32_port_ops,
1068 .sff_irq_check = piix_irq_check,
1069 .port_start = piix_port_start,
1070};
1071
1072static struct ata_port_operations piix_pata_ops = {
1073 .inherits = &piix_sata_ops,
1074 .cable_detect = ata_cable_40wire,
1075 .set_piomode = piix_set_piomode,
1076 .set_dmamode = piix_set_dmamode,
1077 .prereset = piix_pata_prereset,
1078};
1079
1080static struct ata_port_operations piix_vmw_ops = {
1081 .inherits = &piix_pata_ops,
1082 .bmdma_status = piix_vmw_bmdma_status,
1083};
1084
1085static struct ata_port_operations ich_pata_ops = {
1086 .inherits = &piix_pata_ops,
1087 .cable_detect = ich_pata_cable_detect,
1088 .set_dmamode = ich_set_dmamode,
1089};
1090
1091static struct device_attribute *piix_sidpr_shost_attrs[] = {
1092 &dev_attr_link_power_management_policy,
1093 NULL
1094};
1095
1096static struct scsi_host_template piix_sidpr_sht = {
1097 ATA_BMDMA_SHT(DRV_NAME),
1098 .shost_attrs = piix_sidpr_shost_attrs,
1099};
1100
1101static struct ata_port_operations piix_sidpr_sata_ops = {
1102 .inherits = &piix_sata_ops,
1103 .hardreset = sata_std_hardreset,
1104 .scr_read = piix_sidpr_scr_read,
1105 .scr_write = piix_sidpr_scr_write,
1106 .set_lpm = piix_sidpr_set_lpm,
1107};
1108
1109static struct ata_port_info piix_port_info[] = {
1110 [piix_pata_mwdma] =
1111 {
1112 .flags = PIIX_PATA_FLAGS,
1113 .pio_mask = ATA_PIO4,
1114 .mwdma_mask = ATA_MWDMA12_ONLY,
1115 .port_ops = &piix_pata_ops,
1116 },
1117
1118 [piix_pata_33] =
1119 {
1120 .flags = PIIX_PATA_FLAGS,
1121 .pio_mask = ATA_PIO4,
1122 .mwdma_mask = ATA_MWDMA12_ONLY,
1123 .udma_mask = ATA_UDMA2,
1124 .port_ops = &piix_pata_ops,
1125 },
1126
1127 [ich_pata_33] =
1128 {
1129 .flags = PIIX_PATA_FLAGS,
1130 .pio_mask = ATA_PIO4,
1131 .mwdma_mask = ATA_MWDMA12_ONLY,
1132 .udma_mask = ATA_UDMA2,
1133 .port_ops = &ich_pata_ops,
1134 },
1135
1136 [ich_pata_66] =
1137 {
1138 .flags = PIIX_PATA_FLAGS,
1139 .pio_mask = ATA_PIO4,
1140 .mwdma_mask = ATA_MWDMA12_ONLY,
1141 .udma_mask = ATA_UDMA4,
1142 .port_ops = &ich_pata_ops,
1143 },
1144
1145 [ich_pata_100] =
1146 {
1147 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1148 .pio_mask = ATA_PIO4,
1149 .mwdma_mask = ATA_MWDMA12_ONLY,
1150 .udma_mask = ATA_UDMA5,
1151 .port_ops = &ich_pata_ops,
1152 },
1153
1154 [ich_pata_100_nomwdma1] =
1155 {
1156 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1157 .pio_mask = ATA_PIO4,
1158 .mwdma_mask = ATA_MWDMA2_ONLY,
1159 .udma_mask = ATA_UDMA5,
1160 .port_ops = &ich_pata_ops,
1161 },
1162
1163 [ich5_sata] =
1164 {
1165 .flags = PIIX_SATA_FLAGS,
1166 .pio_mask = ATA_PIO4,
1167 .mwdma_mask = ATA_MWDMA2,
1168 .udma_mask = ATA_UDMA6,
1169 .port_ops = &piix_sata_ops,
1170 },
1171
1172 [ich6_sata] =
1173 {
1174 .flags = PIIX_SATA_FLAGS,
1175 .pio_mask = ATA_PIO4,
1176 .mwdma_mask = ATA_MWDMA2,
1177 .udma_mask = ATA_UDMA6,
1178 .port_ops = &piix_sata_ops,
1179 },
1180
1181 [ich6m_sata] =
1182 {
1183 .flags = PIIX_SATA_FLAGS,
1184 .pio_mask = ATA_PIO4,
1185 .mwdma_mask = ATA_MWDMA2,
1186 .udma_mask = ATA_UDMA6,
1187 .port_ops = &piix_sata_ops,
1188 },
1189
1190 [ich8_sata] =
1191 {
1192 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1193 .pio_mask = ATA_PIO4,
1194 .mwdma_mask = ATA_MWDMA2,
1195 .udma_mask = ATA_UDMA6,
1196 .port_ops = &piix_sata_ops,
1197 },
1198
1199 [ich8_2port_sata] =
1200 {
1201 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1202 .pio_mask = ATA_PIO4,
1203 .mwdma_mask = ATA_MWDMA2,
1204 .udma_mask = ATA_UDMA6,
1205 .port_ops = &piix_sata_ops,
1206 },
1207
1208 [tolapai_sata] =
1209 {
1210 .flags = PIIX_SATA_FLAGS,
1211 .pio_mask = ATA_PIO4,
1212 .mwdma_mask = ATA_MWDMA2,
1213 .udma_mask = ATA_UDMA6,
1214 .port_ops = &piix_sata_ops,
1215 },
1216
1217 [ich8m_apple_sata] =
1218 {
1219 .flags = PIIX_SATA_FLAGS,
1220 .pio_mask = ATA_PIO4,
1221 .mwdma_mask = ATA_MWDMA2,
1222 .udma_mask = ATA_UDMA6,
1223 .port_ops = &piix_sata_ops,
1224 },
1225
1226 [piix_pata_vmw] =
1227 {
1228 .flags = PIIX_PATA_FLAGS,
1229 .pio_mask = ATA_PIO4,
1230 .mwdma_mask = ATA_MWDMA12_ONLY,
1231 .udma_mask = ATA_UDMA2,
1232 .port_ops = &piix_vmw_ops,
1233 },
1234
1235
1236
1237
1238
1239 [ich8_sata_snb] =
1240 {
1241 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
1242 .pio_mask = ATA_PIO4,
1243 .mwdma_mask = ATA_MWDMA2,
1244 .udma_mask = ATA_UDMA6,
1245 .port_ops = &piix_sata_ops,
1246 },
1247
1248 [ich8_2port_sata_snb] =
1249 {
1250 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR
1251 | PIIX_FLAG_PIO16,
1252 .pio_mask = ATA_PIO4,
1253 .mwdma_mask = ATA_MWDMA2,
1254 .udma_mask = ATA_UDMA6,
1255 .port_ops = &piix_sata_ops,
1256 },
1257};
1258
1259#define AHCI_PCI_BAR 5
1260#define AHCI_GLOBAL_CTL 0x04
1261#define AHCI_ENABLE (1 << 31)
1262static int piix_disable_ahci(struct pci_dev *pdev)
1263{
1264 void __iomem *mmio;
1265 u32 tmp;
1266 int rc = 0;
1267
1268
1269
1270
1271
1272 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1273 !pci_resource_len(pdev, AHCI_PCI_BAR))
1274 return 0;
1275
1276 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1277 if (!mmio)
1278 return -ENOMEM;
1279
1280 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1281 if (tmp & AHCI_ENABLE) {
1282 tmp &= ~AHCI_ENABLE;
1283 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1284
1285 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1286 if (tmp & AHCI_ENABLE)
1287 rc = -EIO;
1288 }
1289
1290 pci_iounmap(pdev, mmio);
1291 return rc;
1292}
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302static int piix_check_450nx_errata(struct pci_dev *ata_dev)
1303{
1304 struct pci_dev *pdev = NULL;
1305 u16 cfg;
1306 int no_piix_dma = 0;
1307
1308 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1309
1310
1311 pci_read_config_word(pdev, 0x41, &cfg);
1312
1313 if (pdev->revision == 0x00)
1314 no_piix_dma = 1;
1315
1316 else if (cfg & (1<<14) && pdev->revision < 5)
1317 no_piix_dma = 2;
1318 }
1319 if (no_piix_dma)
1320 dev_warn(&ata_dev->dev,
1321 "450NX errata present, disabling IDE DMA%s\n",
1322 no_piix_dma == 2 ? " - a BIOS update may resolve this"
1323 : "");
1324
1325 return no_piix_dma;
1326}
1327
1328static void piix_init_pcs(struct ata_host *host,
1329 const struct piix_map_db *map_db)
1330{
1331 struct pci_dev *pdev = to_pci_dev(host->dev);
1332 u16 pcs, new_pcs;
1333
1334 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1335
1336 new_pcs = pcs | map_db->port_enable;
1337
1338 if (new_pcs != pcs) {
1339 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1340 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1341 msleep(150);
1342 }
1343}
1344
1345static const int *piix_init_sata_map(struct pci_dev *pdev,
1346 struct ata_port_info *pinfo,
1347 const struct piix_map_db *map_db)
1348{
1349 const int *map;
1350 int i, invalid_map = 0;
1351 u8 map_value;
1352
1353 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1354
1355 map = map_db->map[map_value & map_db->mask];
1356
1357 dev_info(&pdev->dev, "MAP [");
1358 for (i = 0; i < 4; i++) {
1359 switch (map[i]) {
1360 case RV:
1361 invalid_map = 1;
1362 pr_cont(" XX");
1363 break;
1364
1365 case NA:
1366 pr_cont(" --");
1367 break;
1368
1369 case IDE:
1370 WARN_ON((i & 1) || map[i + 1] != IDE);
1371 pinfo[i / 2] = piix_port_info[ich_pata_100];
1372 i++;
1373 pr_cont(" IDE IDE");
1374 break;
1375
1376 default:
1377 pr_cont(" P%d", map[i]);
1378 if (i & 1)
1379 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1380 break;
1381 }
1382 }
1383 pr_cont(" ]\n");
1384
1385 if (invalid_map)
1386 dev_err(&pdev->dev, "invalid MAP value %u\n", map_value);
1387
1388 return map;
1389}
1390
1391static bool piix_no_sidpr(struct ata_host *host)
1392{
1393 struct pci_dev *pdev = to_pci_dev(host->dev);
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1414 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1415 pdev->subsystem_device == 0xb049) {
1416 dev_warn(host->dev,
1417 "Samsung DB-P70 detected, disabling SIDPR\n");
1418 return true;
1419 }
1420
1421 return false;
1422}
1423
1424static int piix_init_sidpr(struct ata_host *host)
1425{
1426 struct pci_dev *pdev = to_pci_dev(host->dev);
1427 struct piix_host_priv *hpriv = host->private_data;
1428 struct ata_link *link0 = &host->ports[0]->link;
1429 u32 scontrol;
1430 int i, rc;
1431
1432
1433 for (i = 0; i < 4; i++)
1434 if (hpriv->map[i] == IDE)
1435 return 0;
1436
1437
1438 if (piix_no_sidpr(host))
1439 return 0;
1440
1441 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1442 return 0;
1443
1444 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1445 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1446 return 0;
1447
1448 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1449 return 0;
1450
1451 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1452
1453
1454
1455
1456
1457 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1458
1459
1460
1461
1462
1463 if ((scontrol & 0xf00) != 0x300) {
1464 scontrol |= 0x300;
1465 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1466 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1467
1468 if ((scontrol & 0xf00) != 0x300) {
1469 dev_info(host->dev,
1470 "SCR access via SIDPR is available but doesn't work\n");
1471 return 0;
1472 }
1473 }
1474
1475
1476 for (i = 0; i < 2; i++) {
1477 struct ata_port *ap = host->ports[i];
1478
1479 ap->ops = &piix_sidpr_sata_ops;
1480
1481 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1482 rc = ata_slave_link_init(ap);
1483 if (rc)
1484 return rc;
1485 }
1486 }
1487
1488 return 0;
1489}
1490
1491static void piix_iocfg_bit18_quirk(struct ata_host *host)
1492{
1493 static const struct dmi_system_id sysids[] = {
1494 {
1495
1496
1497
1498
1499 .ident = "M570U",
1500 .matches = {
1501 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1502 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1503 },
1504 },
1505
1506 { }
1507 };
1508 struct pci_dev *pdev = to_pci_dev(host->dev);
1509 struct piix_host_priv *hpriv = host->private_data;
1510
1511 if (!dmi_check_system(sysids))
1512 return;
1513
1514
1515
1516
1517
1518 if (hpriv->saved_iocfg & (1 << 18)) {
1519 dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
1520 pci_write_config_dword(pdev, PIIX_IOCFG,
1521 hpriv->saved_iocfg & ~(1 << 18));
1522 }
1523}
1524
1525static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1526{
1527 static const struct dmi_system_id broken_systems[] = {
1528 {
1529 .ident = "HP Compaq 2510p",
1530 .matches = {
1531 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1532 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1533 },
1534
1535 .driver_data = (void *)0x1FUL,
1536 },
1537 {
1538 .ident = "HP Compaq nc6000",
1539 .matches = {
1540 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1541 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1542 },
1543
1544 .driver_data = (void *)0x1FUL,
1545 },
1546
1547 { }
1548 };
1549 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1550
1551 if (dmi) {
1552 unsigned long slot = (unsigned long)dmi->driver_data;
1553
1554 return slot == PCI_SLOT(pdev->devfn);
1555 }
1556
1557 return false;
1558}
1559
1560static int prefer_ms_hyperv = 1;
1561module_param(prefer_ms_hyperv, int, 0);
1562MODULE_PARM_DESC(prefer_ms_hyperv,
1563 "Prefer Hyper-V paravirtualization drivers instead of ATA, "
1564 "0 - Use ATA drivers, "
1565 "1 (Default) - Use the paravirtualization drivers.");
1566
1567static void piix_ignore_devices_quirk(struct ata_host *host)
1568{
1569#if IS_ENABLED(CONFIG_HYPERV_STORAGE)
1570 static const struct dmi_system_id ignore_hyperv[] = {
1571 {
1572
1573
1574
1575
1576
1577
1578 .ident = "Hyper-V Virtual Machine",
1579 .matches = {
1580 DMI_MATCH(DMI_SYS_VENDOR,
1581 "Microsoft Corporation"),
1582 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1583 },
1584 },
1585 { }
1586 };
1587 static const struct dmi_system_id allow_virtual_pc[] = {
1588 {
1589
1590
1591
1592
1593
1594
1595 .ident = "MS Virtual PC 2007",
1596 .matches = {
1597 DMI_MATCH(DMI_SYS_VENDOR,
1598 "Microsoft Corporation"),
1599 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1600 DMI_MATCH(DMI_PRODUCT_VERSION, "VS2005R2"),
1601 },
1602 },
1603 { }
1604 };
1605 const struct dmi_system_id *ignore = dmi_first_match(ignore_hyperv);
1606 const struct dmi_system_id *allow = dmi_first_match(allow_virtual_pc);
1607
1608 if (ignore && !allow && prefer_ms_hyperv) {
1609 host->flags |= ATA_HOST_IGNORE_ATA;
1610 dev_info(host->dev, "%s detected, ATA device ignore set\n",
1611 ignore->ident);
1612 }
1613#endif
1614}
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1632{
1633 struct device *dev = &pdev->dev;
1634 struct ata_port_info port_info[2];
1635 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1636 struct scsi_host_template *sht = &piix_sht;
1637 unsigned long port_flags;
1638 struct ata_host *host;
1639 struct piix_host_priv *hpriv;
1640 int rc;
1641
1642 ata_print_version_once(&pdev->dev, DRV_VERSION);
1643
1644
1645 if (!in_module_init && ent->driver_data >= ich5_sata)
1646 return -ENODEV;
1647
1648 if (piix_broken_system_poweroff(pdev)) {
1649 piix_port_info[ent->driver_data].flags |=
1650 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1651 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1652 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1653 "on poweroff and hibernation\n");
1654 }
1655
1656 port_info[0] = piix_port_info[ent->driver_data];
1657 port_info[1] = piix_port_info[ent->driver_data];
1658
1659 port_flags = port_info[0].flags;
1660
1661
1662 rc = pcim_enable_device(pdev);
1663 if (rc)
1664 return rc;
1665
1666 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1667 if (!hpriv)
1668 return -ENOMEM;
1669
1670
1671
1672
1673
1674
1675 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1676
1677
1678
1679
1680
1681 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1682 rc = piix_disable_ahci(pdev);
1683 if (rc)
1684 return rc;
1685 }
1686
1687
1688 if (port_flags & ATA_FLAG_SATA)
1689 hpriv->map = piix_init_sata_map(pdev, port_info,
1690 piix_map_db_table[ent->driver_data]);
1691
1692 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
1693 if (rc)
1694 return rc;
1695 host->private_data = hpriv;
1696
1697
1698 if (port_flags & ATA_FLAG_SATA) {
1699 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1700 rc = piix_init_sidpr(host);
1701 if (rc)
1702 return rc;
1703 if (host->ports[0]->ops == &piix_sidpr_sata_ops)
1704 sht = &piix_sidpr_sht;
1705 }
1706
1707
1708 piix_iocfg_bit18_quirk(host);
1709
1710
1711
1712
1713
1714
1715
1716 if (port_flags & PIIX_FLAG_CHECKINTR)
1717 pci_intx(pdev, 1);
1718
1719 if (piix_check_450nx_errata(pdev)) {
1720
1721
1722
1723 host->ports[0]->mwdma_mask = 0;
1724 host->ports[0]->udma_mask = 0;
1725 host->ports[1]->mwdma_mask = 0;
1726 host->ports[1]->udma_mask = 0;
1727 }
1728 host->flags |= ATA_HOST_PARALLEL_SCAN;
1729
1730
1731 piix_ignore_devices_quirk(host);
1732
1733 pci_set_master(pdev);
1734 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
1735}
1736
1737static void piix_remove_one(struct pci_dev *pdev)
1738{
1739 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1740 struct piix_host_priv *hpriv = host->private_data;
1741
1742 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1743
1744 ata_pci_remove_one(pdev);
1745}
1746
1747static struct pci_driver piix_pci_driver = {
1748 .name = DRV_NAME,
1749 .id_table = piix_pci_tbl,
1750 .probe = piix_init_one,
1751 .remove = piix_remove_one,
1752#ifdef CONFIG_PM
1753 .suspend = piix_pci_device_suspend,
1754 .resume = piix_pci_device_resume,
1755#endif
1756};
1757
1758static int __init piix_init(void)
1759{
1760 int rc;
1761
1762 DPRINTK("pci_register_driver\n");
1763 rc = pci_register_driver(&piix_pci_driver);
1764 if (rc)
1765 return rc;
1766
1767 in_module_init = 0;
1768
1769 DPRINTK("done\n");
1770 return 0;
1771}
1772
1773static void __exit piix_exit(void)
1774{
1775 pci_unregister_driver(&piix_pci_driver);
1776}
1777
1778module_init(piix_init);
1779module_exit(piix_exit);
1780
