linux/drivers/ata/ahci_xgene.c
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   1/*
   2 * AppliedMicro X-Gene SoC SATA Host Controller Driver
   3 *
   4 * Copyright (c) 2014, Applied Micro Circuits Corporation
   5 * Author: Loc Ho <lho@apm.com>
   6 *         Tuan Phan <tphan@apm.com>
   7 *         Suman Tripathi <stripathi@apm.com>
   8 *
   9 * This program is free software; you can redistribute  it and/or modify it
  10 * under  the terms of  the GNU General  Public License as published by the
  11 * Free Software Foundation;  either version 2 of the  License, or (at your
  12 * option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21 *
  22 * NOTE: PM support is not currently available.
  23 *
  24 */
  25#include <linux/module.h>
  26#include <linux/platform_device.h>
  27#include <linux/ahci_platform.h>
  28#include <linux/of_address.h>
  29#include <linux/of_irq.h>
  30#include <linux/phy/phy.h>
  31#include "ahci.h"
  32
  33/* Max # of disk per a controller */
  34#define MAX_AHCI_CHN_PERCTR             2
  35
  36/* MUX CSR */
  37#define SATA_ENET_CONFIG_REG            0x00000000
  38#define  CFG_SATA_ENET_SELECT_MASK      0x00000001
  39
  40/* SATA core host controller CSR */
  41#define SLVRDERRATTRIBUTES              0x00000000
  42#define SLVWRERRATTRIBUTES              0x00000004
  43#define MSTRDERRATTRIBUTES              0x00000008
  44#define MSTWRERRATTRIBUTES              0x0000000c
  45#define BUSCTLREG                       0x00000014
  46#define IOFMSTRWAUX                     0x00000018
  47#define INTSTATUSMASK                   0x0000002c
  48#define ERRINTSTATUS                    0x00000030
  49#define ERRINTSTATUSMASK                0x00000034
  50
  51/* SATA host AHCI CSR */
  52#define PORTCFG                         0x000000a4
  53#define  PORTADDR_SET(dst, src) \
  54                (((dst) & ~0x0000003f) | (((u32)(src)) & 0x0000003f))
  55#define PORTPHY1CFG             0x000000a8
  56#define PORTPHY1CFG_FRCPHYRDY_SET(dst, src) \
  57                (((dst) & ~0x00100000) | (((u32)(src) << 0x14) & 0x00100000))
  58#define PORTPHY2CFG                     0x000000ac
  59#define PORTPHY3CFG                     0x000000b0
  60#define PORTPHY4CFG                     0x000000b4
  61#define PORTPHY5CFG                     0x000000b8
  62#define SCTL0                           0x0000012C
  63#define PORTPHY5CFG_RTCHG_SET(dst, src) \
  64                (((dst) & ~0xfff00000) | (((u32)(src) << 0x14) & 0xfff00000))
  65#define PORTAXICFG_EN_CONTEXT_SET(dst, src) \
  66                (((dst) & ~0x01000000) | (((u32)(src) << 0x18) & 0x01000000))
  67#define PORTAXICFG                      0x000000bc
  68#define PORTAXICFG_OUTTRANS_SET(dst, src) \
  69                (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000))
  70
  71/* SATA host controller AXI CSR */
  72#define INT_SLV_TMOMASK                 0x00000010
  73
  74/* SATA diagnostic CSR */
  75#define CFG_MEM_RAM_SHUTDOWN            0x00000070
  76#define BLOCK_MEM_RDY                   0x00000074
  77
  78struct xgene_ahci_context {
  79        struct ahci_host_priv *hpriv;
  80        struct device *dev;
  81        u8 last_cmd[MAX_AHCI_CHN_PERCTR]; /* tracking the last command issued*/
  82        void __iomem *csr_core;         /* Core CSR address of IP */
  83        void __iomem *csr_diag;         /* Diag CSR address of IP */
  84        void __iomem *csr_axi;          /* AXI CSR address of IP */
  85        void __iomem *csr_mux;          /* MUX CSR address of IP */
  86};
  87
  88static int xgene_ahci_init_memram(struct xgene_ahci_context *ctx)
  89{
  90        dev_dbg(ctx->dev, "Release memory from shutdown\n");
  91        writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN);
  92        readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */
  93        msleep(1);      /* reset may take up to 1ms */
  94        if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) {
  95                dev_err(ctx->dev, "failed to release memory from shutdown\n");
  96                return -ENODEV;
  97        }
  98        return 0;
  99}
 100
 101/**
 102 * xgene_ahci_restart_engine - Restart the dma engine.
 103 * @ap : ATA port of interest
 104 *
 105 * Restarts the dma engine inside the controller.
 106 */
 107static int xgene_ahci_restart_engine(struct ata_port *ap)
 108{
 109        struct ahci_host_priv *hpriv = ap->host->private_data;
 110
 111        ahci_stop_engine(ap);
 112        ahci_start_fis_rx(ap);
 113        hpriv->start_engine(ap);
 114
 115        return 0;
 116}
 117
 118/**
 119 * xgene_ahci_qc_issue - Issue commands to the device
 120 * @qc: Command to issue
 121 *
 122 * Due to Hardware errata for IDENTIFY DEVICE command, the controller cannot
 123 * clear the BSY bit after receiving the PIO setup FIS. This results in the dma
 124 * state machine goes into the CMFatalErrorUpdate state and locks up. By
 125 * restarting the dma engine, it removes the controller out of lock up state.
 126 */
 127static unsigned int xgene_ahci_qc_issue(struct ata_queued_cmd *qc)
 128{
 129        struct ata_port *ap = qc->ap;
 130        struct ahci_host_priv *hpriv = ap->host->private_data;
 131        struct xgene_ahci_context *ctx = hpriv->plat_data;
 132        int rc = 0;
 133
 134        if (unlikely(ctx->last_cmd[ap->port_no] == ATA_CMD_ID_ATA))
 135                xgene_ahci_restart_engine(ap);
 136
 137        rc = ahci_qc_issue(qc);
 138
 139        /* Save the last command issued */
 140        ctx->last_cmd[ap->port_no] = qc->tf.command;
 141
 142        return rc;
 143}
 144
 145/**
 146 * xgene_ahci_read_id - Read ID data from the specified device
 147 * @dev: device
 148 * @tf: proposed taskfile
 149 * @id: data buffer
 150 *
 151 * This custom read ID function is required due to the fact that the HW
 152 * does not support DEVSLP.
 153 */
 154static unsigned int xgene_ahci_read_id(struct ata_device *dev,
 155                                       struct ata_taskfile *tf, u16 *id)
 156{
 157        u32 err_mask;
 158
 159        err_mask = ata_do_dev_read_id(dev, tf, id);
 160        if (err_mask)
 161                return err_mask;
 162
 163        /*
 164         * Mask reserved area. Word78 spec of Link Power Management
 165         * bit15-8: reserved
 166         * bit7: NCQ autosence
 167         * bit6: Software settings preservation supported
 168         * bit5: reserved
 169         * bit4: In-order sata delivery supported
 170         * bit3: DIPM requests supported
 171         * bit2: DMA Setup FIS Auto-Activate optimization supported
 172         * bit1: DMA Setup FIX non-Zero buffer offsets supported
 173         * bit0: Reserved
 174         *
 175         * Clear reserved bit 8 (DEVSLP bit) as we don't support DEVSLP
 176         */
 177        id[ATA_ID_FEATURE_SUPP] &= ~(1 << 8);
 178
 179        return 0;
 180}
 181
 182static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)
 183{
 184        void __iomem *mmio = ctx->hpriv->mmio;
 185        u32 val;
 186
 187        dev_dbg(ctx->dev, "port configure mmio 0x%p channel %d\n",
 188                mmio, channel);
 189        val = readl(mmio + PORTCFG);
 190        val = PORTADDR_SET(val, channel == 0 ? 2 : 3);
 191        writel(val, mmio + PORTCFG);
 192        readl(mmio + PORTCFG);  /* Force a barrier */
 193        /* Disable fix rate */
 194        writel(0x0001fffe, mmio + PORTPHY1CFG);
 195        readl(mmio + PORTPHY1CFG); /* Force a barrier */
 196        writel(0x5018461c, mmio + PORTPHY2CFG);
 197        readl(mmio + PORTPHY2CFG); /* Force a barrier */
 198        writel(0x1c081907, mmio + PORTPHY3CFG);
 199        readl(mmio + PORTPHY3CFG); /* Force a barrier */
 200        writel(0x1c080815, mmio + PORTPHY4CFG);
 201        readl(mmio + PORTPHY4CFG); /* Force a barrier */
 202        /* Set window negotiation */
 203        val = readl(mmio + PORTPHY5CFG);
 204        val = PORTPHY5CFG_RTCHG_SET(val, 0x300);
 205        writel(val, mmio + PORTPHY5CFG);
 206        readl(mmio + PORTPHY5CFG); /* Force a barrier */
 207        val = readl(mmio + PORTAXICFG);
 208        val = PORTAXICFG_EN_CONTEXT_SET(val, 0x1); /* Enable context mgmt */
 209        val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */
 210        writel(val, mmio + PORTAXICFG);
 211        readl(mmio + PORTAXICFG); /* Force a barrier */
 212}
 213
 214/**
 215 * xgene_ahci_do_hardreset - Issue the actual COMRESET
 216 * @link: link to reset
 217 * @deadline: deadline jiffies for the operation
 218 * @online: Return value to indicate if device online
 219 *
 220 * Due to the limitation of the hardware PHY, a difference set of setting is
 221 * required for each supported disk speed - Gen3 (6.0Gbps), Gen2 (3.0Gbps),
 222 * and Gen1 (1.5Gbps). Otherwise during long IO stress test, the PHY will
 223 * report disparity error and etc. In addition, during COMRESET, there can
 224 * be error reported in the register PORT_SCR_ERR. For SERR_DISPARITY and
 225 * SERR_10B_8B_ERR, the PHY receiver line must be reseted. The following
 226 * algorithm is followed to proper configure the hardware PHY during COMRESET:
 227 *
 228 * Alg Part 1:
 229 * 1. Start the PHY at Gen3 speed (default setting)
 230 * 2. Issue the COMRESET
 231 * 3. If no link, go to Alg Part 3
 232 * 4. If link up, determine if the negotiated speed matches the PHY
 233 *    configured speed
 234 * 5. If they matched, go to Alg Part 2
 235 * 6. If they do not matched and first time, configure the PHY for the linked
 236 *    up disk speed and repeat step 2
 237 * 7. Go to Alg Part 2
 238 *
 239 * Alg Part 2:
 240 * 1. On link up, if there are any SERR_DISPARITY and SERR_10B_8B_ERR error
 241 *    reported in the register PORT_SCR_ERR, then reset the PHY receiver line
 242 * 2. Go to Alg Part 3
 243 *
 244 * Alg Part 3:
 245 * 1. Clear any pending from register PORT_SCR_ERR.
 246 *
 247 * NOTE: For the initial version, we will NOT support Gen1/Gen2. In addition
 248 *       and until the underlying PHY supports an method to reset the receiver
 249 *       line, on detection of SERR_DISPARITY or SERR_10B_8B_ERR errors,
 250 *       an warning message will be printed.
 251 */
 252static int xgene_ahci_do_hardreset(struct ata_link *link,
 253                                   unsigned long deadline, bool *online)
 254{
 255        const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
 256        struct ata_port *ap = link->ap;
 257        struct ahci_host_priv *hpriv = ap->host->private_data;
 258        struct xgene_ahci_context *ctx = hpriv->plat_data;
 259        struct ahci_port_priv *pp = ap->private_data;
 260        u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
 261        void __iomem *port_mmio = ahci_port_base(ap);
 262        struct ata_taskfile tf;
 263        int rc;
 264        u32 val;
 265
 266        /* clear D2H reception area to properly wait for D2H FIS */
 267        ata_tf_init(link->device, &tf);
 268        tf.command = ATA_BUSY;
 269        ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 270        rc = sata_link_hardreset(link, timing, deadline, online,
 271                                 ahci_check_ready);
 272
 273        val = readl(port_mmio + PORT_SCR_ERR);
 274        if (val & (SERR_DISPARITY | SERR_10B_8B_ERR))
 275                dev_warn(ctx->dev, "link has error\n");
 276
 277        /* clear all errors if any pending */
 278        val = readl(port_mmio + PORT_SCR_ERR);
 279        writel(val, port_mmio + PORT_SCR_ERR);
 280
 281        return rc;
 282}
 283
 284static int xgene_ahci_hardreset(struct ata_link *link, unsigned int *class,
 285                                unsigned long deadline)
 286{
 287        struct ata_port *ap = link->ap;
 288        struct ahci_host_priv *hpriv = ap->host->private_data;
 289        void __iomem *port_mmio = ahci_port_base(ap);
 290        bool online;
 291        int rc;
 292        u32 portcmd_saved;
 293        u32 portclb_saved;
 294        u32 portclbhi_saved;
 295        u32 portrxfis_saved;
 296        u32 portrxfishi_saved;
 297
 298        /* As hardreset resets these CSR, save it to restore later */
 299        portcmd_saved = readl(port_mmio + PORT_CMD);
 300        portclb_saved = readl(port_mmio + PORT_LST_ADDR);
 301        portclbhi_saved = readl(port_mmio + PORT_LST_ADDR_HI);
 302        portrxfis_saved = readl(port_mmio + PORT_FIS_ADDR);
 303        portrxfishi_saved = readl(port_mmio + PORT_FIS_ADDR_HI);
 304
 305        ahci_stop_engine(ap);
 306
 307        rc = xgene_ahci_do_hardreset(link, deadline, &online);
 308
 309        /* As controller hardreset clears them, restore them */
 310        writel(portcmd_saved, port_mmio + PORT_CMD);
 311        writel(portclb_saved, port_mmio + PORT_LST_ADDR);
 312        writel(portclbhi_saved, port_mmio + PORT_LST_ADDR_HI);
 313        writel(portrxfis_saved, port_mmio + PORT_FIS_ADDR);
 314        writel(portrxfishi_saved, port_mmio + PORT_FIS_ADDR_HI);
 315
 316        hpriv->start_engine(ap);
 317
 318        if (online)
 319                *class = ahci_dev_classify(ap);
 320
 321        return rc;
 322}
 323
 324static void xgene_ahci_host_stop(struct ata_host *host)
 325{
 326        struct ahci_host_priv *hpriv = host->private_data;
 327
 328        ahci_platform_disable_resources(hpriv);
 329}
 330
 331static struct ata_port_operations xgene_ahci_ops = {
 332        .inherits = &ahci_ops,
 333        .host_stop = xgene_ahci_host_stop,
 334        .hardreset = xgene_ahci_hardreset,
 335        .read_id = xgene_ahci_read_id,
 336        .qc_issue = xgene_ahci_qc_issue,
 337};
 338
 339static const struct ata_port_info xgene_ahci_port_info = {
 340        .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
 341        .pio_mask = ATA_PIO4,
 342        .udma_mask = ATA_UDMA6,
 343        .port_ops = &xgene_ahci_ops,
 344};
 345
 346static int xgene_ahci_hw_init(struct ahci_host_priv *hpriv)
 347{
 348        struct xgene_ahci_context *ctx = hpriv->plat_data;
 349        int i;
 350        int rc;
 351        u32 val;
 352
 353        /* Remove IP RAM out of shutdown */
 354        rc = xgene_ahci_init_memram(ctx);
 355        if (rc)
 356                return rc;
 357
 358        for (i = 0; i < MAX_AHCI_CHN_PERCTR; i++)
 359                xgene_ahci_set_phy_cfg(ctx, i);
 360
 361        /* AXI disable Mask */
 362        writel(0xffffffff, hpriv->mmio + HOST_IRQ_STAT);
 363        readl(hpriv->mmio + HOST_IRQ_STAT); /* Force a barrier */
 364        writel(0, ctx->csr_core + INTSTATUSMASK);
 365        val = readl(ctx->csr_core + INTSTATUSMASK); /* Force a barrier */
 366        dev_dbg(ctx->dev, "top level interrupt mask 0x%X value 0x%08X\n",
 367                INTSTATUSMASK, val);
 368
 369        writel(0x0, ctx->csr_core + ERRINTSTATUSMASK);
 370        readl(ctx->csr_core + ERRINTSTATUSMASK); /* Force a barrier */
 371        writel(0x0, ctx->csr_axi + INT_SLV_TMOMASK);
 372        readl(ctx->csr_axi + INT_SLV_TMOMASK);
 373
 374        /* Enable AXI Interrupt */
 375        writel(0xffffffff, ctx->csr_core + SLVRDERRATTRIBUTES);
 376        writel(0xffffffff, ctx->csr_core + SLVWRERRATTRIBUTES);
 377        writel(0xffffffff, ctx->csr_core + MSTRDERRATTRIBUTES);
 378        writel(0xffffffff, ctx->csr_core + MSTWRERRATTRIBUTES);
 379
 380        /* Enable coherency */
 381        val = readl(ctx->csr_core + BUSCTLREG);
 382        val &= ~0x00000002;     /* Enable write coherency */
 383        val &= ~0x00000001;     /* Enable read coherency */
 384        writel(val, ctx->csr_core + BUSCTLREG);
 385
 386        val = readl(ctx->csr_core + IOFMSTRWAUX);
 387        val |= (1 << 3);        /* Enable read coherency */
 388        val |= (1 << 9);        /* Enable write coherency */
 389        writel(val, ctx->csr_core + IOFMSTRWAUX);
 390        val = readl(ctx->csr_core + IOFMSTRWAUX);
 391        dev_dbg(ctx->dev, "coherency 0x%X value 0x%08X\n",
 392                IOFMSTRWAUX, val);
 393
 394        return rc;
 395}
 396
 397static int xgene_ahci_mux_select(struct xgene_ahci_context *ctx)
 398{
 399        u32 val;
 400
 401        /* Check for optional MUX resource */
 402        if (IS_ERR(ctx->csr_mux))
 403                return 0;
 404
 405        val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
 406        val &= ~CFG_SATA_ENET_SELECT_MASK;
 407        writel(val, ctx->csr_mux + SATA_ENET_CONFIG_REG);
 408        val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
 409        return val & CFG_SATA_ENET_SELECT_MASK ? -1 : 0;
 410}
 411
 412static int xgene_ahci_probe(struct platform_device *pdev)
 413{
 414        struct device *dev = &pdev->dev;
 415        struct ahci_host_priv *hpriv;
 416        struct xgene_ahci_context *ctx;
 417        struct resource *res;
 418        unsigned long hflags;
 419        int rc;
 420
 421        hpriv = ahci_platform_get_resources(pdev);
 422        if (IS_ERR(hpriv))
 423                return PTR_ERR(hpriv);
 424
 425        ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 426        if (!ctx)
 427                return -ENOMEM;
 428
 429        hpriv->plat_data = ctx;
 430        ctx->hpriv = hpriv;
 431        ctx->dev = dev;
 432
 433        /* Retrieve the IP core resource */
 434        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 435        ctx->csr_core = devm_ioremap_resource(dev, res);
 436        if (IS_ERR(ctx->csr_core))
 437                return PTR_ERR(ctx->csr_core);
 438
 439        /* Retrieve the IP diagnostic resource */
 440        res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
 441        ctx->csr_diag = devm_ioremap_resource(dev, res);
 442        if (IS_ERR(ctx->csr_diag))
 443                return PTR_ERR(ctx->csr_diag);
 444
 445        /* Retrieve the IP AXI resource */
 446        res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
 447        ctx->csr_axi = devm_ioremap_resource(dev, res);
 448        if (IS_ERR(ctx->csr_axi))
 449                return PTR_ERR(ctx->csr_axi);
 450
 451        /* Retrieve the optional IP mux resource */
 452        res = platform_get_resource(pdev, IORESOURCE_MEM, 4);
 453        ctx->csr_mux = devm_ioremap_resource(dev, res);
 454
 455        dev_dbg(dev, "VAddr 0x%p Mmio VAddr 0x%p\n", ctx->csr_core,
 456                hpriv->mmio);
 457
 458        /* Select ATA */
 459        if ((rc = xgene_ahci_mux_select(ctx))) {
 460                dev_err(dev, "SATA mux selection failed error %d\n", rc);
 461                return -ENODEV;
 462        }
 463
 464        /* Due to errata, HW requires full toggle transition */
 465        rc = ahci_platform_enable_clks(hpriv);
 466        if (rc)
 467                goto disable_resources;
 468        ahci_platform_disable_clks(hpriv);
 469
 470        rc = ahci_platform_enable_resources(hpriv);
 471        if (rc)
 472                goto disable_resources;
 473
 474        /* Configure the host controller */
 475        xgene_ahci_hw_init(hpriv);
 476
 477        /*
 478         * Setup DMA mask. This is preliminary until the DMA range is sorted
 479         * out.
 480         */
 481        rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
 482        if (rc) {
 483                dev_err(dev, "Unable to set dma mask\n");
 484                goto disable_resources;
 485        }
 486
 487        hflags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ;
 488
 489        rc = ahci_platform_init_host(pdev, hpriv, &xgene_ahci_port_info,
 490                                     hflags, 0, 0);
 491        if (rc)
 492                goto disable_resources;
 493
 494        dev_dbg(dev, "X-Gene SATA host controller initialized\n");
 495        return 0;
 496
 497disable_resources:
 498        ahci_platform_disable_resources(hpriv);
 499        return rc;
 500}
 501
 502static const struct of_device_id xgene_ahci_of_match[] = {
 503        {.compatible = "apm,xgene-ahci"},
 504        {},
 505};
 506MODULE_DEVICE_TABLE(of, xgene_ahci_of_match);
 507
 508static struct platform_driver xgene_ahci_driver = {
 509        .probe = xgene_ahci_probe,
 510        .remove = ata_platform_remove_one,
 511        .driver = {
 512                .name = "xgene-ahci",
 513                .owner = THIS_MODULE,
 514                .of_match_table = xgene_ahci_of_match,
 515        },
 516};
 517
 518module_platform_driver(xgene_ahci_driver);
 519
 520MODULE_DESCRIPTION("APM X-Gene AHCI SATA driver");
 521MODULE_AUTHOR("Loc Ho <lho@apm.com>");
 522MODULE_LICENSE("GPL");
 523MODULE_VERSION("0.4");
 524
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