linux/drivers/ata/ahci.c
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   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 *  ahci.c - AHCI SATA support
   4 *
   5 *  Maintained by:  Tejun Heo <tj@kernel.org>
   6 *                  Please ALWAYS copy linux-ide@vger.kernel.org
   7 *                  on emails.
   8 *
   9 *  Copyright 2004-2005 Red Hat, Inc.
  10 *
  11 * libata documentation is available via 'make {ps|pdf}docs',
  12 * as Documentation/driver-api/libata.rst
  13 *
  14 * AHCI hardware documentation:
  15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
  16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
  17 */
  18
  19#include <linux/kernel.h>
  20#include <linux/module.h>
  21#include <linux/pci.h>
  22#include <linux/blkdev.h>
  23#include <linux/delay.h>
  24#include <linux/interrupt.h>
  25#include <linux/dma-mapping.h>
  26#include <linux/device.h>
  27#include <linux/dmi.h>
  28#include <linux/gfp.h>
  29#include <linux/msi.h>
  30#include <scsi/scsi_host.h>
  31#include <scsi/scsi_cmnd.h>
  32#include <linux/libata.h>
  33#include <linux/ahci-remap.h>
  34#include <linux/io-64-nonatomic-lo-hi.h>
  35#include "ahci.h"
  36
  37#define DRV_NAME        "ahci"
  38#define DRV_VERSION     "3.0"
  39
  40enum {
  41        AHCI_PCI_BAR_STA2X11    = 0,
  42        AHCI_PCI_BAR_CAVIUM     = 0,
  43        AHCI_PCI_BAR_LOONGSON   = 0,
  44        AHCI_PCI_BAR_ENMOTUS    = 2,
  45        AHCI_PCI_BAR_CAVIUM_GEN5        = 4,
  46        AHCI_PCI_BAR_STANDARD   = 5,
  47};
  48
  49enum board_ids {
  50        /* board IDs by feature in alphabetical order */
  51        board_ahci,
  52        board_ahci_ign_iferr,
  53        board_ahci_mobile,
  54        board_ahci_no_debounce_delay,
  55        board_ahci_nomsi,
  56        board_ahci_noncq,
  57        board_ahci_nosntf,
  58        board_ahci_yes_fbs,
  59
  60        /* board IDs for specific chipsets in alphabetical order */
  61        board_ahci_al,
  62        board_ahci_avn,
  63        board_ahci_mcp65,
  64        board_ahci_mcp77,
  65        board_ahci_mcp89,
  66        board_ahci_mv,
  67        board_ahci_sb600,
  68        board_ahci_sb700,       /* for SB700 and SB800 */
  69        board_ahci_vt8251,
  70
  71        /*
  72         * board IDs for Intel chipsets that support more than 6 ports
  73         * *and* end up needing the PCS quirk.
  74         */
  75        board_ahci_pcs7,
  76
  77        /* aliases */
  78        board_ahci_mcp_linux    = board_ahci_mcp65,
  79        board_ahci_mcp67        = board_ahci_mcp65,
  80        board_ahci_mcp73        = board_ahci_mcp65,
  81        board_ahci_mcp79        = board_ahci_mcp77,
  82};
  83
  84static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  85static void ahci_remove_one(struct pci_dev *dev);
  86static void ahci_shutdown_one(struct pci_dev *dev);
  87static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
  88                                 unsigned long deadline);
  89static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
  90                              unsigned long deadline);
  91static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
  92static bool is_mcp89_apple(struct pci_dev *pdev);
  93static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
  94                                unsigned long deadline);
  95#ifdef CONFIG_PM
  96static int ahci_pci_device_runtime_suspend(struct device *dev);
  97static int ahci_pci_device_runtime_resume(struct device *dev);
  98#ifdef CONFIG_PM_SLEEP
  99static int ahci_pci_device_suspend(struct device *dev);
 100static int ahci_pci_device_resume(struct device *dev);
 101#endif
 102#endif /* CONFIG_PM */
 103
 104static struct scsi_host_template ahci_sht = {
 105        AHCI_SHT("ahci"),
 106};
 107
 108static struct ata_port_operations ahci_vt8251_ops = {
 109        .inherits               = &ahci_ops,
 110        .hardreset              = ahci_vt8251_hardreset,
 111};
 112
 113static struct ata_port_operations ahci_p5wdh_ops = {
 114        .inherits               = &ahci_ops,
 115        .hardreset              = ahci_p5wdh_hardreset,
 116};
 117
 118static struct ata_port_operations ahci_avn_ops = {
 119        .inherits               = &ahci_ops,
 120        .hardreset              = ahci_avn_hardreset,
 121};
 122
 123static const struct ata_port_info ahci_port_info[] = {
 124        /* by features */
 125        [board_ahci] = {
 126                .flags          = AHCI_FLAG_COMMON,
 127                .pio_mask       = ATA_PIO4,
 128                .udma_mask      = ATA_UDMA6,
 129                .port_ops       = &ahci_ops,
 130        },
 131        [board_ahci_ign_iferr] = {
 132                AHCI_HFLAGS     (AHCI_HFLAG_IGN_IRQ_IF_ERR),
 133                .flags          = AHCI_FLAG_COMMON,
 134                .pio_mask       = ATA_PIO4,
 135                .udma_mask      = ATA_UDMA6,
 136                .port_ops       = &ahci_ops,
 137        },
 138        [board_ahci_mobile] = {
 139                AHCI_HFLAGS     (AHCI_HFLAG_IS_MOBILE),
 140                .flags          = AHCI_FLAG_COMMON,
 141                .pio_mask       = ATA_PIO4,
 142                .udma_mask      = ATA_UDMA6,
 143                .port_ops       = &ahci_ops,
 144        },
 145        [board_ahci_no_debounce_delay] = {
 146                .flags          = AHCI_FLAG_COMMON,
 147                .link_flags     = ATA_LFLAG_NO_DEBOUNCE_DELAY,
 148                .pio_mask       = ATA_PIO4,
 149                .udma_mask      = ATA_UDMA6,
 150                .port_ops       = &ahci_ops,
 151        },
 152        [board_ahci_nomsi] = {
 153                AHCI_HFLAGS     (AHCI_HFLAG_NO_MSI),
 154                .flags          = AHCI_FLAG_COMMON,
 155                .pio_mask       = ATA_PIO4,
 156                .udma_mask      = ATA_UDMA6,
 157                .port_ops       = &ahci_ops,
 158        },
 159        [board_ahci_noncq] = {
 160                AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ),
 161                .flags          = AHCI_FLAG_COMMON,
 162                .pio_mask       = ATA_PIO4,
 163                .udma_mask      = ATA_UDMA6,
 164                .port_ops       = &ahci_ops,
 165        },
 166        [board_ahci_nosntf] = {
 167                AHCI_HFLAGS     (AHCI_HFLAG_NO_SNTF),
 168                .flags          = AHCI_FLAG_COMMON,
 169                .pio_mask       = ATA_PIO4,
 170                .udma_mask      = ATA_UDMA6,
 171                .port_ops       = &ahci_ops,
 172        },
 173        [board_ahci_yes_fbs] = {
 174                AHCI_HFLAGS     (AHCI_HFLAG_YES_FBS),
 175                .flags          = AHCI_FLAG_COMMON,
 176                .pio_mask       = ATA_PIO4,
 177                .udma_mask      = ATA_UDMA6,
 178                .port_ops       = &ahci_ops,
 179        },
 180        /* by chipsets */
 181        [board_ahci_al] = {
 182                AHCI_HFLAGS     (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
 183                .flags          = AHCI_FLAG_COMMON,
 184                .pio_mask       = ATA_PIO4,
 185                .udma_mask      = ATA_UDMA6,
 186                .port_ops       = &ahci_ops,
 187        },
 188        [board_ahci_avn] = {
 189                .flags          = AHCI_FLAG_COMMON,
 190                .pio_mask       = ATA_PIO4,
 191                .udma_mask      = ATA_UDMA6,
 192                .port_ops       = &ahci_avn_ops,
 193        },
 194        [board_ahci_mcp65] = {
 195                AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
 196                                 AHCI_HFLAG_YES_NCQ),
 197                .flags          = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
 198                .pio_mask       = ATA_PIO4,
 199                .udma_mask      = ATA_UDMA6,
 200                .port_ops       = &ahci_ops,
 201        },
 202        [board_ahci_mcp77] = {
 203                AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
 204                .flags          = AHCI_FLAG_COMMON,
 205                .pio_mask       = ATA_PIO4,
 206                .udma_mask      = ATA_UDMA6,
 207                .port_ops       = &ahci_ops,
 208        },
 209        [board_ahci_mcp89] = {
 210                AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA),
 211                .flags          = AHCI_FLAG_COMMON,
 212                .pio_mask       = ATA_PIO4,
 213                .udma_mask      = ATA_UDMA6,
 214                .port_ops       = &ahci_ops,
 215        },
 216        [board_ahci_mv] = {
 217                AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
 218                                 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
 219                .flags          = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
 220                .pio_mask       = ATA_PIO4,
 221                .udma_mask      = ATA_UDMA6,
 222                .port_ops       = &ahci_ops,
 223        },
 224        [board_ahci_sb600] = {
 225                AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL |
 226                                 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
 227                                 AHCI_HFLAG_32BIT_ONLY),
 228                .flags          = AHCI_FLAG_COMMON,
 229                .pio_mask       = ATA_PIO4,
 230                .udma_mask      = ATA_UDMA6,
 231                .port_ops       = &ahci_pmp_retry_srst_ops,
 232        },
 233        [board_ahci_sb700] = {  /* for SB700 and SB800 */
 234                AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL),
 235                .flags          = AHCI_FLAG_COMMON,
 236                .pio_mask       = ATA_PIO4,
 237                .udma_mask      = ATA_UDMA6,
 238                .port_ops       = &ahci_pmp_retry_srst_ops,
 239        },
 240        [board_ahci_vt8251] = {
 241                AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
 242                .flags          = AHCI_FLAG_COMMON,
 243                .pio_mask       = ATA_PIO4,
 244                .udma_mask      = ATA_UDMA6,
 245                .port_ops       = &ahci_vt8251_ops,
 246        },
 247        [board_ahci_pcs7] = {
 248                .flags          = AHCI_FLAG_COMMON,
 249                .pio_mask       = ATA_PIO4,
 250                .udma_mask      = ATA_UDMA6,
 251                .port_ops       = &ahci_ops,
 252        },
 253};
 254
 255static const struct pci_device_id ahci_pci_tbl[] = {
 256        /* Intel */
 257        { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
 258        { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
 259        { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
 260        { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
 261        { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
 262        { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
 263        { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
 264        { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
 265        { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
 266        { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
 267        { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
 268        { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
 269        { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8/Lewisburg RAID*/
 270        { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
 271        { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
 272        { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
 273        { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
 274        { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
 275        { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
 276        { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
 277        { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
 278        { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
 279        { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
 280        { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
 281        { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
 282        { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
 283        { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
 284        { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
 285        { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
 286        { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
 287        { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
 288        { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
 289        { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
 290        { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
 291        { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
 292        { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
 293        { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
 294        { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
 295        { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
 296        { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
 297        { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
 298        { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
 299        { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
 300        { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
 301        { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
 302        { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
 303        { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
 304        { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
 305        { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
 306        { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
 307        { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
 308        { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
 309        { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
 310        { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
 311        { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
 312        { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
 313        { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
 314        { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
 315        { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
 316        { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
 317        { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
 318        { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
 319        { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
 320        { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
 321        { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
 322        { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
 323        { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
 324        { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
 325        { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
 326        { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
 327        { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG/Lewisburg RAID*/
 328        { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
 329        { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
 330        { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
 331        { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
 332        { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
 333        { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
 334        { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
 335        { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
 336        { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
 337        { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
 338        { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
 339        { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
 340        { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
 341        { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
 342        { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
 343        { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
 344        { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
 345        { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
 346        { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
 347        { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
 348        { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
 349        { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
 350        { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
 351        { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
 352        { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
 353        { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
 354        { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
 355        { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
 356        { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
 357        { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
 358        { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
 359        { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
 360        { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
 361        { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
 362        { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
 363        { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
 364        { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
 365        { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
 366        { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
 367        { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
 368        { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
 369        { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg/Lewisburg AHCI*/
 370        { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg/Lewisburg RAID*/
 371        { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
 372        { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
 373        { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
 374        { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
 375        { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
 376        { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
 377        { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
 378        { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
 379        { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
 380        { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
 381        { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
 382        { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
 383        { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
 384        { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
 385        { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
 386        { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
 387        { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
 388        { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
 389        { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
 390        { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
 391        { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
 392        { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
 393        { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
 394        { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
 395        { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
 396        { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
 397        { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
 398        { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
 399        { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
 400        { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
 401        { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
 402        { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
 403        { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
 404        { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
 405        { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
 406        { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
 407        { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
 408        { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
 409        { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
 410        { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
 411        { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
 412        { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
 413        { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
 414        { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
 415        { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
 416        { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
 417        { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
 418        { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
 419        { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
 420        { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
 421        { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_mobile }, /* Comet Lake PCH-U AHCI */
 422        { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_mobile }, /* Comet Lake PCH RAID */
 423
 424        /* JMicron 360/1/3/5/6, match class to avoid IDE function */
 425        { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 426          PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
 427        /* JMicron 362B and 362C have an AHCI function with IDE class code */
 428        { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
 429        { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
 430        /* May need to update quirk_jmicron_async_suspend() for additions */
 431
 432        /* ATI */
 433        { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
 434        { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
 435        { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
 436        { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
 437        { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
 438        { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
 439        { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
 440
 441        /* Amazon's Annapurna Labs support */
 442        { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
 443                .class = PCI_CLASS_STORAGE_SATA_AHCI,
 444                .class_mask = 0xffffff,
 445                board_ahci_al },
 446        /* AMD */
 447        { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
 448        { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
 449        { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
 450        { PCI_VDEVICE(AMD, 0x7901), board_ahci_mobile }, /* AMD Green Sardine */
 451        /* AMD is using RAID class only for ahci controllers */
 452        { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 453          PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
 454
 455        /* Dell S140/S150 */
 456        { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
 457          PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
 458
 459        /* VIA */
 460        { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
 461        { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
 462
 463        /* NVIDIA */
 464        { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 },      /* MCP65 */
 465        { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 },      /* MCP65 */
 466        { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 },      /* MCP65 */
 467        { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 },      /* MCP65 */
 468        { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 },      /* MCP65 */
 469        { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 },      /* MCP65 */
 470        { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 },      /* MCP65 */
 471        { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 },      /* MCP65 */
 472        { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 },      /* MCP67 */
 473        { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 },      /* MCP67 */
 474        { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 },      /* MCP67 */
 475        { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 },      /* MCP67 */
 476        { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 },      /* MCP67 */
 477        { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 },      /* MCP67 */
 478        { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 },      /* MCP67 */
 479        { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 },      /* MCP67 */
 480        { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 },      /* MCP67 */
 481        { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 },      /* MCP67 */
 482        { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 },      /* MCP67 */
 483        { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 },      /* MCP67 */
 484        { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux },  /* Linux ID */
 485        { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux },  /* Linux ID */
 486        { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux },  /* Linux ID */
 487        { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux },  /* Linux ID */
 488        { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux },  /* Linux ID */
 489        { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux },  /* Linux ID */
 490        { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux },  /* Linux ID */
 491        { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux },  /* Linux ID */
 492        { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux },  /* Linux ID */
 493        { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux },  /* Linux ID */
 494        { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux },  /* Linux ID */
 495        { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux },  /* Linux ID */
 496        { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux },  /* Linux ID */
 497        { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux },  /* Linux ID */
 498        { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux },  /* Linux ID */
 499        { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux },  /* Linux ID */
 500        { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 },      /* MCP73 */
 501        { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 },      /* MCP73 */
 502        { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 },      /* MCP73 */
 503        { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 },      /* MCP73 */
 504        { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 },      /* MCP73 */
 505        { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 },      /* MCP73 */
 506        { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 },      /* MCP73 */
 507        { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 },      /* MCP73 */
 508        { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 },      /* MCP73 */
 509        { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 },      /* MCP73 */
 510        { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 },      /* MCP73 */
 511        { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 },      /* MCP73 */
 512        { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 },      /* MCP77 */
 513        { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 },      /* MCP77 */
 514        { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 },      /* MCP77 */
 515        { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 },      /* MCP77 */
 516        { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 },      /* MCP77 */
 517        { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 },      /* MCP77 */
 518        { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 },      /* MCP77 */
 519        { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 },      /* MCP77 */
 520        { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 },      /* MCP77 */
 521        { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 },      /* MCP77 */
 522        { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 },      /* MCP77 */
 523        { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 },      /* MCP77 */
 524        { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 },      /* MCP79 */
 525        { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 },      /* MCP79 */
 526        { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 },      /* MCP79 */
 527        { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 },      /* MCP79 */
 528        { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 },      /* MCP79 */
 529        { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 },      /* MCP79 */
 530        { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 },      /* MCP79 */
 531        { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 },      /* MCP79 */
 532        { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 },      /* MCP79 */
 533        { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 },      /* MCP79 */
 534        { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 },      /* MCP79 */
 535        { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 },      /* MCP79 */
 536        { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 },      /* MCP89 */
 537        { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 },      /* MCP89 */
 538        { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 },      /* MCP89 */
 539        { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 },      /* MCP89 */
 540        { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 },      /* MCP89 */
 541        { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 },      /* MCP89 */
 542        { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 },      /* MCP89 */
 543        { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 },      /* MCP89 */
 544        { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 },      /* MCP89 */
 545        { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 },      /* MCP89 */
 546        { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 },      /* MCP89 */
 547        { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 },      /* MCP89 */
 548
 549        /* SiS */
 550        { PCI_VDEVICE(SI, 0x1184), board_ahci },                /* SiS 966 */
 551        { PCI_VDEVICE(SI, 0x1185), board_ahci },                /* SiS 968 */
 552        { PCI_VDEVICE(SI, 0x0186), board_ahci },                /* SiS 968 */
 553
 554        /* ST Microelectronics */
 555        { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci },           /* ST ConneXt */
 556
 557        /* Marvell */
 558        { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },        /* 6145 */
 559        { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },        /* 6121 */
 560        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
 561          .class = PCI_CLASS_STORAGE_SATA_AHCI,
 562          .class_mask = 0xffffff,
 563          .driver_data = board_ahci_yes_fbs },                  /* 88se9128 */
 564        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
 565          .driver_data = board_ahci_yes_fbs },                  /* 88se9125 */
 566        { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
 567                         PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
 568          .driver_data = board_ahci_yes_fbs },                  /* 88se9170 */
 569        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
 570          .driver_data = board_ahci_yes_fbs },                  /* 88se9172 */
 571        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
 572          .driver_data = board_ahci_yes_fbs },                  /* 88se9182 */
 573        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
 574          .driver_data = board_ahci_yes_fbs },                  /* 88se9172 */
 575        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
 576          .driver_data = board_ahci_yes_fbs },                  /* 88se9172 on some Gigabyte */
 577        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
 578          .driver_data = board_ahci_yes_fbs },
 579        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2),        /* 88se91a2 */
 580          .driver_data = board_ahci_yes_fbs },
 581        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
 582          .driver_data = board_ahci_yes_fbs },
 583        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
 584          .driver_data = board_ahci_yes_fbs },
 585        { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
 586          .driver_data = board_ahci_yes_fbs },
 587        { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
 588          .driver_data = board_ahci_yes_fbs },
 589
 590        /* Promise */
 591        { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci },   /* PDC42819 */
 592        { PCI_VDEVICE(PROMISE, 0x3781), board_ahci },   /* FastTrak TX8660 ahci-mode */
 593
 594        /* Asmedia */
 595        { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci },   /* ASM1060 */
 596        { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci },   /* ASM1060 */
 597        { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci },   /* ASM1061 */
 598        { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci },   /* ASM1062 */
 599        { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci },   /* ASM1061R */
 600        { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci },   /* ASM1062R */
 601        { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci },   /* ASM1062+JMB575 */
 602
 603        /*
 604         * Samsung SSDs found on some macbooks.  NCQ times out if MSI is
 605         * enabled.  https://bugzilla.kernel.org/show_bug.cgi?id=60731
 606         */
 607        { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
 608        { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
 609
 610        /* Enmotus */
 611        { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
 612
 613        /* Loongson */
 614        { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
 615
 616        /* Generic, PCI class code for AHCI */
 617        { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 618          PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
 619
 620        { }     /* terminate list */
 621};
 622
 623static const struct dev_pm_ops ahci_pci_pm_ops = {
 624        SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
 625        SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
 626                           ahci_pci_device_runtime_resume, NULL)
 627};
 628
 629static struct pci_driver ahci_pci_driver = {
 630        .name                   = DRV_NAME,
 631        .id_table               = ahci_pci_tbl,
 632        .probe                  = ahci_init_one,
 633        .remove                 = ahci_remove_one,
 634        .shutdown               = ahci_shutdown_one,
 635        .driver = {
 636                .pm             = &ahci_pci_pm_ops,
 637        },
 638};
 639
 640#if IS_ENABLED(CONFIG_PATA_MARVELL)
 641static int marvell_enable;
 642#else
 643static int marvell_enable = 1;
 644#endif
 645module_param(marvell_enable, int, 0644);
 646MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
 647
 648static int mobile_lpm_policy = -1;
 649module_param(mobile_lpm_policy, int, 0644);
 650MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
 651
 652static void ahci_pci_save_initial_config(struct pci_dev *pdev,
 653                                         struct ahci_host_priv *hpriv)
 654{
 655        if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
 656                dev_info(&pdev->dev, "JMB361 has only one port\n");
 657                hpriv->force_port_map = 1;
 658        }
 659
 660        /*
 661         * Temporary Marvell 6145 hack: PATA port presence
 662         * is asserted through the standard AHCI port
 663         * presence register, as bit 4 (counting from 0)
 664         */
 665        if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
 666                if (pdev->device == 0x6121)
 667                        hpriv->mask_port_map = 0x3;
 668                else
 669                        hpriv->mask_port_map = 0xf;
 670                dev_info(&pdev->dev,
 671                          "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
 672        }
 673
 674        ahci_save_initial_config(&pdev->dev, hpriv);
 675}
 676
 677static void ahci_pci_init_controller(struct ata_host *host)
 678{
 679        struct ahci_host_priv *hpriv = host->private_data;
 680        struct pci_dev *pdev = to_pci_dev(host->dev);
 681        void __iomem *port_mmio;
 682        u32 tmp;
 683        int mv;
 684
 685        if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
 686                if (pdev->device == 0x6121)
 687                        mv = 2;
 688                else
 689                        mv = 4;
 690                port_mmio = __ahci_port_base(host, mv);
 691
 692                writel(0, port_mmio + PORT_IRQ_MASK);
 693
 694                /* clear port IRQ */
 695                tmp = readl(port_mmio + PORT_IRQ_STAT);
 696                dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
 697                if (tmp)
 698                        writel(tmp, port_mmio + PORT_IRQ_STAT);
 699        }
 700
 701        ahci_init_controller(host);
 702}
 703
 704static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
 705                                 unsigned long deadline)
 706{
 707        struct ata_port *ap = link->ap;
 708        struct ahci_host_priv *hpriv = ap->host->private_data;
 709        bool online;
 710        int rc;
 711
 712        hpriv->stop_engine(ap);
 713
 714        rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
 715                                 deadline, &online, NULL);
 716
 717        hpriv->start_engine(ap);
 718
 719        /* vt8251 doesn't clear BSY on signature FIS reception,
 720         * request follow-up softreset.
 721         */
 722        return online ? -EAGAIN : rc;
 723}
 724
 725static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
 726                                unsigned long deadline)
 727{
 728        struct ata_port *ap = link->ap;
 729        struct ahci_port_priv *pp = ap->private_data;
 730        struct ahci_host_priv *hpriv = ap->host->private_data;
 731        u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
 732        struct ata_taskfile tf;
 733        bool online;
 734        int rc;
 735
 736        hpriv->stop_engine(ap);
 737
 738        /* clear D2H reception area to properly wait for D2H FIS */
 739        ata_tf_init(link->device, &tf);
 740        tf.command = ATA_BUSY;
 741        ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 742
 743        rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
 744                                 deadline, &online, NULL);
 745
 746        hpriv->start_engine(ap);
 747
 748        /* The pseudo configuration device on SIMG4726 attached to
 749         * ASUS P5W-DH Deluxe doesn't send signature FIS after
 750         * hardreset if no device is attached to the first downstream
 751         * port && the pseudo device locks up on SRST w/ PMP==0.  To
 752         * work around this, wait for !BSY only briefly.  If BSY isn't
 753         * cleared, perform CLO and proceed to IDENTIFY (achieved by
 754         * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
 755         *
 756         * Wait for two seconds.  Devices attached to downstream port
 757         * which can't process the following IDENTIFY after this will
 758         * have to be reset again.  For most cases, this should
 759         * suffice while making probing snappish enough.
 760         */
 761        if (online) {
 762                rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
 763                                          ahci_check_ready);
 764                if (rc)
 765                        ahci_kick_engine(ap);
 766        }
 767        return rc;
 768}
 769
 770/*
 771 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
 772 *
 773 * It has been observed with some SSDs that the timing of events in the
 774 * link synchronization phase can leave the port in a state that can not
 775 * be recovered by a SATA-hard-reset alone.  The failing signature is
 776 * SStatus.DET stuck at 1 ("Device presence detected but Phy
 777 * communication not established").  It was found that unloading and
 778 * reloading the driver when this problem occurs allows the drive
 779 * connection to be recovered (DET advanced to 0x3).  The critical
 780 * component of reloading the driver is that the port state machines are
 781 * reset by bouncing "port enable" in the AHCI PCS configuration
 782 * register.  So, reproduce that effect by bouncing a port whenever we
 783 * see DET==1 after a reset.
 784 */
 785static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
 786                              unsigned long deadline)
 787{
 788        const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
 789        struct ata_port *ap = link->ap;
 790        struct ahci_port_priv *pp = ap->private_data;
 791        struct ahci_host_priv *hpriv = ap->host->private_data;
 792        u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
 793        unsigned long tmo = deadline - jiffies;
 794        struct ata_taskfile tf;
 795        bool online;
 796        int rc, i;
 797
 798        hpriv->stop_engine(ap);
 799
 800        for (i = 0; i < 2; i++) {
 801                u16 val;
 802                u32 sstatus;
 803                int port = ap->port_no;
 804                struct ata_host *host = ap->host;
 805                struct pci_dev *pdev = to_pci_dev(host->dev);
 806
 807                /* clear D2H reception area to properly wait for D2H FIS */
 808                ata_tf_init(link->device, &tf);
 809                tf.command = ATA_BUSY;
 810                ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 811
 812                rc = sata_link_hardreset(link, timing, deadline, &online,
 813                                ahci_check_ready);
 814
 815                if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
 816                                (sstatus & 0xf) != 1)
 817                        break;
 818
 819                ata_link_info(link,  "avn bounce port%d\n", port);
 820
 821                pci_read_config_word(pdev, 0x92, &val);
 822                val &= ~(1 << port);
 823                pci_write_config_word(pdev, 0x92, val);
 824                ata_msleep(ap, 1000);
 825                val |= 1 << port;
 826                pci_write_config_word(pdev, 0x92, val);
 827                deadline += tmo;
 828        }
 829
 830        hpriv->start_engine(ap);
 831
 832        if (online)
 833                *class = ahci_dev_classify(ap);
 834
 835        return rc;
 836}
 837
 838
 839#ifdef CONFIG_PM
 840static void ahci_pci_disable_interrupts(struct ata_host *host)
 841{
 842        struct ahci_host_priv *hpriv = host->private_data;
 843        void __iomem *mmio = hpriv->mmio;
 844        u32 ctl;
 845
 846        /* AHCI spec rev1.1 section 8.3.3:
 847         * Software must disable interrupts prior to requesting a
 848         * transition of the HBA to D3 state.
 849         */
 850        ctl = readl(mmio + HOST_CTL);
 851        ctl &= ~HOST_IRQ_EN;
 852        writel(ctl, mmio + HOST_CTL);
 853        readl(mmio + HOST_CTL); /* flush */
 854}
 855
 856static int ahci_pci_device_runtime_suspend(struct device *dev)
 857{
 858        struct pci_dev *pdev = to_pci_dev(dev);
 859        struct ata_host *host = pci_get_drvdata(pdev);
 860
 861        ahci_pci_disable_interrupts(host);
 862        return 0;
 863}
 864
 865static int ahci_pci_device_runtime_resume(struct device *dev)
 866{
 867        struct pci_dev *pdev = to_pci_dev(dev);
 868        struct ata_host *host = pci_get_drvdata(pdev);
 869        int rc;
 870
 871        rc = ahci_reset_controller(host);
 872        if (rc)
 873                return rc;
 874        ahci_pci_init_controller(host);
 875        return 0;
 876}
 877
 878#ifdef CONFIG_PM_SLEEP
 879static int ahci_pci_device_suspend(struct device *dev)
 880{
 881        struct pci_dev *pdev = to_pci_dev(dev);
 882        struct ata_host *host = pci_get_drvdata(pdev);
 883        struct ahci_host_priv *hpriv = host->private_data;
 884
 885        if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
 886                dev_err(&pdev->dev,
 887                        "BIOS update required for suspend/resume\n");
 888                return -EIO;
 889        }
 890
 891        ahci_pci_disable_interrupts(host);
 892        return ata_host_suspend(host, PMSG_SUSPEND);
 893}
 894
 895static int ahci_pci_device_resume(struct device *dev)
 896{
 897        struct pci_dev *pdev = to_pci_dev(dev);
 898        struct ata_host *host = pci_get_drvdata(pdev);
 899        int rc;
 900
 901        /* Apple BIOS helpfully mangles the registers on resume */
 902        if (is_mcp89_apple(pdev))
 903                ahci_mcp89_apple_enable(pdev);
 904
 905        if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
 906                rc = ahci_reset_controller(host);
 907                if (rc)
 908                        return rc;
 909
 910                ahci_pci_init_controller(host);
 911        }
 912
 913        ata_host_resume(host);
 914
 915        return 0;
 916}
 917#endif
 918
 919#endif /* CONFIG_PM */
 920
 921static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
 922{
 923        const int dma_bits = using_dac ? 64 : 32;
 924        int rc;
 925
 926        /*
 927         * If the device fixup already set the dma_mask to some non-standard
 928         * value, don't extend it here. This happens on STA2X11, for example.
 929         *
 930         * XXX: manipulating the DMA mask from platform code is completely
 931         * bogus, platform code should use dev->bus_dma_limit instead..
 932         */
 933        if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
 934                return 0;
 935
 936        rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
 937        if (rc)
 938                dev_err(&pdev->dev, "DMA enable failed\n");
 939        return rc;
 940}
 941
 942static void ahci_pci_print_info(struct ata_host *host)
 943{
 944        struct pci_dev *pdev = to_pci_dev(host->dev);
 945        u16 cc;
 946        const char *scc_s;
 947
 948        pci_read_config_word(pdev, 0x0a, &cc);
 949        if (cc == PCI_CLASS_STORAGE_IDE)
 950                scc_s = "IDE";
 951        else if (cc == PCI_CLASS_STORAGE_SATA)
 952                scc_s = "SATA";
 953        else if (cc == PCI_CLASS_STORAGE_RAID)
 954                scc_s = "RAID";
 955        else
 956                scc_s = "unknown";
 957
 958        ahci_print_info(host, scc_s);
 959}
 960
 961/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
 962 * hardwired to on-board SIMG 4726.  The chipset is ICH8 and doesn't
 963 * support PMP and the 4726 either directly exports the device
 964 * attached to the first downstream port or acts as a hardware storage
 965 * controller and emulate a single ATA device (can be RAID 0/1 or some
 966 * other configuration).
 967 *
 968 * When there's no device attached to the first downstream port of the
 969 * 4726, "Config Disk" appears, which is a pseudo ATA device to
 970 * configure the 4726.  However, ATA emulation of the device is very
 971 * lame.  It doesn't send signature D2H Reg FIS after the initial
 972 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
 973 *
 974 * The following function works around the problem by always using
 975 * hardreset on the port and not depending on receiving signature FIS
 976 * afterward.  If signature FIS isn't received soon, ATA class is
 977 * assumed without follow-up softreset.
 978 */
 979static void ahci_p5wdh_workaround(struct ata_host *host)
 980{
 981        static const struct dmi_system_id sysids[] = {
 982                {
 983                        .ident = "P5W DH Deluxe",
 984                        .matches = {
 985                                DMI_MATCH(DMI_SYS_VENDOR,
 986                                          "ASUSTEK COMPUTER INC"),
 987                                DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
 988                        },
 989                },
 990                { }
 991        };
 992        struct pci_dev *pdev = to_pci_dev(host->dev);
 993
 994        if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
 995            dmi_check_system(sysids)) {
 996                struct ata_port *ap = host->ports[1];
 997
 998                dev_info(&pdev->dev,
 999                         "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1000
1001                ap->ops = &ahci_p5wdh_ops;
1002                ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1003        }
1004}
1005
1006/*
1007 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1008 * booting in BIOS compatibility mode.  We restore the registers but not ID.
1009 */
1010static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1011{
1012        u32 val;
1013
1014        printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1015
1016        pci_read_config_dword(pdev, 0xf8, &val);
1017        val |= 1 << 0x1b;
1018        /* the following changes the device ID, but appears not to affect function */
1019        /* val = (val & ~0xf0000000) | 0x80000000; */
1020        pci_write_config_dword(pdev, 0xf8, val);
1021
1022        pci_read_config_dword(pdev, 0x54c, &val);
1023        val |= 1 << 0xc;
1024        pci_write_config_dword(pdev, 0x54c, val);
1025
1026        pci_read_config_dword(pdev, 0x4a4, &val);
1027        val &= 0xff;
1028        val |= 0x01060100;
1029        pci_write_config_dword(pdev, 0x4a4, val);
1030
1031        pci_read_config_dword(pdev, 0x54c, &val);
1032        val &= ~(1 << 0xc);
1033        pci_write_config_dword(pdev, 0x54c, val);
1034
1035        pci_read_config_dword(pdev, 0xf8, &val);
1036        val &= ~(1 << 0x1b);
1037        pci_write_config_dword(pdev, 0xf8, val);
1038}
1039
1040static bool is_mcp89_apple(struct pci_dev *pdev)
1041{
1042        return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1043                pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1044                pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1045                pdev->subsystem_device == 0xcb89;
1046}
1047
1048/* only some SB600 ahci controllers can do 64bit DMA */
1049static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1050{
1051        static const struct dmi_system_id sysids[] = {
1052                /*
1053                 * The oldest version known to be broken is 0901 and
1054                 * working is 1501 which was released on 2007-10-26.
1055                 * Enable 64bit DMA on 1501 and anything newer.
1056                 *
1057                 * Please read bko#9412 for more info.
1058                 */
1059                {
1060                        .ident = "ASUS M2A-VM",
1061                        .matches = {
1062                                DMI_MATCH(DMI_BOARD_VENDOR,
1063                                          "ASUSTeK Computer INC."),
1064                                DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1065                        },
1066                        .driver_data = "20071026",      /* yyyymmdd */
1067                },
1068                /*
1069                 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1070                 * support 64bit DMA.
1071                 *
1072                 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1073                 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1074                 * This spelling mistake was fixed in BIOS version 1.5, so
1075                 * 1.5 and later have the Manufacturer as
1076                 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1077                 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1078                 *
1079                 * BIOS versions earlier than 1.9 had a Board Product Name
1080                 * DMI field of "MS-7376". This was changed to be
1081                 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1082                 * match on DMI_BOARD_NAME of "MS-7376".
1083                 */
1084                {
1085                        .ident = "MSI K9A2 Platinum",
1086                        .matches = {
1087                                DMI_MATCH(DMI_BOARD_VENDOR,
1088                                          "MICRO-STAR INTER"),
1089                                DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1090                        },
1091                },
1092                /*
1093                 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1094                 * 64bit DMA.
1095                 *
1096                 * This board also had the typo mentioned above in the
1097                 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1098                 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1099                 */
1100                {
1101                        .ident = "MSI K9AGM2",
1102                        .matches = {
1103                                DMI_MATCH(DMI_BOARD_VENDOR,
1104                                          "MICRO-STAR INTER"),
1105                                DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1106                        },
1107                },
1108                /*
1109                 * All BIOS versions for the Asus M3A support 64bit DMA.
1110                 * (all release versions from 0301 to 1206 were tested)
1111                 */
1112                {
1113                        .ident = "ASUS M3A",
1114                        .matches = {
1115                                DMI_MATCH(DMI_BOARD_VENDOR,
1116                                          "ASUSTeK Computer INC."),
1117                                DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1118                        },
1119                },
1120                { }
1121        };
1122        const struct dmi_system_id *match;
1123        int year, month, date;
1124        char buf[9];
1125
1126        match = dmi_first_match(sysids);
1127        if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1128            !match)
1129                return false;
1130
1131        if (!match->driver_data)
1132                goto enable_64bit;
1133
1134        dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1135        snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1136
1137        if (strcmp(buf, match->driver_data) >= 0)
1138                goto enable_64bit;
1139        else {
1140                dev_warn(&pdev->dev,
1141                         "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1142                         match->ident);
1143                return false;
1144        }
1145
1146enable_64bit:
1147        dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1148        return true;
1149}
1150
1151static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1152{
1153        static const struct dmi_system_id broken_systems[] = {
1154                {
1155                        .ident = "HP Compaq nx6310",
1156                        .matches = {
1157                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1158                                DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1159                        },
1160                        /* PCI slot number of the controller */
1161                        .driver_data = (void *)0x1FUL,
1162                },
1163                {
1164                        .ident = "HP Compaq 6720s",
1165                        .matches = {
1166                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1167                                DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1168                        },
1169                        /* PCI slot number of the controller */
1170                        .driver_data = (void *)0x1FUL,
1171                },
1172
1173                { }     /* terminate list */
1174        };
1175        const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1176
1177        if (dmi) {
1178                unsigned long slot = (unsigned long)dmi->driver_data;
1179                /* apply the quirk only to on-board controllers */
1180                return slot == PCI_SLOT(pdev->devfn);
1181        }
1182
1183        return false;
1184}
1185
1186static bool ahci_broken_suspend(struct pci_dev *pdev)
1187{
1188        static const struct dmi_system_id sysids[] = {
1189                /*
1190                 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1191                 * to the harddisk doesn't become online after
1192                 * resuming from STR.  Warn and fail suspend.
1193                 *
1194                 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1195                 *
1196                 * Use dates instead of versions to match as HP is
1197                 * apparently recycling both product and version
1198                 * strings.
1199                 *
1200                 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1201                 */
1202                {
1203                        .ident = "dv4",
1204                        .matches = {
1205                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1206                                DMI_MATCH(DMI_PRODUCT_NAME,
1207                                          "HP Pavilion dv4 Notebook PC"),
1208                        },
1209                        .driver_data = "20090105",      /* F.30 */
1210                },
1211                {
1212                        .ident = "dv5",
1213                        .matches = {
1214                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1215                                DMI_MATCH(DMI_PRODUCT_NAME,
1216                                          "HP Pavilion dv5 Notebook PC"),
1217                        },
1218                        .driver_data = "20090506",      /* F.16 */
1219                },
1220                {
1221                        .ident = "dv6",
1222                        .matches = {
1223                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1224                                DMI_MATCH(DMI_PRODUCT_NAME,
1225                                          "HP Pavilion dv6 Notebook PC"),
1226                        },
1227                        .driver_data = "20090423",      /* F.21 */
1228                },
1229                {
1230                        .ident = "HDX18",
1231                        .matches = {
1232                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1233                                DMI_MATCH(DMI_PRODUCT_NAME,
1234                                          "HP HDX18 Notebook PC"),
1235                        },
1236                        .driver_data = "20090430",      /* F.23 */
1237                },
1238                /*
1239                 * Acer eMachines G725 has the same problem.  BIOS
1240                 * V1.03 is known to be broken.  V3.04 is known to
1241                 * work.  Between, there are V1.06, V2.06 and V3.03
1242                 * that we don't have much idea about.  For now,
1243                 * blacklist anything older than V3.04.
1244                 *
1245                 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1246                 */
1247                {
1248                        .ident = "G725",
1249                        .matches = {
1250                                DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1251                                DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1252                        },
1253                        .driver_data = "20091216",      /* V3.04 */
1254                },
1255                { }     /* terminate list */
1256        };
1257        const struct dmi_system_id *dmi = dmi_first_match(sysids);
1258        int year, month, date;
1259        char buf[9];
1260
1261        if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1262                return false;
1263
1264        dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1265        snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1266
1267        return strcmp(buf, dmi->driver_data) < 0;
1268}
1269
1270static bool ahci_broken_lpm(struct pci_dev *pdev)
1271{
1272        static const struct dmi_system_id sysids[] = {
1273                /* Various Lenovo 50 series have LPM issues with older BIOSen */
1274                {
1275                        .matches = {
1276                                DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1277                                DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1278                        },
1279                        .driver_data = "20180406", /* 1.31 */
1280                },
1281                {
1282                        .matches = {
1283                                DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1284                                DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1285                        },
1286                        .driver_data = "20180420", /* 1.28 */
1287                },
1288                {
1289                        .matches = {
1290                                DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1291                                DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1292                        },
1293                        .driver_data = "20180315", /* 1.33 */
1294                },
1295                {
1296                        .matches = {
1297                                DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1298                                DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1299                        },
1300                        /*
1301                         * Note date based on release notes, 2.35 has been
1302                         * reported to be good, but I've been unable to get
1303                         * a hold of the reporter to get the DMI BIOS date.
1304                         * TODO: fix this.
1305                         */
1306                        .driver_data = "20180310", /* 2.35 */
1307                },
1308                { }     /* terminate list */
1309        };
1310        const struct dmi_system_id *dmi = dmi_first_match(sysids);
1311        int year, month, date;
1312        char buf[9];
1313
1314        if (!dmi)
1315                return false;
1316
1317        dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1318        snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1319
1320        return strcmp(buf, dmi->driver_data) < 0;
1321}
1322
1323static bool ahci_broken_online(struct pci_dev *pdev)
1324{
1325#define ENCODE_BUSDEVFN(bus, slot, func)                        \
1326        (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1327        static const struct dmi_system_id sysids[] = {
1328                /*
1329                 * There are several gigabyte boards which use
1330                 * SIMG5723s configured as hardware RAID.  Certain
1331                 * 5723 firmware revisions shipped there keep the link
1332                 * online but fail to answer properly to SRST or
1333                 * IDENTIFY when no device is attached downstream
1334                 * causing libata to retry quite a few times leading
1335                 * to excessive detection delay.
1336                 *
1337                 * As these firmwares respond to the second reset try
1338                 * with invalid device signature, considering unknown
1339                 * sig as offline works around the problem acceptably.
1340                 */
1341                {
1342                        .ident = "EP45-DQ6",
1343                        .matches = {
1344                                DMI_MATCH(DMI_BOARD_VENDOR,
1345                                          "Gigabyte Technology Co., Ltd."),
1346                                DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1347                        },
1348                        .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1349                },
1350                {
1351                        .ident = "EP45-DS5",
1352                        .matches = {
1353                                DMI_MATCH(DMI_BOARD_VENDOR,
1354                                          "Gigabyte Technology Co., Ltd."),
1355                                DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1356                        },
1357                        .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1358                },
1359                { }     /* terminate list */
1360        };
1361#undef ENCODE_BUSDEVFN
1362        const struct dmi_system_id *dmi = dmi_first_match(sysids);
1363        unsigned int val;
1364
1365        if (!dmi)
1366                return false;
1367
1368        val = (unsigned long)dmi->driver_data;
1369
1370        return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1371}
1372
1373static bool ahci_broken_devslp(struct pci_dev *pdev)
1374{
1375        /* device with broken DEVSLP but still showing SDS capability */
1376        static const struct pci_device_id ids[] = {
1377                { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1378                {}
1379        };
1380
1381        return pci_match_id(ids, pdev);
1382}
1383
1384#ifdef CONFIG_ATA_ACPI
1385static void ahci_gtf_filter_workaround(struct ata_host *host)
1386{
1387        static const struct dmi_system_id sysids[] = {
1388                /*
1389                 * Aspire 3810T issues a bunch of SATA enable commands
1390                 * via _GTF including an invalid one and one which is
1391                 * rejected by the device.  Among the successful ones
1392                 * is FPDMA non-zero offset enable which when enabled
1393                 * only on the drive side leads to NCQ command
1394                 * failures.  Filter it out.
1395                 */
1396                {
1397                        .ident = "Aspire 3810T",
1398                        .matches = {
1399                                DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1400                                DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1401                        },
1402                        .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1403                },
1404                { }
1405        };
1406        const struct dmi_system_id *dmi = dmi_first_match(sysids);
1407        unsigned int filter;
1408        int i;
1409
1410        if (!dmi)
1411                return;
1412
1413        filter = (unsigned long)dmi->driver_data;
1414        dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1415                 filter, dmi->ident);
1416
1417        for (i = 0; i < host->n_ports; i++) {
1418                struct ata_port *ap = host->ports[i];
1419                struct ata_link *link;
1420                struct ata_device *dev;
1421
1422                ata_for_each_link(link, ap, EDGE)
1423                        ata_for_each_dev(dev, link, ALL)
1424                                dev->gtf_filter |= filter;
1425        }
1426}
1427#else
1428static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1429{}
1430#endif
1431
1432/*
1433 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1434 * as DUMMY, or detected but eventually get a "link down" and never get up
1435 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1436 * port_map may hold a value of 0x00.
1437 *
1438 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1439 * and can significantly reduce the occurrence of the problem.
1440 *
1441 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1442 */
1443static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1444                                    struct pci_dev *pdev)
1445{
1446        static const struct dmi_system_id sysids[] = {
1447                {
1448                        .ident = "Acer Switch Alpha 12",
1449                        .matches = {
1450                                DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1451                                DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1452                        },
1453                },
1454                { }
1455        };
1456
1457        if (dmi_check_system(sysids)) {
1458                dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1459                if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1460                        hpriv->port_map = 0x7;
1461                        hpriv->cap = 0xC734FF02;
1462                }
1463        }
1464}
1465
1466#ifdef CONFIG_ARM64
1467/*
1468 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1469 * Workaround is to make sure all pending IRQs are served before leaving
1470 * handler.
1471 */
1472static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1473{
1474        struct ata_host *host = dev_instance;
1475        struct ahci_host_priv *hpriv;
1476        unsigned int rc = 0;
1477        void __iomem *mmio;
1478        u32 irq_stat, irq_masked;
1479        unsigned int handled = 1;
1480
1481        hpriv = host->private_data;
1482        mmio = hpriv->mmio;
1483        irq_stat = readl(mmio + HOST_IRQ_STAT);
1484        if (!irq_stat)
1485                return IRQ_NONE;
1486
1487        do {
1488                irq_masked = irq_stat & hpriv->port_map;
1489                spin_lock(&host->lock);
1490                rc = ahci_handle_port_intr(host, irq_masked);
1491                if (!rc)
1492                        handled = 0;
1493                writel(irq_stat, mmio + HOST_IRQ_STAT);
1494                irq_stat = readl(mmio + HOST_IRQ_STAT);
1495                spin_unlock(&host->lock);
1496        } while (irq_stat);
1497
1498        return IRQ_RETVAL(handled);
1499}
1500#endif
1501
1502static void ahci_remap_check(struct pci_dev *pdev, int bar,
1503                struct ahci_host_priv *hpriv)
1504{
1505        int i;
1506        u32 cap;
1507
1508        /*
1509         * Check if this device might have remapped nvme devices.
1510         */
1511        if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1512            pci_resource_len(pdev, bar) < SZ_512K ||
1513            bar != AHCI_PCI_BAR_STANDARD ||
1514            !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1515                return;
1516
1517        cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1518        for (i = 0; i < AHCI_MAX_REMAP; i++) {
1519                if ((cap & (1 << i)) == 0)
1520                        continue;
1521                if (readl(hpriv->mmio + ahci_remap_dcc(i))
1522                                != PCI_CLASS_STORAGE_EXPRESS)
1523                        continue;
1524
1525                /* We've found a remapped device */
1526                hpriv->remapped_nvme++;
1527        }
1528
1529        if (!hpriv->remapped_nvme)
1530                return;
1531
1532        dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1533                 hpriv->remapped_nvme);
1534        dev_warn(&pdev->dev,
1535                 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1536
1537        /*
1538         * Don't rely on the msi-x capability in the remap case,
1539         * share the legacy interrupt across ahci and remapped devices.
1540         */
1541        hpriv->flags |= AHCI_HFLAG_NO_MSI;
1542}
1543
1544static int ahci_get_irq_vector(struct ata_host *host, int port)
1545{
1546        return pci_irq_vector(to_pci_dev(host->dev), port);
1547}
1548
1549static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1550                        struct ahci_host_priv *hpriv)
1551{
1552        int nvec;
1553
1554        if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1555                return -ENODEV;
1556
1557        /*
1558         * If number of MSIs is less than number of ports then Sharing Last
1559         * Message mode could be enforced. In this case assume that advantage
1560         * of multipe MSIs is negated and use single MSI mode instead.
1561         */
1562        if (n_ports > 1) {
1563                nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1564                                PCI_IRQ_MSIX | PCI_IRQ_MSI);
1565                if (nvec > 0) {
1566                        if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1567                                hpriv->get_irq_vector = ahci_get_irq_vector;
1568                                hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1569                                return nvec;
1570                        }
1571
1572                        /*
1573                         * Fallback to single MSI mode if the controller
1574                         * enforced MRSM mode.
1575                         */
1576                        printk(KERN_INFO
1577                                "ahci: MRSM is on, fallback to single MSI\n");
1578                        pci_free_irq_vectors(pdev);
1579                }
1580        }
1581
1582        /*
1583         * If the host is not capable of supporting per-port vectors, fall
1584         * back to single MSI before finally attempting single MSI-X.
1585         */
1586        nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1587        if (nvec == 1)
1588                return nvec;
1589        return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1590}
1591
1592static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1593                                           struct ahci_host_priv *hpriv)
1594{
1595        int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1596
1597
1598        /* Ignore processing for non mobile platforms */
1599        if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1600                return;
1601
1602        /* user modified policy via module param */
1603        if (mobile_lpm_policy != -1) {
1604                policy = mobile_lpm_policy;
1605                goto update_policy;
1606        }
1607
1608#ifdef CONFIG_ACPI
1609        if (policy > ATA_LPM_MED_POWER &&
1610            (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1611                if (hpriv->cap & HOST_CAP_PART)
1612                        policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1613                else if (hpriv->cap & HOST_CAP_SSC)
1614                        policy = ATA_LPM_MIN_POWER;
1615        }
1616#endif
1617
1618update_policy:
1619        if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1620                ap->target_lpm_policy = policy;
1621}
1622
1623static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1624{
1625        const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1626        u16 tmp16;
1627
1628        /*
1629         * Only apply the 6-port PCS quirk for known legacy platforms.
1630         */
1631        if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1632                return;
1633
1634        /* Skip applying the quirk on Denverton and beyond */
1635        if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1636                return;
1637
1638        /*
1639         * port_map is determined from PORTS_IMPL PCI register which is
1640         * implemented as write or write-once register.  If the register
1641         * isn't programmed, ahci automatically generates it from number
1642         * of ports, which is good enough for PCS programming. It is
1643         * otherwise expected that platform firmware enables the ports
1644         * before the OS boots.
1645         */
1646        pci_read_config_word(pdev, PCS_6, &tmp16);
1647        if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1648                tmp16 |= hpriv->port_map;
1649                pci_write_config_word(pdev, PCS_6, tmp16);
1650        }
1651}
1652
1653static ssize_t remapped_nvme_show(struct device *dev,
1654                                  struct device_attribute *attr,
1655                                  char *buf)
1656{
1657        struct ata_host *host = dev_get_drvdata(dev);
1658        struct ahci_host_priv *hpriv = host->private_data;
1659
1660        return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme);
1661}
1662
1663static DEVICE_ATTR_RO(remapped_nvme);
1664
1665static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1666{
1667        unsigned int board_id = ent->driver_data;
1668        struct ata_port_info pi = ahci_port_info[board_id];
1669        const struct ata_port_info *ppi[] = { &pi, NULL };
1670        struct device *dev = &pdev->dev;
1671        struct ahci_host_priv *hpriv;
1672        struct ata_host *host;
1673        int n_ports, i, rc;
1674        int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1675
1676        WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1677
1678        ata_print_version_once(&pdev->dev, DRV_VERSION);
1679
1680        /* The AHCI driver can only drive the SATA ports, the PATA driver
1681           can drive them all so if both drivers are selected make sure
1682           AHCI stays out of the way */
1683        if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1684                return -ENODEV;
1685
1686        /* Apple BIOS on MCP89 prevents us using AHCI */
1687        if (is_mcp89_apple(pdev))
1688                ahci_mcp89_apple_enable(pdev);
1689
1690        /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1691         * At the moment, we can only use the AHCI mode. Let the users know
1692         * that for SAS drives they're out of luck.
1693         */
1694        if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1695                dev_info(&pdev->dev,
1696                         "PDC42819 can only drive SATA devices with this driver\n");
1697
1698        /* Some devices use non-standard BARs */
1699        if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1700                ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1701        else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1702                ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1703        else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1704                if (pdev->device == 0xa01c)
1705                        ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1706                if (pdev->device == 0xa084)
1707                        ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1708        } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1709                if (pdev->device == 0x7a08)
1710                        ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1711        }
1712
1713        /* acquire resources */
1714        rc = pcim_enable_device(pdev);
1715        if (rc)
1716                return rc;
1717
1718        if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1719            (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1720                u8 map;
1721
1722                /* ICH6s share the same PCI ID for both piix and ahci
1723                 * modes.  Enabling ahci mode while MAP indicates
1724                 * combined mode is a bad idea.  Yield to ata_piix.
1725                 */
1726                pci_read_config_byte(pdev, ICH_MAP, &map);
1727                if (map & 0x3) {
1728                        dev_info(&pdev->dev,
1729                                 "controller is in combined mode, can't enable AHCI mode\n");
1730                        return -ENODEV;
1731                }
1732        }
1733
1734        /* AHCI controllers often implement SFF compatible interface.
1735         * Grab all PCI BARs just in case.
1736         */
1737        rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1738        if (rc == -EBUSY)
1739                pcim_pin_device(pdev);
1740        if (rc)
1741                return rc;
1742
1743        hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1744        if (!hpriv)
1745                return -ENOMEM;
1746        hpriv->flags |= (unsigned long)pi.private_data;
1747
1748        /* MCP65 revision A1 and A2 can't do MSI */
1749        if (board_id == board_ahci_mcp65 &&
1750            (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1751                hpriv->flags |= AHCI_HFLAG_NO_MSI;
1752
1753        /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1754        if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1755                hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1756
1757        /* only some SB600s can do 64bit DMA */
1758        if (ahci_sb600_enable_64bit(pdev))
1759                hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1760
1761        hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1762
1763        /* detect remapped nvme devices */
1764        ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1765
1766        sysfs_add_file_to_group(&pdev->dev.kobj,
1767                                &dev_attr_remapped_nvme.attr,
1768                                NULL);
1769
1770        /* must set flag prior to save config in order to take effect */
1771        if (ahci_broken_devslp(pdev))
1772                hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1773
1774#ifdef CONFIG_ARM64
1775        if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1776            pdev->device == 0xa235 &&
1777            pdev->revision < 0x30)
1778                hpriv->flags |= AHCI_HFLAG_NO_SXS;
1779
1780        if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1781                hpriv->irq_handler = ahci_thunderx_irq_handler;
1782#endif
1783
1784        /* save initial config */
1785        ahci_pci_save_initial_config(pdev, hpriv);
1786
1787        /*
1788         * If platform firmware failed to enable ports, try to enable
1789         * them here.
1790         */
1791        ahci_intel_pcs_quirk(pdev, hpriv);
1792
1793        /* prepare host */
1794        if (hpriv->cap & HOST_CAP_NCQ) {
1795                pi.flags |= ATA_FLAG_NCQ;
1796                /*
1797                 * Auto-activate optimization is supposed to be
1798                 * supported on all AHCI controllers indicating NCQ
1799                 * capability, but it seems to be broken on some
1800                 * chipsets including NVIDIAs.
1801                 */
1802                if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1803                        pi.flags |= ATA_FLAG_FPDMA_AA;
1804
1805                /*
1806                 * All AHCI controllers should be forward-compatible
1807                 * with the new auxiliary field. This code should be
1808                 * conditionalized if any buggy AHCI controllers are
1809                 * encountered.
1810                 */
1811                pi.flags |= ATA_FLAG_FPDMA_AUX;
1812        }
1813
1814        if (hpriv->cap & HOST_CAP_PMP)
1815                pi.flags |= ATA_FLAG_PMP;
1816
1817        ahci_set_em_messages(hpriv, &pi);
1818
1819        if (ahci_broken_system_poweroff(pdev)) {
1820                pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1821                dev_info(&pdev->dev,
1822                        "quirky BIOS, skipping spindown on poweroff\n");
1823        }
1824
1825        if (ahci_broken_lpm(pdev)) {
1826                pi.flags |= ATA_FLAG_NO_LPM;
1827                dev_warn(&pdev->dev,
1828                         "BIOS update required for Link Power Management support\n");
1829        }
1830
1831        if (ahci_broken_suspend(pdev)) {
1832                hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1833                dev_warn(&pdev->dev,
1834                         "BIOS update required for suspend/resume\n");
1835        }
1836
1837        if (ahci_broken_online(pdev)) {
1838                hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1839                dev_info(&pdev->dev,
1840                         "online status unreliable, applying workaround\n");
1841        }
1842
1843
1844        /* Acer SA5-271 workaround modifies private_data */
1845        acer_sa5_271_workaround(hpriv, pdev);
1846
1847        /* CAP.NP sometimes indicate the index of the last enabled
1848         * port, at other times, that of the last possible port, so
1849         * determining the maximum port number requires looking at
1850         * both CAP.NP and port_map.
1851         */
1852        n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1853
1854        host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1855        if (!host)
1856                return -ENOMEM;
1857        host->private_data = hpriv;
1858
1859        if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1860                /* legacy intx interrupts */
1861                pci_intx(pdev, 1);
1862        }
1863        hpriv->irq = pci_irq_vector(pdev, 0);
1864
1865        if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1866                host->flags |= ATA_HOST_PARALLEL_SCAN;
1867        else
1868                dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1869
1870        if (pi.flags & ATA_FLAG_EM)
1871                ahci_reset_em(host);
1872
1873        for (i = 0; i < host->n_ports; i++) {
1874                struct ata_port *ap = host->ports[i];
1875
1876                ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1877                ata_port_pbar_desc(ap, ahci_pci_bar,
1878                                   0x100 + ap->port_no * 0x80, "port");
1879
1880                /* set enclosure management message type */
1881                if (ap->flags & ATA_FLAG_EM)
1882                        ap->em_message_type = hpriv->em_msg_type;
1883
1884                ahci_update_initial_lpm_policy(ap, hpriv);
1885
1886                /* disabled/not-implemented port */
1887                if (!(hpriv->port_map & (1 << i)))
1888                        ap->ops = &ata_dummy_port_ops;
1889        }
1890
1891        /* apply workaround for ASUS P5W DH Deluxe mainboard */
1892        ahci_p5wdh_workaround(host);
1893
1894        /* apply gtf filter quirk */
1895        ahci_gtf_filter_workaround(host);
1896
1897        /* initialize adapter */
1898        rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1899        if (rc)
1900                return rc;
1901
1902        rc = ahci_reset_controller(host);
1903        if (rc)
1904                return rc;
1905
1906        ahci_pci_init_controller(host);
1907        ahci_pci_print_info(host);
1908
1909        pci_set_master(pdev);
1910
1911        rc = ahci_host_activate(host, &ahci_sht);
1912        if (rc)
1913                return rc;
1914
1915        pm_runtime_put_noidle(&pdev->dev);
1916        return 0;
1917}
1918
1919static void ahci_shutdown_one(struct pci_dev *pdev)
1920{
1921        ata_pci_shutdown_one(pdev);
1922}
1923
1924static void ahci_remove_one(struct pci_dev *pdev)
1925{
1926        sysfs_remove_file_from_group(&pdev->dev.kobj,
1927                                     &dev_attr_remapped_nvme.attr,
1928                                     NULL);
1929        pm_runtime_get_noresume(&pdev->dev);
1930        ata_pci_remove_one(pdev);
1931}
1932
1933module_pci_driver(ahci_pci_driver);
1934
1935MODULE_AUTHOR("Jeff Garzik");
1936MODULE_DESCRIPTION("AHCI SATA low-level driver");
1937MODULE_LICENSE("GPL");
1938MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1939MODULE_VERSION(DRV_VERSION);
1940