linux/arch/x86/kernel/process.c
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   1// SPDX-License-Identifier: GPL-2.0
   2#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   3
   4#include <linux/errno.h>
   5#include <linux/kernel.h>
   6#include <linux/mm.h>
   7#include <linux/smp.h>
   8#include <linux/prctl.h>
   9#include <linux/slab.h>
  10#include <linux/sched.h>
  11#include <linux/sched/idle.h>
  12#include <linux/sched/debug.h>
  13#include <linux/sched/task.h>
  14#include <linux/sched/task_stack.h>
  15#include <linux/init.h>
  16#include <linux/export.h>
  17#include <linux/pm.h>
  18#include <linux/tick.h>
  19#include <linux/random.h>
  20#include <linux/user-return-notifier.h>
  21#include <linux/dmi.h>
  22#include <linux/utsname.h>
  23#include <linux/stackprotector.h>
  24#include <linux/tick.h>
  25#include <linux/cpuidle.h>
  26#include <trace/events/power.h>
  27#include <linux/hw_breakpoint.h>
  28#include <asm/cpu.h>
  29#include <asm/apic.h>
  30#include <asm/syscalls.h>
  31#include <linux/uaccess.h>
  32#include <asm/mwait.h>
  33#include <asm/fpu/internal.h>
  34#include <asm/debugreg.h>
  35#include <asm/nmi.h>
  36#include <asm/tlbflush.h>
  37#include <asm/mce.h>
  38#include <asm/vm86.h>
  39#include <asm/switch_to.h>
  40#include <asm/desc.h>
  41#include <asm/prctl.h>
  42
  43/*
  44 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
  45 * no more per-task TSS's. The TSS size is kept cacheline-aligned
  46 * so they are allowed to end up in the .data..cacheline_aligned
  47 * section. Since TSS's are completely CPU-local, we want them
  48 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
  49 */
  50__visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
  51        .x86_tss = {
  52                /*
  53                 * .sp0 is only used when entering ring 0 from a lower
  54                 * privilege level.  Since the init task never runs anything
  55                 * but ring 0 code, there is no need for a valid value here.
  56                 * Poison it.
  57                 */
  58                .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
  59
  60#ifdef CONFIG_X86_64
  61                /*
  62                 * .sp1 is cpu_current_top_of_stack.  The init task never
  63                 * runs user code, but cpu_current_top_of_stack should still
  64                 * be well defined before the first context switch.
  65                 */
  66                .sp1 = TOP_OF_INIT_STACK,
  67#endif
  68
  69#ifdef CONFIG_X86_32
  70                .ss0 = __KERNEL_DS,
  71                .ss1 = __KERNEL_CS,
  72                .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
  73#endif
  74         },
  75#ifdef CONFIG_X86_32
  76         /*
  77          * Note that the .io_bitmap member must be extra-big. This is because
  78          * the CPU will access an additional byte beyond the end of the IO
  79          * permission bitmap. The extra byte must be all 1 bits, and must
  80          * be within the limit.
  81          */
  82        .io_bitmap              = { [0 ... IO_BITMAP_LONGS] = ~0 },
  83#endif
  84};
  85EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
  86
  87DEFINE_PER_CPU(bool, __tss_limit_invalid);
  88EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
  89
  90/*
  91 * this gets called so that we can store lazy state into memory and copy the
  92 * current task into the new thread.
  93 */
  94int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  95{
  96        memcpy(dst, src, arch_task_struct_size);
  97#ifdef CONFIG_VM86
  98        dst->thread.vm86 = NULL;
  99#endif
 100
 101        return fpu__copy(&dst->thread.fpu, &src->thread.fpu);
 102}
 103
 104/*
 105 * Free current thread data structures etc..
 106 */
 107void exit_thread(struct task_struct *tsk)
 108{
 109        struct thread_struct *t = &tsk->thread;
 110        unsigned long *bp = t->io_bitmap_ptr;
 111        struct fpu *fpu = &t->fpu;
 112
 113        if (bp) {
 114                struct tss_struct *tss = &per_cpu(cpu_tss_rw, get_cpu());
 115
 116                t->io_bitmap_ptr = NULL;
 117                clear_thread_flag(TIF_IO_BITMAP);
 118                /*
 119                 * Careful, clear this in the TSS too:
 120                 */
 121                memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
 122                t->io_bitmap_max = 0;
 123                put_cpu();
 124                kfree(bp);
 125        }
 126
 127        free_vm86(t);
 128
 129        fpu__drop(fpu);
 130}
 131
 132void flush_thread(void)
 133{
 134        struct task_struct *tsk = current;
 135
 136        flush_ptrace_hw_breakpoint(tsk);
 137        memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
 138
 139        fpu__clear(&tsk->thread.fpu);
 140}
 141
 142void disable_TSC(void)
 143{
 144        preempt_disable();
 145        if (!test_and_set_thread_flag(TIF_NOTSC))
 146                /*
 147                 * Must flip the CPU state synchronously with
 148                 * TIF_NOTSC in the current running context.
 149                 */
 150                cr4_set_bits(X86_CR4_TSD);
 151        preempt_enable();
 152}
 153
 154static void enable_TSC(void)
 155{
 156        preempt_disable();
 157        if (test_and_clear_thread_flag(TIF_NOTSC))
 158                /*
 159                 * Must flip the CPU state synchronously with
 160                 * TIF_NOTSC in the current running context.
 161                 */
 162                cr4_clear_bits(X86_CR4_TSD);
 163        preempt_enable();
 164}
 165
 166int get_tsc_mode(unsigned long adr)
 167{
 168        unsigned int val;
 169
 170        if (test_thread_flag(TIF_NOTSC))
 171                val = PR_TSC_SIGSEGV;
 172        else
 173                val = PR_TSC_ENABLE;
 174
 175        return put_user(val, (unsigned int __user *)adr);
 176}
 177
 178int set_tsc_mode(unsigned int val)
 179{
 180        if (val == PR_TSC_SIGSEGV)
 181                disable_TSC();
 182        else if (val == PR_TSC_ENABLE)
 183                enable_TSC();
 184        else
 185                return -EINVAL;
 186
 187        return 0;
 188}
 189
 190DEFINE_PER_CPU(u64, msr_misc_features_shadow);
 191
 192static void set_cpuid_faulting(bool on)
 193{
 194        u64 msrval;
 195
 196        msrval = this_cpu_read(msr_misc_features_shadow);
 197        msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
 198        msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
 199        this_cpu_write(msr_misc_features_shadow, msrval);
 200        wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
 201}
 202
 203static void disable_cpuid(void)
 204{
 205        preempt_disable();
 206        if (!test_and_set_thread_flag(TIF_NOCPUID)) {
 207                /*
 208                 * Must flip the CPU state synchronously with
 209                 * TIF_NOCPUID in the current running context.
 210                 */
 211                set_cpuid_faulting(true);
 212        }
 213        preempt_enable();
 214}
 215
 216static void enable_cpuid(void)
 217{
 218        preempt_disable();
 219        if (test_and_clear_thread_flag(TIF_NOCPUID)) {
 220                /*
 221                 * Must flip the CPU state synchronously with
 222                 * TIF_NOCPUID in the current running context.
 223                 */
 224                set_cpuid_faulting(false);
 225        }
 226        preempt_enable();
 227}
 228
 229static int get_cpuid_mode(void)
 230{
 231        return !test_thread_flag(TIF_NOCPUID);
 232}
 233
 234static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
 235{
 236        if (!static_cpu_has(X86_FEATURE_CPUID_FAULT))
 237                return -ENODEV;
 238
 239        if (cpuid_enabled)
 240                enable_cpuid();
 241        else
 242                disable_cpuid();
 243
 244        return 0;
 245}
 246
 247/*
 248 * Called immediately after a successful exec.
 249 */
 250void arch_setup_new_exec(void)
 251{
 252        /* If cpuid was previously disabled for this task, re-enable it. */
 253        if (test_thread_flag(TIF_NOCPUID))
 254                enable_cpuid();
 255}
 256
 257static inline void switch_to_bitmap(struct tss_struct *tss,
 258                                    struct thread_struct *prev,
 259                                    struct thread_struct *next,
 260                                    unsigned long tifp, unsigned long tifn)
 261{
 262        if (tifn & _TIF_IO_BITMAP) {
 263                /*
 264                 * Copy the relevant range of the IO bitmap.
 265                 * Normally this is 128 bytes or less:
 266                 */
 267                memcpy(tss->io_bitmap, next->io_bitmap_ptr,
 268                       max(prev->io_bitmap_max, next->io_bitmap_max));
 269                /*
 270                 * Make sure that the TSS limit is correct for the CPU
 271                 * to notice the IO bitmap.
 272                 */
 273                refresh_tss_limit();
 274        } else if (tifp & _TIF_IO_BITMAP) {
 275                /*
 276                 * Clear any possible leftover bits:
 277                 */
 278                memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
 279        }
 280}
 281
 282void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
 283                      struct tss_struct *tss)
 284{
 285        struct thread_struct *prev, *next;
 286        unsigned long tifp, tifn;
 287
 288        prev = &prev_p->thread;
 289        next = &next_p->thread;
 290
 291        tifn = READ_ONCE(task_thread_info(next_p)->flags);
 292        tifp = READ_ONCE(task_thread_info(prev_p)->flags);
 293        switch_to_bitmap(tss, prev, next, tifp, tifn);
 294
 295        propagate_user_return_notify(prev_p, next_p);
 296
 297        if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
 298            arch_has_block_step()) {
 299                unsigned long debugctl, msk;
 300
 301                rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
 302                debugctl &= ~DEBUGCTLMSR_BTF;
 303                msk = tifn & _TIF_BLOCKSTEP;
 304                debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
 305                wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
 306        }
 307
 308        if ((tifp ^ tifn) & _TIF_NOTSC)
 309                cr4_toggle_bits_irqsoff(X86_CR4_TSD);
 310
 311        if ((tifp ^ tifn) & _TIF_NOCPUID)
 312                set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
 313}
 314
 315/*
 316 * Idle related variables and functions
 317 */
 318unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
 319EXPORT_SYMBOL(boot_option_idle_override);
 320
 321static void (*x86_idle)(void);
 322
 323#ifndef CONFIG_SMP
 324static inline void play_dead(void)
 325{
 326        BUG();
 327}
 328#endif
 329
 330void arch_cpu_idle_enter(void)
 331{
 332        tsc_verify_tsc_adjust(false);
 333        local_touch_nmi();
 334}
 335
 336void arch_cpu_idle_dead(void)
 337{
 338        play_dead();
 339}
 340
 341/*
 342 * Called from the generic idle code.
 343 */
 344void arch_cpu_idle(void)
 345{
 346        x86_idle();
 347}
 348
 349/*
 350 * We use this if we don't have any better idle routine..
 351 */
 352void __cpuidle default_idle(void)
 353{
 354        trace_cpu_idle_rcuidle(1, smp_processor_id());
 355        safe_halt();
 356        trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
 357}
 358#ifdef CONFIG_APM_MODULE
 359EXPORT_SYMBOL(default_idle);
 360#endif
 361
 362#ifdef CONFIG_XEN
 363bool xen_set_default_idle(void)
 364{
 365        bool ret = !!x86_idle;
 366
 367        x86_idle = default_idle;
 368
 369        return ret;
 370}
 371#endif
 372
 373void stop_this_cpu(void *dummy)
 374{
 375        local_irq_disable();
 376        /*
 377         * Remove this CPU:
 378         */
 379        set_cpu_online(smp_processor_id(), false);
 380        disable_local_APIC();
 381        mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
 382
 383        /*
 384         * Use wbinvd on processors that support SME. This provides support
 385         * for performing a successful kexec when going from SME inactive
 386         * to SME active (or vice-versa). The cache must be cleared so that
 387         * if there are entries with the same physical address, both with and
 388         * without the encryption bit, they don't race each other when flushed
 389         * and potentially end up with the wrong entry being committed to
 390         * memory.
 391         */
 392        if (boot_cpu_has(X86_FEATURE_SME))
 393                native_wbinvd();
 394        for (;;) {
 395                /*
 396                 * Use native_halt() so that memory contents don't change
 397                 * (stack usage and variables) after possibly issuing the
 398                 * native_wbinvd() above.
 399                 */
 400                native_halt();
 401        }
 402}
 403
 404/*
 405 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
 406 * states (local apic timer and TSC stop).
 407 */
 408static void amd_e400_idle(void)
 409{
 410        /*
 411         * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
 412         * gets set after static_cpu_has() places have been converted via
 413         * alternatives.
 414         */
 415        if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
 416                default_idle();
 417                return;
 418        }
 419
 420        tick_broadcast_enter();
 421
 422        default_idle();
 423
 424        /*
 425         * The switch back from broadcast mode needs to be called with
 426         * interrupts disabled.
 427         */
 428        local_irq_disable();
 429        tick_broadcast_exit();
 430        local_irq_enable();
 431}
 432
 433/*
 434 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
 435 * We can't rely on cpuidle installing MWAIT, because it will not load
 436 * on systems that support only C1 -- so the boot default must be MWAIT.
 437 *
 438 * Some AMD machines are the opposite, they depend on using HALT.
 439 *
 440 * So for default C1, which is used during boot until cpuidle loads,
 441 * use MWAIT-C1 on Intel HW that has it, else use HALT.
 442 */
 443static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
 444{
 445        if (c->x86_vendor != X86_VENDOR_INTEL)
 446                return 0;
 447
 448        if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR))
 449                return 0;
 450
 451        return 1;
 452}
 453
 454/*
 455 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
 456 * with interrupts enabled and no flags, which is backwards compatible with the
 457 * original MWAIT implementation.
 458 */
 459static __cpuidle void mwait_idle(void)
 460{
 461        if (!current_set_polling_and_test()) {
 462                trace_cpu_idle_rcuidle(1, smp_processor_id());
 463                if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
 464                        mb(); /* quirk */
 465                        clflush((void *)&current_thread_info()->flags);
 466                        mb(); /* quirk */
 467                }
 468
 469                __monitor((void *)&current_thread_info()->flags, 0, 0);
 470                if (!need_resched())
 471                        __sti_mwait(0, 0);
 472                else
 473                        local_irq_enable();
 474                trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
 475        } else {
 476                local_irq_enable();
 477        }
 478        __current_clr_polling();
 479}
 480
 481void select_idle_routine(const struct cpuinfo_x86 *c)
 482{
 483#ifdef CONFIG_SMP
 484        if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
 485                pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
 486#endif
 487        if (x86_idle || boot_option_idle_override == IDLE_POLL)
 488                return;
 489
 490        if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
 491                pr_info("using AMD E400 aware idle routine\n");
 492                x86_idle = amd_e400_idle;
 493        } else if (prefer_mwait_c1_over_halt(c)) {
 494                pr_info("using mwait in idle threads\n");
 495                x86_idle = mwait_idle;
 496        } else
 497                x86_idle = default_idle;
 498}
 499
 500void amd_e400_c1e_apic_setup(void)
 501{
 502        if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
 503                pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
 504                local_irq_disable();
 505                tick_broadcast_force();
 506                local_irq_enable();
 507        }
 508}
 509
 510void __init arch_post_acpi_subsys_init(void)
 511{
 512        u32 lo, hi;
 513
 514        if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
 515                return;
 516
 517        /*
 518         * AMD E400 detection needs to happen after ACPI has been enabled. If
 519         * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
 520         * MSR_K8_INT_PENDING_MSG.
 521         */
 522        rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 523        if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
 524                return;
 525
 526        boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
 527
 528        if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 529                mark_tsc_unstable("TSC halt in AMD C1E");
 530        pr_info("System has AMD C1E enabled\n");
 531}
 532
 533static int __init idle_setup(char *str)
 534{
 535        if (!str)
 536                return -EINVAL;
 537
 538        if (!strcmp(str, "poll")) {
 539                pr_info("using polling idle threads\n");
 540                boot_option_idle_override = IDLE_POLL;
 541                cpu_idle_poll_ctrl(true);
 542        } else if (!strcmp(str, "halt")) {
 543                /*
 544                 * When the boot option of idle=halt is added, halt is
 545                 * forced to be used for CPU idle. In such case CPU C2/C3
 546                 * won't be used again.
 547                 * To continue to load the CPU idle driver, don't touch
 548                 * the boot_option_idle_override.
 549                 */
 550                x86_idle = default_idle;
 551                boot_option_idle_override = IDLE_HALT;
 552        } else if (!strcmp(str, "nomwait")) {
 553                /*
 554                 * If the boot option of "idle=nomwait" is added,
 555                 * it means that mwait will be disabled for CPU C2/C3
 556                 * states. In such case it won't touch the variable
 557                 * of boot_option_idle_override.
 558                 */
 559                boot_option_idle_override = IDLE_NOMWAIT;
 560        } else
 561                return -1;
 562
 563        return 0;
 564}
 565early_param("idle", idle_setup);
 566
 567unsigned long arch_align_stack(unsigned long sp)
 568{
 569        if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
 570                sp -= get_random_int() % 8192;
 571        return sp & ~0xf;
 572}
 573
 574unsigned long arch_randomize_brk(struct mm_struct *mm)
 575{
 576        return randomize_page(mm->brk, 0x02000000);
 577}
 578
 579/*
 580 * Called from fs/proc with a reference on @p to find the function
 581 * which called into schedule(). This needs to be done carefully
 582 * because the task might wake up and we might look at a stack
 583 * changing under us.
 584 */
 585unsigned long get_wchan(struct task_struct *p)
 586{
 587        unsigned long start, bottom, top, sp, fp, ip, ret = 0;
 588        int count = 0;
 589
 590        if (!p || p == current || p->state == TASK_RUNNING)
 591                return 0;
 592
 593        if (!try_get_task_stack(p))
 594                return 0;
 595
 596        start = (unsigned long)task_stack_page(p);
 597        if (!start)
 598                goto out;
 599
 600        /*
 601         * Layout of the stack page:
 602         *
 603         * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
 604         * PADDING
 605         * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
 606         * stack
 607         * ----------- bottom = start
 608         *
 609         * The tasks stack pointer points at the location where the
 610         * framepointer is stored. The data on the stack is:
 611         * ... IP FP ... IP FP
 612         *
 613         * We need to read FP and IP, so we need to adjust the upper
 614         * bound by another unsigned long.
 615         */
 616        top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
 617        top -= 2 * sizeof(unsigned long);
 618        bottom = start;
 619
 620        sp = READ_ONCE(p->thread.sp);
 621        if (sp < bottom || sp > top)
 622                goto out;
 623
 624        fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
 625        do {
 626                if (fp < bottom || fp > top)
 627                        goto out;
 628                ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
 629                if (!in_sched_functions(ip)) {
 630                        ret = ip;
 631                        goto out;
 632                }
 633                fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
 634        } while (count++ < 16 && p->state != TASK_RUNNING);
 635
 636out:
 637        put_task_stack(p);
 638        return ret;
 639}
 640
 641long do_arch_prctl_common(struct task_struct *task, int option,
 642                          unsigned long cpuid_enabled)
 643{
 644        switch (option) {
 645        case ARCH_GET_CPUID:
 646                return get_cpuid_mode();
 647        case ARCH_SET_CPUID:
 648                return set_cpuid_mode(task, cpuid_enabled);
 649        }
 650
 651        return -EINVAL;
 652}
 653
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