linux/arch/powerpc/sysdev/fsl_pci.c
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   1/*
   2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
   3 *
   4 * Copyright 2007-2012 Freescale Semiconductor, Inc.
   5 * Copyright 2008-2009 MontaVista Software, Inc.
   6 *
   7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
   8 * Recode: ZHANG WEI <wei.zhang@freescale.com>
   9 * Rewrite the routing for Frescale PCI and PCI Express
  10 *      Roy Zang <tie-fei.zang@freescale.com>
  11 * MPC83xx PCI-Express support:
  12 *      Tony Li <tony.li@freescale.com>
  13 *      Anton Vorontsov <avorontsov@ru.mvista.com>
  14 *
  15 * This program is free software; you can redistribute  it and/or modify it
  16 * under  the terms of  the GNU General  Public License as published by the
  17 * Free Software Foundation;  either version 2 of the  License, or (at your
  18 * option) any later version.
  19 */
  20#include <linux/kernel.h>
  21#include <linux/pci.h>
  22#include <linux/delay.h>
  23#include <linux/string.h>
  24#include <linux/init.h>
  25#include <linux/interrupt.h>
  26#include <linux/memblock.h>
  27#include <linux/log2.h>
  28#include <linux/slab.h>
  29#include <linux/suspend.h>
  30#include <linux/syscore_ops.h>
  31#include <linux/uaccess.h>
  32
  33#include <asm/io.h>
  34#include <asm/prom.h>
  35#include <asm/pci-bridge.h>
  36#include <asm/ppc-pci.h>
  37#include <asm/machdep.h>
  38#include <asm/disassemble.h>
  39#include <asm/ppc-opcode.h>
  40#include <sysdev/fsl_soc.h>
  41#include <sysdev/fsl_pci.h>
  42
  43static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
  44
  45static void quirk_fsl_pcie_early(struct pci_dev *dev)
  46{
  47        u8 hdr_type;
  48
  49        /* if we aren't a PCIe don't bother */
  50        if (!pci_is_pcie(dev))
  51                return;
  52
  53        /* if we aren't in host mode don't bother */
  54        pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
  55        if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
  56                return;
  57
  58        dev->class = PCI_CLASS_BRIDGE_PCI << 8;
  59        fsl_pcie_bus_fixup = 1;
  60        return;
  61}
  62
  63static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
  64                                    int, int, u32 *);
  65
  66static int fsl_pcie_check_link(struct pci_controller *hose)
  67{
  68        u32 val = 0;
  69
  70        if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
  71                if (hose->ops->read == fsl_indirect_read_config) {
  72                        struct pci_bus bus;
  73                        bus.number = hose->first_busno;
  74                        bus.sysdata = hose;
  75                        bus.ops = hose->ops;
  76                        indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);
  77                } else
  78                        early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
  79                if (val < PCIE_LTSSM_L0)
  80                        return 1;
  81        } else {
  82                struct ccsr_pci __iomem *pci = hose->private_data;
  83                /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
  84                val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
  85                                >> PEX_CSR0_LTSSM_SHIFT;
  86                if (val != PEX_CSR0_LTSSM_L0)
  87                        return 1;
  88        }
  89
  90        return 0;
  91}
  92
  93static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
  94                                    int offset, int len, u32 *val)
  95{
  96        struct pci_controller *hose = pci_bus_to_host(bus);
  97
  98        if (fsl_pcie_check_link(hose))
  99                hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
 100        else
 101                hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
 102
 103        return indirect_read_config(bus, devfn, offset, len, val);
 104}
 105
 106#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
 107
 108static struct pci_ops fsl_indirect_pcie_ops =
 109{
 110        .read = fsl_indirect_read_config,
 111        .write = indirect_write_config,
 112};
 113
 114#define MAX_PHYS_ADDR_BITS      40
 115static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
 116
 117static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
 118{
 119        if (!dev->dma_mask || !dma_supported(dev, dma_mask))
 120                return -EIO;
 121
 122        /*
 123         * Fixup PCI devices that are able to DMA to above the physical
 124         * address width of the SoC such that we can address any internal
 125         * SoC address from across PCI if needed
 126         */
 127        if ((dev_is_pci(dev)) &&
 128            dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
 129                set_dma_ops(dev, &dma_direct_ops);
 130                set_dma_offset(dev, pci64_dma_offset);
 131        }
 132
 133        *dev->dma_mask = dma_mask;
 134        return 0;
 135}
 136
 137static int setup_one_atmu(struct ccsr_pci __iomem *pci,
 138        unsigned int index, const struct resource *res,
 139        resource_size_t offset)
 140{
 141        resource_size_t pci_addr = res->start - offset;
 142        resource_size_t phys_addr = res->start;
 143        resource_size_t size = resource_size(res);
 144        u32 flags = 0x80044000; /* enable & mem R/W */
 145        unsigned int i;
 146
 147        pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
 148                (u64)res->start, (u64)size);
 149
 150        if (res->flags & IORESOURCE_PREFETCH)
 151                flags |= 0x10000000; /* enable relaxed ordering */
 152
 153        for (i = 0; size > 0; i++) {
 154                unsigned int bits = min_t(u32, ilog2(size),
 155                                        __ffs(pci_addr | phys_addr));
 156
 157                if (index + i >= 5)
 158                        return -1;
 159
 160                out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
 161                out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
 162                out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
 163                out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
 164
 165                pci_addr += (resource_size_t)1U << bits;
 166                phys_addr += (resource_size_t)1U << bits;
 167                size -= (resource_size_t)1U << bits;
 168        }
 169
 170        return i;
 171}
 172
 173/* atmu setup for fsl pci/pcie controller */
 174static void setup_pci_atmu(struct pci_controller *hose)
 175{
 176        struct ccsr_pci __iomem *pci = hose->private_data;
 177        int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
 178        u64 mem, sz, paddr_hi = 0;
 179        u64 offset = 0, paddr_lo = ULLONG_MAX;
 180        u32 pcicsrbar = 0, pcicsrbar_sz;
 181        u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
 182                        PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
 183        const char *name = hose->dn->full_name;
 184        const u64 *reg;
 185        int len;
 186
 187        if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
 188                if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
 189                        win_idx = 2;
 190                        start_idx = 0;
 191                        end_idx = 3;
 192                }
 193        }
 194
 195        /* Disable all windows (except powar0 since it's ignored) */
 196        for(i = 1; i < 5; i++)
 197                out_be32(&pci->pow[i].powar, 0);
 198        for (i = start_idx; i < end_idx; i++)
 199                out_be32(&pci->piw[i].piwar, 0);
 200
 201        /* Setup outbound MEM window */
 202        for(i = 0, j = 1; i < 3; i++) {
 203                if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
 204                        continue;
 205
 206                paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
 207                paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
 208
 209                /* We assume all memory resources have the same offset */
 210                offset = hose->mem_offset[i];
 211                n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
 212
 213                if (n < 0 || j >= 5) {
 214                        pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
 215                        hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
 216                } else
 217                        j += n;
 218        }
 219
 220        /* Setup outbound IO window */
 221        if (hose->io_resource.flags & IORESOURCE_IO) {
 222                if (j >= 5) {
 223                        pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
 224                } else {
 225                        pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
 226                                 "phy base 0x%016llx.\n",
 227                                 (u64)hose->io_resource.start,
 228                                 (u64)resource_size(&hose->io_resource),
 229                                 (u64)hose->io_base_phys);
 230                        out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
 231                        out_be32(&pci->pow[j].potear, 0);
 232                        out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
 233                        /* Enable, IO R/W */
 234                        out_be32(&pci->pow[j].powar, 0x80088000
 235                                | (ilog2(hose->io_resource.end
 236                                - hose->io_resource.start + 1) - 1));
 237                }
 238        }
 239
 240        /* convert to pci address space */
 241        paddr_hi -= offset;
 242        paddr_lo -= offset;
 243
 244        if (paddr_hi == paddr_lo) {
 245                pr_err("%s: No outbound window space\n", name);
 246                return;
 247        }
 248
 249        if (paddr_lo == 0) {
 250                pr_err("%s: No space for inbound window\n", name);
 251                return;
 252        }
 253
 254        /* setup PCSRBAR/PEXCSRBAR */
 255        early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
 256        early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
 257        pcicsrbar_sz = ~pcicsrbar_sz + 1;
 258
 259        if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
 260                (paddr_lo > 0x100000000ull))
 261                pcicsrbar = 0x100000000ull - pcicsrbar_sz;
 262        else
 263                pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
 264        early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
 265
 266        paddr_lo = min(paddr_lo, (u64)pcicsrbar);
 267
 268        pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
 269
 270        /* Setup inbound mem window */
 271        mem = memblock_end_of_DRAM();
 272
 273        /*
 274         * The msi-address-64 property, if it exists, indicates the physical
 275         * address of the MSIIR register.  Normally, this register is located
 276         * inside CCSR, so the ATMU that covers all of CCSR is used. But if
 277         * this property exists, then we normally need to create a new ATMU
 278         * for it.  For now, however, we cheat.  The only entity that creates
 279         * this property is the Freescale hypervisor, and the address is
 280         * specified in the partition configuration.  Typically, the address
 281         * is located in the page immediately after the end of DDR.  If so, we
 282         * can avoid allocating a new ATMU by extending the DDR ATMU by one
 283         * page.
 284         */
 285        reg = of_get_property(hose->dn, "msi-address-64", &len);
 286        if (reg && (len == sizeof(u64))) {
 287                u64 address = be64_to_cpup(reg);
 288
 289                if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
 290                        pr_info("%s: extending DDR ATMU to cover MSIIR", name);
 291                        mem += PAGE_SIZE;
 292                } else {
 293                        /* TODO: Create a new ATMU for MSIIR */
 294                        pr_warn("%s: msi-address-64 address of %llx is "
 295                                "unsupported\n", name, address);
 296                }
 297        }
 298
 299        sz = min(mem, paddr_lo);
 300        mem_log = ilog2(sz);
 301
 302        /* PCIe can overmap inbound & outbound since RX & TX are separated */
 303        if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
 304                /* Size window to exact size if power-of-two or one size up */
 305                if ((1ull << mem_log) != mem) {
 306                        mem_log++;
 307                        if ((1ull << mem_log) > mem)
 308                                pr_info("%s: Setting PCI inbound window "
 309                                        "greater than memory size\n", name);
 310                }
 311
 312                piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
 313
 314                /* Setup inbound memory window */
 315                out_be32(&pci->piw[win_idx].pitar,  0x00000000);
 316                out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
 317                out_be32(&pci->piw[win_idx].piwar,  piwar);
 318                win_idx--;
 319
 320                hose->dma_window_base_cur = 0x00000000;
 321                hose->dma_window_size = (resource_size_t)sz;
 322
 323                /*
 324                 * if we have >4G of memory setup second PCI inbound window to
 325                 * let devices that are 64-bit address capable to work w/o
 326                 * SWIOTLB and access the full range of memory
 327                 */
 328                if (sz != mem) {
 329                        mem_log = ilog2(mem);
 330
 331                        /* Size window up if we dont fit in exact power-of-2 */
 332                        if ((1ull << mem_log) != mem)
 333                                mem_log++;
 334
 335                        piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
 336
 337                        /* Setup inbound memory window */
 338                        out_be32(&pci->piw[win_idx].pitar,  0x00000000);
 339                        out_be32(&pci->piw[win_idx].piwbear,
 340                                        pci64_dma_offset >> 44);
 341                        out_be32(&pci->piw[win_idx].piwbar,
 342                                        pci64_dma_offset >> 12);
 343                        out_be32(&pci->piw[win_idx].piwar,  piwar);
 344
 345                        /*
 346                         * install our own dma_set_mask handler to fixup dma_ops
 347                         * and dma_offset
 348                         */
 349                        ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
 350
 351                        pr_info("%s: Setup 64-bit PCI DMA window\n", name);
 352                }
 353        } else {
 354                u64 paddr = 0;
 355
 356                /* Setup inbound memory window */
 357                out_be32(&pci->piw[win_idx].pitar,  paddr >> 12);
 358                out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
 359                out_be32(&pci->piw[win_idx].piwar,  (piwar | (mem_log - 1)));
 360                win_idx--;
 361
 362                paddr += 1ull << mem_log;
 363                sz -= 1ull << mem_log;
 364
 365                if (sz) {
 366                        mem_log = ilog2(sz);
 367                        piwar |= (mem_log - 1);
 368
 369                        out_be32(&pci->piw[win_idx].pitar,  paddr >> 12);
 370                        out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
 371                        out_be32(&pci->piw[win_idx].piwar,  piwar);
 372                        win_idx--;
 373
 374                        paddr += 1ull << mem_log;
 375                }
 376
 377                hose->dma_window_base_cur = 0x00000000;
 378                hose->dma_window_size = (resource_size_t)paddr;
 379        }
 380
 381        if (hose->dma_window_size < mem) {
 382#ifdef CONFIG_SWIOTLB
 383                ppc_swiotlb_enable = 1;
 384#else
 385                pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
 386                        "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
 387                         name);
 388#endif
 389                /* adjusting outbound windows could reclaim space in mem map */
 390                if (paddr_hi < 0xffffffffull)
 391                        pr_warning("%s: WARNING: Outbound window cfg leaves "
 392                                "gaps in memory map. Adjusting the memory map "
 393                                "could reduce unnecessary bounce buffering.\n",
 394                                name);
 395
 396                pr_info("%s: DMA window size is 0x%llx\n", name,
 397                        (u64)hose->dma_window_size);
 398        }
 399}
 400
 401static void __init setup_pci_cmd(struct pci_controller *hose)
 402{
 403        u16 cmd;
 404        int cap_x;
 405
 406        early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
 407        cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
 408                | PCI_COMMAND_IO;
 409        early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
 410
 411        cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
 412        if (cap_x) {
 413                int pci_x_cmd = cap_x + PCI_X_CMD;
 414                cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
 415                        | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
 416                early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
 417        } else {
 418                early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
 419        }
 420}
 421
 422void fsl_pcibios_fixup_bus(struct pci_bus *bus)
 423{
 424        struct pci_controller *hose = pci_bus_to_host(bus);
 425        int i, is_pcie = 0, no_link;
 426
 427        /* The root complex bridge comes up with bogus resources,
 428         * we copy the PHB ones in.
 429         *
 430         * With the current generic PCI code, the PHB bus no longer
 431         * has bus->resource[0..4] set, so things are a bit more
 432         * tricky.
 433         */
 434
 435        if (fsl_pcie_bus_fixup)
 436                is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
 437        no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
 438
 439        if (bus->parent == hose->bus && (is_pcie || no_link)) {
 440                for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {
 441                        struct resource *res = bus->resource[i];
 442                        struct resource *par;
 443
 444                        if (!res)
 445                                continue;
 446                        if (i == 0)
 447                                par = &hose->io_resource;
 448                        else if (i < 4)
 449                                par = &hose->mem_resources[i-1];
 450                        else par = NULL;
 451
 452                        res->start = par ? par->start : 0;
 453                        res->end   = par ? par->end   : 0;
 454                        res->flags = par ? par->flags : 0;
 455                }
 456        }
 457}
 458
 459int fsl_add_bridge(struct platform_device *pdev, int is_primary)
 460{
 461        int len;
 462        struct pci_controller *hose;
 463        struct resource rsrc;
 464        const int *bus_range;
 465        u8 hdr_type, progif;
 466        struct device_node *dev;
 467        struct ccsr_pci __iomem *pci;
 468
 469        dev = pdev->dev.of_node;
 470
 471        if (!of_device_is_available(dev)) {
 472                pr_warning("%s: disabled\n", dev->full_name);
 473                return -ENODEV;
 474        }
 475
 476        pr_debug("Adding PCI host bridge %s\n", dev->full_name);
 477
 478        /* Fetch host bridge registers address */
 479        if (of_address_to_resource(dev, 0, &rsrc)) {
 480                printk(KERN_WARNING "Can't get pci register base!");
 481                return -ENOMEM;
 482        }
 483
 484        /* Get bus range if any */
 485        bus_range = of_get_property(dev, "bus-range", &len);
 486        if (bus_range == NULL || len < 2 * sizeof(int))
 487                printk(KERN_WARNING "Can't get bus-range for %s, assume"
 488                        " bus 0\n", dev->full_name);
 489
 490        pci_add_flags(PCI_REASSIGN_ALL_BUS);
 491        hose = pcibios_alloc_controller(dev);
 492        if (!hose)
 493                return -ENOMEM;
 494
 495        /* set platform device as the parent */
 496        hose->parent = &pdev->dev;
 497        hose->first_busno = bus_range ? bus_range[0] : 0x0;
 498        hose->last_busno = bus_range ? bus_range[1] : 0xff;
 499
 500        pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
 501                 (u64)rsrc.start, (u64)resource_size(&rsrc));
 502
 503        pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
 504        if (!hose->private_data)
 505                goto no_bridge;
 506
 507        setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
 508                           PPC_INDIRECT_TYPE_BIG_ENDIAN);
 509
 510        if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
 511                hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
 512
 513        if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
 514                /* use fsl_indirect_read_config for PCIe */
 515                hose->ops = &fsl_indirect_pcie_ops;
 516                /* For PCIE read HEADER_TYPE to identify controler mode */
 517                early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
 518                if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
 519                        goto no_bridge;
 520
 521        } else {
 522                /* For PCI read PROG to identify controller mode */
 523                early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
 524                if ((progif & 1) &&
 525                    !of_property_read_bool(dev, "fsl,pci-agent-force-enum"))
 526                        goto no_bridge;
 527        }
 528
 529        setup_pci_cmd(hose);
 530
 531        /* check PCI express link status */
 532        if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
 533                hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
 534                        PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
 535                if (fsl_pcie_check_link(hose))
 536                        hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
 537        }
 538
 539        printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
 540                "Firmware bus number: %d->%d\n",
 541                (unsigned long long)rsrc.start, hose->first_busno,
 542                hose->last_busno);
 543
 544        pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
 545                hose, hose->cfg_addr, hose->cfg_data);
 546
 547        /* Interpret the "ranges" property */
 548        /* This also maps the I/O region and sets isa_io/mem_base */
 549        pci_process_bridge_OF_ranges(hose, dev, is_primary);
 550
 551        /* Setup PEX window registers */
 552        setup_pci_atmu(hose);
 553
 554        return 0;
 555
 556no_bridge:
 557        iounmap(hose->private_data);
 558        /* unmap cfg_data & cfg_addr separately if not on same page */
 559        if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
 560            ((unsigned long)hose->cfg_addr & PAGE_MASK))
 561                iounmap(hose->cfg_data);
 562        iounmap(hose->cfg_addr);
 563        pcibios_free_controller(hose);
 564        return -ENODEV;
 565}
 566#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
 567
 568DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
 569                        quirk_fsl_pcie_early);
 570
 571#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
 572struct mpc83xx_pcie_priv {
 573        void __iomem *cfg_type0;
 574        void __iomem *cfg_type1;
 575        u32 dev_base;
 576};
 577
 578struct pex_inbound_window {
 579        u32 ar;
 580        u32 tar;
 581        u32 barl;
 582        u32 barh;
 583};
 584
 585/*
 586 * With the convention of u-boot, the PCIE outbound window 0 serves
 587 * as configuration transactions outbound.
 588 */
 589#define PEX_OUTWIN0_BAR         0xCA4
 590#define PEX_OUTWIN0_TAL         0xCA8
 591#define PEX_OUTWIN0_TAH         0xCAC
 592#define PEX_RC_INWIN_BASE       0xE60
 593#define PEX_RCIWARn_EN          0x1
 594
 595static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
 596{
 597        struct pci_controller *hose = pci_bus_to_host(bus);
 598
 599        if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
 600                return PCIBIOS_DEVICE_NOT_FOUND;
 601        /*
 602         * Workaround for the HW bug: for Type 0 configure transactions the
 603         * PCI-E controller does not check the device number bits and just
 604         * assumes that the device number bits are 0.
 605         */
 606        if (bus->number == hose->first_busno ||
 607                        bus->primary == hose->first_busno) {
 608                if (devfn & 0xf8)
 609                        return PCIBIOS_DEVICE_NOT_FOUND;
 610        }
 611
 612        if (ppc_md.pci_exclude_device) {
 613                if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
 614                        return PCIBIOS_DEVICE_NOT_FOUND;
 615        }
 616
 617        return PCIBIOS_SUCCESSFUL;
 618}
 619
 620static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
 621                                            unsigned int devfn, int offset)
 622{
 623        struct pci_controller *hose = pci_bus_to_host(bus);
 624        struct mpc83xx_pcie_priv *pcie = hose->dn->data;
 625        u32 dev_base = bus->number << 24 | devfn << 16;
 626        int ret;
 627
 628        ret = mpc83xx_pcie_exclude_device(bus, devfn);
 629        if (ret)
 630                return NULL;
 631
 632        offset &= 0xfff;
 633
 634        /* Type 0 */
 635        if (bus->number == hose->first_busno)
 636                return pcie->cfg_type0 + offset;
 637
 638        if (pcie->dev_base == dev_base)
 639                goto mapped;
 640
 641        out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
 642
 643        pcie->dev_base = dev_base;
 644mapped:
 645        return pcie->cfg_type1 + offset;
 646}
 647
 648static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
 649                                    int offset, int len, u32 *val)
 650{
 651        void __iomem *cfg_addr;
 652
 653        cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
 654        if (!cfg_addr)
 655                return PCIBIOS_DEVICE_NOT_FOUND;
 656
 657        switch (len) {
 658        case 1:
 659                *val = in_8(cfg_addr);
 660                break;
 661        case 2:
 662                *val = in_le16(cfg_addr);
 663                break;
 664        default:
 665                *val = in_le32(cfg_addr);
 666                break;
 667        }
 668
 669        return PCIBIOS_SUCCESSFUL;
 670}
 671
 672static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
 673                                     int offset, int len, u32 val)
 674{
 675        struct pci_controller *hose = pci_bus_to_host(bus);
 676        void __iomem *cfg_addr;
 677
 678        cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
 679        if (!cfg_addr)
 680                return PCIBIOS_DEVICE_NOT_FOUND;
 681
 682        /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
 683        if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
 684                val &= 0xffffff00;
 685
 686        switch (len) {
 687        case 1:
 688                out_8(cfg_addr, val);
 689                break;
 690        case 2:
 691                out_le16(cfg_addr, val);
 692                break;
 693        default:
 694                out_le32(cfg_addr, val);
 695                break;
 696        }
 697
 698        return PCIBIOS_SUCCESSFUL;
 699}
 700
 701static struct pci_ops mpc83xx_pcie_ops = {
 702        .read = mpc83xx_pcie_read_config,
 703        .write = mpc83xx_pcie_write_config,
 704};
 705
 706static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
 707                                     struct resource *reg)
 708{
 709        struct mpc83xx_pcie_priv *pcie;
 710        u32 cfg_bar;
 711        int ret = -ENOMEM;
 712
 713        pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
 714        if (!pcie)
 715                return ret;
 716
 717        pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
 718        if (!pcie->cfg_type0)
 719                goto err0;
 720
 721        cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
 722        if (!cfg_bar) {
 723                /* PCI-E isn't configured. */
 724                ret = -ENODEV;
 725                goto err1;
 726        }
 727
 728        pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
 729        if (!pcie->cfg_type1)
 730                goto err1;
 731
 732        WARN_ON(hose->dn->data);
 733        hose->dn->data = pcie;
 734        hose->ops = &mpc83xx_pcie_ops;
 735        hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
 736
 737        out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
 738        out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
 739
 740        if (fsl_pcie_check_link(hose))
 741                hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
 742
 743        return 0;
 744err1:
 745        iounmap(pcie->cfg_type0);
 746err0:
 747        kfree(pcie);
 748        return ret;
 749
 750}
 751
 752int __init mpc83xx_add_bridge(struct device_node *dev)
 753{
 754        int ret;
 755        int len;
 756        struct pci_controller *hose;
 757        struct resource rsrc_reg;
 758        struct resource rsrc_cfg;
 759        const int *bus_range;
 760        int primary;
 761
 762        is_mpc83xx_pci = 1;
 763
 764        if (!of_device_is_available(dev)) {
 765                pr_warning("%s: disabled by the firmware.\n",
 766                           dev->full_name);
 767                return -ENODEV;
 768        }
 769        pr_debug("Adding PCI host bridge %s\n", dev->full_name);
 770
 771        /* Fetch host bridge registers address */
 772        if (of_address_to_resource(dev, 0, &rsrc_reg)) {
 773                printk(KERN_WARNING "Can't get pci register base!\n");
 774                return -ENOMEM;
 775        }
 776
 777        memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
 778
 779        if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
 780                printk(KERN_WARNING
 781                        "No pci config register base in dev tree, "
 782                        "using default\n");
 783                /*
 784                 * MPC83xx supports up to two host controllers
 785                 *      one at 0x8500 has config space registers at 0x8300
 786                 *      one at 0x8600 has config space registers at 0x8380
 787                 */
 788                if ((rsrc_reg.start & 0xfffff) == 0x8500)
 789                        rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
 790                else if ((rsrc_reg.start & 0xfffff) == 0x8600)
 791                        rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
 792        }
 793        /*
 794         * Controller at offset 0x8500 is primary
 795         */
 796        if ((rsrc_reg.start & 0xfffff) == 0x8500)
 797                primary = 1;
 798        else
 799                primary = 0;
 800
 801        /* Get bus range if any */
 802        bus_range = of_get_property(dev, "bus-range", &len);
 803        if (bus_range == NULL || len < 2 * sizeof(int)) {
 804                printk(KERN_WARNING "Can't get bus-range for %s, assume"
 805                       " bus 0\n", dev->full_name);
 806        }
 807
 808        pci_add_flags(PCI_REASSIGN_ALL_BUS);
 809        hose = pcibios_alloc_controller(dev);
 810        if (!hose)
 811                return -ENOMEM;
 812
 813        hose->first_busno = bus_range ? bus_range[0] : 0;
 814        hose->last_busno = bus_range ? bus_range[1] : 0xff;
 815
 816        if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
 817                ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
 818                if (ret)
 819                        goto err0;
 820        } else {
 821                setup_indirect_pci(hose, rsrc_cfg.start,
 822                                   rsrc_cfg.start + 4, 0);
 823        }
 824
 825        printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
 826               "Firmware bus number: %d->%d\n",
 827               (unsigned long long)rsrc_reg.start, hose->first_busno,
 828               hose->last_busno);
 829
 830        pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
 831            hose, hose->cfg_addr, hose->cfg_data);
 832
 833        /* Interpret the "ranges" property */
 834        /* This also maps the I/O region and sets isa_io/mem_base */
 835        pci_process_bridge_OF_ranges(hose, dev, primary);
 836
 837        return 0;
 838err0:
 839        pcibios_free_controller(hose);
 840        return ret;
 841}
 842#endif /* CONFIG_PPC_83xx */
 843
 844u64 fsl_pci_immrbar_base(struct pci_controller *hose)
 845{
 846#ifdef CONFIG_PPC_83xx
 847        if (is_mpc83xx_pci) {
 848                struct mpc83xx_pcie_priv *pcie = hose->dn->data;
 849                struct pex_inbound_window *in;
 850                int i;
 851
 852                /* Walk the Root Complex Inbound windows to match IMMR base */
 853                in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
 854                for (i = 0; i < 4; i++) {
 855                        /* not enabled, skip */
 856                        if (!(in_le32(&in[i].ar) & PEX_RCIWARn_EN))
 857                                continue;
 858
 859                        if (get_immrbase() == in_le32(&in[i].tar))
 860                                return (u64)in_le32(&in[i].barh) << 32 |
 861                                            in_le32(&in[i].barl);
 862                }
 863
 864                printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
 865        }
 866#endif
 867
 868#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
 869        if (!is_mpc83xx_pci) {
 870                u32 base;
 871
 872                pci_bus_read_config_dword(hose->bus,
 873                        PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
 874
 875                /*
 876                 * For PEXCSRBAR, bit 3-0 indicate prefetchable and
 877                 * address type. So when getting base address, these
 878                 * bits should be masked
 879                 */
 880                base &= PCI_BASE_ADDRESS_MEM_MASK;
 881
 882                return base;
 883        }
 884#endif
 885
 886        return 0;
 887}
 888
 889#ifdef CONFIG_E500
 890static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
 891{
 892        unsigned int rd, ra, rb, d;
 893
 894        rd = get_rt(inst);
 895        ra = get_ra(inst);
 896        rb = get_rb(inst);
 897        d = get_d(inst);
 898
 899        switch (get_op(inst)) {
 900        case 31:
 901                switch (get_xop(inst)) {
 902                case OP_31_XOP_LWZX:
 903                case OP_31_XOP_LWBRX:
 904                        regs->gpr[rd] = 0xffffffff;
 905                        break;
 906
 907                case OP_31_XOP_LWZUX:
 908                        regs->gpr[rd] = 0xffffffff;
 909                        regs->gpr[ra] += regs->gpr[rb];
 910                        break;
 911
 912                case OP_31_XOP_LBZX:
 913                        regs->gpr[rd] = 0xff;
 914                        break;
 915
 916                case OP_31_XOP_LBZUX:
 917                        regs->gpr[rd] = 0xff;
 918                        regs->gpr[ra] += regs->gpr[rb];
 919                        break;
 920
 921                case OP_31_XOP_LHZX:
 922                case OP_31_XOP_LHBRX:
 923                        regs->gpr[rd] = 0xffff;
 924                        break;
 925
 926                case OP_31_XOP_LHZUX:
 927                        regs->gpr[rd] = 0xffff;
 928                        regs->gpr[ra] += regs->gpr[rb];
 929                        break;
 930
 931                case OP_31_XOP_LHAX:
 932                        regs->gpr[rd] = ~0UL;
 933                        break;
 934
 935                case OP_31_XOP_LHAUX:
 936                        regs->gpr[rd] = ~0UL;
 937                        regs->gpr[ra] += regs->gpr[rb];
 938                        break;
 939
 940                default:
 941                        return 0;
 942                }
 943                break;
 944
 945        case OP_LWZ:
 946                regs->gpr[rd] = 0xffffffff;
 947                break;
 948
 949        case OP_LWZU:
 950                regs->gpr[rd] = 0xffffffff;
 951                regs->gpr[ra] += (s16)d;
 952                break;
 953
 954        case OP_LBZ:
 955                regs->gpr[rd] = 0xff;
 956                break;
 957
 958        case OP_LBZU:
 959                regs->gpr[rd] = 0xff;
 960                regs->gpr[ra] += (s16)d;
 961                break;
 962
 963        case OP_LHZ:
 964                regs->gpr[rd] = 0xffff;
 965                break;
 966
 967        case OP_LHZU:
 968                regs->gpr[rd] = 0xffff;
 969                regs->gpr[ra] += (s16)d;
 970                break;
 971
 972        case OP_LHA:
 973                regs->gpr[rd] = ~0UL;
 974                break;
 975
 976        case OP_LHAU:
 977                regs->gpr[rd] = ~0UL;
 978                regs->gpr[ra] += (s16)d;
 979                break;
 980
 981        default:
 982                return 0;
 983        }
 984
 985        return 1;
 986}
 987
 988static int is_in_pci_mem_space(phys_addr_t addr)
 989{
 990        struct pci_controller *hose;
 991        struct resource *res;
 992        int i;
 993
 994        list_for_each_entry(hose, &hose_list, list_node) {
 995                if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG))
 996                        continue;
 997
 998                for (i = 0; i < 3; i++) {
 999                        res = &hose->mem_resources[i];
1000                        if ((res->flags & IORESOURCE_MEM) &&
1001                                addr >= res->start && addr <= res->end)
1002                                return 1;
1003                }
1004        }
1005        return 0;
1006}
1007
1008int fsl_pci_mcheck_exception(struct pt_regs *regs)
1009{
1010        u32 inst;
1011        int ret;
1012        phys_addr_t addr = 0;
1013
1014        /* Let KVM/QEMU deal with the exception */
1015        if (regs->msr & MSR_GS)
1016                return 0;
1017
1018#ifdef CONFIG_PHYS_64BIT
1019        addr = mfspr(SPRN_MCARU);
1020        addr <<= 32;
1021#endif
1022        addr += mfspr(SPRN_MCAR);
1023
1024        if (is_in_pci_mem_space(addr)) {
1025                if (user_mode(regs)) {
1026                        pagefault_disable();
1027                        ret = get_user(regs->nip, &inst);
1028                        pagefault_enable();
1029                } else {
1030                        ret = probe_kernel_address(regs->nip, inst);
1031                }
1032
1033                if (mcheck_handle_load(regs, inst)) {
1034                        regs->nip += 4;
1035                        return 1;
1036                }
1037        }
1038
1039        return 0;
1040}
1041#endif
1042
1043#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
1044static const struct of_device_id pci_ids[] = {
1045        { .compatible = "fsl,mpc8540-pci", },
1046        { .compatible = "fsl,mpc8548-pcie", },
1047        { .compatible = "fsl,mpc8610-pci", },
1048        { .compatible = "fsl,mpc8641-pcie", },
1049        { .compatible = "fsl,qoriq-pcie", },
1050        { .compatible = "fsl,qoriq-pcie-v2.1", },
1051        { .compatible = "fsl,qoriq-pcie-v2.2", },
1052        { .compatible = "fsl,qoriq-pcie-v2.3", },
1053        { .compatible = "fsl,qoriq-pcie-v2.4", },
1054        { .compatible = "fsl,qoriq-pcie-v3.0", },
1055
1056        /*
1057         * The following entries are for compatibility with older device
1058         * trees.
1059         */
1060        { .compatible = "fsl,p1022-pcie", },
1061        { .compatible = "fsl,p4080-pcie", },
1062
1063        {},
1064};
1065
1066struct device_node *fsl_pci_primary;
1067
1068void fsl_pci_assign_primary(void)
1069{
1070        struct device_node *np;
1071
1072        /* Callers can specify the primary bus using other means. */
1073        if (fsl_pci_primary)
1074                return;
1075
1076        /* If a PCI host bridge contains an ISA node, it's primary. */
1077        np = of_find_node_by_type(NULL, "isa");
1078        while ((fsl_pci_primary = of_get_parent(np))) {
1079                of_node_put(np);
1080                np = fsl_pci_primary;
1081
1082                if (of_match_node(pci_ids, np) && of_device_is_available(np))
1083                        return;
1084        }
1085
1086        /*
1087         * If there's no PCI host bridge with ISA, arbitrarily
1088         * designate one as primary.  This can go away once
1089         * various bugs with primary-less systems are fixed.
1090         */
1091        for_each_matching_node(np, pci_ids) {
1092                if (of_device_is_available(np)) {
1093                        fsl_pci_primary = np;
1094                        of_node_put(np);
1095                        return;
1096                }
1097        }
1098}
1099
1100#ifdef CONFIG_PM_SLEEP
1101static irqreturn_t fsl_pci_pme_handle(int irq, void *dev_id)
1102{
1103        struct pci_controller *hose = dev_id;
1104        struct ccsr_pci __iomem *pci = hose->private_data;
1105        u32 dr;
1106
1107        dr = in_be32(&pci->pex_pme_mes_dr);
1108        if (!dr)
1109                return IRQ_NONE;
1110
1111        out_be32(&pci->pex_pme_mes_dr, dr);
1112
1113        return IRQ_HANDLED;
1114}
1115
1116static int fsl_pci_pme_probe(struct pci_controller *hose)
1117{
1118        struct ccsr_pci __iomem *pci;
1119        struct pci_dev *dev;
1120        int pme_irq;
1121        int res;
1122        u16 pms;
1123
1124        /* Get hose's pci_dev */
1125        dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list);
1126
1127        /* PME Disable */
1128        pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
1129        pms &= ~PCI_PM_CTRL_PME_ENABLE;
1130        pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms);
1131
1132        pme_irq = irq_of_parse_and_map(hose->dn, 0);
1133        if (!pme_irq) {
1134                dev_err(&dev->dev, "Failed to map PME interrupt.\n");
1135
1136                return -ENXIO;
1137        }
1138
1139        res = devm_request_irq(hose->parent, pme_irq,
1140                        fsl_pci_pme_handle,
1141                        IRQF_SHARED,
1142                        "[PCI] PME", hose);
1143        if (res < 0) {
1144                dev_err(&dev->dev, "Unable to requiest irq %d for PME\n", pme_irq);
1145                irq_dispose_mapping(pme_irq);
1146
1147                return -ENODEV;
1148        }
1149
1150        pci = hose->private_data;
1151
1152        /* Enable PTOD, ENL23D & EXL23D */
1153        clrbits32(&pci->pex_pme_mes_disr,
1154                  PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
1155
1156        out_be32(&pci->pex_pme_mes_ier, 0);
1157        setbits32(&pci->pex_pme_mes_ier,
1158                  PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
1159
1160        /* PME Enable */
1161        pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
1162        pms |= PCI_PM_CTRL_PME_ENABLE;
1163        pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms);
1164
1165        return 0;
1166}
1167
1168static void send_pme_turnoff_message(struct pci_controller *hose)
1169{
1170        struct ccsr_pci __iomem *pci = hose->private_data;
1171        u32 dr;
1172        int i;
1173
1174        /* Send PME_Turn_Off Message Request */
1175        setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR);
1176
1177        /* Wait trun off done */
1178        for (i = 0; i < 150; i++) {
1179                dr = in_be32(&pci->pex_pme_mes_dr);
1180                if (dr) {
1181                        out_be32(&pci->pex_pme_mes_dr, dr);
1182                        break;
1183                }
1184
1185                udelay(1000);
1186        }
1187}
1188
1189static void fsl_pci_syscore_do_suspend(struct pci_controller *hose)
1190{
1191        send_pme_turnoff_message(hose);
1192}
1193
1194static int fsl_pci_syscore_suspend(void)
1195{
1196        struct pci_controller *hose, *tmp;
1197
1198        list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1199                fsl_pci_syscore_do_suspend(hose);
1200
1201        return 0;
1202}
1203
1204static void fsl_pci_syscore_do_resume(struct pci_controller *hose)
1205{
1206        struct ccsr_pci __iomem *pci = hose->private_data;
1207        u32 dr;
1208        int i;
1209
1210        /* Send Exit L2 State Message */
1211        setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S);
1212
1213        /* Wait exit done */
1214        for (i = 0; i < 150; i++) {
1215                dr = in_be32(&pci->pex_pme_mes_dr);
1216                if (dr) {
1217                        out_be32(&pci->pex_pme_mes_dr, dr);
1218                        break;
1219                }
1220
1221                udelay(1000);
1222        }
1223
1224        setup_pci_atmu(hose);
1225}
1226
1227static void fsl_pci_syscore_resume(void)
1228{
1229        struct pci_controller *hose, *tmp;
1230
1231        list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1232                fsl_pci_syscore_do_resume(hose);
1233}
1234
1235static struct syscore_ops pci_syscore_pm_ops = {
1236        .suspend = fsl_pci_syscore_suspend,
1237        .resume = fsl_pci_syscore_resume,
1238};
1239#endif
1240
1241void fsl_pcibios_fixup_phb(struct pci_controller *phb)
1242{
1243#ifdef CONFIG_PM_SLEEP
1244        fsl_pci_pme_probe(phb);
1245#endif
1246}
1247
1248static int fsl_pci_probe(struct platform_device *pdev)
1249{
1250        struct device_node *node;
1251        int ret;
1252
1253        node = pdev->dev.of_node;
1254        ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
1255
1256        mpc85xx_pci_err_probe(pdev);
1257
1258        return 0;
1259}
1260
1261static struct platform_driver fsl_pci_driver = {
1262        .driver = {
1263                .name = "fsl-pci",
1264                .of_match_table = pci_ids,
1265        },
1266        .probe = fsl_pci_probe,
1267};
1268
1269static int __init fsl_pci_init(void)
1270{
1271#ifdef CONFIG_PM_SLEEP
1272        register_syscore_ops(&pci_syscore_pm_ops);
1273#endif
1274        return platform_driver_register(&fsl_pci_driver);
1275}
1276arch_initcall(fsl_pci_init);
1277#endif
1278
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