LXR linux/arch/powerpc/platforms/cell/Kconfig

   1config PPC_CELL
   2        bool
   3        default n
   4
   5config PPC_CELL_COMMON
   6        bool
   7        select PPC_CELL
   8        select PPC_DCR_MMIO
   9        select PPC_INDIRECT_PIO
  10        select PPC_INDIRECT_MMIO
  11        select PPC_NATIVE
  12        select PPC_RTAS
  13        select IRQ_EDGE_EOI_HANDLER
  14
  15config PPC_CELL_NATIVE
  16        bool
  17        select PPC_CELL_COMMON
  18        select MPIC
  19        select PPC_IO_WORKAROUNDS
  20        select IBM_EMAC_EMAC4
  21        select IBM_EMAC_RGMII
  22        select IBM_EMAC_ZMII #test only
  23        select IBM_EMAC_TAH  #test only
  24        default n
  25
  26config PPC_IBM_CELL_BLADE
  27        bool "IBM Cell Blade"
  28        depends on PPC64 && PPC_BOOK3S
  29        select PPC_CELL_NATIVE
  30        select PPC_OF_PLATFORM_PCI
  31        select PCI
  32        select MMIO_NVRAM
  33        select PPC_UDBG_16550
  34        select UDBG_RTAS_CONSOLE
  35
  36config PPC_CELLEB
  37        bool "Toshiba's Cell Reference Set 'Celleb' Architecture"
  38        depends on PPC64 && PPC_BOOK3S
  39        select PPC_CELL_NATIVE
  40        select PPC_OF_PLATFORM_PCI
  41        select PCI
  42        select HAS_TXX9_SERIAL
  43        select PPC_UDBG_BEAT
  44        select USB_OHCI_BIG_ENDIAN_MMIO
  45        select USB_EHCI_BIG_ENDIAN_MMIO
  46
  47config PPC_CELL_QPACE
  48        bool "IBM Cell - QPACE"
  49        depends on PPC64 && PPC_BOOK3S
  50        select PPC_CELL_COMMON
  51
  52config AXON_MSI
  53        bool
  54        depends on PPC_IBM_CELL_BLADE && PCI_MSI
  55        default y
  56
  57menu "Cell Broadband Engine options"
  58        depends on PPC_CELL
  59
  60config SPU_FS
  61        tristate "SPU file system"
  62        default m
  63        depends on PPC_CELL
  64        select SPU_BASE
  65        select MEMORY_HOTPLUG
  66        help
  67          The SPU file system is used to access Synergistic Processing
  68          Units on machines implementing the Broadband Processor
  69          Architecture.
  70
  71config SPU_FS_64K_LS
  72        bool "Use 64K pages to map SPE local  store"
  73        # we depend on PPC_MM_SLICES for now rather than selecting
  74        # it because we depend on hugetlbfs hooks being present. We
  75        # will fix that when the generic code has been improved to
  76        # not require hijacking hugetlbfs hooks.
  77        depends on SPU_FS && PPC_MM_SLICES && !PPC_64K_PAGES
  78        default y
  79        select PPC_HAS_HASH_64K
  80        help
  81          This option causes SPE local stores to be mapped in process
  82          address spaces using 64K pages while the rest of the kernel
  83          uses 4K pages. This can improve performances of applications
  84          using multiple SPEs by lowering the TLB pressure on them.
  85
  86config SPU_BASE
  87        bool
  88        default n
  89
  90config CBE_RAS
  91        bool "RAS features for bare metal Cell BE"
  92        depends on PPC_CELL_NATIVE
  93        default y
  94
  95config PPC_IBM_CELL_RESETBUTTON
  96        bool "IBM Cell Blade Pinhole reset button"
  97        depends on CBE_RAS && PPC_IBM_CELL_BLADE
  98        default y
  99        help
 100          Support Pinhole Resetbutton on IBM Cell blades.
 101          This adds a method to trigger system reset via front panel pinhole button.
 102
 103config PPC_IBM_CELL_POWERBUTTON
 104        tristate "IBM Cell Blade power button"
 105        depends on PPC_IBM_CELL_BLADE && INPUT_EVDEV
 106        default y
 107        help
 108          Support Powerbutton on IBM Cell blades.
 109          This will enable the powerbutton as an input device.
 110
 111config CBE_THERM
 112        tristate "CBE thermal support"
 113        default m
 114        depends on CBE_RAS && SPU_BASE
 115
 116config CBE_CPUFREQ
 117        tristate "CBE frequency scaling"
 118        depends on CBE_RAS && CPU_FREQ
 119        default m
 120        help
 121          This adds the cpufreq driver for Cell BE processors.
 122          For details, take a look at <file:Documentation/cpu-freq/>.
 123          If you don't have such processor, say N
 124
 125config CBE_CPUFREQ_PMI_ENABLE
 126        bool "CBE frequency scaling using PMI interface"
 127        depends on CBE_CPUFREQ
 128        default n
 129        help
 130          Select this, if you want to use the PMI interface
 131          to switch frequencies. Using PMI, the
 132          processor will not only be able to run at lower speed,
 133          but also at lower core voltage.
 134
 135config CBE_CPUFREQ_PMI
 136        tristate
 137        depends on CBE_CPUFREQ_PMI_ENABLE
 138        default CBE_CPUFREQ
 139
 140config PPC_PMI
 141        tristate
 142        default y
 143        depends on CBE_CPUFREQ_PMI || PPC_IBM_CELL_POWERBUTTON
 144        help
 145          PMI (Platform Management Interrupt) is a way to
 146          communicate with the BMC (Baseboard Management Controller).
 147          It is used in some IBM Cell blades.
 148
 149config CBE_CPUFREQ_SPU_GOVERNOR
 150        tristate "CBE frequency scaling based on SPU usage"
 151        depends on SPU_FS && CPU_FREQ
 152        default m
 153        help
 154          This governor checks for spu usage to adjust the cpu frequency.
 155          If no spu is running on a given cpu, that cpu will be throttled to
 156          the minimal possible frequency.
 157
 158endmenu
 159
 160config OPROFILE_CELL
 161        def_bool y
 162        depends on PPC_CELL_NATIVE && (OPROFILE = m || OPROFILE = y) && SPU_BASE
 163
 164