LXR linux/arch/mips/cavium-octeon/Kconfig

   1config CAVIUM_OCTEON_SPECIFIC_OPTIONS
   2        bool "Enable Octeon specific options"
   3        depends on CPU_CAVIUM_OCTEON
   4        default "y"
   5
   6config CAVIUM_OCTEON_2ND_KERNEL
   7        bool "Build the kernel to be used as a 2nd kernel on the same chip"
   8        depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
   9        default "n"
  10        help
  11          This option configures this kernel to be linked at a different
  12          address and use the 2nd uart for output. This allows a kernel built
  13          with this option to be run at the same time as one built without this
  14          option.
  15
  16config CAVIUM_OCTEON_HW_FIX_UNALIGNED
  17        bool "Enable hardware fixups of unaligned loads and stores"
  18        depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
  19        default "y"
  20        help
  21          Configure the Octeon hardware to automatically fix unaligned loads
  22          and stores. Normally unaligned accesses are fixed using a kernel
  23          exception handler. This option enables the hardware automatic fixups,
  24          which requires only an extra 3 cycles. Disable this option if you
  25          are running code that relies on address exceptions on unaligned
  26          accesses.
  27
  28config CAVIUM_OCTEON_CVMSEG_SIZE
  29        int "Number of L1 cache lines reserved for CVMSEG memory"
  30        depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
  31        range 0 54
  32        default 1
  33        help
  34          CVMSEG LM is a segment that accesses portions of the dcache as a
  35          local memory; the larger CVMSEG is, the smaller the cache is.
  36          This selects the size of CVMSEG LM, which is in cache blocks. The
  37          legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
  38          between zero and 6192 bytes).
  39
  40config CAVIUM_OCTEON_LOCK_L2
  41        bool "Lock often used kernel code in the L2"
  42        depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
  43        default "y"
  44        help
  45          Enable locking parts of the kernel into the L2 cache.
  46
  47config CAVIUM_OCTEON_LOCK_L2_TLB
  48        bool "Lock the TLB handler in L2"
  49        depends on CAVIUM_OCTEON_LOCK_L2
  50        default "y"
  51        help
  52          Lock the low level TLB fast path into L2.
  53
  54config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
  55        bool "Lock the exception handler in L2"
  56        depends on CAVIUM_OCTEON_LOCK_L2
  57        default "y"
  58        help
  59          Lock the low level exception handler into L2.
  60
  61config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
  62        bool "Lock the interrupt handler in L2"
  63        depends on CAVIUM_OCTEON_LOCK_L2
  64        default "y"
  65        help
  66          Lock the low level interrupt handler into L2.
  67
  68config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
  69        bool "Lock the 2nd level interrupt handler in L2"
  70        depends on CAVIUM_OCTEON_LOCK_L2
  71        default "y"
  72        help
  73          Lock the 2nd level interrupt handler in L2.
  74
  75config CAVIUM_OCTEON_LOCK_L2_MEMCPY
  76        bool "Lock memcpy() in L2"
  77        depends on CAVIUM_OCTEON_LOCK_L2
  78        default "y"
  79        help
  80          Lock the kernel's implementation of memcpy() into L2.
  81
  82config ARCH_SPARSEMEM_ENABLE
  83        def_bool y
  84        select SPARSEMEM_STATIC
  85        depends on CPU_CAVIUM_OCTEON
  86