1comment "Processor Type" 2 3# Select CPU types depending on the architecture selected. This selects 4# which CPUs we support in the kernel image, and the compiler instruction 5# optimiser behaviour. 6 7# ARM7TDMI 8config CPU_ARM7TDMI 9 bool "Support ARM7TDMI processor" 10 depends on !MMU 11 select CPU_32v4T 12 select CPU_ABRT_LV4T 13 select CPU_CACHE_V4 14 select CPU_PABRT_LEGACY 15 help 16 A 32-bit RISC microprocessor based on the ARM7 processor core 17 which has no memory control unit and cache. 18 19 Say Y if you want support for the ARM7TDMI processor. 20 Otherwise, say N. 21 22# ARM720T 23config CPU_ARM720T 24 bool "Support ARM720T processor" if ARCH_INTEGRATOR 25 select CPU_32v4T 26 select CPU_ABRT_LV4T 27 select CPU_CACHE_V4 28 select CPU_CACHE_VIVT 29 select CPU_COPY_V4WT if MMU 30 select CPU_CP15_MMU 31 select CPU_PABRT_LEGACY 32 select CPU_TLB_V4WT if MMU 33 help 34 A 32-bit RISC processor with 8kByte Cache, Write Buffer and 35 MMU built around an ARM7TDMI core. 36 37 Say Y if you want support for the ARM720T processor. 38 Otherwise, say N. 39 40# ARM740T 41config CPU_ARM740T 42 bool "Support ARM740T processor" if ARCH_INTEGRATOR 43 depends on !MMU 44 select CPU_32v4T 45 select CPU_ABRT_LV4T 46 select CPU_CACHE_V4 47 select CPU_CP15_MPU 48 select CPU_PABRT_LEGACY 49 help 50 A 32-bit RISC processor with 8KB cache or 4KB variants, 51 write buffer and MPU(Protection Unit) built around 52 an ARM7TDMI core. 53 54 Say Y if you want support for the ARM740T processor. 55 Otherwise, say N. 56 57# ARM9TDMI 58config CPU_ARM9TDMI 59 bool "Support ARM9TDMI processor" 60 depends on !MMU 61 select CPU_32v4T 62 select CPU_ABRT_NOMMU 63 select CPU_CACHE_V4 64 select CPU_PABRT_LEGACY 65 help 66 A 32-bit RISC microprocessor based on the ARM9 processor core 67 which has no memory control unit and cache. 68 69 Say Y if you want support for the ARM9TDMI processor. 70 Otherwise, say N. 71 72# ARM920T 73config CPU_ARM920T 74 bool "Support ARM920T processor" if ARCH_INTEGRATOR 75 select CPU_32v4T 76 select CPU_ABRT_EV4T 77 select CPU_CACHE_V4WT 78 select CPU_CACHE_VIVT 79 select CPU_COPY_V4WB if MMU 80 select CPU_CP15_MMU 81 select CPU_PABRT_LEGACY 82 select CPU_TLB_V4WBI if MMU 83 help 84 The ARM920T is licensed to be produced by numerous vendors, 85 and is used in the Cirrus EP93xx and the Samsung S3C2410. 86 87 Say Y if you want support for the ARM920T processor. 88 Otherwise, say N. 89 90# ARM922T 91config CPU_ARM922T 92 bool "Support ARM922T processor" if ARCH_INTEGRATOR 93 select CPU_32v4T 94 select CPU_ABRT_EV4T 95 select CPU_CACHE_V4WT 96 select CPU_CACHE_VIVT 97 select CPU_COPY_V4WB if MMU 98 select CPU_CP15_MMU 99 select CPU_PABRT_LEGACY 100 select CPU_TLB_V4WBI if MMU 101 help 102 The ARM922T is a version of the ARM920T, but with smaller 103 instruction and data caches. It is used in Altera's 104 Excalibur XA device family and Micrel's KS8695 Centaur. 105 106 Say Y if you want support for the ARM922T processor. 107 Otherwise, say N. 108 109# ARM925T 110config CPU_ARM925T 111 bool "Support ARM925T processor" if ARCH_OMAP1 112 select CPU_32v4T 113 select CPU_ABRT_EV4T 114 select CPU_CACHE_V4WT 115 select CPU_CACHE_VIVT 116 select CPU_COPY_V4WB if MMU 117 select CPU_CP15_MMU 118 select CPU_PABRT_LEGACY 119 select CPU_TLB_V4WBI if MMU 120 help 121 The ARM925T is a mix between the ARM920T and ARM926T, but with 122 different instruction and data caches. It is used in TI's OMAP 123 device family. 124 125 Say Y if you want support for the ARM925T processor. 126 Otherwise, say N. 127 128# ARM926T 129config CPU_ARM926T 130 bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB 131 select CPU_32v5 132 select CPU_ABRT_EV5TJ 133 select CPU_CACHE_VIVT 134 select CPU_COPY_V4WB if MMU 135 select CPU_CP15_MMU 136 select CPU_PABRT_LEGACY 137 select CPU_TLB_V4WBI if MMU 138 help 139 This is a variant of the ARM920. It has slightly different 140 instruction sequences for cache and TLB operations. Curiously, 141 there is no documentation on it at the ARM corporate website. 142 143 Say Y if you want support for the ARM926T processor. 144 Otherwise, say N. 145 146# FA526 147config CPU_FA526 148 bool 149 select CPU_32v4 150 select CPU_ABRT_EV4 151 select CPU_CACHE_FA 152 select CPU_CACHE_VIVT 153 select CPU_COPY_FA if MMU 154 select CPU_CP15_MMU 155 select CPU_PABRT_LEGACY 156 select CPU_TLB_FA if MMU 157 help 158 The FA526 is a version of the ARMv4 compatible processor with 159 Branch Target Buffer, Unified TLB and cache line size 16. 160 161 Say Y if you want support for the FA526 processor. 162 Otherwise, say N. 163 164# ARM940T 165config CPU_ARM940T 166 bool "Support ARM940T processor" if ARCH_INTEGRATOR 167 depends on !MMU 168 select CPU_32v4T 169 select CPU_ABRT_NOMMU 170 select CPU_CACHE_VIVT 171 select CPU_CP15_MPU 172 select CPU_PABRT_LEGACY 173 help 174 ARM940T is a member of the ARM9TDMI family of general- 175 purpose microprocessors with MPU and separate 4KB 176 instruction and 4KB data cases, each with a 4-word line 177 length. 178 179 Say Y if you want support for the ARM940T processor. 180 Otherwise, say N. 181 182# ARM946E-S 183config CPU_ARM946E 184 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR 185 depends on !MMU 186 select CPU_32v5 187 select CPU_ABRT_NOMMU 188 select CPU_CACHE_VIVT 189 select CPU_CP15_MPU 190 select CPU_PABRT_LEGACY 191 help 192 ARM946E-S is a member of the ARM9E-S family of high- 193 performance, 32-bit system-on-chip processor solutions. 194 The TCM and ARMv5TE 32-bit instruction set is supported. 195 196 Say Y if you want support for the ARM946E-S processor. 197 Otherwise, say N. 198 199# ARM1020 - needs validating 200config CPU_ARM1020 201 bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR 202 select CPU_32v5 203 select CPU_ABRT_EV4T 204 select CPU_CACHE_V4WT 205 select CPU_CACHE_VIVT 206 select CPU_COPY_V4WB if MMU 207 select CPU_CP15_MMU 208 select CPU_PABRT_LEGACY 209 select CPU_TLB_V4WBI if MMU 210 help 211 The ARM1020 is the 32K cached version of the ARM10 processor, 212 with an addition of a floating-point unit. 213 214 Say Y if you want support for the ARM1020 processor. 215 Otherwise, say N. 216 217# ARM1020E - needs validating 218config CPU_ARM1020E 219 bool "Support ARM1020E processor" if ARCH_INTEGRATOR 220 depends on n 221 select CPU_32v5 222 select CPU_ABRT_EV4T 223 select CPU_CACHE_V4WT 224 select CPU_CACHE_VIVT 225 select CPU_COPY_V4WB if MMU 226 select CPU_CP15_MMU 227 select CPU_PABRT_LEGACY 228 select CPU_TLB_V4WBI if MMU 229 230# ARM1022E 231config CPU_ARM1022 232 bool "Support ARM1022E processor" if ARCH_INTEGRATOR 233 select CPU_32v5 234 select CPU_ABRT_EV4T 235 select CPU_CACHE_VIVT 236 select CPU_COPY_V4WB if MMU # can probably do better 237 select CPU_CP15_MMU 238 select CPU_PABRT_LEGACY 239 select CPU_TLB_V4WBI if MMU 240 help 241 The ARM1022E is an implementation of the ARMv5TE architecture 242 based upon the ARM10 integer core with a 16KiB L1 Harvard cache, 243 embedded trace macrocell, and a floating-point unit. 244 245 Say Y if you want support for the ARM1022E processor. 246 Otherwise, say N. 247 248# ARM1026EJ-S 249config CPU_ARM1026 250 bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR 251 select CPU_32v5 252 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 253 select CPU_CACHE_VIVT 254 select CPU_COPY_V4WB if MMU # can probably do better 255 select CPU_CP15_MMU 256 select CPU_PABRT_LEGACY 257 select CPU_TLB_V4WBI if MMU 258 help 259 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture 260 based upon the ARM10 integer core. 261 262 Say Y if you want support for the ARM1026EJ-S processor. 263 Otherwise, say N. 264 265# SA110 266config CPU_SA110 267 bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC 268 select CPU_32v3 if ARCH_RPC 269 select CPU_32v4 if !ARCH_RPC 270 select CPU_ABRT_EV4 271 select CPU_CACHE_V4WB 272 select CPU_CACHE_VIVT 273 select CPU_COPY_V4WB if MMU 274 select CPU_CP15_MMU 275 select CPU_PABRT_LEGACY 276 select CPU_TLB_V4WB if MMU 277 help 278 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and 279 is available at five speeds ranging from 100 MHz to 233 MHz. 280 More information is available at 281 <http://developer.intel.com/design/strong/sa110.htm>. 282 283 Say Y if you want support for the SA-110 processor. 284 Otherwise, say N. 285 286# SA1100 287config CPU_SA1100 288 bool 289 select CPU_32v4 290 select CPU_ABRT_EV4 291 select CPU_CACHE_V4WB 292 select CPU_CACHE_VIVT 293 select CPU_CP15_MMU 294 select CPU_PABRT_LEGACY 295 select CPU_TLB_V4WB if MMU 296 297# XScale 298config CPU_XSCALE 299 bool 300 select CPU_32v5 301 select CPU_ABRT_EV5T 302 select CPU_CACHE_VIVT 303 select CPU_CP15_MMU 304 select CPU_PABRT_LEGACY 305 select CPU_TLB_V4WBI if MMU 306 307# XScale Core Version 3 308config CPU_XSC3 309 bool 310 select CPU_32v5 311 select CPU_ABRT_EV5T 312 select CPU_CACHE_VIVT 313 select CPU_CP15_MMU 314 select CPU_PABRT_LEGACY 315 select CPU_TLB_V4WBI if MMU 316 select IO_36 317 318# Marvell PJ1 (Mohawk) 319config CPU_MOHAWK 320 bool 321 select CPU_32v5 322 select CPU_ABRT_EV5T 323 select CPU_CACHE_VIVT 324 select CPU_COPY_V4WB if MMU 325 select CPU_CP15_MMU 326 select CPU_PABRT_LEGACY 327 select CPU_TLB_V4WBI if MMU 328 329# Feroceon 330config CPU_FEROCEON 331 bool 332 select CPU_32v5 333 select CPU_ABRT_EV5T 334 select CPU_CACHE_VIVT 335 select CPU_COPY_FEROCEON if MMU 336 select CPU_CP15_MMU 337 select CPU_PABRT_LEGACY 338 select CPU_TLB_FEROCEON if MMU 339 340config CPU_FEROCEON_OLD_ID 341 bool "Accept early Feroceon cores with an ARM926 ID" 342 depends on CPU_FEROCEON && !CPU_ARM926T 343 default y 344 help 345 This enables the usage of some old Feroceon cores 346 for which the CPU ID is equal to the ARM926 ID. 347 Relevant for Feroceon-1850 and early Feroceon-2850. 348 349# Marvell PJ4 350config CPU_PJ4 351 bool 352 select ARM_THUMBEE 353 select CPU_V7 354 355config CPU_PJ4B 356 bool 357 select CPU_V7 358 359# ARMv6 360config CPU_V6 361 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX 362 select CPU_32v6 363 select CPU_ABRT_EV6 364 select CPU_CACHE_V6 365 select CPU_CACHE_VIPT 366 select CPU_COPY_V6 if MMU 367 select CPU_CP15_MMU 368 select CPU_HAS_ASID if MMU 369 select CPU_PABRT_V6 370 select CPU_TLB_V6 if MMU 371 372# ARMv6k 373config CPU_V6K 374 bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX 375 select CPU_32v6 376 select CPU_32v6K 377 select CPU_ABRT_EV6 378 select CPU_CACHE_V6 379 select CPU_CACHE_VIPT 380 select CPU_COPY_V6 if MMU 381 select CPU_CP15_MMU 382 select CPU_HAS_ASID if MMU 383 select CPU_PABRT_V6 384 select CPU_TLB_V6 if MMU 385 386# ARMv7 387config CPU_V7 388 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX 389 select CPU_32v6K 390 select CPU_32v7 391 select CPU_ABRT_EV7 392 select CPU_CACHE_V7 393 select CPU_CACHE_VIPT 394 select CPU_COPY_V6 if MMU 395 select CPU_CP15_MMU 396 select CPU_HAS_ASID if MMU 397 select CPU_PABRT_V7 398 select CPU_TLB_V7 if MMU 399 400# Figure out what processor architecture version we should be using. 401# This defines the compiler instruction set which depends on the machine type. 402config CPU_32v3 403 bool 404 select CPU_USE_DOMAINS if MMU 405 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 406 select TLS_REG_EMUL if SMP || !MMU 407 408config CPU_32v4 409 bool 410 select CPU_USE_DOMAINS if MMU 411 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 412 select TLS_REG_EMUL if SMP || !MMU 413 414config CPU_32v4T 415 bool 416 select CPU_USE_DOMAINS if MMU 417 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 418 select TLS_REG_EMUL if SMP || !MMU 419 420config CPU_32v5 421 bool 422 select CPU_USE_DOMAINS if MMU 423 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 424 select TLS_REG_EMUL if SMP || !MMU 425 426config CPU_32v6 427 bool 428 select CPU_USE_DOMAINS if CPU_V6 && MMU 429 select TLS_REG_EMUL if !CPU_32v6K && !MMU 430 431config CPU_32v6K 432 bool 433 434config CPU_32v7 435 bool 436 437# The abort model 438config CPU_ABRT_NOMMU 439 bool 440 441config CPU_ABRT_EV4 442 bool 443 444config CPU_ABRT_EV4T 445 bool 446 447config CPU_ABRT_LV4T 448 bool 449 450config CPU_ABRT_EV5T 451 bool 452 453config CPU_ABRT_EV5TJ 454 bool 455 456config CPU_ABRT_EV6 457 bool 458 459config CPU_ABRT_EV7 460 bool 461 462config CPU_PABRT_LEGACY 463 bool 464 465config CPU_PABRT_V6 466 bool 467 468config CPU_PABRT_V7 469 bool 470 471# The cache model 472config CPU_CACHE_V4 473 bool 474 475config CPU_CACHE_V4WT 476 bool 477 478config CPU_CACHE_V4WB 479 bool 480 481config CPU_CACHE_V6 482 bool 483 484config CPU_CACHE_V7 485 bool 486 487config CPU_CACHE_VIVT 488 bool 489 490config CPU_CACHE_VIPT 491 bool 492 493config CPU_CACHE_FA 494 bool 495 496if MMU 497# The copy-page model 498config CPU_COPY_V4WT 499 bool 500 501config CPU_COPY_V4WB 502 bool 503 504config CPU_COPY_FEROCEON 505 bool 506 507config CPU_COPY_FA 508 bool 509 510config CPU_COPY_V6 511 bool 512 513# This selects the TLB model 514config CPU_TLB_V4WT 515 bool 516 help 517 ARM Architecture Version 4 TLB with writethrough cache. 518 519config CPU_TLB_V4WB 520 bool 521 help 522 ARM Architecture Version 4 TLB with writeback cache. 523 524config CPU_TLB_V4WBI 525 bool 526 help 527 ARM Architecture Version 4 TLB with writeback cache and invalidate 528 instruction cache entry. 529 530config CPU_TLB_FEROCEON 531 bool 532 help 533 Feroceon TLB (v4wbi with non-outer-cachable page table walks). 534 535config CPU_TLB_FA 536 bool 537 help 538 Faraday ARM FA526 architecture, unified TLB with writeback cache 539 and invalidate instruction cache entry. Branch target buffer is 540 also supported. 541 542config CPU_TLB_V6 543 bool 544 545config CPU_TLB_V7 546 bool 547 548config VERIFY_PERMISSION_FAULT 549 bool 550endif 551 552config CPU_HAS_ASID 553 bool 554 help 555 This indicates whether the CPU has the ASID register; used to 556 tag TLB and possibly cache entries. 557 558config CPU_CP15 559 bool 560 help 561 Processor has the CP15 register. 562 563config CPU_CP15_MMU 564 bool 565 select CPU_CP15 566 help 567 Processor has the CP15 register, which has MMU related registers. 568 569config CPU_CP15_MPU 570 bool 571 select CPU_CP15 572 help 573 Processor has the CP15 register, which has MPU related registers. 574 575config CPU_USE_DOMAINS 576 bool 577 help 578 This option enables or disables the use of domain switching 579 via the set_fs() function. 580 581# 582# CPU supports 36-bit I/O 583# 584config IO_36 585 bool 586 587comment "Processor Features" 588 589config ARM_LPAE 590 bool "Support for the Large Physical Address Extension" 591 depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \ 592 !CPU_32v4 && !CPU_32v3 593 help 594 Say Y if you have an ARMv7 processor supporting the LPAE page 595 table format and you would like to access memory beyond the 596 4GB limit. The resulting kernel image will not run on 597 processors without the LPA extension. 598 599 If unsure, say N. 600 601config ARCH_PHYS_ADDR_T_64BIT 602 def_bool ARM_LPAE 603 604config ARCH_DMA_ADDR_T_64BIT 605 bool 606 607config ARM_THUMB 608 bool "Support Thumb user binaries" 609 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON 610 default y 611 help 612 Say Y if you want to include kernel support for running user space 613 Thumb binaries. 614 615 The Thumb instruction set is a compressed form of the standard ARM 616 instruction set resulting in smaller binaries at the expense of 617 slightly less efficient code. 618 619 If you don't know what this all is, saying Y is a safe choice. 620 621config ARM_THUMBEE 622 bool "Enable ThumbEE CPU extension" 623 depends on CPU_V7 624 help 625 Say Y here if you have a CPU with the ThumbEE extension and code to 626 make use of it. Say N for code that can run on CPUs without ThumbEE. 627 628config ARM_VIRT_EXT 629 bool 630 depends on MMU 631 default y if CPU_V7 632 help 633 Enable the kernel to make use of the ARM Virtualization 634 Extensions to install hypervisors without run-time firmware 635 assistance. 636 637 A compliant bootloader is required in order to make maximum 638 use of this feature. Refer to Documentation/arm/Booting for 639 details. 640 641config SWP_EMULATE 642 bool "Emulate SWP/SWPB instructions" 643 depends on !CPU_USE_DOMAINS && CPU_V7 644 default y if SMP 645 select HAVE_PROC_CPU if PROC_FS 646 help 647 ARMv6 architecture deprecates use of the SWP/SWPB instructions. 648 ARMv7 multiprocessing extensions introduce the ability to disable 649 these instructions, triggering an undefined instruction exception 650 when executed. Say Y here to enable software emulation of these 651 instructions for userspace (not kernel) using LDREX/STREX. 652 Also creates /proc/cpu/swp_emulation for statistics. 653 654 In some older versions of glibc [<=2.8] SWP is used during futex 655 trylock() operations with the assumption that the code will not 656 be preempted. This invalid assumption may be more likely to fail 657 with SWP emulation enabled, leading to deadlock of the user 658 application. 659 660 NOTE: when accessing uncached shared regions, LDREX/STREX rely 661 on an external transaction monitoring block called a global 662 monitor to maintain update atomicity. If your system does not 663 implement a global monitor, this option can cause programs that 664 perform SWP operations to uncached memory to deadlock. 665 666 If unsure, say Y. 667 668config CPU_BIG_ENDIAN 669 bool "Build big-endian kernel" 670 depends on ARCH_SUPPORTS_BIG_ENDIAN 671 help 672 Say Y if you plan on running a kernel in big-endian mode. 673 Note that your board must be properly built and your board 674 port must properly enable any big-endian related features 675 of your chipset/board/processor. 676 677config CPU_ENDIAN_BE8 678 bool 679 depends on CPU_BIG_ENDIAN 680 default CPU_V6 || CPU_V6K || CPU_V7 681 help 682 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors. 683 684config CPU_ENDIAN_BE32 685 bool 686 depends on CPU_BIG_ENDIAN 687 default !CPU_ENDIAN_BE8 688 help 689 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors. 690 691config CPU_HIGH_VECTOR 692 depends on !MMU && CPU_CP15 && !CPU_ARM740T 693 bool "Select the High exception vector" 694 help 695 Say Y here to select high exception vector(0xFFFF0000~). 696 The exception vector can vary depending on the platform 697 design in nommu mode. If your platform needs to select 698 high exception vector, say Y. 699 Otherwise or if you are unsure, say N, and the low exception 700 vector (0x00000000~) will be used. 701 702config CPU_ICACHE_DISABLE 703 bool "Disable I-Cache (I-bit)" 704 depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) 705 help 706 Say Y here to disable the processor instruction cache. Unless 707 you have a reason not to or are unsure, say N. 708 709config CPU_DCACHE_DISABLE 710 bool "Disable D-Cache (C-bit)" 711 depends on CPU_CP15 712 help 713 Say Y here to disable the processor data cache. Unless 714 you have a reason not to or are unsure, say N. 715 716config CPU_DCACHE_SIZE 717 hex 718 depends on CPU_ARM740T || CPU_ARM946E 719 default 0x00001000 if CPU_ARM740T 720 default 0x00002000 # default size for ARM946E-S 721 help 722 Some cores are synthesizable to have various sized cache. For 723 ARM946E-S case, it can vary from 0KB to 1MB. 724 To support such cache operations, it is efficient to know the size 725 before compile time. 726 If your SoC is configured to have a different size, define the value 727 here with proper conditions. 728 729config CPU_DCACHE_WRITETHROUGH 730 bool "Force write through D-cache" 731 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE 732 default y if CPU_ARM925T 733 help 734 Say Y here to use the data cache in writethrough mode. Unless you 735 specifically require this or are unsure, say N. 736 737config CPU_CACHE_ROUND_ROBIN 738 bool "Round robin I and D cache replacement algorithm" 739 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) 740 help 741 Say Y here to use the predictable round-robin cache replacement 742 policy. Unless you specifically require this or are unsure, say N. 743 744config CPU_BPREDICT_DISABLE 745 bool "Disable branch prediction" 746 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 747 help 748 Say Y here to disable branch prediction. If unsure, say N. 749 750config TLS_REG_EMUL 751 bool 752 help 753 An SMP system using a pre-ARMv6 processor (there are apparently 754 a few prototypes like that in existence) and therefore access to 755 that required register must be emulated. 756 757config NEEDS_SYSCALL_FOR_CMPXCHG 758 bool 759 help 760 SMP on a pre-ARMv6 processor? Well OK then. 761 Forget about fast user space cmpxchg support. 762 It is just not possible. 763 764config DMA_CACHE_RWFO 765 bool "Enable read/write for ownership DMA cache maintenance" 766 depends on CPU_V6K && SMP 767 default y 768 help 769 The Snoop Control Unit on ARM11MPCore does not detect the 770 cache maintenance operations and the dma_{map,unmap}_area() 771 functions may leave stale cache entries on other CPUs. By 772 enabling this option, Read or Write For Ownership in the ARMv6 773 DMA cache maintenance functions is performed. These LDR/STR 774 instructions change the cache line state to shared or modified 775 so that the cache operation has the desired effect. 776 777 Note that the workaround is only valid on processors that do 778 not perform speculative loads into the D-cache. For such 779 processors, if cache maintenance operations are not broadcast 780 in hardware, other workarounds are needed (e.g. cache 781 maintenance broadcasting in software via FIQ). 782 783config OUTER_CACHE 784 bool 785 786config OUTER_CACHE_SYNC 787 bool 788 help 789 The outer cache has a outer_cache_fns.sync function pointer 790 that can be used to drain the write buffer of the outer cache. 791 792config CACHE_FEROCEON_L2 793 bool "Enable the Feroceon L2 cache controller" 794 depends on ARCH_KIRKWOOD || ARCH_MV78XX0 795 default y 796 select OUTER_CACHE 797 help 798 This option enables the Feroceon L2 cache controller. 799 800config CACHE_FEROCEON_L2_WRITETHROUGH 801 bool "Force Feroceon L2 cache write through" 802 depends on CACHE_FEROCEON_L2 803 help 804 Say Y here to use the Feroceon L2 cache in writethrough mode. 805 Unless you specifically require this, say N for writeback mode. 806 807config MIGHT_HAVE_CACHE_L2X0 808 bool 809 help 810 This option should be selected by machines which have a L2x0 811 or PL310 cache controller, but where its use is optional. 812 813 The only effect of this option is to make CACHE_L2X0 and 814 related options available to the user for configuration. 815 816 Boards or SoCs which always require the cache controller 817 support to be present should select CACHE_L2X0 directly 818 instead of this option, thus preventing the user from 819 inadvertently configuring a broken kernel. 820 821config CACHE_L2X0 822 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0 823 default MIGHT_HAVE_CACHE_L2X0 824 select OUTER_CACHE 825 select OUTER_CACHE_SYNC 826 help 827 This option enables the L2x0 PrimeCell. 828 829config CACHE_PL310 830 bool 831 depends on CACHE_L2X0 832 default y if CPU_V7 && !(CPU_V6 || CPU_V6K) 833 help 834 This option enables optimisations for the PL310 cache 835 controller. 836 837config CACHE_TAUROS2 838 bool "Enable the Tauros2 L2 cache controller" 839 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4) 840 default y 841 select OUTER_CACHE 842 help 843 This option enables the Tauros2 L2 cache controller (as 844 found on PJ1/PJ4). 845 846config CACHE_XSC3L2 847 bool "Enable the L2 cache on XScale3" 848 depends on CPU_XSC3 849 default y 850 select OUTER_CACHE 851 help 852 This option enables the L2 cache on XScale3. 853 854config ARM_L1_CACHE_SHIFT_6 855 bool 856 default y if CPU_V7 857 help 858 Setting ARM L1 cache line size to 64 Bytes. 859 860config ARM_L1_CACHE_SHIFT 861 int 862 default 6 if ARM_L1_CACHE_SHIFT_6 863 default 5 864 865config ARM_DMA_MEM_BUFFERABLE 866 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7 867 depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \ 868 MACH_REALVIEW_PB11MP) 869 default y if CPU_V6 || CPU_V6K || CPU_V7 870 help 871 Historically, the kernel has used strongly ordered mappings to 872 provide DMA coherent memory. With the advent of ARMv7, mapping 873 memory with differing types results in unpredictable behaviour, 874 so on these CPUs, this option is forced on. 875 876 Multiple mappings with differing attributes is also unpredictable 877 on ARMv6 CPUs, but since they do not have aggressive speculative 878 prefetch, no harm appears to occur. 879 880 However, drivers may be missing the necessary barriers for ARMv6, 881 and therefore turning this on may result in unpredictable driver 882 behaviour. Therefore, we offer this as an option. 883 884 You are recommended say 'Y' here and debug any affected drivers. 885 886config ARCH_HAS_BARRIERS 887 bool 888 help 889 This option allows the use of custom mandatory barriers 890 included via the mach/barriers.h file. 891