1config ARM 2 bool 3 default y 4 select HAVE_AOUT 5 select HAVE_DMA_API_DEBUG 6 select HAVE_IDE if PCI || ISA || PCMCIA 7 select HAVE_MEMBLOCK 8 select RTC_LIB 9 select SYS_SUPPORTS_APM_EMULATION 10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) 11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 12 select HAVE_ARCH_KGDB 13 select HAVE_KPROBES if !XIP_KERNEL 14 select HAVE_KRETPROBES if (HAVE_KPROBES) 15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) 18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 19 select HAVE_GENERIC_DMA_COHERENT 20 select HAVE_KERNEL_GZIP 21 select HAVE_KERNEL_LZO 22 select HAVE_KERNEL_LZMA 23 select HAVE_IRQ_WORK 24 select HAVE_PERF_EVENTS 25 select PERF_USE_VMALLOC 26 select HAVE_REGS_AND_STACK_ACCESS_API 27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 28 select HAVE_C_RECORDMCOUNT 29 select HAVE_GENERIC_HARDIRQS 30 select HAVE_SPARSE_IRQ 31 select GENERIC_IRQ_SHOW 32 select CPU_PM if (SUSPEND || CPU_IDLE) 33 help 34 The ARM series is a line of low-power-consumption RISC chip designs 35 licensed by ARM Ltd and targeted at embedded applications and 36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 37 manufactured, but legacy ARM-based PC hardware remains popular in 38 Europe. There is an ARM Linux project with a web page at 39 <http://www.arm.linux.org.uk/>. 40 41config ARM_HAS_SG_CHAIN 42 bool 43 44config HAVE_PWM 45 bool 46 47config MIGHT_HAVE_PCI 48 bool 49 50config SYS_SUPPORTS_APM_EMULATION 51 bool 52 53config HAVE_SCHED_CLOCK 54 bool 55 56config GENERIC_GPIO 57 bool 58 59config ARCH_USES_GETTIMEOFFSET 60 bool 61 default n 62 63config GENERIC_CLOCKEVENTS 64 bool 65 66config GENERIC_CLOCKEVENTS_BROADCAST 67 bool 68 depends on GENERIC_CLOCKEVENTS 69 default y if SMP 70 71config KTIME_SCALAR 72 bool 73 default y 74 75config HAVE_TCM 76 bool 77 select GENERIC_ALLOCATOR 78 79config HAVE_PROC_CPU 80 bool 81 82config NO_IOPORT 83 bool 84 85config EISA 86 bool 87 ---help--- 88 The Extended Industry Standard Architecture (EISA) bus was 89 developed as an open alternative to the IBM MicroChannel bus. 90 91 The EISA bus provided some of the features of the IBM MicroChannel 92 bus while maintaining backward compatibility with cards made for 93 the older ISA bus. The EISA bus saw limited use between 1988 and 94 1995 when it was made obsolete by the PCI bus. 95 96 Say Y here if you are building a kernel for an EISA-based machine. 97 98 Otherwise, say N. 99 100config SBUS 101 bool 102 103config MCA 104 bool 105 help 106 MicroChannel Architecture is found in some IBM PS/2 machines and 107 laptops. It is a bus system similar to PCI or ISA. See 108 <file:Documentation/mca.txt> (and especially the web page given 109 there) before attempting to build an MCA bus kernel. 110 111config STACKTRACE_SUPPORT 112 bool 113 default y 114 115config HAVE_LATENCYTOP_SUPPORT 116 bool 117 depends on !SMP 118 default y 119 120config LOCKDEP_SUPPORT 121 bool 122 default y 123 124config TRACE_IRQFLAGS_SUPPORT 125 bool 126 default y 127 128config HARDIRQS_SW_RESEND 129 bool 130 default y 131 132config GENERIC_IRQ_PROBE 133 bool 134 default y 135 136config GENERIC_LOCKBREAK 137 bool 138 default y 139 depends on SMP && PREEMPT 140 141config RWSEM_GENERIC_SPINLOCK 142 bool 143 default y 144 145config RWSEM_XCHGADD_ALGORITHM 146 bool 147 148config ARCH_HAS_ILOG2_U32 149 bool 150 151config ARCH_HAS_ILOG2_U64 152 bool 153 154config ARCH_HAS_CPUFREQ 155 bool 156 help 157 Internal node to signify that the ARCH has CPUFREQ support 158 and that the relevant menu configurations are displayed for 159 it. 160 161config ARCH_HAS_CPU_IDLE_WAIT 162 def_bool y 163 164config GENERIC_HWEIGHT 165 bool 166 default y 167 168config GENERIC_CALIBRATE_DELAY 169 bool 170 default y 171 172config ARCH_MAY_HAVE_PC_FDC 173 bool 174 175config ZONE_DMA 176 bool 177 178config NEED_DMA_MAP_STATE 179 def_bool y 180 181config GENERIC_ISA_DMA 182 bool 183 184config FIQ 185 bool 186 187config ARCH_MTD_XIP 188 bool 189 190config VECTORS_BASE 191 hex 192 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 193 default DRAM_BASE if REMAP_VECTORS_TO_RAM 194 default 0x00000000 195 help 196 The base address of exception vectors. 197 198config ARM_PATCH_PHYS_VIRT 199 bool "Patch physical to virtual translations at runtime" if EMBEDDED 200 default y 201 depends on !XIP_KERNEL && MMU 202 depends on !ARCH_REALVIEW || !SPARSEMEM 203 help 204 Patch phys-to-virt and virt-to-phys translation functions at 205 boot and module load time according to the position of the 206 kernel in system memory. 207 208 This can only be used with non-XIP MMU kernels where the base 209 of physical memory is at a 16MB boundary. 210 211 Only disable this option if you know that you do not require 212 this feature (eg, building a kernel for a single machine) and 213 you need to shrink the kernel to the minimal size. 214 215config NEED_MACH_MEMORY_H 216 bool 217 help 218 Select this when mach/memory.h is required to provide special 219 definitions for this platform. The need for mach/memory.h should 220 be avoided when possible. 221 222config PHYS_OFFSET 223 hex "Physical address of main memory" if MMU 224 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H 225 default DRAM_BASE if !MMU 226 help 227 Please provide the physical address corresponding to the 228 location of main memory in your system. 229 230config GENERIC_BUG 231 def_bool y 232 depends on BUG 233 234source "init/Kconfig" 235 236source "kernel/Kconfig.freezer" 237 238menu "System Type" 239 240config MMU 241 bool "MMU-based Paged Memory Management Support" 242 default y 243 help 244 Select if you want MMU-based virtualised addressing space 245 support by paged memory management. If unsure, say 'Y'. 246 247# 248# The "ARM system type" choice list is ordered alphabetically by option 249# text. Please add new entries in the option alphabetic order. 250# 251choice 252 prompt "ARM system type" 253 default ARCH_VERSATILE 254 255config ARCH_INTEGRATOR 256 bool "ARM Ltd. Integrator family" 257 select ARM_AMBA 258 select ARCH_HAS_CPUFREQ 259 select CLKDEV_LOOKUP 260 select HAVE_MACH_CLKDEV 261 select ICST 262 select GENERIC_CLOCKEVENTS 263 select PLAT_VERSATILE 264 select PLAT_VERSATILE_FPGA_IRQ 265 select NEED_MACH_MEMORY_H 266 help 267 Support for ARM's Integrator platform. 268 269config ARCH_REALVIEW 270 bool "ARM Ltd. RealView family" 271 select ARM_AMBA 272 select CLKDEV_LOOKUP 273 select HAVE_MACH_CLKDEV 274 select ICST 275 select GENERIC_CLOCKEVENTS 276 select ARCH_WANT_OPTIONAL_GPIOLIB 277 select PLAT_VERSATILE 278 select PLAT_VERSATILE_CLCD 279 select ARM_TIMER_SP804 280 select GPIO_PL061 if GPIOLIB 281 select NEED_MACH_MEMORY_H 282 help 283 This enables support for ARM Ltd RealView boards. 284 285config ARCH_VERSATILE 286 bool "ARM Ltd. Versatile family" 287 select ARM_AMBA 288 select ARM_VIC 289 select CLKDEV_LOOKUP 290 select HAVE_MACH_CLKDEV 291 select ICST 292 select GENERIC_CLOCKEVENTS 293 select ARCH_WANT_OPTIONAL_GPIOLIB 294 select PLAT_VERSATILE 295 select PLAT_VERSATILE_CLCD 296 select PLAT_VERSATILE_FPGA_IRQ 297 select ARM_TIMER_SP804 298 help 299 This enables support for ARM Ltd Versatile board. 300 301config ARCH_VEXPRESS 302 bool "ARM Ltd. Versatile Express family" 303 select ARCH_WANT_OPTIONAL_GPIOLIB 304 select ARM_AMBA 305 select ARM_TIMER_SP804 306 select CLKDEV_LOOKUP 307 select HAVE_MACH_CLKDEV 308 select GENERIC_CLOCKEVENTS 309 select HAVE_CLK 310 select HAVE_PATA_PLATFORM 311 select ICST 312 select PLAT_VERSATILE 313 select PLAT_VERSATILE_CLCD 314 help 315 This enables support for the ARM Ltd Versatile Express boards. 316 317config ARCH_AT91 318 bool "Atmel AT91" 319 select ARCH_REQUIRE_GPIOLIB 320 select HAVE_CLK 321 select CLKDEV_LOOKUP 322 help 323 This enables support for systems based on the Atmel AT91RM9200, 324 AT91SAM9 and AT91CAP9 processors. 325 326config ARCH_BCMRING 327 bool "Broadcom BCMRING" 328 depends on MMU 329 select CPU_V6 330 select ARM_AMBA 331 select ARM_TIMER_SP804 332 select CLKDEV_LOOKUP 333 select GENERIC_CLOCKEVENTS 334 select ARCH_WANT_OPTIONAL_GPIOLIB 335 help 336 Support for Broadcom's BCMRing platform. 337 338config ARCH_HIGHBANK 339 bool "Calxeda Highbank-based" 340 select ARCH_WANT_OPTIONAL_GPIOLIB 341 select ARM_AMBA 342 select ARM_GIC 343 select ARM_TIMER_SP804 344 select CLKDEV_LOOKUP 345 select CPU_V7 346 select GENERIC_CLOCKEVENTS 347 select HAVE_ARM_SCU 348 select USE_OF 349 help 350 Support for the Calxeda Highbank SoC based boards. 351 352config ARCH_CLPS711X 353 bool "Cirrus Logic CLPS711x/EP721x-based" 354 select CPU_ARM720T 355 select ARCH_USES_GETTIMEOFFSET 356 select NEED_MACH_MEMORY_H 357 help 358 Support for Cirrus Logic 711x/721x based boards. 359 360config ARCH_CNS3XXX 361 bool "Cavium Networks CNS3XXX family" 362 select CPU_V6K 363 select GENERIC_CLOCKEVENTS 364 select ARM_GIC 365 select MIGHT_HAVE_PCI 366 select PCI_DOMAINS if PCI 367 help 368 Support for Cavium Networks CNS3XXX platform. 369 370config ARCH_GEMINI 371 bool "Cortina Systems Gemini" 372 select CPU_FA526 373 select ARCH_REQUIRE_GPIOLIB 374 select ARCH_USES_GETTIMEOFFSET 375 help 376 Support for the Cortina Systems Gemini family SoCs 377 378config ARCH_PRIMA2 379 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" 380 select CPU_V7 381 select NO_IOPORT 382 select GENERIC_CLOCKEVENTS 383 select CLKDEV_LOOKUP 384 select GENERIC_IRQ_CHIP 385 select USE_OF 386 select ZONE_DMA 387 help 388 Support for CSR SiRFSoC ARM Cortex A9 Platform 389 390config ARCH_EBSA110 391 bool "EBSA-110" 392 select CPU_SA110 393 select ISA 394 select NO_IOPORT 395 select ARCH_USES_GETTIMEOFFSET 396 select NEED_MACH_MEMORY_H 397 help 398 This is an evaluation board for the StrongARM processor available 399 from Digital. It has limited hardware on-board, including an 400 Ethernet interface, two PCMCIA sockets, two serial ports and a 401 parallel port. 402 403config ARCH_EP93XX 404 bool "EP93xx-based" 405 select CPU_ARM920T 406 select ARM_AMBA 407 select ARM_VIC 408 select CLKDEV_LOOKUP 409 select ARCH_REQUIRE_GPIOLIB 410 select ARCH_HAS_HOLES_MEMORYMODEL 411 select ARCH_USES_GETTIMEOFFSET 412 select NEED_MACH_MEMORY_H 413 help 414 This enables support for the Cirrus EP93xx series of CPUs. 415 416config ARCH_FOOTBRIDGE 417 bool "FootBridge" 418 select CPU_SA110 419 select FOOTBRIDGE 420 select GENERIC_CLOCKEVENTS 421 select HAVE_IDE 422 select NEED_MACH_MEMORY_H 423 help 424 Support for systems based on the DC21285 companion chip 425 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 426 427config ARCH_MXC 428 bool "Freescale MXC/iMX-based" 429 select GENERIC_CLOCKEVENTS 430 select ARCH_REQUIRE_GPIOLIB 431 select CLKDEV_LOOKUP 432 select CLKSRC_MMIO 433 select GENERIC_IRQ_CHIP 434 select HAVE_SCHED_CLOCK 435 select MULTI_IRQ_HANDLER 436 help 437 Support for Freescale MXC/iMX-based family of processors 438 439config ARCH_MXS 440 bool "Freescale MXS-based" 441 select GENERIC_CLOCKEVENTS 442 select ARCH_REQUIRE_GPIOLIB 443 select CLKDEV_LOOKUP 444 select CLKSRC_MMIO 445 help 446 Support for Freescale MXS-based family of processors 447 448config ARCH_NETX 449 bool "Hilscher NetX based" 450 select CLKSRC_MMIO 451 select CPU_ARM926T 452 select ARM_VIC 453 select GENERIC_CLOCKEVENTS 454 help 455 This enables support for systems based on the Hilscher NetX Soc 456 457config ARCH_H720X 458 bool "Hynix HMS720x-based" 459 select CPU_ARM720T 460 select ISA_DMA_API 461 select ARCH_USES_GETTIMEOFFSET 462 help 463 This enables support for systems based on the Hynix HMS720x 464 465config ARCH_IOP13XX 466 bool "IOP13xx-based" 467 depends on MMU 468 select CPU_XSC3 469 select PLAT_IOP 470 select PCI 471 select ARCH_SUPPORTS_MSI 472 select VMSPLIT_1G 473 select NEED_MACH_MEMORY_H 474 help 475 Support for Intel's IOP13XX (XScale) family of processors. 476 477config ARCH_IOP32X 478 bool "IOP32x-based" 479 depends on MMU 480 select CPU_XSCALE 481 select PLAT_IOP 482 select PCI 483 select ARCH_REQUIRE_GPIOLIB 484 help 485 Support for Intel's 80219 and IOP32X (XScale) family of 486 processors. 487 488config ARCH_IOP33X 489 bool "IOP33x-based" 490 depends on MMU 491 select CPU_XSCALE 492 select PLAT_IOP 493 select PCI 494 select ARCH_REQUIRE_GPIOLIB 495 help 496 Support for Intel's IOP33X (XScale) family of processors. 497 498config ARCH_IXP23XX 499 bool "IXP23XX-based" 500 depends on MMU 501 select CPU_XSC3 502 select PCI 503 select ARCH_USES_GETTIMEOFFSET 504 select NEED_MACH_MEMORY_H 505 help 506 Support for Intel's IXP23xx (XScale) family of processors. 507 508config ARCH_IXP2000 509 bool "IXP2400/2800-based" 510 depends on MMU 511 select CPU_XSCALE 512 select PCI 513 select ARCH_USES_GETTIMEOFFSET 514 select NEED_MACH_MEMORY_H 515 help 516 Support for Intel's IXP2400/2800 (XScale) family of processors. 517 518config ARCH_IXP4XX 519 bool "IXP4xx-based" 520 depends on MMU 521 select CLKSRC_MMIO 522 select CPU_XSCALE 523 select GENERIC_GPIO 524 select GENERIC_CLOCKEVENTS 525 select HAVE_SCHED_CLOCK 526 select MIGHT_HAVE_PCI 527 select DMABOUNCE if PCI 528 help 529 Support for Intel's IXP4XX (XScale) family of processors. 530 531config ARCH_DOVE 532 bool "Marvell Dove" 533 select CPU_V7 534 select PCI 535 select ARCH_REQUIRE_GPIOLIB 536 select GENERIC_CLOCKEVENTS 537 select PLAT_ORION 538 help 539 Support for the Marvell Dove SoC 88AP510 540 541config ARCH_KIRKWOOD 542 bool "Marvell Kirkwood" 543 select CPU_FEROCEON 544 select PCI 545 select ARCH_REQUIRE_GPIOLIB 546 select GENERIC_CLOCKEVENTS 547 select PLAT_ORION 548 help 549 Support for the following Marvell Kirkwood series SoCs: 550 88F6180, 88F6192 and 88F6281. 551 552config ARCH_LPC32XX 553 bool "NXP LPC32XX" 554 select CLKSRC_MMIO 555 select CPU_ARM926T 556 select ARCH_REQUIRE_GPIOLIB 557 select HAVE_IDE 558 select ARM_AMBA 559 select USB_ARCH_HAS_OHCI 560 select CLKDEV_LOOKUP 561 select GENERIC_CLOCKEVENTS 562 help 563 Support for the NXP LPC32XX family of processors 564 565config ARCH_MV78XX0 566 bool "Marvell MV78xx0" 567 select CPU_FEROCEON 568 select PCI 569 select ARCH_REQUIRE_GPIOLIB 570 select GENERIC_CLOCKEVENTS 571 select PLAT_ORION 572 help 573 Support for the following Marvell MV78xx0 series SoCs: 574 MV781x0, MV782x0. 575 576config ARCH_ORION5X 577 bool "Marvell Orion" 578 depends on MMU 579 select CPU_FEROCEON 580 select PCI 581 select ARCH_REQUIRE_GPIOLIB 582 select GENERIC_CLOCKEVENTS 583 select PLAT_ORION 584 help 585 Support for the following Marvell Orion 5x series SoCs: 586 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), 587 Orion-2 (5281), Orion-1-90 (6183). 588 589config ARCH_MMP 590 bool "Marvell PXA168/910/MMP2" 591 depends on MMU 592 select ARCH_REQUIRE_GPIOLIB 593 select CLKDEV_LOOKUP 594 select GENERIC_CLOCKEVENTS 595 select HAVE_SCHED_CLOCK 596 select TICK_ONESHOT 597 select PLAT_PXA 598 select SPARSE_IRQ 599 select GENERIC_ALLOCATOR 600 help 601 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. 602 603config ARCH_KS8695 604 bool "Micrel/Kendin KS8695" 605 select CPU_ARM922T 606 select ARCH_REQUIRE_GPIOLIB 607 select ARCH_USES_GETTIMEOFFSET 608 select NEED_MACH_MEMORY_H 609 help 610 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 611 System-on-Chip devices. 612 613config ARCH_W90X900 614 bool "Nuvoton W90X900 CPU" 615 select CPU_ARM926T 616 select ARCH_REQUIRE_GPIOLIB 617 select CLKDEV_LOOKUP 618 select CLKSRC_MMIO 619 select GENERIC_CLOCKEVENTS 620 help 621 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 622 At present, the w90x900 has been renamed nuc900, regarding 623 the ARM series product line, you can login the following 624 link address to know more. 625 626 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 627 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 628 629config ARCH_TEGRA 630 bool "NVIDIA Tegra" 631 select CLKDEV_LOOKUP 632 select CLKSRC_MMIO 633 select GENERIC_CLOCKEVENTS 634 select GENERIC_GPIO 635 select HAVE_CLK 636 select HAVE_SCHED_CLOCK 637 select ARCH_HAS_CPUFREQ 638 help 639 This enables support for NVIDIA Tegra based systems (Tegra APX, 640 Tegra 6xx and Tegra 2 series). 641 642config ARCH_PICOXCELL 643 bool "Picochip picoXcell" 644 select ARCH_REQUIRE_GPIOLIB 645 select ARM_PATCH_PHYS_VIRT 646 select ARM_VIC 647 select CPU_V6K 648 select DW_APB_TIMER 649 select GENERIC_CLOCKEVENTS 650 select GENERIC_GPIO 651 select HAVE_SCHED_CLOCK 652 select HAVE_TCM 653 select NO_IOPORT 654 select USE_OF 655 help 656 This enables support for systems based on the Picochip picoXcell 657 family of Femtocell devices. The picoxcell support requires device tree 658 for all boards. 659 660config ARCH_PNX4008 661 bool "Philips Nexperia PNX4008 Mobile" 662 select CPU_ARM926T 663 select CLKDEV_LOOKUP 664 select ARCH_USES_GETTIMEOFFSET 665 help 666 This enables support for Philips PNX4008 mobile platform. 667 668config ARCH_PXA 669 bool "PXA2xx/PXA3xx-based" 670 depends on MMU 671 select ARCH_MTD_XIP 672 select ARCH_HAS_CPUFREQ 673 select CLKDEV_LOOKUP 674 select CLKSRC_MMIO 675 select ARCH_REQUIRE_GPIOLIB 676 select GENERIC_CLOCKEVENTS 677 select HAVE_SCHED_CLOCK 678 select TICK_ONESHOT 679 select PLAT_PXA 680 select SPARSE_IRQ 681 select AUTO_ZRELADDR 682 select MULTI_IRQ_HANDLER 683 select ARM_CPU_SUSPEND if PM 684 select HAVE_IDE 685 help 686 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 687 688config ARCH_MSM 689 bool "Qualcomm MSM" 690 select HAVE_CLK 691 select GENERIC_CLOCKEVENTS 692 select ARCH_REQUIRE_GPIOLIB 693 select CLKDEV_LOOKUP 694 help 695 Support for Qualcomm MSM/QSD based systems. This runs on the 696 apps processor of the MSM/QSD and depends on a shared memory 697 interface to the modem processor which runs the baseband 698 stack and controls some vital subsystems 699 (clock and power control, etc). 700 701config ARCH_SHMOBILE 702 bool "Renesas SH-Mobile / R-Mobile" 703 select HAVE_CLK 704 select CLKDEV_LOOKUP 705 select HAVE_MACH_CLKDEV 706 select GENERIC_CLOCKEVENTS 707 select NO_IOPORT 708 select SPARSE_IRQ 709 select MULTI_IRQ_HANDLER 710 select PM_GENERIC_DOMAINS if PM 711 select NEED_MACH_MEMORY_H 712 help 713 Support for Renesas's SH-Mobile and R-Mobile ARM platforms. 714 715config ARCH_RPC 716 bool "RiscPC" 717 select ARCH_ACORN 718 select FIQ 719 select TIMER_ACORN 720 select ARCH_MAY_HAVE_PC_FDC 721 select HAVE_PATA_PLATFORM 722 select ISA_DMA_API 723 select NO_IOPORT 724 select ARCH_SPARSEMEM_ENABLE 725 select ARCH_USES_GETTIMEOFFSET 726 select HAVE_IDE 727 select NEED_MACH_MEMORY_H 728 help 729 On the Acorn Risc-PC, Linux can support the internal IDE disk and 730 CD-ROM interface, serial and parallel port, and the floppy drive. 731 732config ARCH_SA1100 733 bool "SA1100-based" 734 select CLKSRC_MMIO 735 select CPU_SA1100 736 select ISA 737 select ARCH_SPARSEMEM_ENABLE 738 select ARCH_MTD_XIP 739 select ARCH_HAS_CPUFREQ 740 select CPU_FREQ 741 select GENERIC_CLOCKEVENTS 742 select HAVE_CLK 743 select HAVE_SCHED_CLOCK 744 select TICK_ONESHOT 745 select ARCH_REQUIRE_GPIOLIB 746 select HAVE_IDE 747 select NEED_MACH_MEMORY_H 748 help 749 Support for StrongARM 11x0 based boards. 750 751config ARCH_S3C2410 752 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450" 753 select GENERIC_GPIO 754 select ARCH_HAS_CPUFREQ 755 select HAVE_CLK 756 select CLKDEV_LOOKUP 757 select ARCH_USES_GETTIMEOFFSET 758 select HAVE_S3C2410_I2C if I2C 759 help 760 Samsung S3C2410X CPU based systems, such as the Simtec Electronics 761 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or 762 the Samsung SMDK2410 development board (and derivatives). 763 764 Note, the S3C2416 and the S3C2450 are so close that they even share 765 the same SoC ID code. This means that there is no separate machine 766 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first. 767 768config ARCH_S3C64XX 769 bool "Samsung S3C64XX" 770 select PLAT_SAMSUNG 771 select CPU_V6 772 select ARM_VIC 773 select HAVE_CLK 774 select HAVE_TCM 775 select CLKDEV_LOOKUP 776 select NO_IOPORT 777 select ARCH_USES_GETTIMEOFFSET 778 select ARCH_HAS_CPUFREQ 779 select ARCH_REQUIRE_GPIOLIB 780 select SAMSUNG_CLKSRC 781 select SAMSUNG_IRQ_VIC_TIMER 782 select S3C_GPIO_TRACK 783 select S3C_DEV_NAND 784 select USB_ARCH_HAS_OHCI 785 select SAMSUNG_GPIOLIB_4BIT 786 select HAVE_S3C2410_I2C if I2C 787 select HAVE_S3C2410_WATCHDOG if WATCHDOG 788 help 789 Samsung S3C64XX series based systems 790 791config ARCH_S5P64X0 792 bool "Samsung S5P6440 S5P6450" 793 select CPU_V6 794 select GENERIC_GPIO 795 select HAVE_CLK 796 select CLKDEV_LOOKUP 797 select CLKSRC_MMIO 798 select HAVE_S3C2410_WATCHDOG if WATCHDOG 799 select GENERIC_CLOCKEVENTS 800 select HAVE_SCHED_CLOCK 801 select HAVE_S3C2410_I2C if I2C 802 select HAVE_S3C_RTC if RTC_CLASS 803 help 804 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, 805 SMDK6450. 806 807config ARCH_S5PC100 808 bool "Samsung S5PC100" 809 select GENERIC_GPIO 810 select HAVE_CLK 811 select CLKDEV_LOOKUP 812 select CPU_V7 813 select ARM_L1_CACHE_SHIFT_6 814 select ARCH_USES_GETTIMEOFFSET 815 select HAVE_S3C2410_I2C if I2C 816 select HAVE_S3C_RTC if RTC_CLASS 817 select HAVE_S3C2410_WATCHDOG if WATCHDOG 818 help 819 Samsung S5PC100 series based systems 820 821config ARCH_S5PV210 822 bool "Samsung S5PV210/S5PC110" 823 select CPU_V7 824 select ARCH_SPARSEMEM_ENABLE 825 select ARCH_HAS_HOLES_MEMORYMODEL 826 select GENERIC_GPIO 827 select HAVE_CLK 828 select CLKDEV_LOOKUP 829 select CLKSRC_MMIO 830 select ARM_L1_CACHE_SHIFT_6 831 select ARCH_HAS_CPUFREQ 832 select GENERIC_CLOCKEVENTS 833 select HAVE_SCHED_CLOCK 834 select HAVE_S3C2410_I2C if I2C 835 select HAVE_S3C_RTC if RTC_CLASS 836 select HAVE_S3C2410_WATCHDOG if WATCHDOG 837 select NEED_MACH_MEMORY_H 838 help 839 Samsung S5PV210/S5PC110 series based systems 840 841config ARCH_EXYNOS 842 bool "SAMSUNG EXYNOS" 843 select CPU_V7 844 select ARCH_SPARSEMEM_ENABLE 845 select ARCH_HAS_HOLES_MEMORYMODEL 846 select GENERIC_GPIO 847 select HAVE_CLK 848 select CLKDEV_LOOKUP 849 select ARCH_HAS_CPUFREQ 850 select GENERIC_CLOCKEVENTS 851 select HAVE_S3C_RTC if RTC_CLASS 852 select HAVE_S3C2410_I2C if I2C 853 select HAVE_S3C2410_WATCHDOG if WATCHDOG 854 select NEED_MACH_MEMORY_H 855 help 856 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) 857 858config ARCH_SHARK 859 bool "Shark" 860 select CPU_SA110 861 select ISA 862 select ISA_DMA 863 select ZONE_DMA 864 select PCI 865 select ARCH_USES_GETTIMEOFFSET 866 select NEED_MACH_MEMORY_H 867 help 868 Support for the StrongARM based Digital DNARD machine, also known 869 as "Shark" (<http://www.shark-linux.de/shark.html>). 870 871config ARCH_TCC_926 872 bool "Telechips TCC ARM926-based systems" 873 select CLKSRC_MMIO 874 select CPU_ARM926T 875 select HAVE_CLK 876 select CLKDEV_LOOKUP 877 select GENERIC_CLOCKEVENTS 878 help 879 Support for Telechips TCC ARM926-based systems. 880 881config ARCH_U300 882 bool "ST-Ericsson U300 Series" 883 depends on MMU 884 select CLKSRC_MMIO 885 select CPU_ARM926T 886 select HAVE_SCHED_CLOCK 887 select HAVE_TCM 888 select ARM_AMBA 889 select ARM_PATCH_PHYS_VIRT 890 select ARM_VIC 891 select GENERIC_CLOCKEVENTS 892 select CLKDEV_LOOKUP 893 select HAVE_MACH_CLKDEV 894 select GENERIC_GPIO 895 select ARCH_REQUIRE_GPIOLIB 896 select NEED_MACH_MEMORY_H 897 help 898 Support for ST-Ericsson U300 series mobile platforms. 899 900config ARCH_U8500 901 bool "ST-Ericsson U8500 Series" 902 select CPU_V7 903 select ARM_AMBA 904 select GENERIC_CLOCKEVENTS 905 select CLKDEV_LOOKUP 906 select ARCH_REQUIRE_GPIOLIB 907 select ARCH_HAS_CPUFREQ 908 help 909 Support for ST-Ericsson's Ux500 architecture 910 911config ARCH_NOMADIK 912 bool "STMicroelectronics Nomadik" 913 select ARM_AMBA 914 select ARM_VIC 915 select CPU_ARM926T 916 select CLKDEV_LOOKUP 917 select GENERIC_CLOCKEVENTS 918 select ARCH_REQUIRE_GPIOLIB 919 help 920 Support for the Nomadik platform by ST-Ericsson 921 922config ARCH_DAVINCI 923 bool "TI DaVinci" 924 select GENERIC_CLOCKEVENTS 925 select ARCH_REQUIRE_GPIOLIB 926 select ZONE_DMA 927 select HAVE_IDE 928 select CLKDEV_LOOKUP 929 select GENERIC_ALLOCATOR 930 select GENERIC_IRQ_CHIP 931 select ARCH_HAS_HOLES_MEMORYMODEL 932 help 933 Support for TI's DaVinci platform. 934 935config ARCH_OMAP 936 bool "TI OMAP" 937 select HAVE_CLK 938 select ARCH_REQUIRE_GPIOLIB 939 select ARCH_HAS_CPUFREQ 940 select CLKSRC_MMIO 941 select GENERIC_CLOCKEVENTS 942 select HAVE_SCHED_CLOCK 943 select ARCH_HAS_HOLES_MEMORYMODEL 944 help 945 Support for TI's OMAP platform (OMAP1/2/3/4). 946 947config PLAT_SPEAR 948 bool "ST SPEAr" 949 select ARM_AMBA 950 select ARCH_REQUIRE_GPIOLIB 951 select CLKDEV_LOOKUP 952 select CLKSRC_MMIO 953 select GENERIC_CLOCKEVENTS 954 select HAVE_CLK 955 help 956 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). 957 958config ARCH_VT8500 959 bool "VIA/WonderMedia 85xx" 960 select CPU_ARM926T 961 select GENERIC_GPIO 962 select ARCH_HAS_CPUFREQ 963 select GENERIC_CLOCKEVENTS 964 select ARCH_REQUIRE_GPIOLIB 965 select HAVE_PWM 966 help 967 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. 968 969config ARCH_ZYNQ 970 bool "Xilinx Zynq ARM Cortex A9 Platform" 971 select CPU_V7 972 select GENERIC_CLOCKEVENTS 973 select CLKDEV_LOOKUP 974 select ARM_GIC 975 select ARM_AMBA 976 select ICST 977 select USE_OF 978 help 979 Support for Xilinx Zynq ARM Cortex A9 Platform 980endchoice 981 982# 983# This is sorted alphabetically by mach-* pathname. However, plat-* 984# Kconfigs may be included either alphabetically (according to the 985# plat- suffix) or along side the corresponding mach-* source. 986# 987source "arch/arm/mach-at91/Kconfig" 988 989source "arch/arm/mach-bcmring/Kconfig" 990 991source "arch/arm/mach-clps711x/Kconfig" 992 993source "arch/arm/mach-cns3xxx/Kconfig" 994 995source "arch/arm/mach-davinci/Kconfig" 996 997source "arch/arm/mach-dove/Kconfig" 998 999source "arch/arm/mach-ep93xx/Kconfig" 1000
1001source "arch/arm/mach-footbridge/Kconfig" 1002 1003source "arch/arm/mach-gemini/Kconfig" 1004 1005source "arch/arm/mach-h720x/Kconfig" 1006 1007source "arch/arm/mach-integrator/Kconfig" 1008 1009source "arch/arm/mach-iop32x/Kconfig" 1010 1011source "arch/arm/mach-iop33x/Kconfig" 1012 1013source "arch/arm/mach-iop13xx/Kconfig" 1014 1015source "arch/arm/mach-ixp4xx/Kconfig" 1016 1017source "arch/arm/mach-ixp2000/Kconfig" 1018 1019source "arch/arm/mach-ixp23xx/Kconfig" 1020 1021source "arch/arm/mach-kirkwood/Kconfig" 1022 1023source "arch/arm/mach-ks8695/Kconfig" 1024 1025source "arch/arm/mach-lpc32xx/Kconfig" 1026 1027source "arch/arm/mach-msm/Kconfig" 1028 1029source "arch/arm/mach-mv78xx0/Kconfig" 1030 1031source "arch/arm/plat-mxc/Kconfig" 1032 1033source "arch/arm/mach-mxs/Kconfig" 1034 1035source "arch/arm/mach-netx/Kconfig" 1036 1037source "arch/arm/mach-nomadik/Kconfig" 1038source "arch/arm/plat-nomadik/Kconfig" 1039 1040source "arch/arm/plat-omap/Kconfig" 1041 1042source "arch/arm/mach-omap1/Kconfig" 1043 1044source "arch/arm/mach-omap2/Kconfig" 1045 1046source "arch/arm/mach-orion5x/Kconfig" 1047 1048source "arch/arm/mach-pxa/Kconfig" 1049source "arch/arm/plat-pxa/Kconfig" 1050 1051source "arch/arm/mach-mmp/Kconfig" 1052 1053source "arch/arm/mach-realview/Kconfig" 1054 1055source "arch/arm/mach-sa1100/Kconfig" 1056 1057source "arch/arm/plat-samsung/Kconfig" 1058source "arch/arm/plat-s3c24xx/Kconfig" 1059source "arch/arm/plat-s5p/Kconfig" 1060 1061source "arch/arm/plat-spear/Kconfig" 1062 1063source "arch/arm/plat-tcc/Kconfig" 1064 1065if ARCH_S3C2410 1066source "arch/arm/mach-s3c2410/Kconfig" 1067source "arch/arm/mach-s3c2412/Kconfig" 1068source "arch/arm/mach-s3c2416/Kconfig" 1069source "arch/arm/mach-s3c2440/Kconfig" 1070source "arch/arm/mach-s3c2443/Kconfig" 1071endif 1072 1073if ARCH_S3C64XX 1074source "arch/arm/mach-s3c64xx/Kconfig" 1075endif 1076 1077source "arch/arm/mach-s5p64x0/Kconfig" 1078 1079source "arch/arm/mach-s5pc100/Kconfig" 1080 1081source "arch/arm/mach-s5pv210/Kconfig" 1082 1083source "arch/arm/mach-exynos/Kconfig" 1084 1085source "arch/arm/mach-shmobile/Kconfig" 1086 1087source "arch/arm/mach-tegra/Kconfig" 1088 1089source "arch/arm/mach-u300/Kconfig" 1090 1091source "arch/arm/mach-ux500/Kconfig" 1092 1093source "arch/arm/mach-versatile/Kconfig" 1094 1095source "arch/arm/mach-vexpress/Kconfig" 1096source "arch/arm/plat-versatile/Kconfig" 1097 1098source "arch/arm/mach-vt8500/Kconfig" 1099 1100source "arch/arm/mach-w90x900/Kconfig" 1101 1102# Definitions to make life easier 1103config ARCH_ACORN 1104 bool 1105 1106config PLAT_IOP 1107 bool 1108 select GENERIC_CLOCKEVENTS 1109 select HAVE_SCHED_CLOCK 1110 1111config PLAT_ORION 1112 bool 1113 select CLKSRC_MMIO 1114 select GENERIC_IRQ_CHIP 1115 select HAVE_SCHED_CLOCK 1116 1117config PLAT_PXA 1118 bool 1119 1120config PLAT_VERSATILE 1121 bool 1122 1123config ARM_TIMER_SP804 1124 bool 1125 select CLKSRC_MMIO 1126 1127source arch/arm/mm/Kconfig 1128 1129config IWMMXT 1130 bool "Enable iWMMXt support" 1131 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 1132 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP 1133 help 1134 Enable support for iWMMXt context switching at run time if 1135 running on a CPU that supports it. 1136 1137# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER 1138config XSCALE_PMU 1139 bool 1140 depends on CPU_XSCALE && !XSCALE_PMU_TIMER 1141 default y 1142 1143config CPU_HAS_PMU 1144 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \ 1145 (!ARCH_OMAP3 || OMAP3_EMU) 1146 default y 1147 bool 1148 1149config MULTI_IRQ_HANDLER 1150 bool 1151 help 1152 Allow each machine to specify it's own IRQ handler at run time. 1153 1154if !MMU 1155source "arch/arm/Kconfig-nommu" 1156endif 1157 1158config ARM_ERRATA_411920 1159 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 1160 depends on CPU_V6 || CPU_V6K 1161 help 1162 Invalidation of the Instruction Cache operation can 1163 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 1164 It does not affect the MPCore. This option enables the ARM Ltd. 1165 recommended workaround. 1166 1167config ARM_ERRATA_430973 1168 bool "ARM errata: Stale prediction on replaced interworking branch" 1169 depends on CPU_V7 1170 help 1171 This option enables the workaround for the 430973 Cortex-A8 1172 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb 1173 interworking branch is replaced with another code sequence at the 1174 same virtual address, whether due to self-modifying code or virtual 1175 to physical address re-mapping, Cortex-A8 does not recover from the 1176 stale interworking branch prediction. This results in Cortex-A8 1177 executing the new code sequence in the incorrect ARM or Thumb state. 1178 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 1179 and also flushes the branch target cache at every context switch. 1180 Note that setting specific bits in the ACTLR register may not be 1181 available in non-secure mode. 1182 1183config ARM_ERRATA_458693 1184 bool "ARM errata: Processor deadlock when a false hazard is created" 1185 depends on CPU_V7 1186 help 1187 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 1188 erratum. For very specific sequences of memory operations, it is 1189 possible for a hazard condition intended for a cache line to instead 1190 be incorrectly associated with a different cache line. This false 1191 hazard might then cause a processor deadlock. The workaround enables 1192 the L1 caching of the NEON accesses and disables the PLD instruction 1193 in the ACTLR register. Note that setting specific bits in the ACTLR 1194 register may not be available in non-secure mode. 1195 1196config ARM_ERRATA_460075 1197 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1198 depends on CPU_V7 1199 help 1200 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1201 erratum. Any asynchronous access to the L2 cache may encounter a 1202 situation in which recent store transactions to the L2 cache are lost 1203 and overwritten with stale memory contents from external memory. The 1204 workaround disables the write-allocate mode for the L2 cache via the 1205 ACTLR register. Note that setting specific bits in the ACTLR register 1206 may not be available in non-secure mode. 1207 1208config ARM_ERRATA_742230 1209 bool "ARM errata: DMB operation may be faulty" 1210 depends on CPU_V7 && SMP 1211 help 1212 This option enables the workaround for the 742230 Cortex-A9 1213 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1214 between two write operations may not ensure the correct visibility 1215 ordering of the two writes. This workaround sets a specific bit in 1216 the diagnostic register of the Cortex-A9 which causes the DMB 1217 instruction to behave as a DSB, ensuring the correct behaviour of 1218 the two writes. 1219 1220config ARM_ERRATA_742231 1221 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1222 depends on CPU_V7 && SMP 1223 help 1224 This option enables the workaround for the 742231 Cortex-A9 1225 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1226 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1227 accessing some data located in the same cache line, may get corrupted 1228 data due to bad handling of the address hazard when the line gets 1229 replaced from one of the CPUs at the same time as another CPU is 1230 accessing it. This workaround sets specific bits in the diagnostic 1231 register of the Cortex-A9 which reduces the linefill issuing 1232 capabilities of the processor. 1233 1234config PL310_ERRATA_588369 1235 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" 1236 depends on CACHE_L2X0 1237 help 1238 The PL310 L2 cache controller implements three types of Clean & 1239 Invalidate maintenance operations: by Physical Address 1240 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). 1241 They are architecturally defined to behave as the execution of a 1242 clean operation followed immediately by an invalidate operation, 1243 both performing to the same memory location. This functionality 1244 is not correctly implemented in PL310 as clean lines are not 1245 invalidated as a result of these operations. 1246 1247config ARM_ERRATA_720789 1248 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1249 depends on CPU_V7 1250 help 1251 This option enables the workaround for the 720789 Cortex-A9 (prior to 1252 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1253 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1254 As a consequence of this erratum, some TLB entries which should be 1255 invalidated are not, resulting in an incoherency in the system page 1256 tables. The workaround changes the TLB flushing routines to invalidate 1257 entries regardless of the ASID. 1258 1259config PL310_ERRATA_727915 1260 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" 1261 depends on CACHE_L2X0 1262 help 1263 PL310 implements the Clean & Invalidate by Way L2 cache maintenance 1264 operation (offset 0x7FC). This operation runs in background so that 1265 PL310 can handle normal accesses while it is in progress. Under very 1266 rare circumstances, due to this erratum, write data can be lost when 1267 PL310 treats a cacheable write transaction during a Clean & 1268 Invalidate by Way operation. 1269 1270config ARM_ERRATA_743622 1271 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1272 depends on CPU_V7 1273 help 1274 This option enables the workaround for the 743622 Cortex-A9 1275 (r2p0..r2p2) erratum. Under very rare conditions, a faulty 1276 optimisation in the Cortex-A9 Store Buffer may lead to data 1277 corruption. This workaround sets a specific bit in the diagnostic 1278 register of the Cortex-A9 which disables the Store Buffer 1279 optimisation, preventing the defect from occurring. This has no 1280 visible impact on the overall performance or power consumption of the 1281 processor. 1282 1283config ARM_ERRATA_751472 1284 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1285 depends on CPU_V7 1286 help 1287 This option enables the workaround for the 751472 Cortex-A9 (prior 1288 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1289 completion of a following broadcasted operation if the second 1290 operation is received by a CPU before the ICIALLUIS has completed, 1291 potentially leading to corrupted entries in the cache or TLB. 1292 1293config PL310_ERRATA_753970 1294 bool "PL310 errata: cache sync operation may be faulty" 1295 depends on CACHE_PL310 1296 help 1297 This option enables the workaround for the 753970 PL310 (r3p0) erratum. 1298 1299 Under some condition the effect of cache sync operation on 1300 the store buffer still remains when the operation completes. 1301 This means that the store buffer is always asked to drain and 1302 this prevents it from merging any further writes. The workaround 1303 is to replace the normal offset of cache sync operation (0x730) 1304 by another offset targeting an unmapped PL310 register 0x740. 1305 This has the same effect as the cache sync operation: store buffer 1306 drain and waiting for all buffers empty. 1307 1308config ARM_ERRATA_754322 1309 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1310 depends on CPU_V7 1311 help 1312 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1313 r3p*) erratum. A speculative memory access may cause a page table walk 1314 which starts prior to an ASID switch but completes afterwards. This 1315 can populate the micro-TLB with a stale entry which may be hit with 1316 the new ASID. This workaround places two dsb instructions in the mm 1317 switching code so that no page table walks can cross the ASID switch. 1318 1319config ARM_ERRATA_754327 1320 bool "ARM errata: no automatic Store Buffer drain" 1321 depends on CPU_V7 && SMP 1322 help 1323 This option enables the workaround for the 754327 Cortex-A9 (prior to 1324 r2p0) erratum. The Store Buffer does not have any automatic draining 1325 mechanism and therefore a livelock may occur if an external agent 1326 continuously polls a memory location waiting to observe an update. 1327 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1328 written polling loops from denying visibility of updates to memory. 1329 1330config ARM_ERRATA_364296 1331 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1332 depends on CPU_V6 && !SMP 1333 help 1334 This options enables the workaround for the 364296 ARM1136 1335 r0p2 erratum (possible cache data corruption with 1336 hit-under-miss enabled). It sets the undocumented bit 31 in 1337 the auxiliary control register and the FI bit in the control 1338 register, thus disabling hit-under-miss without putting the 1339 processor into full low interrupt latency mode. ARM11MPCore 1340 is not affected. 1341 1342config ARM_ERRATA_764369 1343 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1344 depends on CPU_V7 && SMP 1345 help 1346 This option enables the workaround for erratum 764369 1347 affecting Cortex-A9 MPCore with two or more processors (all 1348 current revisions). Under certain timing circumstances, a data 1349 cache line maintenance operation by MVA targeting an Inner 1350 Shareable memory region may fail to proceed up to either the 1351 Point of Coherency or to the Point of Unification of the 1352 system. This workaround adds a DSB instruction before the 1353 relevant cache maintenance functions and sets a specific bit 1354 in the diagnostic control register of the SCU. 1355 1356config PL310_ERRATA_769419 1357 bool "PL310 errata: no automatic Store Buffer drain" 1358 depends on CACHE_L2X0 1359 help 1360 On revisions of the PL310 prior to r3p2, the Store Buffer does 1361 not automatically drain. This can cause normal, non-cacheable 1362 writes to be retained when the memory system is idle, leading 1363 to suboptimal I/O performance for drivers using coherent DMA. 1364 This option adds a write barrier to the cpu_idle loop so that, 1365 on systems with an outer cache, the store buffer is drained 1366 explicitly. 1367 1368endmenu 1369 1370source "arch/arm/common/Kconfig" 1371 1372menu "Bus support" 1373 1374config ARM_AMBA 1375 bool 1376 1377config ISA 1378 bool 1379 help 1380 Find out whether you have ISA slots on your motherboard. ISA is the 1381 name of a bus system, i.e. the way the CPU talks to the other stuff 1382 inside your box. Other bus systems are PCI, EISA, MicroChannel 1383 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1384 newer boards don't support it. If you have ISA, say Y, otherwise N. 1385 1386# Select ISA DMA controller support 1387config ISA_DMA 1388 bool 1389 select ISA_DMA_API 1390 1391# Select ISA DMA interface 1392config ISA_DMA_API 1393 bool 1394 1395config PCI 1396 bool "PCI support" if MIGHT_HAVE_PCI 1397 help 1398 Find out whether you have a PCI motherboard. PCI is the name of a 1399 bus system, i.e. the way the CPU talks to the other stuff inside 1400 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1401 VESA. If you have PCI, say Y, otherwise N. 1402 1403config PCI_DOMAINS 1404 bool 1405 depends on PCI 1406 1407config PCI_NANOENGINE 1408 bool "BSE nanoEngine PCI support" 1409 depends on SA1100_NANOENGINE 1410 help 1411 Enable PCI on the BSE nanoEngine board. 1412 1413config PCI_SYSCALL 1414 def_bool PCI 1415 1416# Select the host bridge type 1417config PCI_HOST_VIA82C505 1418 bool 1419 depends on PCI && ARCH_SHARK 1420 default y 1421 1422config PCI_HOST_ITE8152 1423 bool 1424 depends on PCI && MACH_ARMCORE 1425 default y 1426 select DMABOUNCE 1427 1428source "drivers/pci/Kconfig" 1429 1430source "drivers/pcmcia/Kconfig" 1431 1432endmenu 1433 1434menu "Kernel Features" 1435 1436source "kernel/time/Kconfig" 1437 1438config SMP 1439 bool "Symmetric Multi-Processing" 1440 depends on CPU_V6K || CPU_V7 1441 depends on GENERIC_CLOCKEVENTS 1442 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ 1443 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ 1444 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \ 1445 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q 1446 depends on MMU 1447 select USE_GENERIC_SMP_HELPERS 1448 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP 1449 help 1450 This enables support for systems with more than one CPU. If you have 1451 a system with only one CPU, like most personal computers, say N. If 1452 you have a system with more than one CPU, say Y. 1453 1454 If you say N here, the kernel will run on single and multiprocessor 1455 machines, but will use only one CPU of a multiprocessor machine. If 1456 you say Y here, the kernel will run on many, but not all, single 1457 processor machines. On a single processor machine, the kernel will 1458 run faster if you say N here. 1459 1460 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1461 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1462 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1463 1464 If you don't know what to do here, say N. 1465 1466config SMP_ON_UP 1467 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" 1468 depends on EXPERIMENTAL 1469 depends on SMP && !XIP_KERNEL 1470 default y 1471 help 1472 SMP kernels contain instructions which fail on non-SMP processors. 1473 Enabling this option allows the kernel to modify itself to make 1474 these instructions safe. Disabling it allows about 1K of space 1475 savings. 1476 1477 If you don't know what to do here, say Y. 1478 1479config ARM_CPU_TOPOLOGY 1480 bool "Support cpu topology definition" 1481 depends on SMP && CPU_V7 1482 default y 1483 help 1484 Support ARM cpu topology definition. The MPIDR register defines 1485 affinity between processors which is then used to describe the cpu 1486 topology of an ARM System. 1487 1488config SCHED_MC 1489 bool "Multi-core scheduler support" 1490 depends on ARM_CPU_TOPOLOGY 1491 help 1492 Multi-core scheduler support improves the CPU scheduler's decision 1493 making when dealing with multi-core CPU chips at a cost of slightly 1494 increased overhead in some places. If unsure say N here. 1495 1496config SCHED_SMT 1497 bool "SMT scheduler support" 1498 depends on ARM_CPU_TOPOLOGY 1499 help 1500 Improves the CPU scheduler's decision making when dealing with 1501 MultiThreading at a cost of slightly increased overhead in some 1502 places. If unsure say N here. 1503 1504config HAVE_ARM_SCU 1505 bool 1506 help 1507 This option enables support for the ARM system coherency unit 1508 1509config HAVE_ARM_TWD 1510 bool 1511 depends on SMP 1512 select TICK_ONESHOT 1513 help 1514 This options enables support for the ARM timer and watchdog unit 1515 1516choice 1517 prompt "Memory split" 1518 default VMSPLIT_3G 1519 help 1520 Select the desired split between kernel and user memory. 1521 1522 If you are not absolutely sure what you are doing, leave this 1523 option alone! 1524 1525 config VMSPLIT_3G 1526 bool "3G/1G user/kernel split" 1527 config VMSPLIT_2G 1528 bool "2G/2G user/kernel split" 1529 config VMSPLIT_1G 1530 bool "1G/3G user/kernel split" 1531endchoice 1532 1533config PAGE_OFFSET 1534 hex 1535 default 0x40000000 if VMSPLIT_1G 1536 default 0x80000000 if VMSPLIT_2G 1537 default 0xC0000000 1538 1539config NR_CPUS 1540 int "Maximum number of CPUs (2-32)" 1541 range 2 32 1542 depends on SMP 1543 default "4" 1544 1545config HOTPLUG_CPU 1546 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" 1547 depends on SMP && HOTPLUG && EXPERIMENTAL 1548 help 1549 Say Y here to experiment with turning CPUs off and on. CPUs 1550 can be controlled through /sys/devices/system/cpu. 1551 1552config LOCAL_TIMERS 1553 bool "Use local timer interrupts" 1554 depends on SMP 1555 default y 1556 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT) 1557 help 1558 Enable support for local timers on SMP platforms, rather then the 1559 legacy IPI broadcast method. Local timers allows the system 1560 accounting to be spread across the timer interval, preventing a 1561 "thundering herd" at every timer tick. 1562 1563source kernel/Kconfig.preempt 1564 1565config HZ 1566 int 1567 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \ 1568 ARCH_S5PV210 || ARCH_EXYNOS4 1569 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER 1570 default AT91_TIMER_HZ if ARCH_AT91 1571 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE 1572 default 100 1573 1574config THUMB2_KERNEL 1575 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)" 1576 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL 1577 select AEABI 1578 select ARM_ASM_UNIFIED 1579 select ARM_UNWIND 1580 help 1581 By enabling this option, the kernel will be compiled in 1582 Thumb-2 mode. A compiler/assembler that understand the unified 1583 ARM-Thumb syntax is needed. 1584 1585 If unsure, say N. 1586 1587config THUMB2_AVOID_R_ARM_THM_JUMP11 1588 bool "Work around buggy Thumb-2 short branch relocations in gas" 1589 depends on THUMB2_KERNEL && MODULES 1590 default y 1591 help 1592 Various binutils versions can resolve Thumb-2 branches to 1593 locally-defined, preemptible global symbols as short-range "b.n" 1594 branch instructions. 1595 1596 This is a problem, because there's no guarantee the final 1597 destination of the symbol, or any candidate locations for a 1598 trampoline, are within range of the branch. For this reason, the 1599 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1600 relocation in modules at all, and it makes little sense to add 1601 support. 1602 1603 The symptom is that the kernel fails with an "unsupported 1604 relocation" error when loading some modules. 1605 1606 Until fixed tools are available, passing 1607 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1608 code which hits this problem, at the cost of a bit of extra runtime 1609 stack usage in some cases. 1610 1611 The problem is described in more detail at: 1612 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1613 1614 Only Thumb-2 kernels are affected. 1615 1616 Unless you are sure your tools don't have this problem, say Y. 1617 1618config ARM_ASM_UNIFIED 1619 bool 1620 1621config AEABI 1622 bool "Use the ARM EABI to compile the kernel" 1623 help 1624 This option allows for the kernel to be compiled using the latest 1625 ARM ABI (aka EABI). This is only useful if you are using a user 1626 space environment that is also compiled with EABI. 1627 1628 Since there are major incompatibilities between the legacy ABI and 1629 EABI, especially with regard to structure member alignment, this 1630 option also changes the kernel syscall calling convention to 1631 disambiguate both ABIs and allow for backward compatibility support 1632 (selected with CONFIG_OABI_COMPAT). 1633 1634 To use this you need GCC version 4.0.0 or later. 1635 1636config OABI_COMPAT 1637 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1638 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL 1639 default y 1640 help 1641 This option preserves the old syscall interface along with the 1642 new (ARM EABI) one. It also provides a compatibility layer to 1643 intercept syscalls that have structure arguments which layout 1644 in memory differs between the legacy ABI and the new ARM EABI 1645 (only for non "thumb" binaries). This option adds a tiny 1646 overhead to all syscalls and produces a slightly larger kernel. 1647 If you know you'll be using only pure EABI user space then you 1648 can say N here. If this option is not selected and you attempt 1649 to execute a legacy ABI binary then the result will be 1650 UNPREDICTABLE (in fact it can be predicted that it won't work 1651 at all). If in doubt say Y. 1652 1653config ARCH_HAS_HOLES_MEMORYMODEL 1654 bool 1655 1656config ARCH_SPARSEMEM_ENABLE 1657 bool 1658 1659config ARCH_SPARSEMEM_DEFAULT 1660 def_bool ARCH_SPARSEMEM_ENABLE 1661 1662config ARCH_SELECT_MEMORY_MODEL 1663 def_bool ARCH_SPARSEMEM_ENABLE 1664 1665config HAVE_ARCH_PFN_VALID 1666 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1667 1668config HIGHMEM 1669 bool "High Memory Support" 1670 depends on MMU 1671 help 1672 The address space of ARM processors is only 4 Gigabytes large 1673 and it has to accommodate user address space, kernel address 1674 space as well as some memory mapped IO. That means that, if you 1675 have a large amount of physical memory and/or IO, not all of the 1676 memory can be "permanently mapped" by the kernel. The physical 1677 memory that is not permanently mapped is called "high memory". 1678 1679 Depending on the selected kernel/user memory split, minimum 1680 vmalloc space and actual amount of RAM, you may not need this 1681 option which should result in a slightly faster kernel. 1682 1683 If unsure, say n. 1684 1685config HIGHPTE 1686 bool "Allocate 2nd-level pagetables from highmem" 1687 depends on HIGHMEM 1688 1689config HW_PERF_EVENTS 1690 bool "Enable hardware performance counter support for perf events" 1691 depends on PERF_EVENTS && CPU_HAS_PMU 1692 default y 1693 help 1694 Enable hardware performance counter support for perf events. If 1695 disabled, perf events will use software events only. 1696 1697source "mm/Kconfig" 1698 1699config FORCE_MAX_ZONEORDER 1700 int "Maximum zone order" if ARCH_SHMOBILE 1701 range 11 64 if ARCH_SHMOBILE 1702 default "9" if SA1111 1703 default "11" 1704 help 1705 The kernel memory allocator divides physically contiguous memory 1706 blocks into "zones", where each zone is a power of two number of 1707 pages. This option selects the largest power of two that the kernel 1708 keeps in the memory allocator. If you need to allocate very large 1709 blocks of physically contiguous memory, then you may need to 1710 increase this value. 1711 1712 This config option is actually maximum order plus one. For example, 1713 a value of 11 means that the largest free memory block is 2^10 pages. 1714 1715config LEDS 1716 bool "Timer and CPU usage LEDs" 1717 depends on ARCH_CDB89712 || ARCH_EBSA110 || \ 1718 ARCH_EBSA285 || ARCH_INTEGRATOR || \ 1719 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ 1720 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ 1721 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ 1722 ARCH_AT91 || ARCH_DAVINCI || \ 1723 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW 1724 help 1725 If you say Y here, the LEDs on your machine will be used 1726 to provide useful information about your current system status. 1727 1728 If you are compiling a kernel for a NetWinder or EBSA-285, you will 1729 be able to select which LEDs are active using the options below. If 1730 you are compiling a kernel for the EBSA-110 or the LART however, the 1731 red LED will simply flash regularly to indicate that the system is 1732 still functional. It is safe to say Y here if you have a CATS 1733 system, but the driver will do nothing. 1734 1735config LEDS_TIMER 1736 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \ 1737 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1738 || MACH_OMAP_PERSEUS2 1739 depends on LEDS 1740 depends on !GENERIC_CLOCKEVENTS 1741 default y if ARCH_EBSA110 1742 help 1743 If you say Y here, one of the system LEDs (the green one on the 1744 NetWinder, the amber one on the EBSA285, or the red one on the LART) 1745 will flash regularly to indicate that the system is still 1746 operational. This is mainly useful to kernel hackers who are 1747 debugging unstable kernels. 1748 1749 The LART uses the same LED for both Timer LED and CPU usage LED 1750 functions. You may choose to use both, but the Timer LED function 1751 will overrule the CPU usage LED. 1752 1753config LEDS_CPU 1754 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \ 1755 !ARCH_OMAP) \ 1756 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1757 || MACH_OMAP_PERSEUS2 1758 depends on LEDS 1759 help 1760 If you say Y here, the red LED will be used to give a good real 1761 time indication of CPU usage, by lighting whenever the idle task 1762 is not currently executing. 1763 1764 The LART uses the same LED for both Timer LED and CPU usage LED 1765 functions. You may choose to use both, but the Timer LED function 1766 will overrule the CPU usage LED. 1767 1768config ALIGNMENT_TRAP 1769 bool 1770 depends on CPU_CP15_MMU 1771 default y if !ARCH_EBSA110 1772 select HAVE_PROC_CPU if PROC_FS 1773 help 1774 ARM processors cannot fetch/store information which is not 1775 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1776 address divisible by 4. On 32-bit ARM processors, these non-aligned 1777 fetch/store instructions will be emulated in software if you say 1778 here, which has a severe performance impact. This is necessary for 1779 correct operation of some network protocols. With an IP-only 1780 configuration it is safe to say N, otherwise say Y. 1781 1782config UACCESS_WITH_MEMCPY 1783 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)" 1784 depends on MMU && EXPERIMENTAL 1785 default y if CPU_FEROCEON 1786 help 1787 Implement faster copy_to_user and clear_user methods for CPU 1788 cores where a 8-word STM instruction give significantly higher 1789 memory write throughput than a sequence of individual 32bit stores. 1790 1791 A possible side effect is a slight increase in scheduling latency 1792 between threads sharing the same address space if they invoke 1793 such copy operations with large buffers. 1794 1795 However, if the CPU data cache is using a write-allocate mode, 1796 this option is unlikely to provide any performance gain. 1797 1798config SECCOMP 1799 bool 1800 prompt "Enable seccomp to safely compute untrusted bytecode" 1801 ---help--- 1802 This kernel feature is useful for number crunching applications 1803 that may need to compute untrusted bytecode during their 1804 execution. By using pipes or other transports made available to 1805 the process as file descriptors supporting the read/write 1806 syscalls, it's possible to isolate those applications in 1807 their own address space using seccomp. Once seccomp is 1808 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1809 and the task is only allowed to execute a few safe syscalls 1810 defined by each seccomp mode. 1811 1812config CC_STACKPROTECTOR 1813 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" 1814 depends on EXPERIMENTAL 1815 help 1816 This option turns on the -fstack-protector GCC feature. This 1817 feature puts, at the beginning of functions, a canary value on 1818 the stack just before the return address, and validates 1819 the value just before actually returning. Stack based buffer 1820 overflows (that need to overwrite this return address) now also 1821 overwrite the canary, which gets detected and the attack is then 1822 neutralized via a kernel panic. 1823 This feature requires gcc version 4.2 or above. 1824 1825config DEPRECATED_PARAM_STRUCT 1826 bool "Provide old way to pass kernel parameters" 1827 help 1828 This was deprecated in 2001 and announced to live on for 5 years. 1829 Some old boot loaders still use this way. 1830 1831endmenu 1832 1833menu "Boot options" 1834 1835config USE_OF 1836 bool "Flattened Device Tree support" 1837 select OF 1838 select OF_EARLY_FLATTREE 1839 select IRQ_DOMAIN 1840 help 1841 Include support for flattened device tree machine descriptions. 1842 1843# Compressed boot loader in ROM. Yes, we really want to ask about 1844# TEXT and BSS so we preserve their values in the config files. 1845config ZBOOT_ROM_TEXT 1846 hex "Compressed ROM boot loader base address" 1847 default "0" 1848 help 1849 The physical address at which the ROM-able zImage is to be 1850 placed in the target. Platforms which normally make use of 1851 ROM-able zImage formats normally set this to a suitable 1852 value in their defconfig file. 1853 1854 If ZBOOT_ROM is not enabled, this has no effect. 1855 1856config ZBOOT_ROM_BSS 1857 hex "Compressed ROM boot loader BSS address" 1858 default "0" 1859 help 1860 The base address of an area of read/write memory in the target 1861 for the ROM-able zImage which must be available while the 1862 decompressor is running. It must be large enough to hold the 1863 entire decompressed kernel plus an additional 128 KiB. 1864 Platforms which normally make use of ROM-able zImage formats 1865 normally set this to a suitable value in their defconfig file. 1866 1867 If ZBOOT_ROM is not enabled, this has no effect. 1868 1869config ZBOOT_ROM 1870 bool "Compressed boot loader in ROM/flash" 1871 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1872 help 1873 Say Y here if you intend to execute your compressed kernel image 1874 (zImage) directly from ROM or flash. If unsure, say N. 1875 1876choice 1877 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" 1878 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL 1879 default ZBOOT_ROM_NONE 1880 help 1881 Include experimental SD/MMC loading code in the ROM-able zImage. 1882 With this enabled it is possible to write the the ROM-able zImage 1883 kernel image to an MMC or SD card and boot the kernel straight 1884 from the reset vector. At reset the processor Mask ROM will load 1885 the first part of the the ROM-able zImage which in turn loads the 1886 rest the kernel image to RAM. 1887 1888config ZBOOT_ROM_NONE 1889 bool "No SD/MMC loader in zImage (EXPERIMENTAL)" 1890 help 1891 Do not load image from SD or MMC 1892 1893config ZBOOT_ROM_MMCIF 1894 bool "Include MMCIF loader in zImage (EXPERIMENTAL)" 1895 help 1896 Load image from MMCIF hardware block. 1897 1898config ZBOOT_ROM_SH_MOBILE_SDHI 1899 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" 1900 help 1901 Load image from SDHI hardware block 1902 1903endchoice 1904 1905config ARM_APPENDED_DTB 1906 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1907 depends on OF && !ZBOOT_ROM && EXPERIMENTAL 1908 help 1909 With this option, the boot code will look for a device tree binary 1910 (DTB) appended to zImage 1911 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1912 1913 This is meant as a backward compatibility convenience for those 1914 systems with a bootloader that can't be upgraded to accommodate 1915 the documented boot protocol using a device tree. 1916 1917 Beware that there is very little in terms of protection against 1918 this option being confused by leftover garbage in memory that might 1919 look like a DTB header after a reboot if no actual DTB is appended 1920 to zImage. Do not leave this option active in a production kernel 1921 if you don't intend to always append a DTB. Proper passing of the 1922 location into r2 of a bootloader provided DTB is always preferable 1923 to this option. 1924 1925config ARM_ATAG_DTB_COMPAT 1926 bool "Supplement the appended DTB with traditional ATAG information" 1927 depends on ARM_APPENDED_DTB 1928 help 1929 Some old bootloaders can't be updated to a DTB capable one, yet 1930 they provide ATAGs with memory configuration, the ramdisk address, 1931 the kernel cmdline string, etc. Such information is dynamically 1932 provided by the bootloader and can't always be stored in a static 1933 DTB. To allow a device tree enabled kernel to be used with such 1934 bootloaders, this option allows zImage to extract the information 1935 from the ATAG list and store it at run time into the appended DTB. 1936 1937config CMDLINE 1938 string "Default kernel command string" 1939 default "" 1940 help 1941 On some architectures (EBSA110 and CATS), there is currently no way 1942 for the boot loader to pass arguments to the kernel. For these 1943 architectures, you should supply some command-line options at build 1944 time by entering them here. As a minimum, you should specify the 1945 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1946 1947choice 1948 prompt "Kernel command line type" if CMDLINE != "" 1949 default CMDLINE_FROM_BOOTLOADER 1950 1951config CMDLINE_FROM_BOOTLOADER 1952 bool "Use bootloader kernel arguments if available" 1953 help 1954 Uses the command-line options passed by the boot loader. If 1955 the boot loader doesn't provide any, the default kernel command 1956 string provided in CMDLINE will be used. 1957 1958config CMDLINE_EXTEND 1959 bool "Extend bootloader kernel arguments" 1960 help 1961 The command-line arguments provided by the boot loader will be 1962 appended to the default kernel command string. 1963 1964config CMDLINE_FORCE 1965 bool "Always use the default kernel command string" 1966 help 1967 Always use the default kernel command string, even if the boot 1968 loader passes other arguments to the kernel. 1969 This is useful if you cannot or don't want to change the 1970 command-line options your boot loader passes to the kernel. 1971endchoice 1972 1973config XIP_KERNEL 1974 bool "Kernel Execute-In-Place from ROM" 1975 depends on !ZBOOT_ROM 1976 help 1977 Execute-In-Place allows the kernel to run from non-volatile storage 1978 directly addressable by the CPU, such as NOR flash. This saves RAM 1979 space since the text section of the kernel is not loaded from flash 1980 to RAM. Read-write sections, such as the data section and stack, 1981 are still copied to RAM. The XIP kernel is not compressed since 1982 it has to run directly from flash, so it will take more space to 1983 store it. The flash address used to link the kernel object files, 1984 and for storing it, is configuration dependent. Therefore, if you 1985 say Y here, you must know the proper physical address where to 1986 store the kernel image depending on your own flash memory usage. 1987 1988 Also note that the make target becomes "make xipImage" rather than 1989 "make zImage" or "make Image". The final kernel binary to put in 1990 ROM memory will be arch/arm/boot/xipImage. 1991 1992 If unsure, say N. 1993 1994config XIP_PHYS_ADDR 1995 hex "XIP Kernel Physical Location" 1996 depends on XIP_KERNEL 1997 default "0x00080000" 1998 help 1999 This is the physical address in your flash memory the kernel will 2000 be linked for and stored to. This address is dependent on your
2001 own flash usage. 2002 2003config KEXEC 2004 bool "Kexec system call (EXPERIMENTAL)" 2005 depends on EXPERIMENTAL 2006 help 2007 kexec is a system call that implements the ability to shutdown your 2008 current kernel, and to start another kernel. It is like a reboot 2009 but it is independent of the system firmware. And like a reboot 2010 you can start any kernel with it, not just Linux. 2011 2012 It is an ongoing process to be certain the hardware in a machine 2013 is properly shutdown, so do not be surprised if this code does not 2014 initially work for you. It may help to enable device hotplugging 2015 support. 2016 2017config ATAGS_PROC 2018 bool "Export atags in procfs" 2019 depends on KEXEC 2020 default y 2021 help 2022 Should the atags used to boot the kernel be exported in an "atags" 2023 file in procfs. Useful with kexec. 2024 2025config CRASH_DUMP 2026 bool "Build kdump crash kernel (EXPERIMENTAL)" 2027 depends on EXPERIMENTAL 2028 help 2029 Generate crash dump after being started by kexec. This should 2030 be normally only set in special crash dump kernels which are 2031 loaded in the main kernel with kexec-tools into a specially 2032 reserved region and then later executed after a crash by 2033 kdump/kexec. The crash dump kernel must be compiled to a 2034 memory address not used by the main kernel 2035 2036 For more details see Documentation/kdump/kdump.txt 2037 2038config AUTO_ZRELADDR 2039 bool "Auto calculation of the decompressed kernel image address" 2040 depends on !ZBOOT_ROM && !ARCH_U300 2041 help 2042 ZRELADDR is the physical address where the decompressed kernel 2043 image will be placed. If AUTO_ZRELADDR is selected, the address 2044 will be determined at run-time by masking the current IP with 2045 0xf8000000. This assumes the zImage being placed in the first 128MB 2046 from start of memory. 2047 2048endmenu 2049 2050menu "CPU Power Management" 2051 2052if ARCH_HAS_CPUFREQ 2053 2054source "drivers/cpufreq/Kconfig" 2055 2056config CPU_FREQ_IMX 2057 tristate "CPUfreq driver for i.MX CPUs" 2058 depends on ARCH_MXC && CPU_FREQ 2059 help 2060 This enables the CPUfreq driver for i.MX CPUs. 2061 2062config CPU_FREQ_SA1100 2063 bool 2064 2065config CPU_FREQ_SA1110 2066 bool 2067 2068config CPU_FREQ_INTEGRATOR 2069 tristate "CPUfreq driver for ARM Integrator CPUs" 2070 depends on ARCH_INTEGRATOR && CPU_FREQ 2071 default y 2072 help 2073 This enables the CPUfreq driver for ARM Integrator CPUs. 2074 2075 For details, take a look at <file:Documentation/cpu-freq>. 2076 2077 If in doubt, say Y. 2078 2079config CPU_FREQ_PXA 2080 bool 2081 depends on CPU_FREQ && ARCH_PXA && PXA25x 2082 default y 2083 select CPU_FREQ_TABLE 2084 select CPU_FREQ_DEFAULT_GOV_USERSPACE 2085 2086config CPU_FREQ_S3C 2087 bool 2088 help 2089 Internal configuration node for common cpufreq on Samsung SoC 2090 2091config CPU_FREQ_S3C24XX 2092 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" 2093 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL 2094 select CPU_FREQ_S3C 2095 help 2096 This enables the CPUfreq driver for the Samsung S3C24XX family 2097 of CPUs. 2098 2099 For details, take a look at <file:Documentation/cpu-freq>. 2100 2101 If in doubt, say N. 2102 2103config CPU_FREQ_S3C24XX_PLL 2104 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" 2105 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL 2106 help 2107 Compile in support for changing the PLL frequency from the 2108 S3C24XX series CPUfreq driver. The PLL takes time to settle 2109 after a frequency change, so by default it is not enabled. 2110 2111 This also means that the PLL tables for the selected CPU(s) will 2112 be built which may increase the size of the kernel image. 2113 2114config CPU_FREQ_S3C24XX_DEBUG 2115 bool "Debug CPUfreq Samsung driver core" 2116 depends on CPU_FREQ_S3C24XX 2117 help 2118 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core 2119 2120config CPU_FREQ_S3C24XX_IODEBUG 2121 bool "Debug CPUfreq Samsung driver IO timing" 2122 depends on CPU_FREQ_S3C24XX 2123 help 2124 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core 2125 2126config CPU_FREQ_S3C24XX_DEBUGFS 2127 bool "Export debugfs for CPUFreq" 2128 depends on CPU_FREQ_S3C24XX && DEBUG_FS 2129 help 2130 Export status information via debugfs. 2131 2132endif 2133 2134source "drivers/cpuidle/Kconfig" 2135 2136endmenu 2137 2138menu "Floating point emulation" 2139 2140comment "At least one emulation must be selected" 2141 2142config FPE_NWFPE 2143 bool "NWFPE math emulation" 2144 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2145 ---help--- 2146 Say Y to include the NWFPE floating point emulator in the kernel. 2147 This is necessary to run most binaries. Linux does not currently 2148 support floating point hardware so you need to say Y here even if 2149 your machine has an FPA or floating point co-processor podule. 2150 2151 You may say N here if you are going to load the Acorn FPEmulator 2152 early in the bootup. 2153 2154config FPE_NWFPE_XP 2155 bool "Support extended precision" 2156 depends on FPE_NWFPE 2157 help 2158 Say Y to include 80-bit support in the kernel floating-point 2159 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2160 Note that gcc does not generate 80-bit operations by default, 2161 so in most cases this option only enlarges the size of the 2162 floating point emulator without any good reason. 2163 2164 You almost surely want to say N here. 2165 2166config FPE_FASTFPE 2167 bool "FastFPE math emulation (EXPERIMENTAL)" 2168 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL 2169 ---help--- 2170 Say Y here to include the FAST floating point emulator in the kernel. 2171 This is an experimental much faster emulator which now also has full 2172 precision for the mantissa. It does not support any exceptions. 2173 It is very simple, and approximately 3-6 times faster than NWFPE. 2174 2175 It should be sufficient for most programs. It may be not suitable 2176 for scientific calculations, but you have to check this for yourself. 2177 If you do not feel you need a faster FP emulation you should better 2178 choose NWFPE. 2179 2180config VFP 2181 bool "VFP-format floating point maths" 2182 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2183 help 2184 Say Y to include VFP support code in the kernel. This is needed 2185 if your hardware includes a VFP unit. 2186 2187 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2188 release notes and additional status information. 2189 2190 Say N if your target does not have VFP hardware. 2191 2192config VFPv3 2193 bool 2194 depends on VFP 2195 default y if CPU_V7 2196 2197config NEON 2198 bool "Advanced SIMD (NEON) Extension support" 2199 depends on VFPv3 && CPU_V7 2200 help 2201 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2202 Extension. 2203 2204endmenu 2205 2206menu "Userspace binary formats" 2207 2208source "fs/Kconfig.binfmt" 2209 2210config ARTHUR 2211 tristate "RISC OS personality" 2212 depends on !AEABI 2213 help 2214 Say Y here to include the kernel code necessary if you want to run 2215 Acorn RISC OS/Arthur binaries under Linux. This code is still very 2216 experimental; if this sounds frightening, say N and sleep in peace. 2217 You can also say M here to compile this support as a module (which 2218 will be called arthur). 2219 2220endmenu 2221 2222menu "Power management options" 2223 2224source "kernel/power/Kconfig" 2225 2226config ARCH_SUSPEND_POSSIBLE 2227 depends on !ARCH_S5PC100 2228 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ 2229 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE 2230 def_bool y 2231 2232config ARM_CPU_SUSPEND 2233 def_bool PM_SLEEP 2234 2235endmenu 2236 2237source "net/Kconfig" 2238 2239source "drivers/Kconfig" 2240 2241source "fs/Kconfig" 2242 2243source "arch/arm/Kconfig.debug" 2244 2245source "security/Kconfig" 2246 2247source "crypto/Kconfig" 2248 2249source "lib/Kconfig" 2250