LXR linux-old/include/asm-sparc64/cache.h

   1/*
   2 * include/asm-sparc64/cache.h
   3 */
   4#ifndef __ARCH_SPARC64_CACHE_H
   5#define __ARCH_SPARC64_CACHE_H
   6
   7/* bytes per L1 cache line */
   8#define        L1_CACHE_BYTES           32 /* Two 16-byte sub-blocks per line. */
   9
  10#define        L1_CACHE_ALIGN(x)       (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
  11
  12#define        SMP_CACHE_BYTES_SHIFT    6
  13#define        SMP_CACHE_BYTES          (1 << SMP_CACHE_BYTES_SHIFT) /* L2 cache line size. */
  14
  15#ifdef MODULE
  16#define __cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
  17#else
  18#define __cacheline_aligned                                     \
  19  __attribute__((__aligned__(SMP_CACHE_BYTES),                  \
  20                 __section__(".data.cacheline_aligned")))
  21#endif
  22
  23#endif
  24