1/* 2 * AMD Alchemy Semi PB1550 Referrence Board 3 * Board Registers defines. 4 * 5 * Copyright 2004 Embedded Edge LLC. 6 * 7 * ######################################################################## 8 * 9 * This program is free software; you can distribute it and/or modify it 10 * under the terms of the GNU General Public License (Version 2) as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, write to the Free Software Foundation, Inc., 20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 21 * 22 * ######################################################################## 23 * 24 * 25 */ 26#ifndef __ASM_PB1550_H 27#define __ASM_PB1550_H 28 29#include <linux/types.h> 30 31#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX 32#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX 33#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX 34#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX 35 36#define SPI_PSC_BASE PSC0_BASE_ADDR 37#define AC97_PSC_BASE PSC1_BASE_ADDR 38#define SMBUS_PSC_BASE PSC2_BASE_ADDR 39#define I2S_PSC_BASE PSC3_BASE_ADDR 40 41#define BCSR_PHYS_ADDR 0xAF000000 42 43typedef volatile struct 44{ 45 /*00*/ u16 whoami; 46 u16 reserved0; 47 /*04*/ u16 status; 48 u16 reserved1; 49 /*08*/ u16 switches; 50 u16 reserved2; 51 /*0C*/ u16 resets; 52 u16 reserved3; 53 /*10*/ u16 pcmcia; 54 u16 reserved4; 55 /*14*/ u16 pci; 56 u16 reserved5; 57 /*18*/ u16 leds; 58 u16 reserved6; 59 /*1C*/ u16 system; 60 u16 reserved7; 61 62} BCSR; 63 64static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR; 65 66/* 67 * Register bit definitions for the BCSRs 68 */ 69#define BCSR_WHOAMI_DCID 0x000F 70#define BCSR_WHOAMI_CPLD 0x00F0 71#define BCSR_WHOAMI_BOARD 0x0F00 72 73#define BCSR_STATUS_PCMCIA0VS 0x0003 74#define BCSR_STATUS_PCMCIA1VS 0x000C 75#define BCSR_STATUS_PCMCIA0FI 0x0010 76#define BCSR_STATUS_PCMCIA1FI 0x0020 77#define BCSR_STATUS_SWAPBOOT 0x0040 78#define BCSR_STATUS_SRAMWIDTH 0x0080 79#define BCSR_STATUS_FLASHBUSY 0x0100 80#define BCSR_STATUS_ROMBUSY 0x0200 81#define BCSR_STATUS_USBOTGID 0x0800 82#define BCSR_STATUS_U0RXD 0x1000 83#define BCSR_STATUS_U1RXD 0x2000 84#define BCSR_STATUS_U3RXD 0x8000 85 86#define BCSR_SWITCHES_OCTAL 0x00FF 87#define BCSR_SWITCHES_DIP_1 0x0080 88#define BCSR_SWITCHES_DIP_2 0x0040 89#define BCSR_SWITCHES_DIP_3 0x0020 90#define BCSR_SWITCHES_DIP_4 0x0010 91#define BCSR_SWITCHES_DIP_5 0x0008 92#define BCSR_SWITCHES_DIP_6 0x0004 93#define BCSR_SWITCHES_DIP_7 0x0002 94#define BCSR_SWITCHES_DIP_8 0x0001 95#define BCSR_SWITCHES_ROTARY 0x0F00 96 97#define BCSR_RESETS_PHY0 0x0001 98#define BCSR_RESETS_PHY1 0x0002 99#define BCSR_RESETS_DC 0x0004 100#define BCSR_RESETS_WSC 0x2000 101#define BCSR_RESETS_SPISEL 0x4000 102#define BCSR_RESETS_DMAREQ 0x8000 103 104#define BCSR_PCMCIA_PC0VPP 0x0003 105#define BCSR_PCMCIA_PC0VCC 0x000C 106#define BCSR_PCMCIA_PC0DRVEN 0x0010 107#define BCSR_PCMCIA_PC0RST 0x0080 108#define BCSR_PCMCIA_PC1VPP 0x0300 109#define BCSR_PCMCIA_PC1VCC 0x0C00 110#define BCSR_PCMCIA_PC1DRVEN 0x1000 111#define BCSR_PCMCIA_PC1RST 0x8000 112 113#define BCSR_PCI_M66EN 0x0001 114#define BCSR_PCI_M33 0x0100 115#define BCSR_PCI_EXTERNARB 0x0200 116#define BCSR_PCI_GPIO200RST 0x0400 117#define BCSR_PCI_CLKOUT 0x0800 118#define BCSR_PCI_CFGHOST 0x1000 119 120#define BCSR_LEDS_DECIMALS 0x00FF 121#define BCSR_LEDS_LED0 0x0100 122#define BCSR_LEDS_LED1 0x0200 123#define BCSR_LEDS_LED2 0x0400 124#define BCSR_LEDS_LED3 0x0800 125 126#define BCSR_SYSTEM_VDDI 0x001F 127#define BCSR_SYSTEM_POWEROFF 0x4000 128#define BCSR_SYSTEM_RESET 0x8000 129 130#define PCMCIA_MAX_SOCK 1 131#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) 132 133/* VPP/VCC */ 134#define SET_VCC_VPP(VCC, VPP, SLOT)\ 135 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) 136 137#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER) 138#define PB1550_BOTH_BANKS 139#elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER) 140#define PB1550_BOOT_ONLY 141#elif !defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER) 142#define PB1550_USER_ONLY 143#endif 144 145#define NAND_PHYS_ADDR 0x20000000 146/* Timing values as described in databook, * ns value stripped of 147 * lower 2 bits. 148 * These defines are here rather than an SOC1550 generic file because 149 * the parts chosen on another board may be different and may require 150 * different timings. 151 */ 152#define NAND_T_H (18 >> 2) 153#define NAND_T_PUL (30 >> 2) 154#define NAND_T_SU (30 >> 2) 155#define NAND_T_WH (30 >> 2) 156 157/* Bitfield shift amounts */ 158#define NAND_T_H_SHIFT 0 159#define NAND_T_PUL_SHIFT 4 160#define NAND_T_SU_SHIFT 8 161#define NAND_T_WH_SHIFT 12 162 163#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ 164 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ 165 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ 166 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) 167 168#endif /* __ASM_PB1550_H */ 169