LXR linux-old/include/asm-alpha/core

   1#ifndef __ALPHA_TSUNAMI__H__
   2#define __ALPHA_TSUNAMI__H__
   3
   4#include <linux/types.h>
   5#include <asm/compiler.h>
   6
   7/*
   8 * TSUNAMI/TYPHOON are the internal names for the core logic chipset which
   9 * provides memory controller and PCI access for the 21264 based systems.
  10 *
  11 * This file is based on:
  12 *
  13 * Tsunami System Programmers Manual
  14 * Preliminary, Chapters 2-5
  15 *
  16 */
  17
  18/* XXX: Do we need to conditionalize on this?  */
  19#ifdef USE_48_BIT_KSEG
  20#define TS_BIAS 0x80000000000UL
  21#else
  22#define TS_BIAS 0x10000000000UL
  23#endif
  24
  25/*
  26 * CChip, DChip, and PChip registers
  27 */
  28
  29typedef struct {
  30        volatile unsigned long csr __attribute__((aligned(64)));
  31} tsunami_64;
  32
  33typedef struct {
  34        tsunami_64      csc;
  35        tsunami_64      mtr;
  36        tsunami_64      misc;
  37        tsunami_64      mpd;
  38        tsunami_64      aar0;
  39        tsunami_64      aar1;
  40        tsunami_64      aar2;
  41        tsunami_64      aar3;
  42        tsunami_64      dim0;
  43        tsunami_64      dim1;
  44        tsunami_64      dir0;
  45        tsunami_64      dir1;
  46        tsunami_64      drir;
  47        tsunami_64      prben;
  48        tsunami_64      iic;    /* a.k.a. iic0 */
  49        tsunami_64      wdr;    /* a.k.a. iic1 */
  50        tsunami_64      mpr0;
  51        tsunami_64      mpr1;
  52        tsunami_64      mpr2;
  53        tsunami_64      mpr3;
  54        tsunami_64      mctl;
  55        tsunami_64      __pad1;
  56        tsunami_64      ttr;
  57        tsunami_64      tdr;
  58        tsunami_64      dim2;
  59        tsunami_64      dim3;
  60        tsunami_64      dir2;
  61        tsunami_64      dir3;
  62        tsunami_64      iic2;
  63        tsunami_64      iic3;
  64} tsunami_cchip;
  65
  66typedef struct {
  67        tsunami_64      dsc;
  68        tsunami_64      str;
  69        tsunami_64      drev;
  70} tsunami_dchip;
  71
  72typedef struct {
  73        tsunami_64      wsba[4];
  74        tsunami_64      wsm[4];
  75        tsunami_64      tba[4];
  76        tsunami_64      pctl;
  77        tsunami_64      plat;
  78        tsunami_64      reserved;
  79        tsunami_64      perror;
  80        tsunami_64      perrmask;
  81        tsunami_64      perrset;
  82        tsunami_64      tlbiv;
  83        tsunami_64      tlbia;
  84        tsunami_64      pmonctl;
  85        tsunami_64      pmoncnt;
  86} tsunami_pchip;
  87
  88#define TSUNAMI_cchip  ((tsunami_cchip *)(IDENT_ADDR+TS_BIAS+0x1A0000000UL))
  89#define TSUNAMI_dchip  ((tsunami_dchip *)(IDENT_ADDR+TS_BIAS+0x1B0000800UL))
  90#define TSUNAMI_pchip0 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x180000000UL))
  91#define TSUNAMI_pchip1 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x380000000UL))
  92extern int TSUNAMI_bootcpu;
  93
  94/*
  95 * TSUNAMI Pchip Error register.
  96 */
  97
  98#define perror_m_lost 0x1
  99#define perror_m_serr 0x2
 100#define perror_m_perr 0x4
 101#define perror_m_dcrto 0x8
 102#define perror_m_sge 0x10
 103#define perror_m_ape 0x20
 104#define perror_m_ta 0x40
 105#define perror_m_rdpe 0x80
 106#define perror_m_nds 0x100
 107#define perror_m_rto 0x200
 108#define perror_m_uecc 0x400
 109#define perror_m_cre 0x800
 110#define perror_m_addrl 0xFFFFFFFF0000UL
 111#define perror_m_addrh 0x7000000000000UL
 112#define perror_m_cmd 0xF0000000000000UL
 113#define perror_m_syn 0xFF00000000000000UL
 114union TPchipPERROR {   
 115        struct  {
 116                unsigned int perror_v_lost : 1;
 117                unsigned perror_v_serr : 1;
 118                unsigned perror_v_perr : 1;
 119                unsigned perror_v_dcrto : 1;
 120                unsigned perror_v_sge : 1;
 121                unsigned perror_v_ape : 1;
 122                unsigned perror_v_ta : 1;
 123                unsigned perror_v_rdpe : 1;
 124                unsigned perror_v_nds : 1;
 125                unsigned perror_v_rto : 1;
 126                unsigned perror_v_uecc : 1;
 127                unsigned perror_v_cre : 1;                 
 128                unsigned perror_v_rsvd1 : 4;
 129                unsigned perror_v_addrl : 32;
 130                unsigned perror_v_addrh : 3;
 131                unsigned perror_v_rsvd2 : 1;
 132                unsigned perror_v_cmd : 4;
 133                unsigned perror_v_syn : 8;
 134        } perror_r_bits;
 135        int perror_q_whole [2];
 136};                       
 137
 138/*
 139 * TSUNAMI Pchip Window Space Base Address register.
 140 */
 141#define wsba_m_ena 0x1                
 142#define wsba_m_sg 0x2
 143#define wsba_m_ptp 0x4
 144#define wsba_m_addr 0xFFF00000  
 145#define wmask_k_sz1gb 0x3FF00000                   
 146union TPchipWSBA {
 147        struct  {
 148                unsigned wsba_v_ena : 1;
 149                unsigned wsba_v_sg : 1;
 150                unsigned wsba_v_ptp : 1;
 151                unsigned wsba_v_rsvd1 : 17;
 152                unsigned wsba_v_addr : 12;
 153                unsigned wsba_v_rsvd2 : 32;
 154        } wsba_r_bits;
 155        int wsba_q_whole [2];
 156};
 157
 158/*
 159 * TSUNAMI Pchip Control Register
 160 */
 161#define pctl_m_fdsc 0x1
 162#define pctl_m_fbtb 0x2
 163#define pctl_m_thdis 0x4
 164#define pctl_m_chaindis 0x8
 165#define pctl_m_tgtlat 0x10
 166#define pctl_m_hole 0x20
 167#define pctl_m_mwin 0x40
 168#define pctl_m_arbena 0x80
 169#define pctl_m_prigrp 0x7F00
 170#define pctl_m_ppri 0x8000
 171#define pctl_m_rsvd1 0x30000
 172#define pctl_m_eccen 0x40000
 173#define pctl_m_padm 0x80000
 174#define pctl_m_cdqmax 0xF00000
 175#define pctl_m_rev 0xFF000000
 176#define pctl_m_crqmax 0xF00000000UL
 177#define pctl_m_ptpmax 0xF000000000UL
 178#define pctl_m_pclkx 0x30000000000UL
 179#define pctl_m_fdsdis 0x40000000000UL
 180#define pctl_m_fdwdis 0x80000000000UL
 181#define pctl_m_ptevrfy 0x100000000000UL
 182#define pctl_m_rpp 0x200000000000UL
 183#define pctl_m_pid 0xC00000000000UL
 184#define pctl_m_rsvd2 0xFFFF000000000000UL
 185
 186union TPchipPCTL {
 187        struct {
 188                unsigned pctl_v_fdsc : 1;
 189                unsigned pctl_v_fbtb : 1;
 190                unsigned pctl_v_thdis : 1;
 191                unsigned pctl_v_chaindis : 1;
 192                unsigned pctl_v_tgtlat : 1;
 193                unsigned pctl_v_hole : 1;
 194                unsigned pctl_v_mwin : 1;
 195                unsigned pctl_v_arbena : 1;
 196                unsigned pctl_v_prigrp : 7;
 197                unsigned pctl_v_ppri : 1;
 198                unsigned pctl_v_rsvd1 : 2;
 199                unsigned pctl_v_eccen : 1;
 200                unsigned pctl_v_padm : 1;
 201                unsigned pctl_v_cdqmax : 4;
 202                unsigned pctl_v_rev : 8;
 203                unsigned pctl_v_crqmax : 4;
 204                unsigned pctl_v_ptpmax : 4;
 205                unsigned pctl_v_pclkx : 2;
 206                unsigned pctl_v_fdsdis : 1;
 207                unsigned pctl_v_fdwdis : 1;
 208                unsigned pctl_v_ptevrfy : 1;
 209                unsigned pctl_v_rpp : 1;
 210                unsigned pctl_v_pid : 2;
 211                unsigned pctl_v_rsvd2 : 16;
 212        } pctl_r_bits;
 213        int pctl_q_whole [2];
 214};
 215
 216/*
 217 * TSUNAMI Pchip Error Mask Register.
 218 */
 219#define perrmask_m_lost 0x1
 220#define perrmask_m_serr 0x2
 221#define perrmask_m_perr 0x4
 222#define perrmask_m_dcrto 0x8
 223#define perrmask_m_sge 0x10
 224#define perrmask_m_ape 0x20
 225#define perrmask_m_ta 0x40
 226#define perrmask_m_rdpe 0x80
 227#define perrmask_m_nds 0x100
 228#define perrmask_m_rto 0x200
 229#define perrmask_m_uecc 0x400
 230#define perrmask_m_cre 0x800
 231#define perrmask_m_rsvd 0xFFFFFFFFFFFFF000UL
 232union TPchipPERRMASK {   
 233        struct  {
 234                unsigned int perrmask_v_lost : 1;
 235                unsigned perrmask_v_serr : 1;
 236                unsigned perrmask_v_perr : 1;
 237                unsigned perrmask_v_dcrto : 1;
 238                unsigned perrmask_v_sge : 1;
 239                unsigned perrmask_v_ape : 1;
 240                unsigned perrmask_v_ta : 1;
 241                unsigned perrmask_v_rdpe : 1;
 242                unsigned perrmask_v_nds : 1;
 243                unsigned perrmask_v_rto : 1;
 244                unsigned perrmask_v_uecc : 1;
 245                unsigned perrmask_v_cre : 1;                 
 246                unsigned perrmask_v_rsvd1 : 20;
 247                unsigned perrmask_v_rsvd2 : 32;
 248        } perrmask_r_bits;
 249        int perrmask_q_whole [2];
 250};                       
 251
 252/*
 253 * Memory spaces:
 254 */
 255#define TSUNAMI_HOSE(h)         (((unsigned long)(h)) << 33)
 256#define TSUNAMI_BASE            (IDENT_ADDR + TS_BIAS)
 257
 258#define TSUNAMI_MEM(h)          (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x000000000UL)
 259#define _TSUNAMI_IACK_SC(h)     (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1F8000000UL)
 260#define TSUNAMI_IO(h)           (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1FC000000UL)
 261#define TSUNAMI_CONF(h)         (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1FE000000UL)
 262
 263#define TSUNAMI_IACK_SC         _TSUNAMI_IACK_SC(0) /* hack! */
 264
 265
 266/* 
 267 * The canonical non-remaped I/O and MEM addresses have these values
 268 * subtracted out.  This is arranged so that folks manipulating ISA
 269 * devices can use their familiar numbers and have them map to bus 0.
 270 */
 271
 272#define TSUNAMI_IO_BIAS          TSUNAMI_IO(0)
 273#define TSUNAMI_MEM_BIAS         TSUNAMI_MEM(0)
 274
 275/* The IO address space is larger than 0xffff */
 276#define TSUNAMI_IO_SPACE        (TSUNAMI_CONF(0) - TSUNAMI_IO(0))
 277
 278/* Offset between ram physical addresses and pci64 DAC bus addresses.  */
 279#define TSUNAMI_DAC_OFFSET      (1UL << 40)
 280
 281/*
 282 * Data structure for handling TSUNAMI machine checks:
 283 */
 284struct el_TSUNAMI_sysdata_mcheck {
 285};
 286
 287
 288#ifdef __KERNEL__
 289
 290#ifndef __EXTERN_INLINE
 291#define __EXTERN_INLINE static inline
 292#define __IO_EXTERN_INLINE
 293#endif
 294
 295/*
 296 * I/O functions:
 297 *
 298 * TSUNAMI, the 21??? PCI/memory support chipset for the EV6 (21264)
 299 * can only use linear accesses to get at PCI memory and I/O spaces.
 300 */
 301
 302#define vucp    volatile unsigned char *
 303#define vusp    volatile unsigned short *
 304#define vuip    volatile unsigned int *
 305#define vulp    volatile unsigned long *
 306
 307__EXTERN_INLINE u8 tsunami_inb(unsigned long addr)
 308{
 309        /* ??? I wish I could get rid of this.  But there's no ioremap
 310           equivalent for I/O space.  PCI I/O can be forced into the
 311           correct hose's I/O region, but that doesn't take care of
 312           legacy ISA crap.  */
 313
 314        addr += TSUNAMI_IO_BIAS;
 315        return __kernel_ldbu(*(vucp)addr);
 316}
 317
 318__EXTERN_INLINE void tsunami_outb(u8 b, unsigned long addr)
 319{
 320        addr += TSUNAMI_IO_BIAS;
 321        __kernel_stb(b, *(vucp)addr);
 322        mb();
 323}
 324
 325__EXTERN_INLINE u16 tsunami_inw(unsigned long addr)
 326{
 327        addr += TSUNAMI_IO_BIAS;
 328        return __kernel_ldwu(*(vusp)addr);
 329}
 330
 331__EXTERN_INLINE void tsunami_outw(u16 b, unsigned long addr)
 332{
 333        addr += TSUNAMI_IO_BIAS;
 334        __kernel_stw(b, *(vusp)addr);
 335        mb();
 336}
 337
 338__EXTERN_INLINE u32 tsunami_inl(unsigned long addr)
 339{
 340        addr += TSUNAMI_IO_BIAS;
 341        return *(vuip)addr;
 342}
 343
 344__EXTERN_INLINE void tsunami_outl(u32 b, unsigned long addr)
 345{
 346        addr += TSUNAMI_IO_BIAS;
 347        *(vuip)addr = b;
 348        mb();
 349}
 350
 351/*
 352 * Memory functions.  all accesses are done through linear space.
 353 */
 354
 355__EXTERN_INLINE unsigned long tsunami_ioremap(unsigned long addr, 
 356                                              unsigned long size
 357                                              __attribute__((unused)))
 358{
 359        return addr + TSUNAMI_MEM_BIAS;
 360}
 361
 362__EXTERN_INLINE void tsunami_iounmap(unsigned long addr)
 363{
 364        return;
 365}
 366
 367__EXTERN_INLINE int tsunami_is_ioaddr(unsigned long addr)
 368{
 369        return addr >= TSUNAMI_BASE;
 370}
 371
 372__EXTERN_INLINE u8 tsunami_readb(unsigned long addr)
 373{
 374        return __kernel_ldbu(*(vucp)addr);
 375}
 376
 377__EXTERN_INLINE u16 tsunami_readw(unsigned long addr)
 378{
 379        return __kernel_ldwu(*(vusp)addr);
 380}
 381
 382__EXTERN_INLINE u32 tsunami_readl(unsigned long addr)
 383{
 384        return *(vuip)addr;
 385}
 386
 387__EXTERN_INLINE u64 tsunami_readq(unsigned long addr)
 388{
 389        return *(vulp)addr;
 390}
 391
 392__EXTERN_INLINE void tsunami_writeb(u8 b, unsigned long addr)
 393{
 394        __kernel_stb(b, *(vucp)addr);
 395}
 396
 397__EXTERN_INLINE void tsunami_writew(u16 b, unsigned long addr)
 398{
 399        __kernel_stw(b, *(vusp)addr);
 400}
 401
 402__EXTERN_INLINE void tsunami_writel(u32 b, unsigned long addr)
 403{
 404        *(vuip)addr = b;
 405}
 406
 407__EXTERN_INLINE void tsunami_writeq(u64 b, unsigned long addr)
 408{
 409        *(vulp)addr = b;
 410}
 411
 412#undef vucp
 413#undef vusp
 414#undef vuip
 415#undef vulp
 416
 417#ifdef __WANT_IO_DEF
 418
 419#define __inb(p)                tsunami_inb((unsigned long)(p))
 420#define __inw(p)                tsunami_inw((unsigned long)(p))
 421#define __inl(p)                tsunami_inl((unsigned long)(p))
 422#define __outb(x,p)             tsunami_outb((x),(unsigned long)(p))
 423#define __outw(x,p)             tsunami_outw((x),(unsigned long)(p))
 424#define __outl(x,p)             tsunami_outl((x),(unsigned long)(p))
 425#define __readb(a)              tsunami_readb((unsigned long)(a))
 426#define __readw(a)              tsunami_readw((unsigned long)(a))
 427#define __readl(a)              tsunami_readl((unsigned long)(a))
 428#define __readq(a)              tsunami_readq((unsigned long)(a))
 429#define __writeb(x,a)           tsunami_writeb((x),(unsigned long)(a))
 430#define __writew(x,a)           tsunami_writew((x),(unsigned long)(a))
 431#define __writel(x,a)           tsunami_writel((x),(unsigned long)(a))
 432#define __writeq(x,a)           tsunami_writeq((x),(unsigned long)(a))
 433#define __ioremap(a,s)          tsunami_ioremap((unsigned long)(a),(s))
 434#define __iounmap(a)            tsunami_iounmap((unsigned long)(a))
 435#define __is_ioaddr(a)          tsunami_is_ioaddr((unsigned long)(a))
 436
 437#define inb(p)                  __inb(p)
 438#define inw(p)                  __inw(p)
 439#define inl(p)                  __inl(p)
 440#define outb(x,p)               __outb((x),(p))
 441#define outw(x,p)               __outw((x),(p))
 442#define outl(x,p)               __outl((x),(p))
 443#define __raw_readb(a)          __readb(a)
 444#define __raw_readw(a)          __readw(a)
 445#define __raw_readl(a)          __readl(a)
 446#define __raw_readq(a)          __readq(a)
 447#define __raw_writeb(v,a)       __writeb((v),(a))
 448#define __raw_writew(v,a)       __writew((v),(a))
 449#define __raw_writel(v,a)       __writel((v),(a))
 450#define __raw_writeq(v,a)       __writeq((v),(a))
 451
 452#endif /* __WANT_IO_DEF */
 453
 454#ifdef __IO_EXTERN_INLINE
 455#undef __EXTERN_INLINE
 456#undef __IO_EXTERN_INLINE
 457#endif
 458
 459#endif /* __KERNEL__ */
 460
 461#endif /* __ALPHA_TSUNAMI__H__ */
 462