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44#include <linux/version.h>
45#include <linux/module.h>
46#include <linux/string.h>
47#include <linux/ioport.h>
48#include <linux/sched.h>
49#include <linux/delay.h>
50#include <linux/sound.h>
51#include <linux/slab.h>
52#include <linux/soundcard.h>
53#include <linux/init.h>
54#include <linux/poll.h>
55#include <linux/pci.h>
56#include <linux/bitops.h>
57#include <linux/proc_fs.h>
58#include <linux/spinlock.h>
59#include <linux/smp_lock.h>
60#include <linux/wrapper.h>
61#include <asm/io.h>
62#include <asm/uaccess.h>
63#include <asm/hardirq.h>
64#include <asm/au1000.h>
65#include <asm/pb1550.h>
66#include <asm/au1xxx_psc.h>
67#include <asm/au1xxx_dbdma.h>
68
69#undef OSS_DOCUMENTED_MIXER_SEMANTICS
70
71#define AU1550_MODULE_NAME "Au1550 i2s audio"
72#define PFX AU1550_MODULE_NAME
73
74
75
76
77
78
79
80#define TRY_441KHz
81
82#ifdef TRY_441KHz
83#define SAMP_RATE 44100
84#else
85#define SAMP_RATE 48000
86#endif
87
88
89
90
91
92#define NUM_DBDMA_DESCRIPTORS 4
93
94#define err(format, arg...) printk(KERN_ERR PFX ": " format "\n" , ## arg)
95#define info(format, arg...) printk(KERN_INFO PFX ": " format "\n" , ## arg)
96
97
98
99
100
101static int vra = 0;
102MODULE_PARM(vra, "i");
103MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it");
104
105static struct au1550_state {
106
107 int dev_audio;
108
109 spinlock_t lock;
110 struct semaphore open_sem;
111 struct semaphore sem;
112 mode_t open_mode;
113 wait_queue_head_t open_wait;
114 int no_vra;
115 volatile psc_i2s_t *psc_addr;
116
117 struct dmabuf {
118 u32 dmanr;
119 unsigned sample_rate;
120 unsigned src_factor;
121 unsigned sample_size;
122 int num_channels;
123 int dma_bytes_per_sample;
124 int user_bytes_per_sample;
125 int cnt_factor;
126
127 void *rawbuf;
128 unsigned buforder;
129 unsigned numfrag;
130 unsigned fragshift;
131 void *nextIn;
132 void *nextOut;
133 int count;
134 unsigned total_bytes;
135 unsigned error;
136 wait_queue_head_t wait;
137
138
139 unsigned fragsize;
140 unsigned dma_fragsize;
141 unsigned dmasize;
142 unsigned dma_qcount;
143
144
145 unsigned mapped:1;
146 unsigned ready:1;
147 unsigned stopped:1;
148 unsigned ossfragshift;
149 int ossmaxfrags;
150 unsigned subdivision;
151 } dma_dac, dma_adc;
152} au1550_state;
153
154static unsigned
155ld2(unsigned int x)
156{
157 unsigned r = 0;
158
159 if (x >= 0x10000) {
160 x >>= 16;
161 r += 16;
162 }
163 if (x >= 0x100) {
164 x >>= 8;
165 r += 8;
166 }
167 if (x >= 0x10) {
168 x >>= 4;
169 r += 4;
170 }
171 if (x >= 4) {
172 x >>= 2;
173 r += 2;
174 }
175 if (x >= 2)
176 r++;
177 return r;
178}
179
180static void
181au1550_delay(int msec)
182{
183 unsigned long tmo;
184 signed long tmo2;
185
186 if (in_interrupt())
187 return;
188
189 tmo = jiffies + (msec * HZ) / 1000;
190 for (;;) {
191 tmo2 = tmo - jiffies;
192 if (tmo2 <= 0)
193 break;
194 schedule_timeout(tmo2);
195 }
196}
197
198
199
200
201#if 0
202static u8
203rdcodec(u8 addr)
204{
205 return 0 ;
206}
207#endif
208
209
210static void
211wrcodec(u8 ctlreg, u8 val)
212{
213 int rcnt;
214 extern int pb1550_wm_codec_write(u8 addr, u8 reg, u8 val);
215
216
217
218
219
220
221 rcnt = 0;
222 while ((pb1550_wm_codec_write((0x36 >> 1), ctlreg, val) != 1)
223 && (rcnt < 50)) {
224 rcnt++;
225#if 0
226 printk("Codec write retry %02x %02x\n", ctlreg, val);
227#endif
228 }
229}
230
231void
232codec_init(void)
233{
234 wrcodec(0x1e, 0x00);
235 au1550_delay(200);
236 wrcodec(0x0c, 0x00);
237 au1550_delay(10);
238 wrcodec(0x12, 0x00);
239 au1550_delay(10);
240 wrcodec(0x08, 0x10);
241 au1550_delay(10);
242 wrcodec(0x0a, 0x00);
243 au1550_delay(10);
244 wrcodec(0x05, 0x70);
245 au1550_delay(10);
246 wrcodec(0x0e, 0x02);
247 au1550_delay(10);
248 wrcodec(0x10, 0x01);
249 au1550_delay(10);
250 wrcodec(0x12, 0x01);
251 au1550_delay(10);
252}
253
254
255static void
256set_adc_rate(struct au1550_state *s, unsigned rate)
257{
258 struct dmabuf *adc = &s->dma_adc;
259 struct dmabuf *dac = &s->dma_dac;
260
261 if (s->no_vra) {
262
263
264 adc->src_factor = (((SAMP_RATE*2) / rate) + 1) >> 1;
265 adc->sample_rate = SAMP_RATE / adc->src_factor;
266 return;
267 }
268
269 adc->src_factor = 1;
270
271
272#if 0
273 rate = rate > SAMP_RATE ? SAMP_RATE : rate;
274
275 wrcodec(0, 0);
276
277 adc->sample_rate = rate;
278 dac->sample_rate = rate;
279#endif
280}
281
282
283static void
284set_dac_rate(struct au1550_state *s, unsigned rate)
285{
286 struct dmabuf *dac = &s->dma_dac;
287 struct dmabuf *adc = &s->dma_adc;
288
289 if (s->no_vra) {
290
291
292 dac->src_factor = (((SAMP_RATE*2) / rate) + 1) >> 1;
293 dac->sample_rate = SAMP_RATE / dac->src_factor;
294 return;
295 }
296
297 dac->src_factor = 1;
298
299#if 0
300 rate = rate > SAMP_RATE ? SAMP_RATE : rate;
301
302 wrcodec(0, 0);
303
304 adc->sample_rate = rate;
305 dac->sample_rate = rate;
306#endif
307}
308
309static void
310stop_dac(struct au1550_state *s)
311{
312 struct dmabuf *db = &s->dma_dac;
313 unsigned long flags;
314 uint stat;
315 volatile psc_i2s_t *ip;
316
317 if (db->stopped)
318 return;
319
320 ip = s->psc_addr;
321 spin_lock_irqsave(&s->lock, flags);
322
323 ip->psc_i2spcr = PSC_I2SPCR_TP;
324 au_sync();
325
326
327
328 do {
329 stat = ip->psc_i2sstat;
330 au_sync();
331 } while ((stat & PSC_I2SSTAT_TB) != 0);
332
333 au1xxx_dbdma_reset(db->dmanr);
334
335 db->stopped = 1;
336
337 spin_unlock_irqrestore(&s->lock, flags);
338}
339
340static void
341stop_adc(struct au1550_state *s)
342{
343 struct dmabuf *db = &s->dma_adc;
344 unsigned long flags;
345 uint stat;
346 volatile psc_i2s_t *ip;
347
348 if (db->stopped)
349 return;
350
351 ip = s->psc_addr;
352 spin_lock_irqsave(&s->lock, flags);
353
354 ip->psc_i2spcr = PSC_I2SPCR_RP;
355 au_sync();
356
357
358
359 do {
360 stat = ip->psc_i2sstat;
361 au_sync();
362 } while ((stat & PSC_I2SSTAT_RB) != 0);
363
364 au1xxx_dbdma_reset(db->dmanr);
365
366 db->stopped = 1;
367
368 spin_unlock_irqrestore(&s->lock, flags);
369}
370
371
372static void
373set_xmit_slots(int num_channels)
374{
375
376
377
378}
379
380static void
381set_recv_slots(int num_channels)
382{
383
384
385
386}
387
388static void
389start_dac(struct au1550_state *s)
390{
391 struct dmabuf *db = &s->dma_dac;
392 unsigned long flags;
393 volatile psc_i2s_t *ip;
394
395 if (!db->stopped)
396 return;
397
398 spin_lock_irqsave(&s->lock, flags);
399
400 ip = s->psc_addr;
401 set_xmit_slots(db->num_channels);
402 ip->psc_i2spcr = PSC_I2SPCR_TC;
403 au_sync();
404 ip->psc_i2spcr = PSC_I2SPCR_TS;
405 au_sync();
406
407 au1xxx_dbdma_start(db->dmanr);
408
409 db->stopped = 0;
410
411 spin_unlock_irqrestore(&s->lock, flags);
412}
413
414static void
415start_adc(struct au1550_state *s)
416{
417 struct dmabuf *db = &s->dma_adc;
418 int i;
419 volatile psc_i2s_t *ip;
420
421 if (!db->stopped)
422 return;
423
424
425
426 for (i=0; i<2; i++) {
427 au1xxx_dbdma_put_dest(db->dmanr, db->nextIn, db->dma_fragsize);
428
429 db->nextIn += db->dma_fragsize;
430 if (db->nextIn >= db->rawbuf + db->dmasize)
431 db->nextIn -= db->dmasize;
432 }
433
434 ip = s->psc_addr;
435 set_recv_slots(db->num_channels);
436 au1xxx_dbdma_start(db->dmanr);
437 ip->psc_i2spcr = PSC_I2SPCR_RC;
438 au_sync();
439 ip->psc_i2spcr = PSC_I2SPCR_RS;
440 au_sync();
441
442 db->stopped = 0;
443}
444
445static int
446prog_dmabuf(struct au1550_state *s, struct dmabuf *db)
447{
448 unsigned user_bytes_per_sec;
449 unsigned bufs;
450 unsigned rate = db->sample_rate;
451
452 if (!db->rawbuf) {
453 db->ready = db->mapped = 0;
454 db->buforder = 5;
455 db->rawbuf = kmalloc((PAGE_SIZE << db->buforder), GFP_KERNEL);
456 if (!db->rawbuf)
457 return -ENOMEM;
458 }
459
460 db->cnt_factor = 1;
461 if (db->sample_size == 8)
462 db->cnt_factor *= 2;
463 if (db->num_channels == 1)
464 db->cnt_factor *= 2;
465 db->cnt_factor *= db->src_factor;
466
467 db->count = 0;
468 db->dma_qcount = 0;
469 db->nextIn = db->nextOut = db->rawbuf;
470
471 db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
472 db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
473 2 : db->num_channels);
474
475 user_bytes_per_sec = rate * db->user_bytes_per_sample;
476 bufs = PAGE_SIZE << db->buforder;
477 if (db->ossfragshift) {
478 if ((1000 << db->ossfragshift) < user_bytes_per_sec)
479 db->fragshift = ld2(user_bytes_per_sec/1000);
480 else
481 db->fragshift = db->ossfragshift;
482 } else {
483 db->fragshift = ld2(user_bytes_per_sec / 100 /
484 (db->subdivision ? db->subdivision : 1));
485 if (db->fragshift < 3)
486 db->fragshift = 3;
487 }
488
489 db->fragsize = 1 << db->fragshift;
490 db->dma_fragsize = db->fragsize * db->cnt_factor;
491 db->numfrag = bufs / db->dma_fragsize;
492
493 while (db->numfrag < 4 && db->fragshift > 3) {
494 db->fragshift--;
495 db->fragsize = 1 << db->fragshift;
496 db->dma_fragsize = db->fragsize * db->cnt_factor;
497 db->numfrag = bufs / db->dma_fragsize;
498 }
499
500 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
501 db->numfrag = db->ossmaxfrags;
502
503 db->dmasize = db->dma_fragsize * db->numfrag;
504 memset(db->rawbuf, 0, bufs);
505
506#ifdef AU1000_VERBOSE_DEBUG
507 dbg("rate=%d, samplesize=%d, channels=%d",
508 rate, db->sample_size, db->num_channels);
509 dbg("fragsize=%d, cnt_factor=%d, dma_fragsize=%d",
510 db->fragsize, db->cnt_factor, db->dma_fragsize);
511 dbg("numfrag=%d, dmasize=%d", db->numfrag, db->dmasize);
512#endif
513
514 db->ready = 1;
515 return 0;
516}
517
518static int
519prog_dmabuf_adc(struct au1550_state *s)
520{
521 stop_adc(s);
522 return prog_dmabuf(s, &s->dma_adc);
523
524}
525
526static int
527prog_dmabuf_dac(struct au1550_state *s)
528{
529 stop_dac(s);
530 return prog_dmabuf(s, &s->dma_dac);
531}
532
533
534
535static void
536dac_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
537{
538 struct au1550_state *s = (struct au1550_state *) dev_id;
539 struct dmabuf *db = &s->dma_dac;
540 u32 i2s_stat;
541 volatile psc_i2s_t *ip;
542
543 ip = s->psc_addr;
544 i2s_stat = ip->psc_i2sstat;
545#ifdef AU1000_VERBOSE_DEBUG
546 if (i2s_stat & (PSC_I2SSTAT_TF | PSC_I2SSTAT_TR | PSC_I2SSTAT_TF))
547 dbg("I2S status = 0x%08x", i2s_stat);
548#endif
549 db->dma_qcount--;
550
551 if (db->count >= db->fragsize) {
552 if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
553 db->fragsize) == 0) {
554 err("qcount < 2 and no ring room!");
555 }
556 db->nextOut += db->fragsize;
557 if (db->nextOut >= db->rawbuf + db->dmasize)
558 db->nextOut -= db->dmasize;
559 db->count -= db->fragsize;
560 db->total_bytes += db->dma_fragsize;
561 db->dma_qcount++;
562 }
563
564
565 if (waitqueue_active(&db->wait))
566 wake_up(&db->wait);
567}
568
569
570static void
571adc_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
572{
573 struct au1550_state *s = (struct au1550_state *)dev_id;
574 struct dmabuf *dp = &s->dma_adc;
575 u32 obytes;
576 char *obuf;
577
578
579
580 au1xxx_dbdma_get_dest(dp->dmanr, (void *)(&obuf), &obytes);
581
582 if ((dp->count + obytes) > dp->dmasize) {
583
584
585 stop_adc(s);
586 dp->error++;
587 err("adc overrun");
588 return;
589 }
590
591
592
593 au1xxx_dbdma_put_dest(dp->dmanr, dp->nextIn, dp->dma_fragsize);
594
595 dp->nextIn += dp->dma_fragsize;
596 if (dp->nextIn >= dp->rawbuf + dp->dmasize)
597 dp->nextIn -= dp->dmasize;
598
599 dp->count += obytes;
600 dp->total_bytes += obytes;
601
602
603
604 if (waitqueue_active(&dp->wait))
605 wake_up(&dp->wait);
606
607}
608
609static loff_t
610au1550_llseek(struct file *file, loff_t offset, int origin)
611{
612 return -ESPIPE;
613}
614
615
616#if 0
617static int
618au1550_open_mixdev(struct inode *inode, struct file *file)
619{
620 file->private_data = &au1550_state;
621 return 0;
622}
623
624static int
625au1550_release_mixdev(struct inode *inode, struct file *file)
626{
627 return 0;
628}
629
630static int
631mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
632 unsigned long arg)
633{
634 return codec->mixer_ioctl(codec, cmd, arg);
635}
636
637static int
638au1550_ioctl_mixdev(struct inode *inode, struct file *file,
639 unsigned int cmd, unsigned long arg)
640{
641 struct au1550_state *s = (struct au1550_state *)file->private_data;
642 struct ac97_codec *codec = s->codec;
643
644 return mixdev_ioctl(codec, cmd, arg);
645}
646
647static struct file_operations au1550_mixer_fops = {
648 owner:THIS_MODULE,
649 llseek:au1550_llseek,
650 ioctl:au1550_ioctl_mixdev,
651 open:au1550_open_mixdev,
652 release:au1550_release_mixdev,
653};
654#endif
655
656static int
657drain_dac(struct au1550_state *s, int nonblock)
658{
659 unsigned long flags;
660 int count, tmo;
661
662 if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
663 return 0;
664
665 for (;;) {
666 spin_lock_irqsave(&s->lock, flags);
667 count = s->dma_dac.count;
668 spin_unlock_irqrestore(&s->lock, flags);
669 if (count <= 0)
670 break;
671 if (signal_pending(current))
672 break;
673 if (nonblock)
674 return -EBUSY;
675 tmo = 1000 * count / (s->no_vra ?
676 SAMP_RATE : s->dma_dac.sample_rate);
677 tmo /= s->dma_dac.dma_bytes_per_sample;
678 au1550_delay(tmo);
679 }
680 if (signal_pending(current))
681 return -ERESTARTSYS;
682 return 0;
683}
684
685static inline u8 S16_TO_U8(s16 ch)
686{
687 return (u8) (ch >> 8) + 0x80;
688}
689static inline s16 U8_TO_S16(u8 ch)
690{
691 return (s16) (ch - 0x80) << 8;
692}
693
694
695
696
697
698
699
700static int
701translate_from_user(struct dmabuf *db, char* dmabuf, char* userbuf,
702 int dmacount)
703{
704 int sample, i;
705 int interp_bytes_per_sample;
706 int num_samples;
707 int mono = (db->num_channels == 1);
708 char usersample[12];
709 s16 ch, dmasample[6];
710
711 if (db->sample_size == 16 && !mono && db->src_factor == 1) {
712
713
714 if (copy_from_user(dmabuf, userbuf, dmacount))
715 return -EFAULT;
716 return dmacount;
717 }
718
719 interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
720 num_samples = dmacount / interp_bytes_per_sample;
721
722 for (sample = 0; sample < num_samples; sample++) {
723 if (copy_from_user(usersample, userbuf,
724 db->user_bytes_per_sample)) {
725 return -EFAULT;
726 }
727
728 for (i = 0; i < db->num_channels; i++) {
729 if (db->sample_size == 8)
730 ch = U8_TO_S16(usersample[i]);
731 else
732 ch = *((s16 *) (&usersample[i * 2]));
733 dmasample[i] = ch;
734 if (mono)
735 dmasample[i + 1] = ch;
736 }
737
738
739
740 for (i = 0; i < db->src_factor; i++)
741 memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
742
743 userbuf += db->user_bytes_per_sample;
744 dmabuf += interp_bytes_per_sample;
745 }
746
747 return num_samples * interp_bytes_per_sample;
748}
749
750
751
752
753
754
755
756static int
757translate_to_user(struct dmabuf *db, char* userbuf, char* dmabuf,
758 int dmacount)
759{
760 int sample, i;
761 int interp_bytes_per_sample;
762 int num_samples;
763 int mono = (db->num_channels == 1);
764 char usersample[12];
765
766 if (db->sample_size == 16 && !mono && db->src_factor == 1) {
767
768
769 if (copy_to_user(userbuf, dmabuf, dmacount))
770 return -EFAULT;
771 return dmacount;
772 }
773
774 interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
775 num_samples = dmacount / interp_bytes_per_sample;
776
777 for (sample = 0; sample < num_samples; sample++) {
778 for (i = 0; i < db->num_channels; i++) {
779 if (db->sample_size == 8)
780 usersample[i] =
781 S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
782 else
783 *((s16 *) (&usersample[i * 2])) =
784 *((s16 *) (&dmabuf[i * 2]));
785 }
786
787 if (copy_to_user(userbuf, usersample,
788 db->user_bytes_per_sample)) {
789 return -EFAULT;
790 }
791
792 userbuf += db->user_bytes_per_sample;
793 dmabuf += interp_bytes_per_sample;
794 }
795
796 return num_samples * interp_bytes_per_sample;
797}
798
799
800
801
802
803
804static int
805copy_dmabuf_user(struct dmabuf *db, char* userbuf, int count, int to_user)
806{
807 char *bufptr = to_user ? db->nextOut : db->nextIn;
808 char *bufend = db->rawbuf + db->dmasize;
809 int cnt, ret;
810
811 if (bufptr + count > bufend) {
812 int partial = (int) (bufend - bufptr);
813 if (to_user) {
814 if ((cnt = translate_to_user(db, userbuf,
815 bufptr, partial)) < 0)
816 return cnt;
817 ret = cnt;
818 if ((cnt = translate_to_user(db, userbuf + partial,
819 db->rawbuf,
820 count - partial)) < 0)
821 return cnt;
822 ret += cnt;
823 } else {
824 if ((cnt = translate_from_user(db, bufptr, userbuf,
825 partial)) < 0)
826 return cnt;
827 ret = cnt;
828 if ((cnt = translate_from_user(db, db->rawbuf,
829 userbuf + partial,
830 count - partial)) < 0)
831 return cnt;
832 ret += cnt;
833 }
834 } else {
835 if (to_user)
836 ret = translate_to_user(db, userbuf, bufptr, count);
837 else
838 ret = translate_from_user(db, bufptr, userbuf, count);
839 }
840
841 return ret;
842}
843
844
845static ssize_t
846au1550_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
847{
848 struct au1550_state *s = (struct au1550_state *)file->private_data;
849 struct dmabuf *db = &s->dma_adc;
850 DECLARE_WAITQUEUE(wait, current);
851 ssize_t ret;
852 unsigned long flags;
853 int cnt, usercnt, avail;
854
855 if (ppos != &file->f_pos)
856 return -ESPIPE;
857 if (db->mapped)
858 return -ENXIO;
859 if (!access_ok(VERIFY_WRITE, buffer, count))
860 return -EFAULT;
861 ret = 0;
862
863 count *= db->cnt_factor;
864
865 down(&s->sem);
866 add_wait_queue(&db->wait, &wait);
867
868 while (count > 0) {
869
870
871 do {
872 if (db->stopped)
873 start_adc(s);
874 spin_lock_irqsave(&s->lock, flags);
875 avail = db->count;
876 if (avail <= 0)
877 __set_current_state(TASK_INTERRUPTIBLE);
878 spin_unlock_irqrestore(&s->lock, flags);
879 if (avail <= 0) {
880 if (file->f_flags & O_NONBLOCK) {
881 if (!ret)
882 ret = -EAGAIN;
883 goto out;
884 }
885 up(&s->sem);
886 schedule();
887 if (signal_pending(current)) {
888 if (!ret)
889 ret = -ERESTARTSYS;
890 goto out2;
891 }
892 down(&s->sem);
893 }
894 } while (avail <= 0);
895
896
897
898 if ((cnt = copy_dmabuf_user(db, buffer,
899 count > avail ?
900 avail : count, 1)) < 0) {
901 if (!ret)
902 ret = -EFAULT;
903 goto out;
904 }
905
906 spin_lock_irqsave(&s->lock, flags);
907 db->count -= cnt;
908 db->nextOut += cnt;
909 if (db->nextOut >= db->rawbuf + db->dmasize)
910 db->nextOut -= db->dmasize;
911 spin_unlock_irqrestore(&s->lock, flags);
912
913 count -= cnt;
914 usercnt = cnt / db->cnt_factor;
915 buffer += usercnt;
916 ret += usercnt;
917 }
918
919out:
920 up(&s->sem);
921out2:
922 remove_wait_queue(&db->wait, &wait);
923 set_current_state(TASK_RUNNING);
924 return ret;
925}
926
927static ssize_t
928au1550_write(struct file *file, const char *buffer, size_t count, loff_t * ppos)
929{
930 struct au1550_state *s = (struct au1550_state *)file->private_data;
931 struct dmabuf *db = &s->dma_dac;
932 DECLARE_WAITQUEUE(wait, current);
933 ssize_t ret = 0;
934 unsigned long flags;
935 int cnt, usercnt, avail;
936
937#ifdef AU1000_VERBOSE_DEBUG
938 dbg("write: count=%d", count);
939#endif
940
941 if (ppos != &file->f_pos)
942 return -ESPIPE;
943 if (db->mapped)
944 return -ENXIO;
945 if (!access_ok(VERIFY_READ, buffer, count))
946 return -EFAULT;
947
948 count *= db->cnt_factor;
949
950 down(&s->sem);
951 add_wait_queue(&db->wait, &wait);
952
953 while (count > 0) {
954
955
956 do {
957 spin_lock_irqsave(&s->lock, flags);
958 avail = (int) db->dmasize - db->count;
959 if (avail <= 0)
960 __set_current_state(TASK_INTERRUPTIBLE);
961 spin_unlock_irqrestore(&s->lock, flags);
962 if (avail <= 0) {
963 if (file->f_flags & O_NONBLOCK) {
964 if (!ret)
965 ret = -EAGAIN;
966 goto out;
967 }
968 up(&s->sem);
969 schedule();
970 if (signal_pending(current)) {
971 if (!ret)
972 ret = -ERESTARTSYS;
973 goto out2;
974 }
975 down(&s->sem);
976 }
977 } while (avail <= 0);
978
979
980
981 if ((cnt = copy_dmabuf_user(db, (char *) buffer,
982 count > avail ?
983 avail : count, 0)) < 0) {
984 if (!ret)
985 ret = -EFAULT;
986 goto out;
987 }
988
989 spin_lock_irqsave(&s->lock, flags);
990 db->count += cnt;
991 db->nextIn += cnt;
992 if (db->nextIn >= db->rawbuf + db->dmasize)
993 db->nextIn -= db->dmasize;
994
995
996
997
998
999 while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) {
1000 if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
1001 db->fragsize) == 0) {
1002 err("qcount < 2 and no ring room!");
1003 }
1004 db->nextOut += db->fragsize;
1005 if (db->nextOut >= db->rawbuf + db->dmasize)
1006 db->nextOut -= db->dmasize;
1007 db->count -= db->fragsize;
1008 db->total_bytes += db->dma_fragsize;
1009 if (db->dma_qcount == 0)
1010 start_dac(s);
1011 db->dma_qcount++;
1012 }
1013 spin_unlock_irqrestore(&s->lock, flags);
1014
1015 count -= cnt;
1016 usercnt = cnt / db->cnt_factor;
1017 buffer += usercnt;
1018 ret += usercnt;
1019 }
1020
1021out:
1022 up(&s->sem);
1023out2:
1024 remove_wait_queue(&db->wait, &wait);
1025 set_current_state(TASK_RUNNING);
1026 return ret;
1027}
1028
1029
1030
1031static unsigned int
1032au1550_poll(struct file *file, struct poll_table_struct *wait)
1033{
1034 struct au1550_state *s = (struct au1550_state *)file->private_data;
1035 unsigned long flags;
1036 unsigned int mask = 0;
1037
1038 if (file->f_mode & FMODE_WRITE) {
1039 if (!s->dma_dac.ready)
1040 return 0;
1041 poll_wait(file, &s->dma_dac.wait, wait);
1042 }
1043 if (file->f_mode & FMODE_READ) {
1044 if (!s->dma_adc.ready)
1045 return 0;
1046 poll_wait(file, &s->dma_adc.wait, wait);
1047 }
1048
1049 spin_lock_irqsave(&s->lock, flags);
1050
1051 if (file->f_mode & FMODE_READ) {
1052 if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
1053 mask |= POLLIN | POLLRDNORM;
1054 }
1055 if (file->f_mode & FMODE_WRITE) {
1056 if (s->dma_dac.mapped) {
1057 if (s->dma_dac.count >=
1058 (signed)s->dma_dac.dma_fragsize)
1059 mask |= POLLOUT | POLLWRNORM;
1060 } else {
1061 if ((signed) s->dma_dac.dmasize >=
1062 s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
1063 mask |= POLLOUT | POLLWRNORM;
1064 }
1065 }
1066 spin_unlock_irqrestore(&s->lock, flags);
1067 return mask;
1068}
1069
1070static int
1071au1550_mmap(struct file *file, struct vm_area_struct *vma)
1072{
1073 struct au1550_state *s = (struct au1550_state *)file->private_data;
1074 struct dmabuf *db;
1075 unsigned long size;
1076 int ret = 0;
1077
1078 lock_kernel();
1079 down(&s->sem);
1080 if (vma->vm_flags & VM_WRITE)
1081 db = &s->dma_dac;
1082 else if (vma->vm_flags & VM_READ)
1083 db = &s->dma_adc;
1084 else {
1085 ret = -EINVAL;
1086 goto out;
1087 }
1088 if (vma->vm_pgoff != 0) {
1089 ret = -EINVAL;
1090 goto out;
1091 }
1092 size = vma->vm_end - vma->vm_start;
1093 if (size > (PAGE_SIZE << db->buforder)) {
1094 ret = -EINVAL;
1095 goto out;
1096 }
1097 if (remap_page_range(vma->vm_start, virt_to_phys(db->rawbuf),
1098 size, vma->vm_page_prot)) {
1099 ret = -EAGAIN;
1100 goto out;
1101 }
1102 vma->vm_flags &= ~VM_IO;
1103 db->mapped = 1;
1104out:
1105 up(&s->sem);
1106 unlock_kernel();
1107 return ret;
1108}
1109
1110
1111#ifdef AU1000_VERBOSE_DEBUG
1112static struct ioctl_str_t {
1113 unsigned int cmd;
1114 const char *str;
1115} ioctl_str[] = {
1116 {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
1117 {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
1118 {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
1119 {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
1120 {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
1121 {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
1122 {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
1123 {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
1124 {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
1125 {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
1126 {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
1127 {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
1128 {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
1129 {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
1130 {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
1131 {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
1132 {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
1133 {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
1134 {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
1135 {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
1136 {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
1137 {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
1138 {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
1139 {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
1140 {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
1141 {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
1142 {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
1143 {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
1144 {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
1145 {OSS_GETVERSION, "OSS_GETVERSION"},
1146 {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
1147 {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
1148 {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
1149 {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
1150};
1151#endif
1152
1153static int
1154dma_count_done(struct dmabuf *db)
1155{
1156 if (db->stopped)
1157 return 0;
1158
1159 return db->dma_fragsize - au1xxx_get_dma_residue(db->dmanr);
1160}
1161
1162
1163static int
1164au1550_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
1165 unsigned long arg)
1166{
1167 struct au1550_state *s = (struct au1550_state *)file->private_data;
1168 unsigned long flags;
1169 audio_buf_info abinfo;
1170 count_info cinfo;
1171 int count;
1172 int val, mapped, ret, diff;
1173
1174 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1175 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1176
1177#ifdef AU1000_VERBOSE_DEBUG
1178 for (count=0; count<sizeof(ioctl_str)/sizeof(ioctl_str[0]); count++) {
1179 if (ioctl_str[count].cmd == cmd)
1180 break;
1181 }
1182 if (count < sizeof(ioctl_str) / sizeof(ioctl_str[0]))
1183 dbg("ioctl %s, arg=0x%lx", ioctl_str[count].str, arg);
1184 else
1185 dbg("ioctl 0x%x unknown, arg=0x%lx", cmd, arg);
1186#endif
1187
1188 switch (cmd) {
1189 case OSS_GETVERSION:
1190 return put_user(SOUND_VERSION, (int *) arg);
1191
1192 case SNDCTL_DSP_SYNC:
1193 if (file->f_mode & FMODE_WRITE)
1194 return drain_dac(s, file->f_flags & O_NONBLOCK);
1195 return 0;
1196
1197 case SNDCTL_DSP_SETDUPLEX:
1198 return 0;
1199
1200 case SNDCTL_DSP_GETCAPS:
1201 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1202 DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1203
1204 case SNDCTL_DSP_RESET:
1205 if (file->f_mode & FMODE_WRITE) {
1206 stop_dac(s);
1207 synchronize_irq();
1208 s->dma_dac.count = s->dma_dac.total_bytes = 0;
1209 s->dma_dac.nextIn = s->dma_dac.nextOut =
1210 s->dma_dac.rawbuf;
1211 }
1212 if (file->f_mode & FMODE_READ) {
1213 stop_adc(s);
1214 synchronize_irq();
1215 s->dma_adc.count = s->dma_adc.total_bytes = 0;
1216 s->dma_adc.nextIn = s->dma_adc.nextOut =
1217 s->dma_adc.rawbuf;
1218 }
1219 return 0;
1220
1221 case SNDCTL_DSP_SPEED:
1222 if (get_user(val, (int *) arg))
1223 return -EFAULT;
1224 if (val >= 0) {
1225 if (file->f_mode & FMODE_READ) {
1226 stop_adc(s);
1227 set_adc_rate(s, val);
1228 }
1229 if (file->f_mode & FMODE_WRITE) {
1230 stop_dac(s);
1231 set_dac_rate(s, val);
1232 }
1233 if (s->open_mode & FMODE_READ)
1234 if ((ret = prog_dmabuf_adc(s)))
1235 return ret;
1236 if (s->open_mode & FMODE_WRITE)
1237 if ((ret = prog_dmabuf_dac(s)))
1238 return ret;
1239 }
1240 return put_user((file->f_mode & FMODE_READ) ?
1241 s->dma_adc.sample_rate :
1242 s->dma_dac.sample_rate,
1243 (int *)arg);
1244
1245 case SNDCTL_DSP_STEREO:
1246 if (get_user(val, (int *) arg))
1247 return -EFAULT;
1248 if (file->f_mode & FMODE_READ) {
1249 stop_adc(s);
1250 s->dma_adc.num_channels = val ? 2 : 1;
1251 if ((ret = prog_dmabuf_adc(s)))
1252 return ret;
1253 }
1254 if (file->f_mode & FMODE_WRITE) {
1255 stop_dac(s);
1256 s->dma_dac.num_channels = val ? 2 : 1;
1257 if ((ret = prog_dmabuf_dac(s)))
1258 return ret;
1259 }
1260 return 0;
1261
1262 case SNDCTL_DSP_CHANNELS:
1263 if (get_user(val, (int *) arg))
1264 return -EFAULT;
1265 if (val != 0) {
1266 if (file->f_mode & FMODE_READ) {
1267 if (val < 0 || val > 2)
1268 return -EINVAL;
1269 stop_adc(s);
1270 s->dma_adc.num_channels = val;
1271 if ((ret = prog_dmabuf_adc(s)))
1272 return ret;
1273 }
1274 if (file->f_mode & FMODE_WRITE) {
1275 switch (val) {
1276 case 1:
1277 case 2:
1278 break;
1279 default:
1280 return -EINVAL;
1281 }
1282
1283 stop_dac(s);
1284 s->dma_dac.num_channels = val;
1285 if ((ret = prog_dmabuf_dac(s)))
1286 return ret;
1287 }
1288 }
1289 return put_user(val, (int *) arg);
1290
1291 case SNDCTL_DSP_GETFMTS:
1292 return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
1293
1294 case SNDCTL_DSP_SETFMT:
1295 if (get_user(val, (int *) arg))
1296 return -EFAULT;
1297 if (val != AFMT_QUERY) {
1298 if (file->f_mode & FMODE_READ) {
1299 stop_adc(s);
1300 if (val == AFMT_S16_LE)
1301 s->dma_adc.sample_size = 16;
1302 else {
1303 val = AFMT_U8;
1304 s->dma_adc.sample_size = 8;
1305 }
1306 if ((ret = prog_dmabuf_adc(s)))
1307 return ret;
1308 }
1309 if (file->f_mode & FMODE_WRITE) {
1310 stop_dac(s);
1311 if (val == AFMT_S16_LE)
1312 s->dma_dac.sample_size = 16;
1313 else {
1314 val = AFMT_U8;
1315 s->dma_dac.sample_size = 8;
1316 }
1317 if ((ret = prog_dmabuf_dac(s)))
1318 return ret;
1319 }
1320 } else {
1321 if (file->f_mode & FMODE_READ)
1322 val = (s->dma_adc.sample_size == 16) ?
1323 AFMT_S16_LE : AFMT_U8;
1324 else
1325 val = (s->dma_dac.sample_size == 16) ?
1326 AFMT_S16_LE : AFMT_U8;
1327 }
1328 return put_user(val, (int *) arg);
1329
1330 case SNDCTL_DSP_POST:
1331 return 0;
1332
1333 case SNDCTL_DSP_GETTRIGGER:
1334 val = 0;
1335 spin_lock_irqsave(&s->lock, flags);
1336 if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
1337 val |= PCM_ENABLE_INPUT;
1338 if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
1339 val |= PCM_ENABLE_OUTPUT;
1340 spin_unlock_irqrestore(&s->lock, flags);
1341 return put_user(val, (int *) arg);
1342
1343 case SNDCTL_DSP_SETTRIGGER:
1344 if (get_user(val, (int *) arg))
1345 return -EFAULT;
1346 if (file->f_mode & FMODE_READ) {
1347 if (val & PCM_ENABLE_INPUT)
1348 start_adc(s);
1349 else
1350 stop_adc(s);
1351 }
1352 if (file->f_mode & FMODE_WRITE) {
1353 if (val & PCM_ENABLE_OUTPUT)
1354 start_dac(s);
1355 else
1356 stop_dac(s);
1357 }
1358 return 0;
1359
1360 case SNDCTL_DSP_GETOSPACE:
1361 if (!(file->f_mode & FMODE_WRITE))
1362 return -EINVAL;
1363 abinfo.fragsize = s->dma_dac.fragsize;
1364 spin_lock_irqsave(&s->lock, flags);
1365 count = s->dma_dac.count;
1366 count -= dma_count_done(&s->dma_dac);
1367 spin_unlock_irqrestore(&s->lock, flags);
1368 if (count < 0)
1369 count = 0;
1370 abinfo.bytes = (s->dma_dac.dmasize - count) /
1371 s->dma_dac.cnt_factor;
1372 abinfo.fragstotal = s->dma_dac.numfrag;
1373 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1374#ifdef AU1000_VERBOSE_DEBUG
1375 dbg("bytes=%d, fragments=%d", abinfo.bytes, abinfo.fragments);
1376#endif
1377 return copy_to_user((void *) arg, &abinfo,
1378 sizeof(abinfo)) ? -EFAULT : 0;
1379
1380 case SNDCTL_DSP_GETISPACE:
1381 if (!(file->f_mode & FMODE_READ))
1382 return -EINVAL;
1383 abinfo.fragsize = s->dma_adc.fragsize;
1384 spin_lock_irqsave(&s->lock, flags);
1385 count = s->dma_adc.count;
1386 count += dma_count_done(&s->dma_adc);
1387 spin_unlock_irqrestore(&s->lock, flags);
1388 if (count < 0)
1389 count = 0;
1390 abinfo.bytes = count / s->dma_adc.cnt_factor;
1391 abinfo.fragstotal = s->dma_adc.numfrag;
1392 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1393 return copy_to_user((void *) arg, &abinfo,
1394 sizeof(abinfo)) ? -EFAULT : 0;
1395
1396 case SNDCTL_DSP_NONBLOCK:
1397 file->f_flags |= O_NONBLOCK;
1398 return 0;
1399
1400 case SNDCTL_DSP_GETODELAY:
1401 if (!(file->f_mode & FMODE_WRITE))
1402 return -EINVAL;
1403 spin_lock_irqsave(&s->lock, flags);
1404 count = s->dma_dac.count;
1405 count -= dma_count_done(&s->dma_dac);
1406 spin_unlock_irqrestore(&s->lock, flags);
1407 if (count < 0)
1408 count = 0;
1409 count /= s->dma_dac.cnt_factor;
1410 return put_user(count, (int *) arg);
1411
1412 case SNDCTL_DSP_GETIPTR:
1413 if (!(file->f_mode & FMODE_READ))
1414 return -EINVAL;
1415 spin_lock_irqsave(&s->lock, flags);
1416 cinfo.bytes = s->dma_adc.total_bytes;
1417 count = s->dma_adc.count;
1418 if (!s->dma_adc.stopped) {
1419 diff = dma_count_done(&s->dma_adc);
1420 count += diff;
1421 cinfo.bytes += diff;
1422 cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) + diff -
1423 virt_to_phys(s->dma_adc.rawbuf);
1424 } else
1425 cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
1426 virt_to_phys(s->dma_adc.rawbuf);
1427 if (s->dma_adc.mapped)
1428 s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
1429 spin_unlock_irqrestore(&s->lock, flags);
1430 if (count < 0)
1431 count = 0;
1432 cinfo.blocks = count >> s->dma_adc.fragshift;
1433 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1434
1435 case SNDCTL_DSP_GETOPTR:
1436 if (!(file->f_mode & FMODE_READ))
1437 return -EINVAL;
1438 spin_lock_irqsave(&s->lock, flags);
1439 cinfo.bytes = s->dma_dac.total_bytes;
1440 count = s->dma_dac.count;
1441 if (!s->dma_dac.stopped) {
1442 diff = dma_count_done(&s->dma_dac);
1443 count -= diff;
1444 cinfo.bytes += diff;
1445 cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
1446 virt_to_phys(s->dma_dac.rawbuf);
1447 } else
1448 cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
1449 virt_to_phys(s->dma_dac.rawbuf);
1450 if (s->dma_dac.mapped)
1451 s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
1452 spin_unlock_irqrestore(&s->lock, flags);
1453 if (count < 0)
1454 count = 0;
1455 cinfo.blocks = count >> s->dma_dac.fragshift;
1456 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1457
1458 case SNDCTL_DSP_GETBLKSIZE:
1459 if (file->f_mode & FMODE_WRITE)
1460 return put_user(s->dma_dac.fragsize, (int *) arg);
1461 else
1462 return put_user(s->dma_adc.fragsize, (int *) arg);
1463
1464 case SNDCTL_DSP_SETFRAGMENT:
1465 if (get_user(val, (int *) arg))
1466 return -EFAULT;
1467 if (file->f_mode & FMODE_READ) {
1468 stop_adc(s);
1469 s->dma_adc.ossfragshift = val & 0xffff;
1470 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1471 if (s->dma_adc.ossfragshift < 4)
1472 s->dma_adc.ossfragshift = 4;
1473 if (s->dma_adc.ossfragshift > 15)
1474 s->dma_adc.ossfragshift = 15;
1475 if (s->dma_adc.ossmaxfrags < 4)
1476 s->dma_adc.ossmaxfrags = 4;
1477 if ((ret = prog_dmabuf_adc(s)))
1478 return ret;
1479 }
1480 if (file->f_mode & FMODE_WRITE) {
1481 stop_dac(s);
1482 s->dma_dac.ossfragshift = val & 0xffff;
1483 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1484 if (s->dma_dac.ossfragshift < 4)
1485 s->dma_dac.ossfragshift = 4;
1486 if (s->dma_dac.ossfragshift > 15)
1487 s->dma_dac.ossfragshift = 15;
1488 if (s->dma_dac.ossmaxfrags < 4)
1489 s->dma_dac.ossmaxfrags = 4;
1490 if ((ret = prog_dmabuf_dac(s)))
1491 return ret;
1492 }
1493 return 0;
1494
1495 case SNDCTL_DSP_SUBDIVIDE:
1496 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1497 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1498 return -EINVAL;
1499 if (get_user(val, (int *) arg))
1500 return -EFAULT;
1501 if (val != 1 && val != 2 && val != 4)
1502 return -EINVAL;
1503 if (file->f_mode & FMODE_READ) {
1504 stop_adc(s);
1505 s->dma_adc.subdivision = val;
1506 if ((ret = prog_dmabuf_adc(s)))
1507 return ret;
1508 }
1509 if (file->f_mode & FMODE_WRITE) {
1510 stop_dac(s);
1511 s->dma_dac.subdivision = val;
1512 if ((ret = prog_dmabuf_dac(s)))
1513 return ret;
1514 }
1515 return 0;
1516
1517 case SOUND_PCM_READ_RATE:
1518 return put_user((file->f_mode & FMODE_READ) ?
1519 s->dma_adc.sample_rate :
1520 s->dma_dac.sample_rate,
1521 (int *)arg);
1522
1523 case SOUND_PCM_READ_CHANNELS:
1524 if (file->f_mode & FMODE_READ)
1525 return put_user(s->dma_adc.num_channels, (int *)arg);
1526 else
1527 return put_user(s->dma_dac.num_channels, (int *)arg);
1528
1529 case SOUND_PCM_READ_BITS:
1530 if (file->f_mode & FMODE_READ)
1531 return put_user(s->dma_adc.sample_size, (int *)arg);
1532 else
1533 return put_user(s->dma_dac.sample_size, (int *)arg);
1534
1535 case SOUND_PCM_WRITE_FILTER:
1536 case SNDCTL_DSP_SETSYNCRO:
1537 case SOUND_PCM_READ_FILTER:
1538 return -EINVAL;
1539 }
1540
1541#if 0
1542 return mixdev_ioctl(s->codec, cmd, arg);
1543#else
1544 return 0;
1545#endif
1546}
1547
1548
1549static int
1550au1550_open(struct inode *inode, struct file *file)
1551{
1552 int minor = MINOR(inode->i_rdev);
1553 DECLARE_WAITQUEUE(wait, current);
1554 struct au1550_state *s = &au1550_state;
1555 int ret;
1556
1557#ifdef AU1000_VERBOSE_DEBUG
1558 if (file->f_flags & O_NONBLOCK)
1559 dbg(__FUNCTION__ ": non-blocking");
1560 else
1561 dbg(__FUNCTION__ ": blocking");
1562#endif
1563
1564 file->private_data = s;
1565
1566 down(&s->open_sem);
1567 while (s->open_mode & file->f_mode) {
1568 if (file->f_flags & O_NONBLOCK) {
1569 up(&s->open_sem);
1570 return -EBUSY;
1571 }
1572 add_wait_queue(&s->open_wait, &wait);
1573 __set_current_state(TASK_INTERRUPTIBLE);
1574 up(&s->open_sem);
1575 schedule();
1576 remove_wait_queue(&s->open_wait, &wait);
1577 set_current_state(TASK_RUNNING);
1578 if (signal_pending(current))
1579 return -ERESTARTSYS;
1580 down(&s->open_sem);
1581 }
1582
1583 stop_dac(s);
1584 stop_adc(s);
1585
1586 if (file->f_mode & FMODE_READ) {
1587 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
1588 s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
1589 s->dma_adc.num_channels = 1;
1590 s->dma_adc.sample_size = 8;
1591 set_adc_rate(s, 8000);
1592 if ((minor & 0xf) == SND_DEV_DSP16)
1593 s->dma_adc.sample_size = 16;
1594 }
1595
1596 if (file->f_mode & FMODE_WRITE) {
1597 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
1598 s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
1599 s->dma_dac.num_channels = 1;
1600 s->dma_dac.sample_size = 8;
1601 set_dac_rate(s, 8000);
1602 if ((minor & 0xf) == SND_DEV_DSP16)
1603 s->dma_dac.sample_size = 16;
1604 }
1605
1606 if (file->f_mode & FMODE_READ) {
1607 if ((ret = prog_dmabuf_adc(s)))
1608 return ret;
1609 }
1610 if (file->f_mode & FMODE_WRITE) {
1611 if ((ret = prog_dmabuf_dac(s)))
1612 return ret;
1613 }
1614
1615 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1616 up(&s->open_sem);
1617 init_MUTEX(&s->sem);
1618 return 0;
1619}
1620
1621static int
1622au1550_release(struct inode *inode, struct file *file)
1623{
1624 struct au1550_state *s = (struct au1550_state *)file->private_data;
1625
1626 lock_kernel();
1627
1628 if (file->f_mode & FMODE_WRITE) {
1629 unlock_kernel();
1630 drain_dac(s, file->f_flags & O_NONBLOCK);
1631 lock_kernel();
1632 }
1633
1634 down(&s->open_sem);
1635 if (file->f_mode & FMODE_WRITE) {
1636 stop_dac(s);
1637 kfree(s->dma_dac.rawbuf);
1638 s->dma_dac.rawbuf = NULL;
1639 }
1640 if (file->f_mode & FMODE_READ) {
1641 stop_adc(s);
1642 kfree(s->dma_adc.rawbuf);
1643 s->dma_adc.rawbuf = NULL;
1644 }
1645 s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
1646 up(&s->open_sem);
1647 wake_up(&s->open_wait);
1648 unlock_kernel();
1649 return 0;
1650}
1651
1652static struct file_operations au1550_audio_fops = {
1653 owner: THIS_MODULE,
1654 llseek: au1550_llseek,
1655 read: au1550_read,
1656 write: au1550_write,
1657 poll: au1550_poll,
1658 ioctl: au1550_ioctl,
1659 mmap: au1550_mmap,
1660 open: au1550_open,
1661 release: au1550_release,
1662};
1663
1664MODULE_AUTHOR("Advanced Micro Devices (AMD), dan@embeddededge.com");
1665MODULE_DESCRIPTION("Au1550 Audio Driver");
1666
1667
1668
1669
1670static void
1671intclk_setup(void)
1672{
1673 uint clk, rate, stat;
1674
1675
1676
1677
1678
1679
1680 rate = get_au1x00_speed();
1681#ifdef TRY_441KHz
1682 rate /= (11 * 1000000);
1683#else
1684 rate /= (12 * 1000000);
1685#endif
1686
1687
1688
1689 rate /=2;
1690 rate--;
1691 clk = au_readl(SYS_FREQCTRL1);
1692 au_sync();
1693 clk &= ~(SYS_FC_FRDIV4_MASK | SYS_FC_FS4);;
1694 clk |= (rate << SYS_FC_FRDIV4_BIT);
1695 clk |= SYS_FC_FE4;
1696 au_writel(clk, SYS_FREQCTRL1);
1697 au_sync();
1698
1699
1700
1701 clk = au_readl(SYS_CLKSRC);
1702 au_sync();
1703 clk &= ~0x01f00000;
1704 clk |= (6 << 22);
1705 au_writel(clk, SYS_CLKSRC);
1706 au_sync();
1707}
1708
1709static int __devinit
1710au1550_probe(void)
1711{
1712 struct au1550_state *s = &au1550_state;
1713 int val;
1714 volatile psc_i2s_t *ip;
1715#ifdef AU1550_DEBUG
1716 char proc_str[80];
1717#endif
1718
1719 memset(s, 0, sizeof(struct au1550_state));
1720
1721 init_waitqueue_head(&s->dma_adc.wait);
1722 init_waitqueue_head(&s->dma_dac.wait);
1723 init_waitqueue_head(&s->open_wait);
1724 init_MUTEX(&s->open_sem);
1725 spin_lock_init(&s->lock);
1726
1727
1728 s->psc_addr = (volatile psc_i2s_t *)I2S_PSC_BASE;
1729 ip = s->psc_addr;
1730
1731 if (!request_region(PHYSADDR(ip),
1732 0x30, AU1550_MODULE_NAME)) {
1733 err("I2S Audio ports in use");
1734 }
1735
1736
1737
1738 if ((s->dma_dac.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_MEM_CHAN,
1739 DBDMA_I2S_TX_CHAN, dac_dma_interrupt, (void *)s)) == 0) {
1740 err("Can't get DAC DMA");
1741 goto err_dma1;
1742 }
1743 au1xxx_dbdma_set_devwidth(s->dma_dac.dmanr, 16);
1744 if (au1xxx_dbdma_ring_alloc(s->dma_dac.dmanr,
1745 NUM_DBDMA_DESCRIPTORS) == 0) {
1746 err("Can't get DAC DMA descriptors");
1747 goto err_dma1;
1748 }
1749
1750 if ((s->dma_adc.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_I2S_RX_CHAN,
1751 DBDMA_MEM_CHAN, adc_dma_interrupt, (void *)s)) == 0) {
1752 err("Can't get ADC DMA");
1753 goto err_dma2;
1754 }
1755 au1xxx_dbdma_set_devwidth(s->dma_adc.dmanr, 16);
1756 if (au1xxx_dbdma_ring_alloc(s->dma_adc.dmanr,
1757 NUM_DBDMA_DESCRIPTORS) == 0) {
1758 err("Can't get ADC DMA descriptors");
1759 goto err_dma2;
1760 }
1761
1762 info("DAC: DMA%d, ADC: DMA%d", DBDMA_I2S_TX_CHAN, DBDMA_I2S_RX_CHAN);
1763
1764
1765
1766 if ((s->dev_audio = register_sound_dsp(&au1550_audio_fops, -1)) < 0)
1767 goto err_dev1;
1768#if 0
1769 if ((s->codec->dev_mixer =
1770 register_sound_mixer(&au1550_mixer_fops, -1)) < 0)
1771 goto err_dev2;
1772#endif
1773
1774#ifdef AU1550_DEBUG
1775
1776 s->ps = create_proc_read_entry(AU1000_MODULE_NAME, 0, NULL,
1777 proc_au1550_dump, NULL);
1778#endif
1779
1780 intclk_setup();
1781
1782
1783
1784
1785
1786
1787 ip->psc_ctrl = PSC_CTRL_DISABLE;
1788 au_sync();
1789 ip->psc_sel = (PSC_SEL_CLK_INTCLK | PSC_SEL_PS_I2SMODE);
1790 au_sync();
1791
1792
1793
1794 ip->psc_ctrl = PSC_CTRL_ENABLE;
1795 au_sync();
1796
1797
1798
1799 do {
1800 val = ip->psc_i2sstat;
1801 au_sync();
1802 } while ((val & PSC_I2SSTAT_SR) == 0);
1803
1804
1805
1806
1807
1808
1809 val = PSC_I2SCFG_SET_LEN(16);
1810#ifdef TRY_441KHz
1811
1812
1813
1814
1815
1816
1817
1818
1819 val |= PSC_I2SCFG_SET_WS(252);
1820#else
1821 val |= PSC_I2SCFG_SET_WS(250);
1822#endif
1823 val |= PSC_I2SCFG_RT_FIFO8 | PSC_I2SCFG_TT_FIFO8 | \
1824 PSC_I2SCFG_BI | PSC_I2SCFG_XM;
1825
1826 ip->psc_i2scfg = val;
1827 au_sync();
1828 val |= PSC_I2SCFG_DE_ENABLE;
1829 ip->psc_i2scfg = val;
1830 au_sync();
1831
1832
1833
1834 do {
1835 val = ip->psc_i2sstat;
1836 au_sync();
1837 } while ((val & PSC_I2SSTAT_DR) == 0);
1838
1839 val = ip->psc_i2scfg;
1840 au_sync();
1841
1842 codec_init();
1843
1844 s->no_vra = 1;
1845 if (s->no_vra)
1846 info("no VRA, interpolating and decimating");
1847
1848#if 0
1849
1850 val = SOUND_MASK_MIC;
1851 mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC,
1852 (unsigned long) &val);
1853#ifdef AU1550_DEBUG
1854 sprintf(proc_str, "driver/%s/%d/ac97", AU1550_MODULE_NAME,
1855 s->codec->id);
1856 s->ac97_ps = create_proc_read_entry (proc_str, 0, NULL,
1857 ac97_read_proc, &s->codec);
1858#endif
1859#endif
1860
1861 return 0;
1862
1863#if 0
1864 err_dev3:
1865 unregister_sound_mixer(s->codec->dev_mixer);
1866 err_dev2:
1867 unregister_sound_dsp(s->dev_audio);
1868#endif
1869 err_dev1:
1870 au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
1871 err_dma2:
1872 au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
1873 err_dma1:
1874 release_region(PHYSADDR(I2S_PSC_BASE), 0x30);
1875
1876 return -1;
1877}
1878
1879static void __devinit
1880au1550_remove(void)
1881{
1882 struct au1550_state *s = &au1550_state;
1883
1884 if (!s)
1885 return;
1886#ifdef AU1550_DEBUG
1887 if (s->ps)
1888 remove_proc_entry(AU1000_MODULE_NAME, NULL);
1889#endif
1890 synchronize_irq();
1891 au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
1892 au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
1893 release_region(PHYSADDR(I2S_PSC_BASE), 0x30);
1894 unregister_sound_dsp(s->dev_audio);
1895#if 0
1896 unregister_sound_mixer(s->codec->dev_mixer);
1897#endif
1898}
1899
1900static int __init
1901init_au1550(void)
1902{
1903 return au1550_probe();
1904}
1905
1906static void __exit
1907cleanup_au1550(void)
1908{
1909 au1550_remove();
1910}
1911
1912module_init(init_au1550);
1913module_exit(cleanup_au1550);
1914
1915#ifndef MODULE
1916
1917static int __init
1918au1550_setup(char *options)
1919{
1920 char *this_opt;
1921
1922 if (!options || !*options)
1923 return 0;
1924
1925 for(this_opt=strtok(options, ",");
1926 this_opt; this_opt=strtok(NULL, ",")) {
1927 if (!strncmp(this_opt, "vra", 3)) {
1928 vra = 1;
1929 }
1930 }
1931
1932 return 1;
1933}
1934
1935__setup("au1550_audio=", au1550_setup);
1936
1937#endif
1938
