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53#include <linux/version.h>
54#include <linux/module.h>
55#include <linux/string.h>
56#include <linux/ioport.h>
57#include <linux/sched.h>
58#include <linux/delay.h>
59#include <linux/sound.h>
60#include <linux/slab.h>
61#include <linux/soundcard.h>
62#include <linux/init.h>
63#include <linux/poll.h>
64#include <linux/pci.h>
65#include <linux/bitops.h>
66#include <linux/proc_fs.h>
67#include <linux/spinlock.h>
68#include <linux/smp_lock.h>
69#include <linux/ac97_codec.h>
70#include <linux/wrapper.h>
71#include <asm/io.h>
72#include <asm/uaccess.h>
73#include <asm/hardirq.h>
74#include <asm/au1000.h>
75#include <asm/au1000_dma.h>
76
77
78
79#undef OSS_DOCUMENTED_MIXER_SEMANTICS
80#undef AU1000_DEBUG
81#undef AU1000_VERBOSE_DEBUG
82
83#define USE_COHERENT_DMA
84
85#define AU1000_MODULE_NAME "Au1000 audio"
86#define PFX AU1000_MODULE_NAME
87
88#ifdef AU1000_DEBUG
89#define dbg(format, arg...) printk(KERN_DEBUG PFX ": " format "\n" , ## arg)
90#else
91#define dbg(format, arg...) do {} while (0)
92#endif
93#define err(format, arg...) printk(KERN_ERR PFX ": " format "\n" , ## arg)
94#define info(format, arg...) printk(KERN_INFO PFX ": " format "\n" , ## arg)
95#define warn(format, arg...) printk(KERN_WARNING PFX ": " format "\n" , ## arg)
96
97
98
99#define POLL_COUNT 0x5000
100#define AC97_EXT_DACS (AC97_EXTID_SDAC | AC97_EXTID_CDAC | AC97_EXTID_LDAC)
101
102
103static int vra = 0;
104MODULE_PARM(vra, "i");
105MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it");
106
107
108
109
110struct au1000_state {
111
112 int dev_audio;
113
114#ifdef AU1000_DEBUG
115
116 struct proc_dir_entry *ps;
117 struct proc_dir_entry *ac97_ps;
118#endif
119
120 struct ac97_codec *codec;
121 unsigned codec_base_caps;
122 unsigned codec_ext_caps;
123 int no_vra;
124
125 spinlock_t lock;
126 struct semaphore open_sem;
127 struct semaphore sem;
128 mode_t open_mode;
129 wait_queue_head_t open_wait;
130
131 struct dmabuf {
132 unsigned int dmanr;
133 unsigned sample_rate;
134 unsigned src_factor;
135 unsigned sample_size;
136 int num_channels;
137 int dma_bytes_per_sample;
138 int user_bytes_per_sample;
139 int cnt_factor;
140
141 void *rawbuf;
142 dma_addr_t dmaaddr;
143 unsigned buforder;
144 unsigned numfrag;
145 unsigned fragshift;
146 void *nextIn;
147 void *nextOut;
148 int count;
149 unsigned total_bytes;
150 unsigned error;
151 wait_queue_head_t wait;
152
153 unsigned fragsize;
154 unsigned dma_fragsize;
155 unsigned dmasize;
156
157
158 unsigned mapped:1;
159 unsigned ready:1;
160 unsigned stopped:1;
161 unsigned ossfragshift;
162 int ossmaxfrags;
163 unsigned subdivision;
164 } dma_dac , dma_adc;
165} au1000_state;
166
167
168
169
170static inline unsigned ld2(unsigned int x)
171{
172 unsigned r = 0;
173
174 if (x >= 0x10000) {
175 x >>= 16;
176 r += 16;
177 }
178 if (x >= 0x100) {
179 x >>= 8;
180 r += 8;
181 }
182 if (x >= 0x10) {
183 x >>= 4;
184 r += 4;
185 }
186 if (x >= 4) {
187 x >>= 2;
188 r += 2;
189 }
190 if (x >= 2)
191 r++;
192 return r;
193}
194
195
196#ifdef USE_COHERENT_DMA
197static inline void * dma_alloc(size_t size, dma_addr_t * dma_handle)
198{
199 void* ret = (void *)__get_free_pages(GFP_ATOMIC | GFP_DMA,
200 get_order(size));
201 if (ret != NULL) {
202 memset(ret, 0, size);
203 *dma_handle = virt_to_phys(ret);
204 }
205 return ret;
206}
207
208static inline void dma_free(size_t size, void* va, dma_addr_t dma_handle)
209{
210 free_pages((unsigned long)va, get_order(size));
211}
212#else
213static inline void * dma_alloc(size_t size, dma_addr_t * dma_handle)
214{
215 return pci_alloc_consistent(NULL, size, dma_handle);
216}
217
218static inline void dma_free(size_t size, void* va, dma_addr_t dma_handle)
219{
220 pci_free_consistent(NULL, size, va, dma_handle);
221}
222#endif
223
224
225
226static void au1000_delay(int msec)
227{
228 unsigned long tmo;
229 signed long tmo2;
230
231 if (in_interrupt())
232 return;
233
234 tmo = jiffies + (msec * HZ) / 1000;
235 for (;;) {
236 tmo2 = tmo - jiffies;
237 if (tmo2 <= 0)
238 break;
239 schedule_timeout(tmo2);
240 }
241}
242
243
244
245
246static u16 rdcodec(struct ac97_codec *codec, u8 addr)
247{
248 struct au1000_state *s = (struct au1000_state *)codec->private_data;
249 unsigned long flags;
250 u32 cmd;
251 u16 data;
252 int i;
253
254 spin_lock_irqsave(&s->lock, flags);
255
256 for (i = 0; i < POLL_COUNT; i++)
257 if (!(au_readl(AC97C_STATUS) & AC97C_CP))
258 break;
259 if (i == POLL_COUNT)
260 err("rdcodec: codec cmd pending expired!");
261
262 cmd = (u32) addr & AC97C_INDEX_MASK;
263 cmd |= AC97C_READ;
264 au_writel(cmd, AC97C_CMD);
265
266
267 for (i = 0; i < POLL_COUNT; i++)
268 if (!(au_readl(AC97C_STATUS) & AC97C_CP))
269 break;
270 if (i == POLL_COUNT) {
271 err("rdcodec: read poll expired!");
272 return 0;
273 }
274
275 data = au_readl(AC97C_CMD) & 0xffff;
276
277 spin_unlock_irqrestore(&s->lock, flags);
278
279 return data;
280}
281
282
283static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
284{
285 struct au1000_state *s = (struct au1000_state *)codec->private_data;
286 unsigned long flags;
287 u32 cmd;
288 int i;
289
290 spin_lock_irqsave(&s->lock, flags);
291
292 for (i = 0; i < POLL_COUNT; i++)
293 if (!(au_readl(AC97C_STATUS) & AC97C_CP))
294 break;
295 if (i == POLL_COUNT)
296 err("wrcodec: codec cmd pending expired!");
297
298 cmd = (u32) addr & AC97C_INDEX_MASK;
299 cmd &= ~AC97C_READ;
300 cmd |= ((u32) data << AC97C_WD_BIT);
301 au_writel(cmd, AC97C_CMD);
302
303 spin_unlock_irqrestore(&s->lock, flags);
304}
305
306static void waitcodec(struct ac97_codec *codec)
307{
308 u16 temp;
309 int i;
310
311
312
313 au1000_delay(10);
314
315
316 for (i = 0; i < POLL_COUNT; i++)
317 if (au_readl(AC97C_STATUS) & AC97C_READY)
318 break;
319 if (i == POLL_COUNT) {
320 err("waitcodec: CODEC_READY poll expired!");
321 return;
322 }
323
324 temp = rdcodec(codec, AC97_POWER_CONTROL);
325
326
327 if (temp & 0x7f00) {
328
329 wrcodec(codec, AC97_POWER_CONTROL, 0);
330 au1000_delay(100);
331
332 temp = rdcodec(codec, AC97_POWER_CONTROL);
333 }
334
335
336 if ((temp & 0x7f0f) != 0x000f)
337 err("codec reg 26 status (0x%x) not ready!!", temp);
338}
339
340
341
342
343
344static void set_adc_rate(struct au1000_state *s, unsigned rate)
345{
346 struct dmabuf *adc = &s->dma_adc;
347 struct dmabuf *dac = &s->dma_dac;
348 unsigned adc_rate, dac_rate;
349 u16 ac97_extstat;
350
351 if (s->no_vra) {
352
353 adc->src_factor = ((96000 / rate) + 1) >> 1;
354 adc->sample_rate = 48000 / adc->src_factor;
355 return;
356 }
357
358 adc->src_factor = 1;
359
360 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
361
362 rate = rate > 48000 ? 48000 : rate;
363
364
365 wrcodec(s->codec, AC97_EXTENDED_STATUS,
366 ac97_extstat | AC97_EXTSTAT_VRA);
367
368 wrcodec(s->codec, AC97_PCM_LR_ADC_RATE, (u16) rate);
369
370 adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
371
372#ifdef AU1000_VERBOSE_DEBUG
373 dbg(__FUNCTION__ ": set to %d Hz", adc_rate);
374#endif
375
376
377
378 dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
379 if (dac->num_channels > 2)
380 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, dac_rate);
381 if (dac->num_channels > 4)
382 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, dac_rate);
383
384 adc->sample_rate = adc_rate;
385 dac->sample_rate = dac_rate;
386}
387
388
389static void set_dac_rate(struct au1000_state *s, unsigned rate)
390{
391 struct dmabuf *dac = &s->dma_dac;
392 struct dmabuf *adc = &s->dma_adc;
393 unsigned adc_rate, dac_rate;
394 u16 ac97_extstat;
395
396 if (s->no_vra) {
397
398 dac->src_factor = ((96000 / rate) + 1) >> 1;
399 dac->sample_rate = 48000 / dac->src_factor;
400 return;
401 }
402
403 dac->src_factor = 1;
404
405 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
406
407 rate = rate > 48000 ? 48000 : rate;
408
409
410 wrcodec(s->codec, AC97_EXTENDED_STATUS,
411 ac97_extstat | AC97_EXTSTAT_VRA);
412
413 wrcodec(s->codec, AC97_PCM_FRONT_DAC_RATE, (u16) rate);
414
415
416 if (dac->num_channels > 2)
417 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, (u16) rate);
418 if (dac->num_channels > 4)
419 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, (u16) rate);
420
421 dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
422
423#ifdef AU1000_VERBOSE_DEBUG
424 dbg(__FUNCTION__ ": set to %d Hz", dac_rate);
425#endif
426
427
428
429 adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
430
431 dac->sample_rate = dac_rate;
432 adc->sample_rate = adc_rate;
433}
434
435static void stop_dac(struct au1000_state *s)
436{
437 struct dmabuf *db = &s->dma_dac;
438 unsigned long flags;
439
440 if (db->stopped)
441 return;
442
443 spin_lock_irqsave(&s->lock, flags);
444
445 disable_dma(db->dmanr);
446
447 db->stopped = 1;
448
449 spin_unlock_irqrestore(&s->lock, flags);
450}
451
452static void stop_adc(struct au1000_state *s)
453{
454 struct dmabuf *db = &s->dma_adc;
455 unsigned long flags;
456
457 if (db->stopped)
458 return;
459
460 spin_lock_irqsave(&s->lock, flags);
461
462 disable_dma(db->dmanr);
463
464 db->stopped = 1;
465
466 spin_unlock_irqrestore(&s->lock, flags);
467}
468
469
470static void set_xmit_slots(int num_channels)
471{
472 u32 ac97_config = au_readl(AC97C_CONFIG) & ~AC97C_XMIT_SLOTS_MASK;
473
474 switch (num_channels) {
475 case 1:
476 case 2:
477 ac97_config |= (0x3 << AC97C_XMIT_SLOTS_BIT);
478 break;
479 case 4:
480 ac97_config |= (0x33 << AC97C_XMIT_SLOTS_BIT);
481 break;
482 case 6:
483 ac97_config |= (0x7b << AC97C_XMIT_SLOTS_BIT);
484 break;
485 }
486
487 au_writel(ac97_config, AC97C_CONFIG);
488}
489
490static void set_recv_slots(int num_channels)
491{
492 u32 ac97_config = au_readl(AC97C_CONFIG) & ~AC97C_RECV_SLOTS_MASK;
493
494
495
496
497
498 ac97_config |= (0x3 << AC97C_RECV_SLOTS_BIT);
499
500 au_writel(ac97_config, AC97C_CONFIG);
501}
502
503static void start_dac(struct au1000_state *s)
504{
505 struct dmabuf *db = &s->dma_dac;
506 unsigned long flags;
507 unsigned long buf1, buf2;
508
509 if (!db->stopped)
510 return;
511
512 spin_lock_irqsave(&s->lock, flags);
513
514 au_readl(AC97C_STATUS);
515
516
517 buf1 = virt_to_phys(db->nextOut);
518 buf2 = buf1 + db->dma_fragsize;
519 if (buf2 >= db->dmaaddr + db->dmasize)
520 buf2 -= db->dmasize;
521
522 set_xmit_slots(db->num_channels);
523
524 init_dma(db->dmanr);
525 if (get_dma_active_buffer(db->dmanr) == 0) {
526 clear_dma_done0(db->dmanr);
527 set_dma_addr0(db->dmanr, buf1);
528 set_dma_addr1(db->dmanr, buf2);
529 } else {
530 clear_dma_done1(db->dmanr);
531 set_dma_addr1(db->dmanr, buf1);
532 set_dma_addr0(db->dmanr, buf2);
533 }
534 set_dma_count(db->dmanr, db->dma_fragsize>>1);
535 enable_dma_buffers(db->dmanr);
536
537 start_dma(db->dmanr);
538
539#ifdef AU1000_VERBOSE_DEBUG
540 dump_au1000_dma_channel(db->dmanr);
541#endif
542
543 db->stopped = 0;
544
545 spin_unlock_irqrestore(&s->lock, flags);
546}
547
548static void start_adc(struct au1000_state *s)
549{
550 struct dmabuf *db = &s->dma_adc;
551 unsigned long flags;
552 unsigned long buf1, buf2;
553
554 if (!db->stopped)
555 return;
556
557 spin_lock_irqsave(&s->lock, flags);
558
559 au_readl(AC97C_STATUS);
560
561
562 buf1 = virt_to_phys(db->nextIn);
563 buf2 = buf1 + db->dma_fragsize;
564 if (buf2 >= db->dmaaddr + db->dmasize)
565 buf2 -= db->dmasize;
566
567 set_recv_slots(db->num_channels);
568
569 init_dma(db->dmanr);
570 if (get_dma_active_buffer(db->dmanr) == 0) {
571 clear_dma_done0(db->dmanr);
572 set_dma_addr0(db->dmanr, buf1);
573 set_dma_addr1(db->dmanr, buf2);
574 } else {
575 clear_dma_done1(db->dmanr);
576 set_dma_addr1(db->dmanr, buf1);
577 set_dma_addr0(db->dmanr, buf2);
578 }
579 set_dma_count(db->dmanr, db->dma_fragsize>>1);
580 enable_dma_buffers(db->dmanr);
581
582 start_dma(db->dmanr);
583
584#ifdef AU1000_VERBOSE_DEBUG
585 dump_au1000_dma_channel(db->dmanr);
586#endif
587
588 db->stopped = 0;
589
590 spin_unlock_irqrestore(&s->lock, flags);
591}
592
593
594
595#define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
596#define DMABUF_MINORDER 1
597
598extern inline void dealloc_dmabuf(struct au1000_state *s, struct dmabuf *db)
599{
600 struct page *page, *pend;
601
602 if (db->rawbuf) {
603
604 pend = virt_to_page(db->rawbuf +
605 (PAGE_SIZE << db->buforder) - 1);
606 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
607 mem_map_unreserve(page);
608 dma_free(PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
609 }
610 db->rawbuf = db->nextIn = db->nextOut = NULL;
611 db->mapped = db->ready = 0;
612}
613
614static int prog_dmabuf(struct au1000_state *s, struct dmabuf *db)
615{
616 int order;
617 unsigned user_bytes_per_sec;
618 unsigned bufs;
619 struct page *page, *pend;
620 unsigned rate = db->sample_rate;
621
622 if (!db->rawbuf) {
623 db->ready = db->mapped = 0;
624 for (order = DMABUF_DEFAULTORDER;
625 order >= DMABUF_MINORDER; order--)
626 if ((db->rawbuf = dma_alloc(PAGE_SIZE << order,
627 &db->dmaaddr)))
628 break;
629 if (!db->rawbuf)
630 return -ENOMEM;
631 db->buforder = order;
632
633
634 pend = virt_to_page(db->rawbuf +
635 (PAGE_SIZE << db->buforder) - 1);
636 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
637 mem_map_reserve(page);
638 }
639
640 db->cnt_factor = 1;
641 if (db->sample_size == 8)
642 db->cnt_factor *= 2;
643 if (db->num_channels == 1)
644 db->cnt_factor *= 2;
645 db->cnt_factor *= db->src_factor;
646
647 db->count = 0;
648 db->nextIn = db->nextOut = db->rawbuf;
649
650 db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
651 db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
652 2 : db->num_channels);
653
654 user_bytes_per_sec = rate * db->user_bytes_per_sample;
655 bufs = PAGE_SIZE << db->buforder;
656 if (db->ossfragshift) {
657 if ((1000 << db->ossfragshift) < user_bytes_per_sec)
658 db->fragshift = ld2(user_bytes_per_sec/1000);
659 else
660 db->fragshift = db->ossfragshift;
661 } else {
662 db->fragshift = ld2(user_bytes_per_sec / 100 /
663 (db->subdivision ? db->subdivision : 1));
664 if (db->fragshift < 3)
665 db->fragshift = 3;
666 }
667
668 db->fragsize = 1 << db->fragshift;
669 db->dma_fragsize = db->fragsize * db->cnt_factor;
670 db->numfrag = bufs / db->dma_fragsize;
671
672 while (db->numfrag < 4 && db->fragshift > 3) {
673 db->fragshift--;
674 db->fragsize = 1 << db->fragshift;
675 db->dma_fragsize = db->fragsize * db->cnt_factor;
676 db->numfrag = bufs / db->dma_fragsize;
677 }
678
679 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
680 db->numfrag = db->ossmaxfrags;
681
682 db->dmasize = db->dma_fragsize * db->numfrag;
683 memset(db->rawbuf, 0, bufs);
684
685#ifdef AU1000_VERBOSE_DEBUG
686 dbg("rate=%d, samplesize=%d, channels=%d",
687 rate, db->sample_size, db->num_channels);
688 dbg("fragsize=%d, cnt_factor=%d, dma_fragsize=%d",
689 db->fragsize, db->cnt_factor, db->dma_fragsize);
690 dbg("numfrag=%d, dmasize=%d", db->numfrag, db->dmasize);
691#endif
692
693 db->ready = 1;
694 return 0;
695}
696
697extern inline int prog_dmabuf_adc(struct au1000_state *s)
698{
699 stop_adc(s);
700 return prog_dmabuf(s, &s->dma_adc);
701
702}
703
704extern inline int prog_dmabuf_dac(struct au1000_state *s)
705{
706 stop_dac(s);
707 return prog_dmabuf(s, &s->dma_dac);
708}
709
710
711
712static void dac_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
713{
714 struct au1000_state *s = (struct au1000_state *) dev_id;
715 struct dmabuf *dac = &s->dma_dac;
716 unsigned long newptr;
717 u32 ac97c_stat, buff_done;
718
719 ac97c_stat = au_readl(AC97C_STATUS);
720#ifdef AU1000_VERBOSE_DEBUG
721 if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE))
722 dbg("AC97C status = 0x%08x", ac97c_stat);
723#endif
724
725 if ((buff_done = get_dma_buffer_done(dac->dmanr)) == 0) {
726
727 return;
728 }
729
730 spin_lock(&s->lock);
731
732 if (buff_done != (DMA_D0 | DMA_D1)) {
733 dac->nextOut += dac->dma_fragsize;
734 if (dac->nextOut >= dac->rawbuf + dac->dmasize)
735 dac->nextOut -= dac->dmasize;
736
737
738 newptr = virt_to_phys(dac->nextOut) + dac->dma_fragsize;
739 if (newptr >= dac->dmaaddr + dac->dmasize)
740 newptr -= dac->dmasize;
741
742 dac->count -= dac->dma_fragsize;
743 dac->total_bytes += dac->dma_fragsize;
744
745 if (dac->count <= 0) {
746#ifdef AU1000_VERBOSE_DEBUG
747 dbg("dac underrun");
748#endif
749 spin_unlock(&s->lock);
750 stop_dac(s);
751 spin_lock(&s->lock);
752 dac->count = 0;
753 dac->nextIn = dac->nextOut;
754 } else if (buff_done == DMA_D0) {
755 clear_dma_done0(dac->dmanr);
756 set_dma_count0(dac->dmanr, dac->dma_fragsize>>1);
757 set_dma_addr0(dac->dmanr, newptr);
758 enable_dma_buffer0(dac->dmanr);
759 } else {
760 clear_dma_done1(dac->dmanr);
761 set_dma_count1(dac->dmanr, dac->dma_fragsize>>1);
762 set_dma_addr1(dac->dmanr, newptr);
763 enable_dma_buffer1(dac->dmanr);
764 }
765 } else {
766
767 spin_unlock(&s->lock);
768 stop_dac(s);
769 spin_lock(&s->lock);
770
771 dac->nextOut += 2*dac->dma_fragsize;
772 if (dac->nextOut >= dac->rawbuf + dac->dmasize)
773 dac->nextOut -= dac->dmasize;
774
775 dac->count -= 2*dac->dma_fragsize;
776 dac->total_bytes += 2*dac->dma_fragsize;
777
778 if (dac->count > 0) {
779 spin_unlock(&s->lock);
780 start_dac(s);
781 spin_lock(&s->lock);
782 }
783 }
784
785
786 if (waitqueue_active(&dac->wait))
787 wake_up(&dac->wait);
788
789 spin_unlock(&s->lock);
790}
791
792
793static void adc_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
794{
795 struct au1000_state *s = (struct au1000_state *) dev_id;
796 struct dmabuf *adc = &s->dma_adc;
797 unsigned long newptr;
798 u32 ac97c_stat, buff_done;
799
800 ac97c_stat = au_readl(AC97C_STATUS);
801#ifdef AU1000_VERBOSE_DEBUG
802 if (ac97c_stat & (AC97C_RU | AC97C_RO))
803 dbg("AC97C status = 0x%08x", ac97c_stat);
804#endif
805
806 if ((buff_done = get_dma_buffer_done(adc->dmanr)) == 0) {
807
808 return;
809 }
810
811 spin_lock(&s->lock);
812
813 if (buff_done != (DMA_D0 | DMA_D1)) {
814 if (adc->count + adc->dma_fragsize > adc->dmasize) {
815
816 spin_unlock(&s->lock);
817 stop_adc(s);
818 adc->error++;
819 err("adc overrun");
820 return;
821 }
822
823 adc->nextIn += adc->dma_fragsize;
824 if (adc->nextIn >= adc->rawbuf + adc->dmasize)
825 adc->nextIn -= adc->dmasize;
826
827
828 newptr = virt_to_phys(adc->nextIn) + adc->dma_fragsize;
829 if (newptr >= adc->dmaaddr + adc->dmasize)
830 newptr -= adc->dmasize;
831
832 adc->count += adc->dma_fragsize;
833 adc->total_bytes += adc->dma_fragsize;
834
835 if (buff_done == DMA_D0) {
836 clear_dma_done0(adc->dmanr);
837 set_dma_count0(adc->dmanr, adc->dma_fragsize>>1);
838 set_dma_addr0(adc->dmanr, newptr);
839 enable_dma_buffer0(adc->dmanr);
840 } else {
841 clear_dma_done1(adc->dmanr);
842 set_dma_count1(adc->dmanr, adc->dma_fragsize>>1);
843 set_dma_addr1(adc->dmanr, newptr);
844 enable_dma_buffer1(adc->dmanr);
845 }
846 } else {
847
848 spin_unlock(&s->lock);
849 stop_adc(s);
850 spin_lock(&s->lock);
851
852 if (adc->count + 2*adc->dma_fragsize > adc->dmasize) {
853
854 adc->error++;
855 err("adc overrun");
856 spin_unlock(&s->lock);
857 return;
858 }
859
860 adc->nextIn += 2*adc->dma_fragsize;
861 if (adc->nextIn >= adc->rawbuf + adc->dmasize)
862 adc->nextIn -= adc->dmasize;
863
864 adc->count += 2*adc->dma_fragsize;
865 adc->total_bytes += 2*adc->dma_fragsize;
866
867 spin_unlock(&s->lock);
868 start_adc(s);
869 spin_lock(&s->lock);
870 }
871
872
873 if (waitqueue_active(&adc->wait))
874 wake_up(&adc->wait);
875
876 spin_unlock(&s->lock);
877}
878
879
880
881static loff_t au1000_llseek(struct file *file, loff_t offset, int origin)
882{
883 return -ESPIPE;
884}
885
886
887static int au1000_open_mixdev(struct inode *inode, struct file *file)
888{
889 file->private_data = &au1000_state;
890 return 0;
891}
892
893static int au1000_release_mixdev(struct inode *inode, struct file *file)
894{
895 return 0;
896}
897
898static int mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
899 unsigned long arg)
900{
901 return codec->mixer_ioctl(codec, cmd, arg);
902}
903
904static int au1000_ioctl_mixdev(struct inode *inode, struct file *file,
905 unsigned int cmd, unsigned long arg)
906{
907 struct au1000_state *s = (struct au1000_state *)file->private_data;
908 struct ac97_codec *codec = s->codec;
909
910 return mixdev_ioctl(codec, cmd, arg);
911}
912
913static struct file_operations au1000_mixer_fops = {
914 owner:THIS_MODULE,
915 llseek:au1000_llseek,
916 ioctl:au1000_ioctl_mixdev,
917 open:au1000_open_mixdev,
918 release:au1000_release_mixdev,
919};
920
921
922
923static int drain_dac(struct au1000_state *s, int nonblock)
924{
925 unsigned long flags;
926 int count, tmo;
927
928 if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
929 return 0;
930
931 for (;;) {
932 spin_lock_irqsave(&s->lock, flags);
933 count = s->dma_dac.count;
934 spin_unlock_irqrestore(&s->lock, flags);
935 if (count <= 0)
936 break;
937 if (signal_pending(current))
938 break;
939 if (nonblock)
940 return -EBUSY;
941 tmo = 1000 * count / (s->no_vra ?
942 48000 : s->dma_dac.sample_rate);
943 tmo /= s->dma_dac.dma_bytes_per_sample;
944 au1000_delay(tmo);
945 }
946 if (signal_pending(current))
947 return -ERESTARTSYS;
948 return 0;
949}
950
951
952
953static inline u8 S16_TO_U8(s16 ch)
954{
955 return (u8) (ch >> 8) + 0x80;
956}
957static inline s16 U8_TO_S16(u8 ch)
958{
959 return (s16) (ch - 0x80) << 8;
960}
961
962
963
964
965
966
967
968static int translate_from_user(struct dmabuf *db,
969 char* dmabuf,
970 char* userbuf,
971 int dmacount)
972{
973 int sample, i;
974 int interp_bytes_per_sample;
975 int num_samples;
976 int mono = (db->num_channels == 1);
977 char usersample[12];
978 s16 ch, dmasample[6];
979
980 if (db->sample_size == 16 && !mono && db->src_factor == 1) {
981
982 if (copy_from_user(dmabuf, userbuf, dmacount))
983 return -EFAULT;
984 return dmacount;
985 }
986
987 interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
988 num_samples = dmacount / interp_bytes_per_sample;
989
990 for (sample = 0; sample < num_samples; sample++) {
991 if (copy_from_user(usersample, userbuf,
992 db->user_bytes_per_sample)) {
993 dbg(__FUNCTION__ ": fault");
994 return -EFAULT;
995 }
996
997 for (i = 0; i < db->num_channels; i++) {
998 if (db->sample_size == 8)
999 ch = U8_TO_S16(usersample[i]);
1000 else
1001 ch = *((s16 *) (&usersample[i * 2]));
1002 dmasample[i] = ch;
1003 if (mono)
1004 dmasample[i + 1] = ch;
1005 }
1006
1007
1008 for (i = 0; i < db->src_factor; i++)
1009 memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
1010
1011 userbuf += db->user_bytes_per_sample;
1012 dmabuf += interp_bytes_per_sample;
1013 }
1014
1015 return num_samples * interp_bytes_per_sample;
1016}
1017
1018
1019
1020
1021
1022
1023
1024static int translate_to_user(struct dmabuf *db,
1025 char* userbuf,
1026 char* dmabuf,
1027 int dmacount)
1028{
1029 int sample, i;
1030 int interp_bytes_per_sample;
1031 int num_samples;
1032 int mono = (db->num_channels == 1);
1033 char usersample[12];
1034
1035 if (db->sample_size == 16 && !mono && db->src_factor == 1) {
1036
1037 if (copy_to_user(userbuf, dmabuf, dmacount))
1038 return -EFAULT;
1039 return dmacount;
1040 }
1041
1042 interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
1043 num_samples = dmacount / interp_bytes_per_sample;
1044
1045 for (sample = 0; sample < num_samples; sample++) {
1046 for (i = 0; i < db->num_channels; i++) {
1047 if (db->sample_size == 8)
1048 usersample[i] =
1049 S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
1050 else
1051 *((s16 *) (&usersample[i * 2])) =
1052 *((s16 *) (&dmabuf[i * 2]));
1053 }
1054
1055 if (copy_to_user(userbuf, usersample,
1056 db->user_bytes_per_sample)) {
1057 dbg(__FUNCTION__ ": fault");
1058 return -EFAULT;
1059 }
1060
1061 userbuf += db->user_bytes_per_sample;
1062 dmabuf += interp_bytes_per_sample;
1063 }
1064
1065 return num_samples * interp_bytes_per_sample;
1066}
1067
1068
1069
1070
1071
1072
1073static int copy_dmabuf_user(struct dmabuf *db, char* userbuf,
1074 int count, int to_user)
1075{
1076 char *bufptr = to_user ? db->nextOut : db->nextIn;
1077 char *bufend = db->rawbuf + db->dmasize;
1078 int cnt, ret;
1079
1080 if (bufptr + count > bufend) {
1081 int partial = (int) (bufend - bufptr);
1082 if (to_user) {
1083 if ((cnt = translate_to_user(db, userbuf,
1084 bufptr, partial)) < 0)
1085 return cnt;
1086 ret = cnt;
1087 if ((cnt = translate_to_user(db, userbuf + partial,
1088 db->rawbuf,
1089 count - partial)) < 0)
1090 return cnt;
1091 ret += cnt;
1092 } else {
1093 if ((cnt = translate_from_user(db, bufptr, userbuf,
1094 partial)) < 0)
1095 return cnt;
1096 ret = cnt;
1097 if ((cnt = translate_from_user(db, db->rawbuf,
1098 userbuf + partial,
1099 count - partial)) < 0)
1100 return cnt;
1101 ret += cnt;
1102 }
1103 } else {
1104 if (to_user)
1105 ret = translate_to_user(db, userbuf, bufptr, count);
1106 else
1107 ret = translate_from_user(db, bufptr, userbuf, count);
1108 }
1109
1110 return ret;
1111}
1112
1113
1114static ssize_t au1000_read(struct file *file, char *buffer,
1115 size_t count, loff_t *ppos)
1116{
1117 struct au1000_state *s = (struct au1000_state *)file->private_data;
1118 struct dmabuf *db = &s->dma_adc;
1119 DECLARE_WAITQUEUE(wait, current);
1120 ssize_t ret;
1121 unsigned long flags;
1122 int cnt, usercnt, avail;
1123
1124 if (ppos != &file->f_pos)
1125 return -ESPIPE;
1126 if (db->mapped)
1127 return -ENXIO;
1128 if (!access_ok(VERIFY_WRITE, buffer, count))
1129 return -EFAULT;
1130 ret = 0;
1131
1132 count *= db->cnt_factor;
1133
1134 down(&s->sem);
1135 add_wait_queue(&db->wait, &wait);
1136
1137 while (count > 0) {
1138
1139 do {
1140 if (db->stopped)
1141 start_adc(s);
1142 spin_lock_irqsave(&s->lock, flags);
1143 avail = db->count;
1144 if (avail <= 0)
1145 __set_current_state(TASK_INTERRUPTIBLE);
1146 spin_unlock_irqrestore(&s->lock, flags);
1147 if (avail <= 0) {
1148 if (file->f_flags & O_NONBLOCK) {
1149 if (!ret)
1150 ret = -EAGAIN;
1151 goto out;
1152 }
1153 up(&s->sem);
1154 schedule();
1155 if (signal_pending(current)) {
1156 if (!ret)
1157 ret = -ERESTARTSYS;
1158 goto out2;
1159 }
1160 down(&s->sem);
1161 }
1162 } while (avail <= 0);
1163
1164
1165 if ((cnt = copy_dmabuf_user(db, buffer,
1166 count > avail ?
1167 avail : count, 1)) < 0) {
1168 if (!ret)
1169 ret = -EFAULT;
1170 goto out;
1171 }
1172
1173 spin_lock_irqsave(&s->lock, flags);
1174 db->count -= cnt;
1175 db->nextOut += cnt;
1176 if (db->nextOut >= db->rawbuf + db->dmasize)
1177 db->nextOut -= db->dmasize;
1178 spin_unlock_irqrestore(&s->lock, flags);
1179
1180 count -= cnt;
1181 usercnt = cnt / db->cnt_factor;
1182 buffer += usercnt;
1183 ret += usercnt;
1184 }
1185
1186out:
1187 up(&s->sem);
1188out2:
1189 remove_wait_queue(&db->wait, &wait);
1190 set_current_state(TASK_RUNNING);
1191 return ret;
1192}
1193
1194static ssize_t au1000_write(struct file *file, const char *buffer,
1195 size_t count, loff_t * ppos)
1196{
1197 struct au1000_state *s = (struct au1000_state *)file->private_data;
1198 struct dmabuf *db = &s->dma_dac;
1199 DECLARE_WAITQUEUE(wait, current);
1200 ssize_t ret = 0;
1201 unsigned long flags;
1202 int cnt, usercnt, avail;
1203
1204#ifdef AU1000_VERBOSE_DEBUG
1205 dbg("write: count=%d", count);
1206#endif
1207
1208 if (ppos != &file->f_pos)
1209 return -ESPIPE;
1210 if (db->mapped)
1211 return -ENXIO;
1212 if (!access_ok(VERIFY_READ, buffer, count))
1213 return -EFAULT;
1214
1215 count *= db->cnt_factor;
1216
1217 down(&s->sem);
1218 add_wait_queue(&db->wait, &wait);
1219
1220 while (count > 0) {
1221
1222 do {
1223 spin_lock_irqsave(&s->lock, flags);
1224 avail = (int) db->dmasize - db->count;
1225 if (avail <= 0)
1226 __set_current_state(TASK_INTERRUPTIBLE);
1227 spin_unlock_irqrestore(&s->lock, flags);
1228 if (avail <= 0) {
1229 if (file->f_flags & O_NONBLOCK) {
1230 if (!ret)
1231 ret = -EAGAIN;
1232 goto out;
1233 }
1234 up(&s->sem);
1235 schedule();
1236 if (signal_pending(current)) {
1237 if (!ret)
1238 ret = -ERESTARTSYS;
1239 goto out2;
1240 }
1241 down(&s->sem);
1242 }
1243 } while (avail <= 0);
1244
1245
1246 if ((cnt = copy_dmabuf_user(db, (char *) buffer,
1247 count > avail ?
1248 avail : count, 0)) < 0) {
1249 if (!ret)
1250 ret = -EFAULT;
1251 goto out;
1252 }
1253
1254 spin_lock_irqsave(&s->lock, flags);
1255 db->count += cnt;
1256 db->nextIn += cnt;
1257 if (db->nextIn >= db->rawbuf + db->dmasize)
1258 db->nextIn -= db->dmasize;
1259 spin_unlock_irqrestore(&s->lock, flags);
1260 if (db->stopped)
1261 start_dac(s);
1262
1263 count -= cnt;
1264 usercnt = cnt / db->cnt_factor;
1265 buffer += usercnt;
1266 ret += usercnt;
1267 }
1268
1269out:
1270 up(&s->sem);
1271out2:
1272 remove_wait_queue(&db->wait, &wait);
1273 set_current_state(TASK_RUNNING);
1274 return ret;
1275}
1276
1277
1278
1279static unsigned int au1000_poll(struct file *file,
1280 struct poll_table_struct *wait)
1281{
1282 struct au1000_state *s = (struct au1000_state *)file->private_data;
1283 unsigned long flags;
1284 unsigned int mask = 0;
1285
1286 if (file->f_mode & FMODE_WRITE) {
1287 if (!s->dma_dac.ready)
1288 return 0;
1289 poll_wait(file, &s->dma_dac.wait, wait);
1290 }
1291 if (file->f_mode & FMODE_READ) {
1292 if (!s->dma_adc.ready)
1293 return 0;
1294 poll_wait(file, &s->dma_adc.wait, wait);
1295 }
1296
1297 spin_lock_irqsave(&s->lock, flags);
1298
1299 if (file->f_mode & FMODE_READ) {
1300 if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
1301 mask |= POLLIN | POLLRDNORM;
1302 }
1303 if (file->f_mode & FMODE_WRITE) {
1304 if (s->dma_dac.mapped) {
1305 if (s->dma_dac.count >=
1306 (signed)s->dma_dac.dma_fragsize)
1307 mask |= POLLOUT | POLLWRNORM;
1308 } else {
1309 if ((signed) s->dma_dac.dmasize >=
1310 s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
1311 mask |= POLLOUT | POLLWRNORM;
1312 }
1313 }
1314 spin_unlock_irqrestore(&s->lock, flags);
1315 return mask;
1316}
1317
1318static int au1000_mmap(struct file *file, struct vm_area_struct *vma)
1319{
1320 struct au1000_state *s = (struct au1000_state *)file->private_data;
1321 struct dmabuf *db;
1322 unsigned long size;
1323 int ret = 0;
1324
1325 dbg(__FUNCTION__);
1326
1327 lock_kernel();
1328 down(&s->sem);
1329 if (vma->vm_flags & VM_WRITE)
1330 db = &s->dma_dac;
1331 else if (vma->vm_flags & VM_READ)
1332 db = &s->dma_adc;
1333 else {
1334 ret = -EINVAL;
1335 goto out;
1336 }
1337 if (vma->vm_pgoff != 0) {
1338 ret = -EINVAL;
1339 goto out;
1340 }
1341 size = vma->vm_end - vma->vm_start;
1342 if (size > (PAGE_SIZE << db->buforder)) {
1343 ret = -EINVAL;
1344 goto out;
1345 }
1346 if (remap_page_range(vma->vm_start, virt_to_phys(db->rawbuf),
1347 size, vma->vm_page_prot)) {
1348 ret = -EAGAIN;
1349 goto out;
1350 }
1351 vma->vm_flags &= ~VM_IO;
1352 db->mapped = 1;
1353out:
1354 up(&s->sem);
1355 unlock_kernel();
1356 return ret;
1357}
1358
1359
1360#ifdef AU1000_VERBOSE_DEBUG
1361static struct ioctl_str_t {
1362 unsigned int cmd;
1363 const char *str;
1364} ioctl_str[] = {
1365 {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
1366 {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
1367 {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
1368 {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
1369 {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
1370 {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
1371 {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
1372 {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
1373 {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
1374 {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
1375 {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
1376 {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
1377 {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
1378 {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
1379 {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
1380 {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
1381 {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
1382 {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
1383 {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
1384 {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
1385 {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
1386 {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
1387 {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
1388 {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
1389 {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
1390 {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
1391 {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
1392 {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
1393 {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
1394 {OSS_GETVERSION, "OSS_GETVERSION"},
1395 {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
1396 {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
1397 {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
1398 {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
1399};
1400#endif
1401
1402
1403static int dma_count_done(struct dmabuf *db)
1404{
1405 if (db->stopped)
1406 return 0;
1407
1408 return db->dma_fragsize - get_dma_residue(db->dmanr);
1409}
1410
1411
1412static int au1000_ioctl(struct inode *inode, struct file *file,
1413 unsigned int cmd, unsigned long arg)
1414{
1415 struct au1000_state *s = (struct au1000_state *)file->private_data;
1416 unsigned long flags;
1417 audio_buf_info abinfo;
1418 count_info cinfo;
1419 int count;
1420 int val, mapped, ret, diff;
1421
1422 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1423 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1424
1425#ifdef AU1000_VERBOSE_DEBUG
1426 for (count=0; count<sizeof(ioctl_str)/sizeof(ioctl_str[0]); count++) {
1427 if (ioctl_str[count].cmd == cmd)
1428 break;
1429 }
1430 if (count < sizeof(ioctl_str) / sizeof(ioctl_str[0]))
1431 dbg("ioctl %s, arg=0x%lx", ioctl_str[count].str, arg);
1432 else
1433 dbg("ioctl 0x%x unknown, arg=0x%lx", cmd, arg);
1434#endif
1435
1436 switch (cmd) {
1437 case OSS_GETVERSION:
1438 return put_user(SOUND_VERSION, (int *) arg);
1439
1440 case SNDCTL_DSP_SYNC:
1441 if (file->f_mode & FMODE_WRITE)
1442 return drain_dac(s, file->f_flags & O_NONBLOCK);
1443 return 0;
1444
1445 case SNDCTL_DSP_SETDUPLEX:
1446 return 0;
1447
1448 case SNDCTL_DSP_GETCAPS:
1449 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1450 DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1451
1452 case SNDCTL_DSP_RESET:
1453 if (file->f_mode & FMODE_WRITE) {
1454 stop_dac(s);
1455 synchronize_irq();
1456 s->dma_dac.count = s->dma_dac.total_bytes = 0;
1457 s->dma_dac.nextIn = s->dma_dac.nextOut =
1458 s->dma_dac.rawbuf;
1459 }
1460 if (file->f_mode & FMODE_READ) {
1461 stop_adc(s);
1462 synchronize_irq();
1463 s->dma_adc.count = s->dma_adc.total_bytes = 0;
1464 s->dma_adc.nextIn = s->dma_adc.nextOut =
1465 s->dma_adc.rawbuf;
1466 }
1467 return 0;
1468
1469 case SNDCTL_DSP_SPEED:
1470 if (get_user(val, (int *) arg))
1471 return -EFAULT;
1472 if (val >= 0) {
1473 if (file->f_mode & FMODE_READ) {
1474 stop_adc(s);
1475 set_adc_rate(s, val);
1476 }
1477 if (file->f_mode & FMODE_WRITE) {
1478 stop_dac(s);
1479 set_dac_rate(s, val);
1480 }
1481 if (s->open_mode & FMODE_READ)
1482 if ((ret = prog_dmabuf_adc(s)))
1483 return ret;
1484 if (s->open_mode & FMODE_WRITE)
1485 if ((ret = prog_dmabuf_dac(s)))
1486 return ret;
1487 }
1488 return put_user((file->f_mode & FMODE_READ) ?
1489 s->dma_adc.sample_rate :
1490 s->dma_dac.sample_rate,
1491 (int *)arg);
1492
1493 case SNDCTL_DSP_STEREO:
1494 if (get_user(val, (int *) arg))
1495 return -EFAULT;
1496 if (file->f_mode & FMODE_READ) {
1497 stop_adc(s);
1498 s->dma_adc.num_channels = val ? 2 : 1;
1499 if ((ret = prog_dmabuf_adc(s)))
1500 return ret;
1501 }
1502 if (file->f_mode & FMODE_WRITE) {
1503 stop_dac(s);
1504 s->dma_dac.num_channels = val ? 2 : 1;
1505 if (s->codec_ext_caps & AC97_EXT_DACS) {
1506
1507 u16 ext_stat = rdcodec(s->codec,
1508 AC97_EXTENDED_STATUS);
1509 wrcodec(s->codec, AC97_EXTENDED_STATUS,
1510 ext_stat | (AC97_EXTSTAT_PRI |
1511 AC97_EXTSTAT_PRJ |
1512 AC97_EXTSTAT_PRK));
1513 }
1514 if ((ret = prog_dmabuf_dac(s)))
1515 return ret;
1516 }
1517 return 0;
1518
1519 case SNDCTL_DSP_CHANNELS:
1520 if (get_user(val, (int *) arg))
1521 return -EFAULT;
1522 if (val != 0) {
1523 if (file->f_mode & FMODE_READ) {
1524 if (val < 0 || val > 2)
1525 return -EINVAL;
1526 stop_adc(s);
1527 s->dma_adc.num_channels = val;
1528 if ((ret = prog_dmabuf_adc(s)))
1529 return ret;
1530 }
1531 if (file->f_mode & FMODE_WRITE) {
1532 switch (val) {
1533 case 1:
1534 case 2:
1535 break;
1536 case 3:
1537 case 5:
1538 return -EINVAL;
1539 case 4:
1540 if (!(s->codec_ext_caps &
1541 AC97_EXTID_SDAC))
1542 return -EINVAL;
1543 break;
1544 case 6:
1545 if ((s->codec_ext_caps &
1546 AC97_EXT_DACS) != AC97_EXT_DACS)
1547 return -EINVAL;
1548 break;
1549 default:
1550 return -EINVAL;
1551 }
1552
1553 stop_dac(s);
1554 if (val <= 2 &&
1555 (s->codec_ext_caps & AC97_EXT_DACS)) {
1556
1557
1558 u16 ext_stat =
1559 rdcodec(s->codec,
1560 AC97_EXTENDED_STATUS);
1561 wrcodec(s->codec,
1562 AC97_EXTENDED_STATUS,
1563 ext_stat | (AC97_EXTSTAT_PRI |
1564 AC97_EXTSTAT_PRJ |
1565 AC97_EXTSTAT_PRK));
1566 } else if (val >= 4) {
1567
1568
1569 u16 ext_stat =
1570 rdcodec(s->codec,
1571 AC97_EXTENDED_STATUS);
1572 ext_stat &= ~AC97_EXTSTAT_PRJ;
1573 if (val == 6)
1574 ext_stat &=
1575 ~(AC97_EXTSTAT_PRI |
1576 AC97_EXTSTAT_PRK);
1577 wrcodec(s->codec,
1578 AC97_EXTENDED_STATUS,
1579 ext_stat);
1580 }
1581
1582 s->dma_dac.num_channels = val;
1583 if ((ret = prog_dmabuf_dac(s)))
1584 return ret;
1585 }
1586 }
1587 return put_user(val, (int *) arg);
1588
1589 case SNDCTL_DSP_GETFMTS:
1590 return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
1591
1592 case SNDCTL_DSP_SETFMT:
1593 if (get_user(val, (int *) arg))
1594 return -EFAULT;
1595 if (val != AFMT_QUERY) {
1596 if (file->f_mode & FMODE_READ) {
1597 stop_adc(s);
1598 if (val == AFMT_S16_LE)
1599 s->dma_adc.sample_size = 16;
1600 else {
1601 val = AFMT_U8;
1602 s->dma_adc.sample_size = 8;
1603 }
1604 if ((ret = prog_dmabuf_adc(s)))
1605 return ret;
1606 }
1607 if (file->f_mode & FMODE_WRITE) {
1608 stop_dac(s);
1609 if (val == AFMT_S16_LE)
1610 s->dma_dac.sample_size = 16;
1611 else {
1612 val = AFMT_U8;
1613 s->dma_dac.sample_size = 8;
1614 }
1615 if ((ret = prog_dmabuf_dac(s)))
1616 return ret;
1617 }
1618 } else {
1619 if (file->f_mode & FMODE_READ)
1620 val = (s->dma_adc.sample_size == 16) ?
1621 AFMT_S16_LE : AFMT_U8;
1622 else
1623 val = (s->dma_dac.sample_size == 16) ?
1624 AFMT_S16_LE : AFMT_U8;
1625 }
1626 return put_user(val, (int *) arg);
1627
1628 case SNDCTL_DSP_POST:
1629 return 0;
1630
1631 case SNDCTL_DSP_GETTRIGGER:
1632 val = 0;
1633 spin_lock_irqsave(&s->lock, flags);
1634 if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
1635 val |= PCM_ENABLE_INPUT;
1636 if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
1637 val |= PCM_ENABLE_OUTPUT;
1638 spin_unlock_irqrestore(&s->lock, flags);
1639 return put_user(val, (int *) arg);
1640
1641 case SNDCTL_DSP_SETTRIGGER:
1642 if (get_user(val, (int *) arg))
1643 return -EFAULT;
1644 if (file->f_mode & FMODE_READ) {
1645 if (val & PCM_ENABLE_INPUT)
1646 start_adc(s);
1647 else
1648 stop_adc(s);
1649 }
1650 if (file->f_mode & FMODE_WRITE) {
1651 if (val & PCM_ENABLE_OUTPUT)
1652 start_dac(s);
1653 else
1654 stop_dac(s);
1655 }
1656 return 0;
1657
1658 case SNDCTL_DSP_GETOSPACE:
1659 if (!(file->f_mode & FMODE_WRITE))
1660 return -EINVAL;
1661 abinfo.fragsize = s->dma_dac.fragsize;
1662 spin_lock_irqsave(&s->lock, flags);
1663 count = s->dma_dac.count;
1664 count -= dma_count_done(&s->dma_dac);
1665 spin_unlock_irqrestore(&s->lock, flags);
1666 if (count < 0)
1667 count = 0;
1668 abinfo.bytes = (s->dma_dac.dmasize - count) /
1669 s->dma_dac.cnt_factor;
1670 abinfo.fragstotal = s->dma_dac.numfrag;
1671 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1672#ifdef AU1000_VERBOSE_DEBUG
1673 dbg("bytes=%d, fragments=%d", abinfo.bytes, abinfo.fragments);
1674#endif
1675 return copy_to_user((void *) arg, &abinfo,
1676 sizeof(abinfo)) ? -EFAULT : 0;
1677
1678 case SNDCTL_DSP_GETISPACE:
1679 if (!(file->f_mode & FMODE_READ))
1680 return -EINVAL;
1681 abinfo.fragsize = s->dma_adc.fragsize;
1682 spin_lock_irqsave(&s->lock, flags);
1683 count = s->dma_adc.count;
1684 count += dma_count_done(&s->dma_adc);
1685 spin_unlock_irqrestore(&s->lock, flags);
1686 if (count < 0)
1687 count = 0;
1688 abinfo.bytes = count / s->dma_adc.cnt_factor;
1689 abinfo.fragstotal = s->dma_adc.numfrag;
1690 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1691 return copy_to_user((void *) arg, &abinfo,
1692 sizeof(abinfo)) ? -EFAULT : 0;
1693
1694 case SNDCTL_DSP_NONBLOCK:
1695 file->f_flags |= O_NONBLOCK;
1696 return 0;
1697
1698 case SNDCTL_DSP_GETODELAY:
1699 if (!(file->f_mode & FMODE_WRITE))
1700 return -EINVAL;
1701 spin_lock_irqsave(&s->lock, flags);
1702 count = s->dma_dac.count;
1703 count -= dma_count_done(&s->dma_dac);
1704 spin_unlock_irqrestore(&s->lock, flags);
1705 if (count < 0)
1706 count = 0;
1707 count /= s->dma_dac.cnt_factor;
1708 return put_user(count, (int *) arg);
1709
1710 case SNDCTL_DSP_GETIPTR:
1711 if (!(file->f_mode & FMODE_READ))
1712 return -EINVAL;
1713 spin_lock_irqsave(&s->lock, flags);
1714 cinfo.bytes = s->dma_adc.total_bytes;
1715 count = s->dma_adc.count;
1716 if (!s->dma_adc.stopped) {
1717 diff = dma_count_done(&s->dma_adc);
1718 count += diff;
1719 cinfo.bytes += diff;
1720 cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) + diff -
1721 s->dma_adc.dmaaddr;
1722 } else
1723 cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
1724 s->dma_adc.dmaaddr;
1725 if (s->dma_adc.mapped)
1726 s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
1727 spin_unlock_irqrestore(&s->lock, flags);
1728 if (count < 0)
1729 count = 0;
1730 cinfo.blocks = count >> s->dma_adc.fragshift;
1731 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1732
1733 case SNDCTL_DSP_GETOPTR:
1734 if (!(file->f_mode & FMODE_READ))
1735 return -EINVAL;
1736 spin_lock_irqsave(&s->lock, flags);
1737 cinfo.bytes = s->dma_dac.total_bytes;
1738 count = s->dma_dac.count;
1739 if (!s->dma_dac.stopped) {
1740 diff = dma_count_done(&s->dma_dac);
1741 count -= diff;
1742 cinfo.bytes += diff;
1743 cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
1744 s->dma_dac.dmaaddr;
1745 } else
1746 cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
1747 s->dma_dac.dmaaddr;
1748 if (s->dma_dac.mapped)
1749 s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
1750 spin_unlock_irqrestore(&s->lock, flags);
1751 if (count < 0)
1752 count = 0;
1753 cinfo.blocks = count >> s->dma_dac.fragshift;
1754 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1755
1756 case SNDCTL_DSP_GETBLKSIZE:
1757 if (file->f_mode & FMODE_WRITE)
1758 return put_user(s->dma_dac.fragsize, (int *) arg);
1759 else
1760 return put_user(s->dma_adc.fragsize, (int *) arg);
1761
1762 case SNDCTL_DSP_SETFRAGMENT:
1763 if (get_user(val, (int *) arg))
1764 return -EFAULT;
1765 if (file->f_mode & FMODE_READ) {
1766 stop_adc(s);
1767 s->dma_adc.ossfragshift = val & 0xffff;
1768 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1769 if (s->dma_adc.ossfragshift < 4)
1770 s->dma_adc.ossfragshift = 4;
1771 if (s->dma_adc.ossfragshift > 15)
1772 s->dma_adc.ossfragshift = 15;
1773 if (s->dma_adc.ossmaxfrags < 4)
1774 s->dma_adc.ossmaxfrags = 4;
1775 if ((ret = prog_dmabuf_adc(s)))
1776 return ret;
1777 }
1778 if (file->f_mode & FMODE_WRITE) {
1779 stop_dac(s);
1780 s->dma_dac.ossfragshift = val & 0xffff;
1781 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1782 if (s->dma_dac.ossfragshift < 4)
1783 s->dma_dac.ossfragshift = 4;
1784 if (s->dma_dac.ossfragshift > 15)
1785 s->dma_dac.ossfragshift = 15;
1786 if (s->dma_dac.ossmaxfrags < 4)
1787 s->dma_dac.ossmaxfrags = 4;
1788 if ((ret = prog_dmabuf_dac(s)))
1789 return ret;
1790 }
1791 return 0;
1792
1793 case SNDCTL_DSP_SUBDIVIDE:
1794 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1795 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1796 return -EINVAL;
1797 if (get_user(val, (int *) arg))
1798 return -EFAULT;
1799 if (val != 1 && val != 2 && val != 4)
1800 return -EINVAL;
1801 if (file->f_mode & FMODE_READ) {
1802 stop_adc(s);
1803 s->dma_adc.subdivision = val;
1804 if ((ret = prog_dmabuf_adc(s)))
1805 return ret;
1806 }
1807 if (file->f_mode & FMODE_WRITE) {
1808 stop_dac(s);
1809 s->dma_dac.subdivision = val;
1810 if ((ret = prog_dmabuf_dac(s)))
1811 return ret;
1812 }
1813 return 0;
1814
1815 case SOUND_PCM_READ_RATE:
1816 return put_user((file->f_mode & FMODE_READ) ?
1817 s->dma_adc.sample_rate :
1818 s->dma_dac.sample_rate,
1819 (int *)arg);
1820
1821 case SOUND_PCM_READ_CHANNELS:
1822 if (file->f_mode & FMODE_READ)
1823 return put_user(s->dma_adc.num_channels, (int *)arg);
1824 else
1825 return put_user(s->dma_dac.num_channels, (int *)arg);
1826
1827 case SOUND_PCM_READ_BITS:
1828 if (file->f_mode & FMODE_READ)
1829 return put_user(s->dma_adc.sample_size, (int *)arg);
1830 else
1831 return put_user(s->dma_dac.sample_size, (int *)arg);
1832
1833 case SOUND_PCM_WRITE_FILTER:
1834 case SNDCTL_DSP_SETSYNCRO:
1835 case SOUND_PCM_READ_FILTER:
1836 return -EINVAL;
1837 }
1838
1839 return mixdev_ioctl(s->codec, cmd, arg);
1840}
1841
1842
1843static int au1000_open(struct inode *inode, struct file *file)
1844{
1845 int minor = MINOR(inode->i_rdev);
1846 DECLARE_WAITQUEUE(wait, current);
1847 struct au1000_state *s = &au1000_state;
1848 int ret;
1849
1850#ifdef AU1000_VERBOSE_DEBUG
1851 if (file->f_flags & O_NONBLOCK)
1852 dbg(__FUNCTION__ ": non-blocking");
1853 else
1854 dbg(__FUNCTION__ ": blocking");
1855#endif
1856
1857 file->private_data = s;
1858
1859 down(&s->open_sem);
1860 while (s->open_mode & file->f_mode) {
1861 if (file->f_flags & O_NONBLOCK) {
1862 up(&s->open_sem);
1863 return -EBUSY;
1864 }
1865 add_wait_queue(&s->open_wait, &wait);
1866 __set_current_state(TASK_INTERRUPTIBLE);
1867 up(&s->open_sem);
1868 schedule();
1869 remove_wait_queue(&s->open_wait, &wait);
1870 set_current_state(TASK_RUNNING);
1871 if (signal_pending(current))
1872 return -ERESTARTSYS;
1873 down(&s->open_sem);
1874 }
1875
1876 stop_dac(s);
1877 stop_adc(s);
1878
1879 if (file->f_mode & FMODE_READ) {
1880 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
1881 s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
1882 s->dma_adc.num_channels = 1;
1883 s->dma_adc.sample_size = 8;
1884 set_adc_rate(s, 8000);
1885 if ((minor & 0xf) == SND_DEV_DSP16)
1886 s->dma_adc.sample_size = 16;
1887 }
1888
1889 if (file->f_mode & FMODE_WRITE) {
1890 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
1891 s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
1892 s->dma_dac.num_channels = 1;
1893 s->dma_dac.sample_size = 8;
1894 set_dac_rate(s, 8000);
1895 if ((minor & 0xf) == SND_DEV_DSP16)
1896 s->dma_dac.sample_size = 16;
1897 }
1898
1899 if (file->f_mode & FMODE_READ) {
1900 if ((ret = prog_dmabuf_adc(s)))
1901 return ret;
1902 }
1903 if (file->f_mode & FMODE_WRITE) {
1904 if ((ret = prog_dmabuf_dac(s)))
1905 return ret;
1906 }
1907
1908 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1909 up(&s->open_sem);
1910 init_MUTEX(&s->sem);
1911 return 0;
1912}
1913
1914static int au1000_release(struct inode *inode, struct file *file)
1915{
1916 struct au1000_state *s = (struct au1000_state *)file->private_data;
1917
1918 lock_kernel();
1919
1920 if (file->f_mode & FMODE_WRITE) {
1921 unlock_kernel();
1922 drain_dac(s, file->f_flags & O_NONBLOCK);
1923 lock_kernel();
1924 }
1925
1926 down(&s->open_sem);
1927 if (file->f_mode & FMODE_WRITE) {
1928 stop_dac(s);
1929 dealloc_dmabuf(s, &s->dma_dac);
1930 }
1931 if (file->f_mode & FMODE_READ) {
1932 stop_adc(s);
1933 dealloc_dmabuf(s, &s->dma_adc);
1934 }
1935 s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
1936 up(&s->open_sem);
1937 wake_up(&s->open_wait);
1938 unlock_kernel();
1939 return 0;
1940}
1941
1942static struct file_operations au1000_audio_fops = {
1943 owner: THIS_MODULE,
1944 llseek: au1000_llseek,
1945 read: au1000_read,
1946 write: au1000_write,
1947 poll: au1000_poll,
1948 ioctl: au1000_ioctl,
1949 mmap: au1000_mmap,
1950 open: au1000_open,
1951 release: au1000_release,
1952};
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965#ifdef AU1000_DEBUG
1966static int proc_au1000_dump(char *buf, char **start, off_t fpos,
1967 int length, int *eof, void *data)
1968{
1969 struct au1000_state *s = &au1000_state;
1970 int cnt, len = 0;
1971
1972
1973 len += sprintf(buf + len, "\n\t\tAU1000 Audio Debug\n\n");
1974
1975
1976 len += sprintf(buf + len, "AU1000 Audio Controller registers\n");
1977 len += sprintf(buf + len, "---------------------------------\n");
1978 len += sprintf (buf + len, "AC97C_CONFIG = %08x\n",
1979 au_readl(AC97C_CONFIG));
1980 len += sprintf (buf + len, "AC97C_STATUS = %08x\n",
1981 au_readl(AC97C_STATUS));
1982 len += sprintf (buf + len, "AC97C_CNTRL = %08x\n",
1983 au_readl(AC97C_CNTRL));
1984
1985
1986 len += sprintf(buf + len, "\nAC97 CODEC registers\n");
1987 len += sprintf(buf + len, "----------------------\n");
1988 for (cnt = 0; cnt <= 0x7e; cnt += 2)
1989 len += sprintf(buf + len, "reg %02x = %04x\n",
1990 cnt, rdcodec(s->codec, cnt));
1991
1992 if (fpos >= len) {
1993 *start = buf;
1994 *eof = 1;
1995 return 0;
1996 }
1997 *start = buf + fpos;
1998 if ((len -= fpos) > length)
1999 return length;
2000 *eof = 1;
2001 return len;
2002
2003}
2004#endif
2005
2006
2007
2008MODULE_AUTHOR("Monta Vista Software, stevel@mvista.com");
2009MODULE_DESCRIPTION("Au1000 Audio Driver");
2010
2011
2012
2013static int __devinit au1000_probe(void)
2014{
2015 struct au1000_state *s = &au1000_state;
2016 int val;
2017 char proc_str[80];
2018
2019 memset(s, 0, sizeof(struct au1000_state));
2020
2021 init_waitqueue_head(&s->dma_adc.wait);
2022 init_waitqueue_head(&s->dma_dac.wait);
2023 init_waitqueue_head(&s->open_wait);
2024 init_MUTEX(&s->open_sem);
2025 spin_lock_init(&s->lock);
2026
2027 s->codec = ac97_alloc_codec();
2028 if(s->codec == NULL)
2029 {
2030 err("Out of memory");
2031 return -1;
2032 }
2033 s->codec->private_data = s;
2034 s->codec->id = 0;
2035 s->codec->codec_read = rdcodec;
2036 s->codec->codec_write = wrcodec;
2037 s->codec->codec_wait = waitcodec;
2038
2039 if (!request_region(PHYSADDR(AC97C_CONFIG),
2040 0x14, AU1000_MODULE_NAME)) {
2041 err("AC'97 ports in use");
2042 }
2043
2044 if ((s->dma_dac.dmanr = request_au1000_dma(DMA_ID_AC97C_TX,
2045 "audio DAC",
2046 dac_dma_interrupt,
2047 SA_INTERRUPT, s)) < 0) {
2048 err("Can't get DAC DMA");
2049 goto err_dma1;
2050 }
2051 if ((s->dma_adc.dmanr = request_au1000_dma(DMA_ID_AC97C_RX,
2052 "audio ADC",
2053 adc_dma_interrupt,
2054 SA_INTERRUPT, s)) < 0) {
2055 err("Can't get ADC DMA");
2056 goto err_dma2;
2057 }
2058
2059 info("DAC: DMA%d/IRQ%d, ADC: DMA%d/IRQ%d",
2060 s->dma_dac.dmanr, get_dma_done_irq(s->dma_dac.dmanr),
2061 s->dma_adc.dmanr, get_dma_done_irq(s->dma_adc.dmanr));
2062
2063#ifdef USE_COHERENT_DMA
2064
2065 set_dma_mode(s->dma_dac.dmanr,
2066 get_dma_mode(s->dma_dac.dmanr) & ~DMA_NC);
2067 set_dma_mode(s->dma_adc.dmanr,
2068 get_dma_mode(s->dma_adc.dmanr) & ~DMA_NC);
2069#else
2070
2071 set_dma_mode(s->dma_dac.dmanr,
2072 get_dma_mode(s->dma_dac.dmanr) | DMA_NC);
2073 set_dma_mode(s->dma_adc.dmanr,
2074 get_dma_mode(s->dma_adc.dmanr) | DMA_NC);
2075#endif
2076
2077
2078
2079 if ((s->dev_audio = register_sound_dsp(&au1000_audio_fops, -1)) < 0)
2080 goto err_dev1;
2081 if ((s->codec->dev_mixer =
2082 register_sound_mixer(&au1000_mixer_fops, -1)) < 0)
2083 goto err_dev2;
2084
2085#ifdef AU1000_DEBUG
2086
2087 s->ps = create_proc_read_entry(AU1000_MODULE_NAME, 0, NULL,
2088 proc_au1000_dump, NULL);
2089#endif
2090
2091
2092 au_writel(au_readl(SYS_PINFUNC) & ~0x02, SYS_PINFUNC);
2093
2094
2095 au_writel(AC97C_RS | AC97C_CE, AC97C_CNTRL);
2096 au1000_delay(10);
2097 au_writel(AC97C_CE, AC97C_CNTRL);
2098 au1000_delay(10);
2099
2100
2101 au_writel(AC97C_RESET, AC97C_CONFIG);
2102 au1000_delay(10);
2103 au_writel(0, AC97C_CONFIG);
2104
2105
2106 au1000_delay(500);
2107
2108
2109 au_writel(AC97C_SG | AC97C_SYNC, AC97C_CONFIG);
2110 udelay(100);
2111 au_writel(0, AC97C_CONFIG);
2112
2113
2114 if (!ac97_probe_codec(s->codec))
2115 goto err_dev3;
2116
2117 s->codec_base_caps = rdcodec(s->codec, AC97_RESET);
2118 s->codec_ext_caps = rdcodec(s->codec, AC97_EXTENDED_ID);
2119 info("AC'97 Base/Extended ID = %04x/%04x",
2120 s->codec_base_caps, s->codec_ext_caps);
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130 s->codec->supported_mixers |= SOUND_MASK_ALTPCM;
2131
2132
2133
2134 val = 0x4343;
2135 mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_ALTPCM,
2136 (unsigned long) &val);
2137
2138 if (!(s->codec_ext_caps & AC97_EXTID_VRA)) {
2139
2140 s->no_vra = 1;
2141 } else if (!vra) {
2142
2143 u16 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
2144 wrcodec(s->codec, AC97_EXTENDED_STATUS,
2145 ac97_extstat & ~AC97_EXTSTAT_VRA);
2146 s->no_vra = 1;
2147 }
2148 if (s->no_vra)
2149 info("no VRA, interpolating and decimating");
2150
2151
2152 val = SOUND_MASK_MIC;
2153 mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC,
2154 (unsigned long) &val);
2155
2156#ifdef AU1000_DEBUG
2157 sprintf(proc_str, "driver/%s/%d/ac97", AU1000_MODULE_NAME,
2158 s->codec->id);
2159 s->ac97_ps = create_proc_read_entry (proc_str, 0, NULL,
2160 ac97_read_proc, &s->codec);
2161#endif
2162
2163#ifdef CONFIG_MIPS_XXS1500
2164
2165 wrcodec(&s->codec, AC97_POWER_CONTROL,
2166 rdcodec(&s->codec, AC97_POWER_CONTROL) & ~0x8000);
2167
2168
2169
2170 wrcodec(&s->codec, AC97_PCBEEP_VOL, 0x8000);
2171 wrcodec(&s->codec, AC97_PHONE_VOL, 0x8008);
2172 wrcodec(&s->codec, AC97_MIC_VOL, 0x8008);
2173 wrcodec(&s->codec, AC97_LINEIN_VOL, 0x8808);
2174 wrcodec(&s->codec, AC97_CD_VOL, 0x8808);
2175 wrcodec(&s->codec, AC97_VIDEO_VOL, 0x8808);
2176 wrcodec(&s->codec, AC97_AUX_VOL, 0x8808);
2177 wrcodec(&s->codec, AC97_PCMOUT_VOL, 0x0808);
2178 wrcodec(&s->codec, AC97_GENERAL_PURPOSE, 0x2000);
2179#endif
2180
2181 return 0;
2182
2183 err_dev3:
2184 unregister_sound_mixer(s->codec->dev_mixer);
2185 err_dev2:
2186 unregister_sound_dsp(s->dev_audio);
2187 err_dev1:
2188 free_au1000_dma(s->dma_adc.dmanr);
2189 err_dma2:
2190 free_au1000_dma(s->dma_dac.dmanr);
2191 err_dma1:
2192 release_region(PHYSADDR(AC97C_CONFIG), 0x14);
2193 err_codec:
2194 ac97_release_codec(s->codec);
2195 return -1;
2196}
2197
2198static void __devinit au1000_remove(void)
2199{
2200 struct au1000_state *s = &au1000_state;
2201
2202 if (!s)
2203 return;
2204#ifdef AU1000_DEBUG
2205 if (s->ps)
2206 remove_proc_entry(AU1000_MODULE_NAME, NULL);
2207#endif
2208 synchronize_irq();
2209 free_au1000_dma(s->dma_adc.dmanr);
2210 free_au1000_dma(s->dma_dac.dmanr);
2211 release_region(PHYSADDR(AC97C_CONFIG), 0x14);
2212 unregister_sound_dsp(s->dev_audio);
2213 unregister_sound_mixer(s->codec->dev_mixer);
2214 ac97_release_codec(s->codec);
2215}
2216
2217static int __init init_au1000(void)
2218{
2219 info("stevel@mvista.com, built " __TIME__ " on " __DATE__);
2220 return au1000_probe();
2221}
2222
2223static void __exit cleanup_au1000(void)
2224{
2225 info("unloading");
2226 au1000_remove();
2227}
2228
2229module_init(init_au1000);
2230module_exit(cleanup_au1000);
2231
2232
2233
2234#ifndef MODULE
2235
2236static int __init au1000_setup(char *options)
2237{
2238 char *this_opt;
2239
2240 if (!options || !*options)
2241 return 0;
2242
2243 for(this_opt=strtok(options, ",");
2244 this_opt; this_opt=strtok(NULL, ",")) {
2245 if (!strncmp(this_opt, "vra", 3)) {
2246 vra = 1;
2247 }
2248 }
2249
2250 return 1;
2251}
2252
2253__setup("au1000_audio=", au1000_setup);
2254
2255#endif
2256