linux-old/drivers/scsi/mesh.c
<<
>>
Prefs
   1/*
   2 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
   3 * bus adaptor found on Power Macintosh computers.
   4 * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
   5 * controller.
   6 *
   7 * Paul Mackerras, August 1996.
   8 * Copyright (C) 1996 Paul Mackerras.
   9 *
  10 * Apr. 14 2002  - BenH         Rework bus reset code for new error handler
  11 *                              Add delay after initial bus reset
  12 *                              Add module parameters
  13 * To do:
  14 * - handle aborts correctly
  15 * - retry arbitration if lost (unless higher levels do this for us)
  16 */
  17#include <linux/config.h>
  18#include <linux/module.h>
  19#include <linux/kernel.h>
  20#include <linux/delay.h>
  21#include <linux/types.h>
  22#include <linux/string.h>
  23#include <linux/slab.h>
  24#include <linux/blk.h>
  25#include <linux/proc_fs.h>
  26#include <linux/stat.h>
  27#include <linux/tqueue.h>
  28#include <linux/interrupt.h>
  29#include <linux/reboot.h>
  30#include <linux/spinlock.h>
  31#include <linux/pci.h>
  32#include <asm/dbdma.h>
  33#include <asm/io.h>
  34#include <asm/pgtable.h>
  35#include <asm/prom.h>
  36#include <asm/system.h>
  37#include <asm/irq.h>
  38#include <asm/hydra.h>
  39#include <asm/processor.h>
  40#include <asm/machdep.h>
  41#include <asm/pmac_feature.h>
  42#include <asm/pci-bridge.h>
  43#ifdef CONFIG_PMAC_PBOOK
  44#include <linux/adb.h>
  45#include <linux/pmu.h>
  46#endif
  47
  48#include "scsi.h"
  49#include "hosts.h"
  50#include "mesh.h"
  51
  52#if 1
  53#undef KERN_DEBUG
  54#define KERN_DEBUG KERN_WARNING
  55#endif
  56
  57MODULE_AUTHOR("Paul Mackerras (paulus@samba.org)");
  58MODULE_DESCRIPTION("PowerMac MESH SCSI driver");
  59MODULE_LICENSE("GPL");
  60
  61MODULE_PARM(sync_rate, "i");
  62MODULE_PARM_DESC(sync_rate, "Synchronous rate (0..10, 0=async)");
  63MODULE_PARM(sync_targets, "i");
  64MODULE_PARM_DESC(sync_targets, "Bitmask of targets allowed to set synchronous");
  65MODULE_PARM(resel_targets, "i");
  66MODULE_PARM_DESC(resel_targets, "Bitmask of targets allowed to set disconnect");
  67MODULE_PARM(debug_targets, "i");
  68MODULE_PARM_DESC(debug_targets, "Bitmask of debugged targets");
  69MODULE_PARM(init_reset_delay, "i");
  70MODULE_PARM_DESC(init_reset_delay, "Initial bus reset delay (0=no reset)");
  71
  72static int sync_rate = CONFIG_SCSI_MESH_SYNC_RATE;
  73static int sync_targets = 0xff;
  74static int resel_targets = 0xff;
  75static int debug_targets = 0;   /* print debug for these targets */
  76static int init_reset_delay = CONFIG_SCSI_MESH_RESET_DELAY_MS;
  77
  78static int mesh_sync_period = 100;
  79static int mesh_sync_offset = 0;
  80static unsigned char use_active_neg = 0;  /* bit mask for SEQ_ACTIVE_NEG if used */
  81
  82#define ALLOW_SYNC(tgt)         ((sync_targets >> (tgt)) & 1)
  83#define ALLOW_RESEL(tgt)        ((resel_targets >> (tgt)) & 1)
  84#define ALLOW_DEBUG(tgt)        ((debug_targets >> (tgt)) & 1)
  85#define DEBUG_TARGET(cmd)       ((cmd) && ALLOW_DEBUG((cmd)->target))
  86
  87#undef MESH_DBG
  88#define N_DBG_LOG       50
  89#define N_DBG_SLOG      20
  90#define NUM_DBG_EVENTS  13
  91#undef  DBG_USE_TB              /* bombs on 601 */
  92
  93struct dbglog {
  94        char    *fmt;
  95        u32     tb;
  96        u8      phase;
  97        u8      bs0;
  98        u8      bs1;
  99        u8      tgt;
 100        int     d;
 101};
 102
 103enum mesh_phase {
 104        idle,
 105        arbitrating,
 106        selecting,
 107        commanding,
 108        dataing,
 109        statusing,
 110        busfreeing,
 111        disconnecting,
 112        reselecting,
 113        sleeping
 114};
 115
 116enum msg_phase {
 117        msg_none,
 118        msg_out,
 119        msg_out_xxx,
 120        msg_out_last,
 121        msg_in,
 122        msg_in_bad,
 123};
 124
 125enum sdtr_phase {
 126        do_sdtr,
 127        sdtr_sent,
 128        sdtr_done
 129};
 130
 131struct mesh_target {
 132        enum sdtr_phase sdtr_state;
 133        int     sync_params;
 134        int     data_goes_out;          /* guess as to data direction */
 135        Scsi_Cmnd *current_req;
 136        u32     saved_ptr;
 137#ifdef MESH_DBG
 138        int     log_ix;
 139        int     n_log;
 140        struct dbglog log[N_DBG_LOG];
 141#endif
 142};
 143
 144struct mesh_state {
 145        volatile struct mesh_regs *mesh;
 146        int     meshintr;
 147        volatile struct dbdma_regs *dma;
 148        int     dmaintr;
 149        struct  Scsi_Host *host;
 150        struct  mesh_state *next;
 151        Scsi_Cmnd *request_q;
 152        Scsi_Cmnd *request_qtail;
 153        enum mesh_phase phase;          /* what we're currently trying to do */
 154        enum msg_phase msgphase;
 155        int     conn_tgt;               /* target we're connected to */
 156        Scsi_Cmnd *current_req;         /* req we're currently working on */
 157        int     data_ptr;
 158        int     dma_started;
 159        int     dma_count;
 160        int     stat;
 161        int     aborting;
 162        int     expect_reply;
 163        int     n_msgin;
 164        u8      msgin[16];
 165        int     n_msgout;
 166        int     last_n_msgout;
 167        u8      msgout[16];
 168        struct dbdma_cmd *dma_cmds;     /* space for dbdma commands, aligned */
 169        int     clk_freq;
 170        struct mesh_target tgts[8];
 171        void    *dma_cmd_space;
 172        struct device_node *ofnode;
 173        struct pci_dev* pdev;
 174#ifdef MESH_DBG
 175        int     log_ix;
 176        int     n_log;
 177        struct dbglog log[N_DBG_SLOG];
 178#endif
 179};
 180
 181#ifdef MESH_DBG
 182
 183static void dlog(struct mesh_state *ms, char *fmt, int a);
 184static void dumplog(struct mesh_state *ms, int tgt);
 185static void dumpslog(struct mesh_state *ms);
 186
 187#else
 188static inline void dlog(struct mesh_state *ms, char *fmt, int a)
 189{}
 190static inline void dumplog(struct mesh_state *ms, int tgt)
 191{}
 192static inline void dumpslog(struct mesh_state *ms)
 193{}
 194
 195#endif /* MESH_DBG */
 196#define MKWORD(a, b, c, d)      (((a) << 24) + ((b) << 16) + ((c) << 8) + (d))
 197
 198static struct mesh_state *all_meshes;
 199
 200static void mesh_init(struct mesh_state *);
 201static int mesh_notify_reboot(struct notifier_block *, unsigned long, void *);
 202static void mesh_dump_regs(struct mesh_state *);
 203static void mesh_start(struct mesh_state *);
 204static void mesh_start_cmd(struct mesh_state *, Scsi_Cmnd *);
 205static void add_sdtr_msg(struct mesh_state *);
 206static void set_sdtr(struct mesh_state *, int, int);
 207static void start_phase(struct mesh_state *);
 208static void get_msgin(struct mesh_state *);
 209static int msgin_length(struct mesh_state *);
 210static void cmd_complete(struct mesh_state *);
 211static void phase_mismatch(struct mesh_state *);
 212static void reselected(struct mesh_state *);
 213static void handle_reset(struct mesh_state *);
 214static void handle_error(struct mesh_state *);
 215static void handle_exception(struct mesh_state *);
 216static void mesh_interrupt(int, void *, struct pt_regs *);
 217static void do_mesh_interrupt(int, void *, struct pt_regs *);
 218static void handle_msgin(struct mesh_state *);
 219static void mesh_done(struct mesh_state *, int);
 220static void mesh_completed(struct mesh_state *, Scsi_Cmnd *);
 221static void set_dma_cmds(struct mesh_state *, Scsi_Cmnd *);
 222static void halt_dma(struct mesh_state *);
 223static int data_goes_out(Scsi_Cmnd *);
 224static void do_abort(struct mesh_state *ms);
 225static void set_mesh_power(struct mesh_state *ms, int state);
 226
 227#ifdef CONFIG_PMAC_PBOOK
 228static int mesh_notify_sleep(struct pmu_sleep_notifier *self, int when);
 229static struct pmu_sleep_notifier mesh_sleep_notifier = {
 230        mesh_notify_sleep,
 231        SLEEP_LEVEL_BLOCK,
 232};
 233#endif
 234
 235static struct notifier_block mesh_notifier = {
 236        mesh_notify_reboot,
 237        NULL,
 238        0
 239};
 240
 241int
 242mesh_detect(Scsi_Host_Template *tp)
 243{
 244        struct device_node *mesh;
 245        int nmeshes, tgt, *cfp, minper;
 246        struct mesh_state *ms, **prev_statep;
 247        struct Scsi_Host *mesh_host;
 248        void *dma_cmd_space;
 249
 250        /* The SCSI layer is dumb ! It calls us with the IO request
 251         * lock held and interrupts disabled here... This doesn't happen
 252         * in 2.5
 253         */
 254        spin_unlock_irq(&io_request_lock);
 255        
 256        if (_machine == _MACH_Pmac) {
 257            use_active_neg = (find_devices("mac-io") ? 0 : SEQ_ACTIVE_NEG);
 258        } else {
 259            /* CHRP mac-io */
 260            use_active_neg = SEQ_ACTIVE_NEG;
 261        }
 262
 263        /* Calculate sync rate from module parameters */
 264        if (sync_rate > 10)
 265                sync_rate = 10;
 266        if (sync_rate > 0) {
 267                printk(KERN_INFO "mesh: configured for synchronous %d MB/s\n", sync_rate);
 268                mesh_sync_period = 1000 / sync_rate;    /* ns */
 269                mesh_sync_offset = 15;
 270        } else
 271                printk(KERN_INFO "mesh: configured for asynchronous\n");
 272
 273        nmeshes = 0;
 274        prev_statep = &all_meshes;
 275        /*
 276         * On powermacs, the MESH node has device_type "mesh".
 277         * On chrp machines, its device_type is "scsi" with
 278         * "chrp,mesh0" as its `compatible' property.
 279         */
 280        mesh = find_devices("mesh");
 281        if (mesh == 0)
 282                mesh = find_compatible_devices("scsi", "chrp,mesh0");
 283        for (; mesh != 0; mesh = mesh->next) {
 284                u8 pci_bus, pci_devfn;
 285                struct pci_dev* pdev = NULL;
 286                
 287                if (mesh->n_addrs != 2 || mesh->n_intrs != 2) {
 288                        printk(KERN_ERR "mesh: expected 2 addrs and 2 intrs"
 289                               " (got %d,%d)\n", mesh->n_addrs, mesh->n_intrs);
 290                        continue;
 291                }
 292                if (mesh->parent != NULL
 293                    && pci_device_from_OF_node(mesh->parent, &pci_bus,
 294                                               &pci_devfn) == 0)
 295                        pdev = pci_find_slot(pci_bus, pci_devfn);
 296                if (pdev == NULL) {
 297                        printk(KERN_ERR "mesh: Can't locate PCI entry\n");
 298                        continue;
 299                }
 300
 301                mesh_host = scsi_register(tp, sizeof(struct mesh_state));
 302                if (mesh_host == 0) {
 303                        printk(KERN_ERR "mesh: couldn't register host");
 304                        continue;
 305                }
 306                mesh_host->unique_id = nmeshes;
 307#if !defined(MODULE)
 308                note_scsi_host(mesh, mesh_host);
 309#endif
 310
 311                ms = (struct mesh_state *) mesh_host->hostdata;
 312                if (ms == 0)
 313                        panic("no mesh state");
 314                memset(ms, 0, sizeof(*ms));
 315                ms->host = mesh_host;
 316                ms->ofnode = mesh;
 317                ms->pdev = pdev;
 318                ms->mesh = (volatile struct mesh_regs *)
 319                        ioremap(mesh->addrs[0].address, 0x1000);
 320                ms->dma = (volatile struct dbdma_regs *)
 321                        ioremap(mesh->addrs[1].address, 0x1000);
 322                ms->meshintr = mesh->intrs[0].line;
 323                ms->dmaintr = mesh->intrs[1].line;
 324
 325                /* Space for dma command list: +1 for stop command,
 326                   +1 to allow for aligning. */
 327                dma_cmd_space = kmalloc((mesh_host->sg_tablesize + 2) *
 328                                        sizeof(struct dbdma_cmd), GFP_KERNEL);
 329                if (dma_cmd_space == 0)
 330                        panic("mesh: couldn't allocate dma command space");
 331                ms->dma_cmds = (struct dbdma_cmd *) DBDMA_ALIGN(dma_cmd_space);
 332                memset(ms->dma_cmds, 0, (mesh_host->sg_tablesize + 1)
 333                       * sizeof(struct dbdma_cmd));
 334                ms->dma_cmd_space = dma_cmd_space;
 335
 336                ms->current_req = 0;
 337                for (tgt = 0; tgt < 8; ++tgt) {
 338                        ms->tgts[tgt].sdtr_state = do_sdtr;
 339                        ms->tgts[tgt].sync_params = ASYNC_PARAMS;
 340                        ms->tgts[tgt].current_req = 0;
 341                }
 342                *prev_statep = ms;
 343                prev_statep = &ms->next;
 344
 345                if ((cfp = (int *) get_property(mesh, "clock-frequency",
 346                                                NULL))) {
 347                        ms->clk_freq = *cfp;
 348                } else {
 349                        printk(KERN_INFO "mesh: assuming 50MHz clock frequency\n");
 350                        ms->clk_freq = 50000000;
 351                }
 352                /* The maximum sync rate is clock / 5; increase
 353                   mesh_sync_period if necessary. */
 354                minper = 1000000000 / (ms->clk_freq / 5);       /* ns */
 355                if (mesh_sync_period < minper)
 356                        mesh_sync_period = minper;
 357
 358                set_mesh_power(ms, 1);
 359
 360                mesh_init(ms);
 361
 362                if (request_irq(ms->meshintr, do_mesh_interrupt, 0, "MESH", ms)) {
 363                        printk(KERN_ERR "MESH: can't get irq %d\n", ms->meshintr);
 364                }
 365
 366                ++nmeshes;
 367        }
 368
 369        if ((_machine == _MACH_Pmac) && (nmeshes > 0)) {
 370#ifdef CONFIG_PMAC_PBOOK
 371                pmu_register_sleep_notifier(&mesh_sleep_notifier);
 372#endif /* CONFIG_PMAC_PBOOK */
 373                register_reboot_notifier(&mesh_notifier);
 374        }
 375
 376        /* Return to the SCSI layer in the same state we got called */
 377        spin_lock_irq(&io_request_lock);
 378
 379        return nmeshes;
 380}
 381
 382int
 383mesh_release(struct Scsi_Host *host)
 384{
 385        struct mesh_state *ms = (struct mesh_state *) host->hostdata;
 386
 387        if (ms == 0)
 388                return 0;
 389        if (ms->mesh)
 390                iounmap((void *) ms->mesh);
 391        if (ms->dma)
 392                iounmap((void *) ms->dma);
 393        kfree(ms->dma_cmd_space);
 394        free_irq(ms->meshintr, ms);
 395        pmac_call_feature(PMAC_FTR_MESH_ENABLE, ms->ofnode, 0, 0);
 396        return 0;
 397}
 398
 399static void
 400set_mesh_power(struct mesh_state *ms, int state)
 401{
 402        if (_machine != _MACH_Pmac)
 403                return;
 404        if (state) {
 405                pmac_call_feature(PMAC_FTR_MESH_ENABLE, ms->ofnode, 0, 1);
 406                mdelay(200);
 407        } else {
 408                pmac_call_feature(PMAC_FTR_MESH_ENABLE, ms->ofnode, 0, 0);
 409                mdelay(10);
 410        }
 411}                       
 412
 413#ifdef CONFIG_PMAC_PBOOK
 414/*
 415 * notify clients before sleep and reset bus afterwards
 416 */
 417int
 418mesh_notify_sleep(struct pmu_sleep_notifier *self, int when)
 419{
 420        struct mesh_state *ms;
 421        
 422        switch (when) {
 423        case PBOOK_SLEEP_REQUEST:
 424                /* XXX We should wait for current transactions and queue
 425                 * new ones that would be posted beyond this point 
 426                 */ 
 427                break;
 428        case PBOOK_SLEEP_REJECT:
 429                break;
 430                
 431        case PBOOK_SLEEP_NOW:
 432                for (ms = all_meshes; ms != 0; ms = ms->next) {
 433                        unsigned long flags;
 434
 435                        scsi_block_requests(ms->host);
 436                        spin_lock_irqsave(&io_request_lock, flags);
 437                        while(ms->phase != idle) {
 438                                spin_unlock_irqrestore(&io_request_lock, flags);
 439                                current->state = TASK_UNINTERRUPTIBLE;
 440                                schedule_timeout(1);
 441                                spin_lock_irqsave(&io_request_lock, flags);
 442                        }
 443                        ms->phase = sleeping;
 444                        spin_unlock_irqrestore(&io_request_lock, flags);
 445                        disable_irq(ms->meshintr);
 446                        set_mesh_power(ms, 0);
 447                }
 448                break;
 449        case PBOOK_WAKE:
 450                for (ms = all_meshes; ms != 0; ms = ms->next) {
 451                        unsigned long flags;
 452                        
 453                        set_mesh_power(ms, 1);
 454                        mesh_init(ms);
 455                        spin_lock_irqsave(&io_request_lock, flags);
 456                        mesh_start(ms);
 457                        spin_unlock_irqrestore(&io_request_lock, flags);
 458                        enable_irq(ms->meshintr);
 459                        scsi_unblock_requests(ms->host);
 460                }
 461                break;
 462        }
 463        return PBOOK_SLEEP_OK;
 464}
 465#endif /* CONFIG_PMAC_PBOOK */
 466
 467/*
 468 * Called by midlayer with host locked to queue a new
 469 * request
 470 */
 471int
 472mesh_queue(Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *))
 473{
 474        struct mesh_state *ms;
 475
 476        cmd->scsi_done = done;
 477        cmd->host_scribble = NULL;
 478
 479        ms = (struct mesh_state *) cmd->host->hostdata;
 480
 481        if (ms->request_q == NULL)
 482                ms->request_q = cmd;
 483        else
 484                ms->request_qtail->host_scribble = (void *) cmd;
 485        ms->request_qtail = cmd;
 486
 487        if (ms->phase == idle)
 488                mesh_start(ms);
 489
 490        return 0;
 491}
 492
 493/* Todo: here we can at least try to remove the command from the
 494 * queue if it isn't connected yet, and for pending command, assert
 495 * ATN until the bus gets freed.
 496 */
 497int
 498mesh_abort(Scsi_Cmnd *cmd)
 499{
 500        struct mesh_state *ms = (struct mesh_state *) cmd->host->hostdata;
 501
 502        printk(KERN_DEBUG "mesh_abort(%p)\n", cmd);
 503        mesh_dump_regs(ms);
 504        dumplog(ms, cmd->target);
 505        dumpslog(ms);
 506        return SCSI_ABORT_SNOOZE;
 507}
 508
 509static void
 510mesh_dump_regs(struct mesh_state *ms)
 511{
 512        volatile struct mesh_regs *mr = ms->mesh;
 513        volatile struct dbdma_regs *md = ms->dma;
 514        int t;
 515        struct mesh_target *tp;
 516
 517        printk(KERN_DEBUG "mesh: state at %p, regs at %p, dma at %p\n",
 518               ms, mr, md);
 519        printk(KERN_DEBUG "    ct=%4x seq=%2x bs=%4x fc=%2x "
 520               "exc=%2x err=%2x im=%2x int=%2x sp=%2x\n",
 521               (mr->count_hi << 8) + mr->count_lo, mr->sequence,
 522               (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count,
 523               mr->exception, mr->error, mr->intr_mask, mr->interrupt,
 524               mr->sync_params);
 525        while(in_8(&mr->fifo_count))
 526                printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo));
 527        printk(KERN_DEBUG "    dma stat=%x cmdptr=%x\n",
 528               in_le32(&md->status), in_le32(&md->cmdptr));
 529        printk(KERN_DEBUG "    phase=%d msgphase=%d conn_tgt=%d data_ptr=%d\n",
 530               ms->phase, ms->msgphase, ms->conn_tgt, ms->data_ptr);
 531        printk(KERN_DEBUG "    dma_st=%d dma_ct=%d n_msgout=%d\n",
 532               ms->dma_started, ms->dma_count, ms->n_msgout);
 533        for (t = 0; t < 8; ++t) {
 534                tp = &ms->tgts[t];
 535                if (tp->current_req == NULL)
 536                        continue;
 537                printk(KERN_DEBUG "    target %d: req=%p goes_out=%d saved_ptr=%d\n",
 538                       t, tp->current_req, tp->data_goes_out, tp->saved_ptr);
 539        }
 540}
 541
 542/*
 543 * Called by the midlayer with the lock held to reset the
 544 * SCSI host and bus.
 545 * The midlayer will wait for devices to come back, we don't need
 546 * to do that ourselves
 547 */
 548int
 549mesh_host_reset(Scsi_Cmnd *cmd)
 550{
 551        struct mesh_state *ms = (struct mesh_state *) cmd->host->hostdata;
 552        volatile struct mesh_regs *mr = ms->mesh;
 553        volatile struct dbdma_regs *md = ms->dma;
 554
 555        printk(KERN_DEBUG "mesh_host_reset\n");
 556
 557        /* Reset the controller & dbdma channel */
 558        out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16);   /* stop dma */
 559        out_8(&mr->exception, 0xff);    /* clear all exception bits */
 560        out_8(&mr->error, 0xff);        /* clear all error bits */
 561        out_8(&mr->sequence, SEQ_RESETMESH);
 562        udelay(1);
 563        out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 564        out_8(&mr->source_id, ms->host->this_id);
 565        out_8(&mr->sel_timeout, 25);    /* 250ms */
 566        out_8(&mr->sync_params, ASYNC_PARAMS);
 567
 568        /* Reset the bus */
 569        out_8(&mr->bus_status1, BS1_RST);       /* assert RST */
 570        udelay(30);                     /* leave it on for >= 25us */
 571        out_8(&mr->bus_status1, 0);     /* negate RST */
 572
 573        /* Complete pending commands */
 574        handle_reset(ms);
 575        
 576        return SUCCESS;
 577}
 578
 579/*
 580 * If we leave drives set for synchronous transfers (especially
 581 * CDROMs), and reboot to MacOS, it gets confused, poor thing.
 582 * So, on reboot we reset the SCSI bus.
 583 */
 584static int
 585mesh_notify_reboot(struct notifier_block *this, unsigned long code, void *x)
 586{
 587        struct mesh_state *ms;
 588        volatile struct mesh_regs *mr;
 589
 590        if (code == SYS_DOWN) {
 591                printk(KERN_INFO "resetting MESH scsi bus(es)\n");
 592                for (ms = all_meshes; ms != 0; ms = ms->next) {
 593                        mr = ms->mesh;
 594                        out_8(&mr->intr_mask, 0);
 595                        out_8(&mr->interrupt,
 596                              INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 597                        out_8(&mr->bus_status1, BS1_RST);
 598                        udelay(30);
 599                        out_8(&mr->bus_status1, 0);
 600                }
 601        }
 602        return NOTIFY_DONE;
 603}
 604
 605/* Called with  meshinterrupt disabled, initialize the chipset
 606 * and eventually do the initial bus reset. The lock must not be
 607 * held since we can schedule.
 608 */
 609static void
 610mesh_init(struct mesh_state *ms)
 611{
 612        volatile struct mesh_regs *mr = ms->mesh;
 613        volatile struct dbdma_regs *md = ms->dma;
 614
 615        udelay(100);
 616
 617        /* Reset controller */
 618        out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16);   /* stop dma */
 619        out_8(&mr->exception, 0xff);    /* clear all exception bits */
 620        out_8(&mr->error, 0xff);        /* clear all error bits */
 621        out_8(&mr->sequence, SEQ_RESETMESH);
 622        udelay(10);
 623        out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 624        out_8(&mr->source_id, ms->host->this_id);
 625        out_8(&mr->sel_timeout, 25);    /* 250ms */
 626        out_8(&mr->sync_params, ASYNC_PARAMS);
 627
 628        if (init_reset_delay) {
 629                printk(KERN_INFO "mesh: performing initial bus reset...\n");
 630                
 631                /* Reset bus */
 632                out_8(&mr->bus_status1, BS1_RST);       /* assert RST */
 633                udelay(30);                     /* leave it on for >= 25us */
 634                out_8(&mr->bus_status1, 0);     /* negate RST */
 635
 636                /* Wait for bus to come back */
 637                current->state = TASK_UNINTERRUPTIBLE;
 638                schedule_timeout((init_reset_delay * HZ) / 1000);
 639        }
 640        
 641        /* Reconfigure controller */
 642        out_8(&mr->interrupt, 0xff);    /* clear all interrupt bits */
 643        out_8(&mr->sequence, SEQ_FLUSHFIFO);
 644        udelay(1);
 645        out_8(&mr->sync_params, ASYNC_PARAMS);
 646        out_8(&mr->sequence, SEQ_ENBRESEL);
 647
 648        ms->phase = idle;
 649        ms->msgphase = msg_none;
 650}
 651
 652/*
 653 * Start the next command for a MESH.
 654 * Should be called with interrupts disabled.
 655 */
 656static void
 657mesh_start(struct mesh_state *ms)
 658{
 659        Scsi_Cmnd *cmd, *prev, *next;
 660
 661        if (ms->phase != idle || ms->current_req != NULL) {
 662                printk(KERN_ERR "inappropriate mesh_start (phase=%d, ms=%p)",
 663                       ms->phase, ms);
 664                return;
 665        }
 666
 667        while (ms->phase == idle) {
 668                prev = NULL;
 669                for (cmd = ms->request_q; ; cmd = (Scsi_Cmnd *) cmd->host_scribble) {
 670                        if (cmd == NULL)
 671                                return;
 672                        if (ms->tgts[cmd->target].current_req == NULL)
 673                                break;
 674                        prev = cmd;
 675                }
 676                next = (Scsi_Cmnd *) cmd->host_scribble;
 677                if (prev == NULL)
 678                        ms->request_q = next;
 679                else
 680                        prev->host_scribble = (void *) next;
 681                if (next == NULL)
 682                        ms->request_qtail = prev;
 683
 684                mesh_start_cmd(ms, cmd);
 685        }
 686}
 687
 688static void
 689mesh_start_cmd(struct mesh_state *ms, Scsi_Cmnd *cmd)
 690{
 691        volatile struct mesh_regs *mr = ms->mesh;
 692        int t;
 693
 694        ms->current_req = cmd;
 695        ms->tgts[cmd->target].data_goes_out = data_goes_out(cmd);
 696        ms->tgts[cmd->target].current_req = cmd;
 697
 698#if 1
 699        if (DEBUG_TARGET(cmd)) {
 700                int i;
 701                printk(KERN_DEBUG "mesh_start: %p ser=%lu tgt=%d cmd=",
 702                       cmd, cmd->serial_number, cmd->target);
 703                for (i = 0; i < cmd->cmd_len; ++i)
 704                        printk(" %x", cmd->cmnd[i]);
 705                printk(" use_sg=%d buffer=%p bufflen=%u\n",
 706                       cmd->use_sg, cmd->request_buffer, cmd->request_bufflen);
 707        }
 708#endif
 709        if (ms->dma_started)
 710                panic("mesh: double DMA start !\n");
 711
 712        ms->phase = arbitrating;
 713        ms->msgphase = msg_none;
 714        ms->data_ptr = 0;
 715        ms->dma_started = 0;
 716        ms->n_msgout = 0;
 717        ms->last_n_msgout = 0;
 718        ms->expect_reply = 0;
 719        ms->conn_tgt = cmd->target;
 720        ms->tgts[cmd->target].saved_ptr = 0;
 721        ms->stat = DID_OK;
 722        ms->aborting = 0;
 723#ifdef MESH_DBG
 724        ms->tgts[cmd->target].n_log = 0;
 725        dlog(ms, "start cmd=%x", (int) cmd);
 726#endif
 727
 728        /* Off we go */
 729        dlog(ms, "about to arb, intr/exc/err/fc=%.8x",
 730             MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
 731        out_8(&mr->interrupt, INT_CMDDONE);
 732        out_8(&mr->sequence, SEQ_ENBRESEL);
 733        udelay(1);
 734
 735        if (mr->bus_status1 & (BS1_BSY | BS1_SEL)) {
 736                /*
 737                 * Some other device has the bus or is arbitrating for it -
 738                 * probably a target which is about to reselect us.
 739                 */
 740                dlog(ms, "busy b4 arb, intr/exc/err/fc=%.8x",
 741                     MKWORD(mr->interrupt, mr->exception,
 742                            mr->error, mr->fifo_count));
 743                for (t = 100; t > 0; --t) {
 744                        if ((mr->bus_status1 & (BS1_BSY | BS1_SEL)) == 0)
 745                                break;
 746                        if (in_8(&mr->interrupt) != 0) {
 747                                dlog(ms, "intr b4 arb, intr/exc/err/fc=%.8x",
 748                                     MKWORD(mr->interrupt, mr->exception,
 749                                            mr->error, mr->fifo_count));
 750                                mesh_interrupt(0, (void *)ms, 0);
 751                                if (ms->phase != arbitrating)
 752                                        return;
 753                        }
 754                        udelay(1);
 755                }
 756                if (mr->bus_status1 & (BS1_BSY | BS1_SEL)) {
 757                        /* XXX should try again in a little while */
 758                        ms->stat = DID_BUS_BUSY;
 759                        ms->phase = idle;
 760                        mesh_done(ms, 0);
 761                        return;
 762                }
 763        }
 764
 765        /*
 766         * Apparently the mesh has a bug where it will assert both its
 767         * own bit and the target's bit on the bus during arbitration.
 768         */
 769        out_8(&mr->dest_id, mr->source_id);
 770
 771        /*
 772         * There appears to be a race with reselection sometimes,
 773         * where a target reselects us just as we issue the
 774         * arbitrate command.  It seems that then the arbitrate
 775         * command just hangs waiting for the bus to be free
 776         * without giving us a reselection exception.
 777         * The only way I have found to get it to respond correctly
 778         * is this: disable reselection before issuing the arbitrate
 779         * command, then after issuing it, if it looks like a target
 780         * is trying to reselect us, reset the mesh and then enable
 781         * reselection.
 782         */
 783        out_8(&mr->sequence, SEQ_DISRESEL);
 784        if (in_8(&mr->interrupt) != 0) {
 785                dlog(ms, "intr after disresel, intr/exc/err/fc=%.8x",
 786                     MKWORD(mr->interrupt, mr->exception,
 787                            mr->error, mr->fifo_count));
 788                mesh_interrupt(0, (void *)ms, 0);
 789                if (ms->phase != arbitrating)
 790                        return;
 791                dlog(ms, "after intr after disresel, intr/exc/err/fc=%.8x",
 792                     MKWORD(mr->interrupt, mr->exception,
 793                            mr->error, mr->fifo_count));
 794        }
 795
 796        out_8(&mr->sequence, SEQ_ARBITRATE);
 797
 798        for (t = 230; t > 0; --t) {
 799                if (in_8(&mr->interrupt) != 0)
 800                        break;
 801                udelay(1);
 802        }
 803        dlog(ms, "after arb, intr/exc/err/fc=%.8x",
 804             MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
 805        if (mr->interrupt == 0 && (mr->bus_status1 & BS1_SEL)
 806            && (mr->bus_status0 & BS0_IO)) {
 807                /* looks like a reselection - try resetting the mesh */
 808                dlog(ms, "resel? after arb, intr/exc/err/fc=%.8x",
 809                     MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
 810                out_8(&mr->sequence, SEQ_RESETMESH);
 811                udelay(10);
 812                out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 813                out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 814                out_8(&mr->sequence, SEQ_ENBRESEL);
 815                for (t = 10; t > 0 && mr->interrupt == 0; --t)
 816                        udelay(1);
 817                dlog(ms, "tried reset after arb, intr/exc/err/fc=%.8x",
 818                     MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
 819#ifndef MESH_MULTIPLE_HOSTS
 820                if (mr->interrupt == 0 && (mr->bus_status1 & BS1_SEL)
 821                    && (mr->bus_status0 & BS0_IO)) {
 822                        printk(KERN_ERR "mesh: controller not responding"
 823                               " to reselection!\n");
 824                        /*
 825                         * If this is a target reselecting us, and the
 826                         * mesh isn't responding, the higher levels of
 827                         * the scsi code will eventually time out and
 828                         * reset the bus.
 829                         */
 830                }
 831#endif
 832        }
 833}
 834
 835static inline void
 836add_sdtr_msg(struct mesh_state *ms)
 837{
 838        int i = ms->n_msgout;
 839
 840        ms->msgout[i] = EXTENDED_MESSAGE;
 841        ms->msgout[i+1] = 3;
 842        ms->msgout[i+2] = EXTENDED_SDTR;
 843        ms->msgout[i+3] = mesh_sync_period/4;
 844        ms->msgout[i+4] = (ALLOW_SYNC(ms->conn_tgt)? mesh_sync_offset: 0);
 845        ms->n_msgout = i + 5;
 846}
 847
 848static void
 849set_sdtr(struct mesh_state *ms, int period, int offset)
 850{
 851        struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
 852        volatile struct mesh_regs *mr = ms->mesh;
 853        int v, tr;
 854
 855        tp->sdtr_state = sdtr_done;
 856        if (offset == 0) {
 857                /* asynchronous */
 858                if (SYNC_OFF(tp->sync_params))
 859                        printk(KERN_INFO "mesh: target %d now asynchronous\n",
 860                               ms->conn_tgt);
 861                tp->sync_params = ASYNC_PARAMS;
 862                out_8(&mr->sync_params, ASYNC_PARAMS);
 863                return;
 864        }
 865        /*
 866         * We need to compute ceil(clk_freq * period / 500e6) - 2
 867         * without incurring overflow.
 868         */
 869        v = (ms->clk_freq / 5000) * period;
 870        if (v <= 250000) {
 871                /* special case: sync_period == 5 * clk_period */
 872                v = 0;
 873                /* units of tr are 100kB/s */
 874                tr = (ms->clk_freq + 250000) / 500000;
 875        } else {
 876                /* sync_period == (v + 2) * 2 * clk_period */
 877                v = (v + 99999) / 100000 - 2;
 878                if (v > 15)
 879                        v = 15; /* oops */
 880                tr = ((ms->clk_freq / (v + 2)) + 199999) / 200000;
 881        }
 882        if (offset > 15)
 883                offset = 15;    /* can't happen */
 884        tp->sync_params = SYNC_PARAMS(offset, v);
 885        out_8(&mr->sync_params, tp->sync_params);
 886        printk(KERN_INFO "mesh: target %d synchronous at %d.%d MB/s\n",
 887               ms->conn_tgt, tr/10, tr%10);
 888}
 889
 890static void
 891start_phase(struct mesh_state *ms)
 892{
 893        int i, seq, nb;
 894        volatile struct mesh_regs *mr = ms->mesh;
 895        volatile struct dbdma_regs *md = ms->dma;
 896        Scsi_Cmnd *cmd = ms->current_req;
 897        struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
 898
 899        dlog(ms, "start_phase nmo/exc/fc/seq = %.8x",
 900             MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence));
 901        out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 902        seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
 903        switch (ms->msgphase) {
 904        case msg_none:
 905                break;
 906
 907        case msg_in:
 908                out_8(&mr->count_hi, 0);
 909                out_8(&mr->count_lo, 1);
 910                out_8(&mr->sequence, SEQ_MSGIN + seq);
 911                ms->n_msgin = 0;
 912                return;
 913
 914        case msg_out:
 915                /*
 916                 * To make sure ATN drops before we assert ACK for
 917                 * the last byte of the message, we have to do the
 918                 * last byte specially.
 919                 */
 920                if (ms->n_msgout <= 0) {
 921                        printk(KERN_ERR "mesh: msg_out but n_msgout=%d\n",
 922                               ms->n_msgout);
 923                        mesh_dump_regs(ms);
 924                        ms->msgphase = msg_none;
 925                        break;
 926                }
 927                if (ALLOW_DEBUG(ms->conn_tgt)) {
 928                        printk(KERN_DEBUG "mesh: sending %d msg bytes:",
 929                               ms->n_msgout);
 930                        for (i = 0; i < ms->n_msgout; ++i)
 931                                printk(" %x", ms->msgout[i]);
 932                        printk("\n");
 933                }
 934                dlog(ms, "msgout msg=%.8x", MKWORD(ms->n_msgout, ms->msgout[0],
 935                                                ms->msgout[1], ms->msgout[2]));
 936                out_8(&mr->count_hi, 0);
 937                out_8(&mr->sequence, SEQ_FLUSHFIFO);
 938                udelay(1);
 939                /*
 940                 * If ATN is not already asserted, we assert it, then
 941                 * issue a SEQ_MSGOUT to get the mesh to drop ACK.
 942                 */
 943                if ((mr->bus_status0 & BS0_ATN) == 0) {
 944                        dlog(ms, "bus0 was %.2x explictly asserting ATN", mr->bus_status0);
 945                        out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */
 946                        udelay(1);
 947                        out_8(&mr->count_lo, 1);
 948                        out_8(&mr->sequence, SEQ_MSGOUT + seq);
 949                        out_8(&mr->bus_status0, 0); /* release explicit ATN */
 950                        dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0);
 951                }
 952                if (ms->n_msgout == 1) {
 953                        /*
 954                         * We can't issue the SEQ_MSGOUT without ATN
 955                         * until the target has asserted REQ.  The logic
 956                         * in cmd_complete handles both situations:
 957                         * REQ already asserted or not.
 958                         */
 959                        cmd_complete(ms);
 960                } else {
 961                        out_8(&mr->count_lo, ms->n_msgout - 1);
 962                        out_8(&mr->sequence, SEQ_MSGOUT + seq);
 963                        for (i = 0; i < ms->n_msgout - 1; ++i)
 964                                out_8(&mr->fifo, ms->msgout[i]);
 965                }
 966                return;
 967
 968        default:
 969                printk(KERN_ERR "mesh bug: start_phase msgphase=%d\n",
 970                       ms->msgphase);
 971        }
 972
 973        switch (ms->phase) {
 974        case selecting:
 975                out_8(&mr->dest_id, ms->conn_tgt);
 976                out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN);
 977                break;
 978        case commanding:
 979                out_8(&mr->sync_params, tp->sync_params);
 980                out_8(&mr->count_hi, 0);
 981                if (cmd) {
 982                        out_8(&mr->count_lo, cmd->cmd_len);
 983                        out_8(&mr->sequence, SEQ_COMMAND + seq);
 984                        for (i = 0; i < cmd->cmd_len; ++i)
 985                                out_8(&mr->fifo, cmd->cmnd[i]);
 986                } else {
 987                        out_8(&mr->count_lo, 6);
 988                        out_8(&mr->sequence, SEQ_COMMAND + seq);
 989                        for (i = 0; i < 6; ++i)
 990                                out_8(&mr->fifo, 0);
 991                }
 992                break;
 993        case dataing:
 994                /* transfer data, if any */
 995                if (!ms->dma_started) {
 996                        set_dma_cmds(ms, cmd);
 997                        out_le32(&md->cmdptr, virt_to_phys(ms->dma_cmds));
 998                        out_le32(&md->control, (RUN << 16) | RUN);
 999                        ms->dma_started = 1;
1000                }
1001                nb = ms->dma_count;
1002                if (nb > 0xfff0)
1003                        nb = 0xfff0;
1004                ms->dma_count -= nb;
1005                ms->data_ptr += nb;
1006                out_8(&mr->count_lo, nb);
1007                out_8(&mr->count_hi, nb >> 8);
1008                out_8(&mr->sequence, (tp->data_goes_out?
1009                                SEQ_DATAOUT: SEQ_DATAIN) + SEQ_DMA_MODE + seq);
1010                break;
1011        case statusing:
1012                out_8(&mr->count_hi, 0);
1013                out_8(&mr->count_lo, 1);
1014                out_8(&mr->sequence, SEQ_STATUS + seq);
1015                break;
1016        case busfreeing:
1017        case disconnecting:
1018                out_8(&mr->sequence, SEQ_ENBRESEL);
1019                udelay(1);
1020                dlog(ms, "enbresel intr/exc/err/fc=%.8x",
1021                     MKWORD(mr->interrupt, mr->exception, mr->error,
1022                            mr->fifo_count));
1023                out_8(&mr->sequence, SEQ_BUSFREE);
1024                break;
1025        default:
1026                printk(KERN_ERR "mesh: start_phase called with phase=%d\n",
1027                       ms->phase);
1028                dumpslog(ms);
1029        }
1030
1031}
1032
1033static inline void
1034get_msgin(struct mesh_state *ms)
1035{
1036        volatile struct mesh_regs *mr = ms->mesh;
1037        int i, n;
1038
1039        n = mr->fifo_count;
1040        if (n != 0) {
1041                i = ms->n_msgin;
1042                ms->n_msgin = i + n;
1043                for (; n > 0; --n)
1044                        ms->msgin[i++] = in_8(&mr->fifo);
1045        }
1046}
1047
1048static inline int
1049msgin_length(struct mesh_state *ms)
1050{
1051        int b, n;
1052
1053        n = 1;
1054        if (ms->n_msgin > 0) {
1055                b = ms->msgin[0];
1056                if (b == 1) {
1057                        /* extended message */
1058                        n = ms->n_msgin < 2? 2: ms->msgin[1] + 2;
1059                } else if (0x20 <= b && b <= 0x2f) {
1060                        /* 2-byte message */
1061                        n = 2;
1062                }
1063        }
1064        return n;
1065}
1066
1067static void
1068cmd_complete(struct mesh_state *ms)
1069{
1070        volatile struct mesh_regs *mr = ms->mesh;
1071        Scsi_Cmnd *cmd = ms->current_req;
1072        struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1073        int seq, n, t;
1074
1075        dlog(ms, "cmd_complete fc=%x", mr->fifo_count);
1076        seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
1077        switch (ms->msgphase) {
1078        case msg_out_xxx:
1079                /* huh?  we expected a phase mismatch */
1080                ms->n_msgin = 0;
1081                ms->msgphase = msg_in;
1082                /* fall through */
1083
1084        case msg_in:
1085                /* should have some message bytes in fifo */
1086                get_msgin(ms);
1087                n = msgin_length(ms);
1088                if (ms->n_msgin < n) {
1089                        out_8(&mr->count_lo, n - ms->n_msgin);
1090                        out_8(&mr->sequence, SEQ_MSGIN + seq);
1091                } else {
1092                        ms->msgphase = msg_none;
1093                        handle_msgin(ms);
1094                        start_phase(ms);
1095                }
1096                break;
1097
1098        case msg_in_bad:
1099                out_8(&mr->sequence, SEQ_FLUSHFIFO);
1100                udelay(1);
1101                out_8(&mr->count_lo, 1);
1102                out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg);
1103                break;
1104
1105        case msg_out:
1106                /*
1107                 * To get the right timing on ATN wrt ACK, we have
1108                 * to get the MESH to drop ACK, wait until REQ gets
1109                 * asserted, then drop ATN.  To do this we first
1110                 * issue a SEQ_MSGOUT with ATN and wait for REQ,
1111                 * then change the command to a SEQ_MSGOUT w/o ATN.
1112                 * If we don't see REQ in a reasonable time, we
1113                 * change the command to SEQ_MSGIN with ATN,
1114                 * wait for the phase mismatch interrupt, then
1115                 * issue the SEQ_MSGOUT without ATN.
1116                 */
1117                out_8(&mr->count_lo, 1);
1118                out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN);
1119                t = 30;         /* wait up to 30us */
1120                while ((mr->bus_status0 & BS0_REQ) == 0 && --t >= 0)
1121                        udelay(1);
1122                dlog(ms, "last_mbyte err/exc/fc/cl=%.8x",
1123                     MKWORD(mr->error, mr->exception,
1124                            mr->fifo_count, mr->count_lo));
1125                if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) {
1126                        /* whoops, target didn't do what we expected */
1127                        ms->last_n_msgout = ms->n_msgout;
1128                        ms->n_msgout = 0;
1129                        if (in_8(&mr->interrupt) & INT_ERROR) {
1130                                printk(KERN_ERR "mesh: error %x in msg_out\n",
1131                                       in_8(&mr->error));
1132                                handle_error(ms);
1133                                return;
1134                        }
1135                        if (in_8(&mr->exception) != EXC_PHASEMM)
1136                                printk(KERN_ERR "mesh: exc %x in msg_out\n",
1137                                       in_8(&mr->exception));
1138                        else
1139                                printk(KERN_DEBUG "mesh: bs0=%x in msg_out\n",
1140                                       in_8(&mr->bus_status0));
1141                        handle_exception(ms);
1142                        return;
1143                }
1144                if (mr->bus_status0 & BS0_REQ) {
1145                        out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1146                        udelay(1);
1147                        out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1148                        ms->msgphase = msg_out_last;
1149                } else {
1150                        out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN);
1151                        ms->msgphase = msg_out_xxx;
1152                }
1153                break;
1154
1155        case msg_out_last:
1156                ms->last_n_msgout = ms->n_msgout;
1157                ms->n_msgout = 0;
1158                ms->msgphase = ms->expect_reply? msg_in: msg_none;
1159                start_phase(ms);
1160                break;
1161
1162        case msg_none:
1163                switch (ms->phase) {
1164                case idle:
1165                        printk(KERN_ERR "mesh: interrupt in idle phase?\n");
1166                        dumpslog(ms);
1167                        return;
1168                case selecting:
1169                        dlog(ms, "Selecting phase at command completion",0);
1170                        ms->msgout[0] = IDENTIFY(ALLOW_RESEL(ms->conn_tgt),
1171                                                 (cmd? cmd->lun: 0));
1172                        ms->n_msgout = 1;
1173                        ms->expect_reply = 0;
1174                        if (ms->aborting) {
1175                                ms->msgout[0] = ABORT;
1176                                ms->n_msgout++;
1177                        } else if (tp->sdtr_state == do_sdtr) {
1178                                /* add SDTR message */
1179                                add_sdtr_msg(ms);
1180                                ms->expect_reply = 1;
1181                                tp->sdtr_state = sdtr_sent;
1182                        }
1183                        ms->msgphase = msg_out;
1184                        /*
1185                         * We need to wait for REQ before dropping ATN.
1186                         * We wait for at most 30us, then fall back to
1187                         * a scheme where we issue a SEQ_COMMAND with ATN,
1188                         * which will give us a phase mismatch interrupt
1189                         * when REQ does come, and then we send the message.
1190                         */
1191                        t = 230;                /* wait up to 230us */
1192                        while ((mr->bus_status0 & BS0_REQ) == 0) {
1193                                if (--t < 0) {
1194                                        dlog(ms, "impatient for req", ms->n_msgout);
1195                                        ms->msgphase = msg_none;
1196                                        break;
1197                                }
1198                                udelay(1);
1199                        }
1200                        break;
1201                case dataing:
1202                        if (ms->dma_count != 0) {
1203                                start_phase(ms);
1204                                return;
1205                        }
1206                        /*
1207                         * We can get a phase mismatch here if the target
1208                         * changes to the status phase, even though we have
1209                         * had a command complete interrupt.  Then, if we
1210                         * issue the SEQ_STATUS command, we'll get a sequence
1211                         * error interrupt.  Which isn't so bad except that
1212                         * occasionally the mesh actually executes the
1213                         * SEQ_STATUS *as well as* giving us the sequence
1214                         * error and phase mismatch exception.
1215                         */
1216                        out_8(&mr->sequence, 0);
1217                        out_8(&mr->interrupt,
1218                              INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1219                        halt_dma(ms);
1220                        break;
1221                case statusing:
1222                        if (cmd) {
1223                                cmd->SCp.Status = mr->fifo;
1224                                if (DEBUG_TARGET(cmd))
1225                                        printk(KERN_DEBUG "mesh: status is %x\n",
1226                                               cmd->SCp.Status);
1227                        }
1228                        ms->msgphase = msg_in;
1229                        break;
1230                case busfreeing:
1231                        mesh_done(ms, 1);
1232                        return;
1233                case disconnecting:
1234                        ms->current_req = 0;
1235                        ms->phase = idle;
1236                        mesh_start(ms);
1237                        return;
1238                default:
1239                        break;
1240                }
1241                ++ms->phase;
1242                start_phase(ms);
1243                break;
1244        }
1245}
1246
1247static void phase_mismatch(struct mesh_state *ms)
1248{
1249        volatile struct mesh_regs *mr = ms->mesh;
1250        int phase;
1251
1252        dlog(ms, "phasemm ch/cl/seq/fc=%.8x",
1253             MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count));
1254        phase = mr->bus_status0 & BS0_PHASE;
1255        if (ms->msgphase == msg_out_xxx && phase == BP_MSGOUT) {
1256                /* output the last byte of the message, without ATN */
1257                out_8(&mr->count_lo, 1);
1258                out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1259                udelay(1);
1260                out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1261                ms->msgphase = msg_out_last;
1262                return;
1263        }
1264
1265        if (ms->msgphase == msg_in) {
1266                get_msgin(ms);
1267                if (ms->n_msgin)
1268                        handle_msgin(ms);
1269        }
1270
1271        if (ms->dma_started)
1272                halt_dma(ms);
1273        if (mr->fifo_count) {
1274                out_8(&mr->sequence, SEQ_FLUSHFIFO);
1275                udelay(1);
1276        }
1277
1278        ms->msgphase = msg_none;
1279        switch (phase) {
1280        case BP_DATAIN:
1281                ms->tgts[ms->conn_tgt].data_goes_out = 0;
1282                ms->phase = dataing;
1283                break;
1284        case BP_DATAOUT:
1285                ms->tgts[ms->conn_tgt].data_goes_out = 1;
1286                ms->phase = dataing;
1287                break;
1288        case BP_COMMAND:
1289                ms->phase = commanding;
1290                break;
1291        case BP_STATUS:
1292                ms->phase = statusing;
1293                break;
1294        case BP_MSGIN:
1295                ms->msgphase = msg_in;
1296                ms->n_msgin = 0;
1297                break;
1298        case BP_MSGOUT:
1299                ms->msgphase = msg_out;
1300                if (ms->n_msgout == 0) {
1301                        if (ms->aborting) {
1302                                do_abort(ms);
1303                        } else {
1304                                if (ms->last_n_msgout == 0) {
1305                                        printk(KERN_DEBUG
1306                                               "mesh: no msg to repeat\n");
1307                                        ms->msgout[0] = NOP;
1308                                        ms->last_n_msgout = 1;
1309                                }
1310                                ms->n_msgout = ms->last_n_msgout;
1311                        }
1312                }
1313                break;
1314        default:
1315                printk(KERN_DEBUG "mesh: unknown scsi phase %x\n", phase);
1316                ms->stat = DID_ERROR;
1317                mesh_done(ms, 1);
1318                return;
1319        }
1320
1321        start_phase(ms);
1322}
1323
1324static void
1325reselected(struct mesh_state *ms)
1326{
1327        volatile struct mesh_regs *mr = ms->mesh;
1328        Scsi_Cmnd *cmd;
1329        struct mesh_target *tp;
1330        int b, t, prev;
1331
1332        switch (ms->phase) {
1333        case idle:
1334                break;
1335        case arbitrating:
1336                if ((cmd = ms->current_req) != NULL) {
1337                        /* put the command back on the queue */
1338                        cmd->host_scribble = (void *) ms->request_q;
1339                        if (ms->request_q == NULL)
1340                                ms->request_qtail = cmd;
1341                        ms->request_q = cmd;
1342                        tp = &ms->tgts[cmd->target];
1343                        tp->current_req = NULL;
1344                }
1345                break;
1346        case busfreeing:
1347                ms->phase = reselecting;
1348                mesh_done(ms, 0);
1349                break;
1350        case disconnecting:
1351                break;
1352        default:
1353                printk(KERN_ERR "mesh: reselected in phase %d/%d tgt %d\n",
1354                       ms->msgphase, ms->phase, ms->conn_tgt);
1355                dumplog(ms, ms->conn_tgt);
1356                dumpslog(ms);
1357        }
1358
1359        if (ms->dma_started) {
1360                printk(KERN_ERR "mesh: reselected with DMA started !\n");
1361                halt_dma(ms);
1362        }
1363        ms->current_req = NULL;
1364        ms->phase = dataing;
1365        ms->msgphase = msg_in;
1366        ms->n_msgout = 0;
1367        ms->last_n_msgout = 0;
1368        prev = ms->conn_tgt;
1369
1370        /*
1371         * We seem to get abortive reselections sometimes.
1372         */
1373        while ((mr->bus_status1 & BS1_BSY) == 0) {
1374                static int mesh_aborted_resels;
1375                mesh_aborted_resels++;
1376                out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1377                udelay(1);
1378                out_8(&mr->sequence, SEQ_ENBRESEL);
1379                udelay(5);
1380                dlog(ms, "extra resel err/exc/fc = %.6x",
1381                     MKWORD(0, mr->error, mr->exception, mr->fifo_count));
1382        }
1383        out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1384        udelay(1);
1385        out_8(&mr->sequence, SEQ_ENBRESEL);
1386        udelay(1);
1387        out_8(&mr->sync_params, ASYNC_PARAMS);
1388
1389        /*
1390         * Find out who reselected us.
1391         */
1392        if (mr->fifo_count == 0) {
1393                printk(KERN_ERR "mesh: reselection but nothing in fifo?\n");
1394                ms->conn_tgt = ms->host->this_id;
1395                goto bogus;
1396        }
1397        /* get the last byte in the fifo */
1398        do {
1399                b = in_8(&mr->fifo);
1400                dlog(ms, "reseldata %x", b);
1401        } while (in_8(&mr->fifo_count));
1402        for (t = 0; t < 8; ++t)
1403                if ((b & (1 << t)) != 0 && t != ms->host->this_id)
1404                        break;
1405        if (b != (1 << t) + (1 << ms->host->this_id)) {
1406                printk(KERN_ERR "mesh: bad reselection data %x\n", b);
1407                ms->conn_tgt = ms->host->this_id;
1408                goto bogus;
1409        }
1410
1411
1412        /*
1413         * Set up to continue with that target's transfer.
1414         */
1415        ms->conn_tgt = t;
1416        tp = &ms->tgts[t];
1417        out_8(&mr->sync_params, tp->sync_params);
1418        if (ALLOW_DEBUG(t)) {
1419                printk(KERN_DEBUG "mesh: reselected by target %d\n", t);
1420                printk(KERN_DEBUG "mesh: saved_ptr=%x goes_out=%d cmd=%p\n",
1421                       tp->saved_ptr, tp->data_goes_out, tp->current_req);
1422        }
1423        ms->current_req = tp->current_req;
1424        if (tp->current_req == NULL) {
1425                printk(KERN_ERR "mesh: reselected by tgt %d but no cmd!\n", t);
1426                goto bogus;
1427        }
1428        ms->data_ptr = tp->saved_ptr;
1429        dlog(ms, "resel prev tgt=%d", prev);
1430        dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception));
1431        start_phase(ms);
1432        return;
1433
1434bogus:
1435        dumplog(ms, ms->conn_tgt);
1436        dumpslog(ms);
1437        ms->data_ptr = 0;
1438        ms->aborting = 1;
1439        start_phase(ms);
1440}
1441
1442static void do_abort(struct mesh_state *ms)
1443{
1444        ms->msgout[0] = ABORT;
1445        ms->n_msgout = 1;
1446        ms->aborting = 1;
1447        ms->stat = DID_ABORT;
1448        dlog(ms, "abort", 0);
1449}
1450
1451static void
1452handle_reset(struct mesh_state *ms)
1453{
1454        int tgt;
1455        struct mesh_target *tp;
1456        Scsi_Cmnd *cmd;
1457        volatile struct mesh_regs *mr = ms->mesh;
1458
1459        for (tgt = 0; tgt < 8; ++tgt) {
1460                tp = &ms->tgts[tgt];
1461                if ((cmd = tp->current_req) != NULL) {
1462                        cmd->result = DID_RESET << 16;
1463                        tp->current_req = NULL;
1464                        mesh_completed(ms, cmd);
1465                }
1466                ms->tgts[tgt].sdtr_state = do_sdtr;
1467                ms->tgts[tgt].sync_params = ASYNC_PARAMS;
1468        }
1469        ms->current_req = NULL;
1470        while ((cmd = ms->request_q) != NULL) {
1471                ms->request_q = (Scsi_Cmnd *) cmd->host_scribble;
1472                cmd->result = DID_RESET << 16;
1473                mesh_completed(ms, cmd);
1474        }
1475        ms->phase = idle;
1476        ms->msgphase = msg_none;
1477        out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1478        out_8(&mr->sequence, SEQ_FLUSHFIFO);
1479        udelay(1);
1480        out_8(&mr->sync_params, ASYNC_PARAMS);
1481        out_8(&mr->sequence, SEQ_ENBRESEL);
1482}
1483
1484static void
1485do_mesh_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
1486{
1487        unsigned long flags;
1488
1489        spin_lock_irqsave(&io_request_lock, flags);
1490        mesh_interrupt(irq, dev_id, ptregs);
1491        spin_unlock_irqrestore(&io_request_lock, flags);
1492}
1493
1494static void handle_error(struct mesh_state *ms)
1495{
1496        int err, exc, count;
1497        volatile struct mesh_regs *mr = ms->mesh;
1498
1499        err = in_8(&mr->error);
1500        exc = in_8(&mr->exception);
1501        out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1502        dlog(ms, "error err/exc/fc/cl=%.8x",
1503             MKWORD(err, exc, mr->fifo_count, mr->count_lo));
1504        if (err & ERR_SCSIRESET) {
1505                /* SCSI bus was reset */
1506                printk(KERN_INFO "mesh: SCSI bus reset detected: "
1507                       "waiting for end...");
1508                while ((mr->bus_status1 & BS1_RST) != 0)
1509                        udelay(1);
1510                printk("done\n");
1511                handle_reset(ms);
1512                /* request_q is empty, no point in mesh_start() */
1513                return;
1514        }
1515        if (err & ERR_UNEXPDISC) {
1516                /* Unexpected disconnect */
1517                if (exc & EXC_RESELECTED) {
1518                        reselected(ms);
1519                        return;
1520                }
1521                if (!ms->aborting) {
1522                        printk(KERN_WARNING "mesh: target %d aborted\n",
1523                               ms->conn_tgt);
1524                        dumplog(ms, ms->conn_tgt);
1525                        dumpslog(ms);
1526                }
1527                out_8(&mr->interrupt, INT_CMDDONE);
1528                ms->stat = DID_ABORT;
1529                mesh_done(ms, 1);
1530                return;
1531        }
1532        if (err & ERR_PARITY) {
1533                if (ms->msgphase == msg_in) {
1534                        printk(KERN_ERR "mesh: msg parity error, target %d\n",
1535                               ms->conn_tgt);
1536                        ms->msgout[0] = MSG_PARITY_ERROR;
1537                        ms->n_msgout = 1;
1538                        ms->msgphase = msg_in_bad;
1539                        cmd_complete(ms);
1540                        return;
1541                }
1542                if (ms->stat == DID_OK) {
1543                        printk(KERN_ERR "mesh: parity error, target %d\n",
1544                               ms->conn_tgt);
1545                        ms->stat = DID_PARITY;
1546                }
1547                count = (mr->count_hi << 8) + mr->count_lo;
1548                if (count == 0) {
1549                        cmd_complete(ms);
1550                } else {
1551                        /* reissue the data transfer command */
1552                        out_8(&mr->sequence, mr->sequence);
1553                }
1554                return;
1555        }
1556        if (err & ERR_SEQERR) {
1557                if (exc & EXC_RESELECTED) {
1558                        /* This can happen if we issue a command to
1559                           get the bus just after the target reselects us. */
1560                        static int mesh_resel_seqerr;
1561                        mesh_resel_seqerr++;
1562                        reselected(ms);
1563                        return;
1564                }
1565                if (exc == EXC_PHASEMM) {
1566                        static int mesh_phasemm_seqerr;
1567                        mesh_phasemm_seqerr++;
1568                        phase_mismatch(ms);
1569                        return;
1570                }
1571                printk(KERN_ERR "mesh: sequence error (err=%x exc=%x)\n",
1572                       err, exc);
1573        } else {
1574                printk(KERN_ERR "mesh: unknown error %x (exc=%x)\n", err, exc);
1575        }
1576        mesh_dump_regs(ms);
1577        dumplog(ms, ms->conn_tgt);
1578        if (ms->phase > selecting && (mr->bus_status1 & BS1_BSY)) {
1579                /* try to do what the target wants */
1580                do_abort(ms);
1581                phase_mismatch(ms);
1582                return;
1583        }
1584        ms->stat = DID_ERROR;
1585        mesh_done(ms, 1);
1586}
1587
1588static void handle_exception(struct mesh_state *ms)
1589{
1590        int exc;
1591        volatile struct mesh_regs *mr = ms->mesh;
1592
1593        exc = in_8(&mr->exception);
1594        out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE);
1595        if (exc & EXC_RESELECTED) {
1596                static int mesh_resel_exc;
1597                mesh_resel_exc++;
1598                reselected(ms);
1599        } else if (exc == EXC_ARBLOST) {
1600                printk(KERN_DEBUG "mesh: lost arbitration\n");
1601                ms->stat = DID_BUS_BUSY;
1602                mesh_done(ms, 1);
1603        } else if (exc == EXC_SELTO) {
1604                /* selection timed out */
1605                ms->stat = DID_BAD_TARGET;
1606                mesh_done(ms, 1);
1607        } else if (exc == EXC_PHASEMM) {
1608                /* target wants to do something different:
1609                   find out what it wants and do it. */
1610                phase_mismatch(ms);
1611        } else {
1612                printk(KERN_ERR "mesh: can't cope with exception %x\n", exc);
1613                mesh_dump_regs(ms);
1614                dumplog(ms, ms->conn_tgt);
1615                do_abort(ms);
1616                phase_mismatch(ms);
1617        }
1618}
1619
1620static void
1621mesh_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
1622{
1623        struct mesh_state *ms = (struct mesh_state *) dev_id;
1624        volatile struct mesh_regs *mr = ms->mesh;
1625        int intr;
1626
1627#if 0
1628        if (ALLOW_DEBUG(ms->conn_tgt))
1629                printk(KERN_DEBUG "mesh_intr, bs0=%x int=%x exc=%x err=%x "
1630                       "phase=%d msgphase=%d\n", mr->bus_status0,
1631                       mr->interrupt, mr->exception, mr->error,
1632                       ms->phase, ms->msgphase);
1633#endif
1634        while ((intr = in_8(&mr->interrupt)) != 0) {
1635                dlog(ms, "interrupt intr/err/exc/seq=%.8x", 
1636                     MKWORD(intr, mr->error, mr->exception, mr->sequence));
1637                if (intr & INT_ERROR) {
1638                        handle_error(ms);
1639                } else if (intr & INT_EXCEPTION) {
1640                        handle_exception(ms);
1641                } else if (intr & INT_CMDDONE) {
1642                        out_8(&mr->interrupt, INT_CMDDONE);
1643                        cmd_complete(ms);
1644                }
1645        }
1646}
1647
1648static void
1649handle_msgin(struct mesh_state *ms)
1650{
1651        int i, code;
1652        Scsi_Cmnd *cmd = ms->current_req;
1653        struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1654
1655        if (ms->n_msgin == 0)
1656                return;
1657        code = ms->msgin[0];
1658        if (ALLOW_DEBUG(ms->conn_tgt)) {
1659                printk(KERN_DEBUG "got %d message bytes:", ms->n_msgin);
1660                for (i = 0; i < ms->n_msgin; ++i)
1661                        printk(" %x", ms->msgin[i]);
1662                printk("\n");
1663        }
1664        dlog(ms, "msgin msg=%.8x",
1665             MKWORD(ms->n_msgin, code, ms->msgin[1], ms->msgin[2]));
1666
1667        ms->expect_reply = 0;
1668        ms->n_msgout = 0;
1669        if (ms->n_msgin < msgin_length(ms))
1670                goto reject;
1671        if (cmd)
1672                cmd->SCp.Message = code;
1673        switch (code) {
1674        case COMMAND_COMPLETE:
1675                break;
1676        case EXTENDED_MESSAGE:
1677                switch (ms->msgin[2]) {
1678                case EXTENDED_MODIFY_DATA_POINTER:
1679                        ms->data_ptr += (ms->msgin[3] << 24) + ms->msgin[6]
1680                                + (ms->msgin[4] << 16) + (ms->msgin[5] << 8);
1681                        break;
1682                case EXTENDED_SDTR:
1683                        if (tp->sdtr_state != sdtr_sent) {
1684                                /* reply with an SDTR */
1685                                add_sdtr_msg(ms);
1686                                /* limit period to at least his value,
1687                                   offset to no more than his */
1688                                if (ms->msgout[3] < ms->msgin[3])
1689                                        ms->msgout[3] = ms->msgin[3];
1690                                if (ms->msgout[4] > ms->msgin[4])
1691                                        ms->msgout[4] = ms->msgin[4];
1692                                set_sdtr(ms, ms->msgout[3], ms->msgout[4]);
1693                                ms->msgphase = msg_out;
1694                        } else {
1695                                set_sdtr(ms, ms->msgin[3], ms->msgin[4]);
1696                        }
1697                        break;
1698                default:
1699                        goto reject;
1700                }
1701                break;
1702        case SAVE_POINTERS:
1703                tp->saved_ptr = ms->data_ptr;
1704                break;
1705        case RESTORE_POINTERS:
1706                ms->data_ptr = tp->saved_ptr;
1707                break;
1708        case DISCONNECT:
1709                ms->phase = disconnecting;
1710                break;
1711        case ABORT:
1712                break;
1713        case MESSAGE_REJECT:
1714                if (tp->sdtr_state == sdtr_sent)
1715                        set_sdtr(ms, 0, 0);
1716                break;
1717        case NOP:
1718                break;
1719        default:
1720                if (IDENTIFY_BASE <= code && code <= IDENTIFY_BASE + 7) {
1721                        if (cmd == NULL) {
1722                                do_abort(ms);
1723                                ms->msgphase = msg_out;
1724                        } else if (code != cmd->lun + IDENTIFY_BASE) {
1725                                printk(KERN_WARNING "mesh: lun mismatch "
1726                                       "(%d != %d) on reselection from "
1727                                       "target %d\n", i, cmd->lun,
1728                                       ms->conn_tgt);
1729                        }
1730                        break;
1731                }
1732                goto reject;
1733        }
1734        return;
1735
1736 reject:
1737        printk(KERN_WARNING "mesh: rejecting message from target %d:",
1738               ms->conn_tgt);
1739        for (i = 0; i < ms->n_msgin; ++i)
1740                printk(" %x", ms->msgin[i]);
1741        printk("\n");
1742        ms->msgout[0] = MESSAGE_REJECT;
1743        ms->n_msgout = 1;
1744        ms->msgphase = msg_out;
1745}
1746
1747static void
1748mesh_done(struct mesh_state *ms, int start_next)
1749{
1750        Scsi_Cmnd *cmd;
1751        struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1752
1753        cmd = ms->current_req;
1754        ms->current_req = 0;
1755        tp->current_req = 0;
1756        if (cmd) {
1757                cmd->result = (ms->stat << 16) + cmd->SCp.Status;
1758                if (ms->stat == DID_OK)
1759                        cmd->result += (cmd->SCp.Message << 8);
1760                if (DEBUG_TARGET(cmd)) {
1761                        printk(KERN_DEBUG "mesh_done: result = %x, data_ptr=%d, buflen=%d\n",
1762                               cmd->result, ms->data_ptr, cmd->request_bufflen);
1763                        if ((cmd->cmnd[0] == 0 || cmd->cmnd[0] == 0x12 || cmd->cmnd[0] == 3)
1764                            && cmd->request_buffer != 0) {
1765                                unsigned char *b = cmd->request_buffer;
1766                                printk(KERN_DEBUG "buffer = %x %x %x %x %x %x %x %x\n",
1767                                       b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
1768                        }
1769                }
1770                cmd->SCp.this_residual -= ms->data_ptr;
1771                mesh_completed(ms, cmd);
1772        }
1773        if (start_next) {
1774                out_8(&ms->mesh->sequence, SEQ_ENBRESEL);
1775                udelay(1);
1776                ms->phase = idle;
1777                mesh_start(ms);
1778        }
1779}
1780
1781static void
1782mesh_completed(struct mesh_state *ms, Scsi_Cmnd *cmd)
1783{
1784        (*cmd->scsi_done)(cmd);
1785}
1786
1787/*
1788 * Set up DMA commands for transferring data.
1789 */
1790static void
1791set_dma_cmds(struct mesh_state *ms, Scsi_Cmnd *cmd)
1792{
1793        int i, dma_cmd, total, off, dtot;
1794        struct scatterlist *scl;
1795        struct dbdma_cmd *dcmds;
1796
1797        dma_cmd = ms->tgts[ms->conn_tgt].data_goes_out?
1798                OUTPUT_MORE: INPUT_MORE;
1799        dcmds = ms->dma_cmds;
1800        dtot = 0;
1801        if (cmd) {
1802                cmd->SCp.this_residual = cmd->request_bufflen;
1803                if (cmd->use_sg > 0) {
1804                        int nseg;
1805                        total = 0;
1806                        scl = (struct scatterlist *) cmd->buffer;
1807                        off = ms->data_ptr;
1808                        nseg = pci_map_sg(ms->pdev, scl, cmd->use_sg,
1809                                 scsi_to_pci_dma_dir(cmd ->sc_data_direction));
1810                        for (i = 0; i <nseg; ++i, ++scl) {
1811                                u32 dma_addr = sg_dma_address(scl);
1812                                u32 dma_len = sg_dma_len(scl);
1813                                
1814                                total += scl->length;
1815                                if (off >= dma_len) {
1816                                        off -= dma_len;
1817                                        continue;
1818                                }
1819                                if (dma_len > 0xffff)
1820                                        panic("mesh: scatterlist element >= 64k");
1821                                st_le16(&dcmds->req_count, dma_len - off);
1822                                st_le16(&dcmds->command, dma_cmd);
1823                                st_le32(&dcmds->phy_addr, dma_addr + off);
1824                                dcmds->xfer_status = 0;
1825                                ++dcmds;
1826                                dtot += dma_len - off;
1827                                off = 0;
1828                        }
1829                } else if (ms->data_ptr < cmd->request_bufflen) {
1830                        dtot = cmd->request_bufflen - ms->data_ptr;
1831                        if (dtot > 0xffff)
1832                                panic("mesh: transfer size >= 64k");
1833                        st_le16(&dcmds->req_count, dtot);
1834                        /* XXX Use pci DMA API here ... */
1835                        st_le32(&dcmds->phy_addr,
1836                                virt_to_phys(cmd->request_buffer) + ms->data_ptr);
1837                        dcmds->xfer_status = 0;
1838                        ++dcmds;
1839                }
1840        }
1841        if (dtot == 0) {
1842                /* Either the target has overrun our buffer,
1843                   or the caller didn't provide a buffer. */
1844                static char mesh_extra_buf[64];
1845
1846                dtot = sizeof(mesh_extra_buf);
1847                st_le16(&dcmds->req_count, dtot);
1848                st_le32(&dcmds->phy_addr, virt_to_phys(mesh_extra_buf));
1849                dcmds->xfer_status = 0;
1850                ++dcmds;
1851        }
1852        dma_cmd += OUTPUT_LAST - OUTPUT_MORE;
1853        st_le16(&dcmds[-1].command, dma_cmd);
1854        memset(dcmds, 0, sizeof(*dcmds));
1855        st_le16(&dcmds->command, DBDMA_STOP);
1856        ms->dma_count = dtot;
1857}
1858
1859static void
1860halt_dma(struct mesh_state *ms)
1861{
1862        volatile struct dbdma_regs *md = ms->dma;
1863        volatile struct mesh_regs *mr = ms->mesh;
1864        Scsi_Cmnd *cmd = ms->current_req;
1865        int t, nb;
1866
1867        if (!ms->tgts[ms->conn_tgt].data_goes_out) {
1868                /* wait a little while until the fifo drains */
1869                t = 50;
1870                while (t > 0 && mr->fifo_count != 0
1871                       && (in_le32(&md->status) & ACTIVE) != 0) {
1872                        --t;
1873                        udelay(1);
1874                }
1875        }
1876        out_le32(&md->control, RUN << 16);      /* turn off RUN bit */
1877        nb = (mr->count_hi << 8) + mr->count_lo;
1878        dlog(ms, "halt_dma fc/count=%.6x",
1879             MKWORD(0, mr->fifo_count, 0, nb));
1880        if (ms->tgts[ms->conn_tgt].data_goes_out)
1881                nb += mr->fifo_count;
1882        /* nb is the number of bytes not yet transferred
1883           to/from the target. */
1884        ms->data_ptr -= nb;
1885        dlog(ms, "data_ptr %x", ms->data_ptr);
1886        if (ms->data_ptr < 0) {
1887                printk(KERN_ERR "mesh: halt_dma: data_ptr=%d (nb=%d, ms=%p)\n",
1888                       ms->data_ptr, nb, ms);
1889                ms->data_ptr = 0;
1890#ifdef MESH_DBG
1891                dumplog(ms, ms->conn_tgt);
1892                dumpslog(ms);
1893#endif /* MESH_DBG */
1894        } else if (cmd && cmd->request_bufflen != 0 &&
1895                   ms->data_ptr > cmd->request_bufflen) {
1896                printk(KERN_DEBUG "mesh: target %d overrun, "
1897                       "data_ptr=%x total=%x goes_out=%d\n",
1898                       ms->conn_tgt, ms->data_ptr, cmd->request_bufflen,
1899                       ms->tgts[ms->conn_tgt].data_goes_out);
1900        }
1901        if (cmd->use_sg != 0) {
1902                struct scatterlist *sg;
1903                sg = (struct scatterlist *)cmd->request_buffer;
1904                pci_unmap_sg(ms->pdev, sg, cmd->use_sg,
1905                             scsi_to_pci_dma_dir(cmd->sc_data_direction));
1906        }
1907        ms->dma_started = 0;
1908}
1909
1910/*
1911 * Work out whether we expect data to go out from the host adaptor or into it.
1912 * (If this information is available from somewhere else in the scsi
1913 * code, somebody please let me know :-)
1914 */
1915static int
1916data_goes_out(Scsi_Cmnd *cmd)
1917{
1918        switch (cmd->cmnd[0]) {
1919        case CHANGE_DEFINITION: 
1920        case COMPARE:     
1921        case COPY:
1922        case COPY_VERIFY:           
1923        case FORMAT_UNIT:        
1924        case LOG_SELECT:
1925        case MEDIUM_SCAN:         
1926        case MODE_SELECT:
1927        case MODE_SELECT_10:
1928        case REASSIGN_BLOCKS: 
1929        case RESERVE:
1930        case SEARCH_EQUAL:        
1931        case SEARCH_EQUAL_12: 
1932        case SEARCH_HIGH:        
1933        case SEARCH_HIGH_12:  
1934        case SEARCH_LOW:
1935        case SEARCH_LOW_12:
1936        case SEND_DIAGNOSTIC: 
1937        case SEND_VOLUME_TAG:        
1938        case SET_WINDOW: 
1939        case UPDATE_BLOCK:      
1940        case WRITE_BUFFER:
1941        case WRITE_6:   
1942        case WRITE_10:  
1943        case WRITE_12:    
1944        case WRITE_LONG:        
1945        case WRITE_LONG_2:      /* alternate code for WRITE_LONG */
1946        case WRITE_SAME:        
1947        case WRITE_VERIFY:
1948        case WRITE_VERIFY_12:
1949                return 1;
1950        default:
1951                return 0;
1952        }
1953}
1954
1955#ifdef MESH_DBG
1956static inline u32 readtb(void)
1957{
1958        u32 tb;
1959
1960#ifdef DBG_USE_TB
1961        /* Beware: if you enable this, it will crash on 601s. */
1962        asm ("mftb %0" : "=r" (tb) : );
1963#else
1964        tb = 0;
1965#endif
1966        return tb;
1967}
1968
1969static void dlog(struct mesh_state *ms, char *fmt, int a)
1970{
1971        struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1972        struct dbglog *tlp, *slp;
1973
1974        tlp = &tp->log[tp->log_ix];
1975        slp = &ms->log[ms->log_ix];
1976        tlp->fmt = fmt;
1977        tlp->tb = readtb();
1978        tlp->phase = (ms->msgphase << 4) + ms->phase;
1979        tlp->bs0 = ms->mesh->bus_status0;
1980        tlp->bs1 = ms->mesh->bus_status1;
1981        tlp->tgt = ms->conn_tgt;
1982        tlp->d = a;
1983        *slp = *tlp;
1984        if (++tp->log_ix >= N_DBG_LOG)
1985                tp->log_ix = 0;
1986        if (tp->n_log < N_DBG_LOG)
1987                ++tp->n_log;
1988        if (++ms->log_ix >= N_DBG_SLOG)
1989                ms->log_ix = 0;
1990        if (ms->n_log < N_DBG_SLOG)
1991                ++ms->n_log;
1992}
1993
1994static void dumplog(struct mesh_state *ms, int t)
1995{
1996        struct mesh_target *tp = &ms->tgts[t];
1997        struct dbglog *lp;
1998        int i;
1999
2000        if (tp->n_log == 0)
2001                return;
2002        i = tp->log_ix - tp->n_log;
2003        if (i < 0)
2004                i += N_DBG_LOG;
2005        tp->n_log = 0;
2006        do {
2007                lp = &tp->log[i];
2008                printk(KERN_DEBUG "mesh log %d: bs=%.2x%.2x ph=%.2x ",
2009                       t, lp->bs1, lp->bs0, lp->phase);
2010#ifdef DBG_USE_TB
2011                printk("tb=%10u ", lp->tb);
2012#endif
2013                printk(lp->fmt, lp->d);
2014                printk("\n");
2015                if (++i >= N_DBG_LOG)
2016                        i = 0;
2017        } while (i != tp->log_ix);
2018}
2019
2020static void dumpslog(struct mesh_state *ms)
2021{
2022        struct dbglog *lp;
2023        int i;
2024
2025        if (ms->n_log == 0)
2026                return;
2027        i = ms->log_ix - ms->n_log;
2028        if (i < 0)
2029                i += N_DBG_SLOG;
2030        ms->n_log = 0;
2031        do {
2032                lp = &ms->log[i];
2033                printk(KERN_DEBUG "mesh log: bs=%.2x%.2x ph=%.2x t%d ",
2034                       lp->bs1, lp->bs0, lp->phase, lp->tgt);
2035#ifdef DBG_USE_TB
2036                printk("tb=%10u ", lp->tb);
2037#endif
2038                printk(lp->fmt, lp->d);
2039                printk("\n");
2040                if (++i >= N_DBG_SLOG)
2041                        i = 0;
2042        } while (i != ms->log_ix);
2043}
2044#endif /* MESH_DBG */
2045
2046static Scsi_Host_Template driver_template = SCSI_MESH;
2047
2048#include "scsi_module.c"
2049
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.