LXR linux-old/drivers/scsi/gdth.h

   1#ifndef _GDTH_H
   2#define _GDTH_H
   3
   4/*
   5 * Header file for the GDT Disk Array/Storage RAID controllers driver for Linux
   6 * 
   7 * gdth.h Copyright (C) 1995-03 ICP vortex, Achim Leubner
   8 * See gdth.c for further informations and 
   9 * below for supported controller types
  10 *
  11 * <achim_leubner@adaptec.com>
  12 *
  13 * $Id: gdth.h,v 1.57 2004/03/31 11:52:09 achim Exp $
  14 */
  15
  16#include <linux/version.h>
  17#include <linux/types.h>
  18
  19#ifndef TRUE
  20#define TRUE 1
  21#endif
  22#ifndef FALSE
  23#define FALSE 0
  24#endif
  25
  26/* defines, macros */
  27
  28/* driver version */
  29#define GDTH_VERSION_STR        "3.04"
  30#define GDTH_VERSION            3
  31#define GDTH_SUBVERSION         4
  32
  33/* protocol version */
  34#define PROTOCOL_VERSION        1
  35
  36/* OEM IDs */
  37#define OEM_ID_ICP      0x941c
  38#define OEM_ID_INTEL    0x8000
  39
  40/* controller classes */
  41#define GDT_ISA         0x01                    /* ISA controller */
  42#define GDT_EISA        0x02                    /* EISA controller */
  43#define GDT_PCI         0x03                    /* PCI controller */
  44#define GDT_PCINEW      0x04                    /* new PCI controller */
  45#define GDT_PCIMPR      0x05                    /* PCI MPR controller */
  46/* GDT_EISA, controller subtypes EISA */
  47#define GDT3_ID         0x0130941c              /* GDT3000/3020 */
  48#define GDT3A_ID        0x0230941c              /* GDT3000A/3020A/3050A */
  49#define GDT3B_ID        0x0330941c              /* GDT3000B/3010A */
  50/* GDT_ISA */
  51#define GDT2_ID         0x0120941c              /* GDT2000/2020 */
  52
  53/* vendor ID, device IDs (PCI) */
  54/* these defines should already exist in <linux/pci.h> */
  55#ifndef PCI_VENDOR_ID_VORTEX
  56#define PCI_VENDOR_ID_VORTEX            0x1119  /* PCI controller vendor ID */
  57#endif
  58#ifndef PCI_VENDOR_ID_INTEL
  59#define PCI_VENDOR_ID_INTEL             0x8086  
  60#endif
  61
  62#ifndef PCI_DEVICE_ID_VORTEX_GDT60x0
  63/* GDT_PCI */
  64#define PCI_DEVICE_ID_VORTEX_GDT60x0    0       /* GDT6000/6020/6050 */
  65#define PCI_DEVICE_ID_VORTEX_GDT6000B   1       /* GDT6000B/6010 */
  66/* GDT_PCINEW */
  67#define PCI_DEVICE_ID_VORTEX_GDT6x10    2       /* GDT6110/6510 */
  68#define PCI_DEVICE_ID_VORTEX_GDT6x20    3       /* GDT6120/6520 */
  69#define PCI_DEVICE_ID_VORTEX_GDT6530    4       /* GDT6530 */
  70#define PCI_DEVICE_ID_VORTEX_GDT6550    5       /* GDT6550 */
  71/* GDT_PCINEW, wide/ultra SCSI controllers */
  72#define PCI_DEVICE_ID_VORTEX_GDT6x17    6       /* GDT6117/6517 */
  73#define PCI_DEVICE_ID_VORTEX_GDT6x27    7       /* GDT6127/6527 */
  74#define PCI_DEVICE_ID_VORTEX_GDT6537    8       /* GDT6537 */
  75#define PCI_DEVICE_ID_VORTEX_GDT6557    9       /* GDT6557/6557-ECC */
  76/* GDT_PCINEW, wide SCSI controllers */
  77#define PCI_DEVICE_ID_VORTEX_GDT6x15    10      /* GDT6115/6515 */
  78#define PCI_DEVICE_ID_VORTEX_GDT6x25    11      /* GDT6125/6525 */
  79#define PCI_DEVICE_ID_VORTEX_GDT6535    12      /* GDT6535 */
  80#define PCI_DEVICE_ID_VORTEX_GDT6555    13      /* GDT6555/6555-ECC */
  81#endif
  82
  83#ifndef PCI_DEVICE_ID_VORTEX_GDT6x17RP
  84/* GDT_MPR, RP series, wide/ultra SCSI */
  85#define PCI_DEVICE_ID_VORTEX_GDT6x17RP  0x100   /* GDT6117RP/GDT6517RP */
  86#define PCI_DEVICE_ID_VORTEX_GDT6x27RP  0x101   /* GDT6127RP/GDT6527RP */
  87#define PCI_DEVICE_ID_VORTEX_GDT6537RP  0x102   /* GDT6537RP */
  88#define PCI_DEVICE_ID_VORTEX_GDT6557RP  0x103   /* GDT6557RP */
  89/* GDT_MPR, RP series, narrow/ultra SCSI */
  90#define PCI_DEVICE_ID_VORTEX_GDT6x11RP  0x104   /* GDT6111RP/GDT6511RP */
  91#define PCI_DEVICE_ID_VORTEX_GDT6x21RP  0x105   /* GDT6121RP/GDT6521RP */
  92#endif
  93#ifndef PCI_DEVICE_ID_VORTEX_GDT6x17RD
  94/* GDT_MPR, RD series, wide/ultra SCSI */
  95#define PCI_DEVICE_ID_VORTEX_GDT6x17RD  0x110   /* GDT6117RD/GDT6517RD */
  96#define PCI_DEVICE_ID_VORTEX_GDT6x27RD  0x111   /* GDT6127RD/GDT6527RD */
  97#define PCI_DEVICE_ID_VORTEX_GDT6537RD  0x112   /* GDT6537RD */
  98#define PCI_DEVICE_ID_VORTEX_GDT6557RD  0x113   /* GDT6557RD */
  99/* GDT_MPR, RD series, narrow/ultra SCSI */
 100#define PCI_DEVICE_ID_VORTEX_GDT6x11RD  0x114   /* GDT6111RD/GDT6511RD */
 101#define PCI_DEVICE_ID_VORTEX_GDT6x21RD  0x115   /* GDT6121RD/GDT6521RD */
 102/* GDT_MPR, RD series, wide/ultra2 SCSI */
 103#define PCI_DEVICE_ID_VORTEX_GDT6x18RD  0x118   /* GDT6118RD/GDT6518RD/
 104                                                   GDT6618RD */
 105#define PCI_DEVICE_ID_VORTEX_GDT6x28RD  0x119   /* GDT6128RD/GDT6528RD/
 106                                                   GDT6628RD */
 107#define PCI_DEVICE_ID_VORTEX_GDT6x38RD  0x11A   /* GDT6538RD/GDT6638RD */
 108#define PCI_DEVICE_ID_VORTEX_GDT6x58RD  0x11B   /* GDT6558RD/GDT6658RD */
 109/* GDT_MPR, RN series (64-bit PCI), wide/ultra2 SCSI */
 110#define PCI_DEVICE_ID_VORTEX_GDT7x18RN  0x168   /* GDT7118RN/GDT7518RN/
 111                                                   GDT7618RN */
 112#define PCI_DEVICE_ID_VORTEX_GDT7x28RN  0x169   /* GDT7128RN/GDT7528RN/
 113                                                   GDT7628RN */
 114#define PCI_DEVICE_ID_VORTEX_GDT7x38RN  0x16A   /* GDT7538RN/GDT7638RN */
 115#define PCI_DEVICE_ID_VORTEX_GDT7x58RN  0x16B   /* GDT7558RN/GDT7658RN */
 116#endif
 117
 118#ifndef PCI_DEVICE_ID_VORTEX_GDT6x19RD
 119/* GDT_MPR, RD series, Fibre Channel */
 120#define PCI_DEVICE_ID_VORTEX_GDT6x19RD  0x210   /* GDT6519RD/GDT6619RD */
 121#define PCI_DEVICE_ID_VORTEX_GDT6x29RD  0x211   /* GDT6529RD/GDT6629RD */
 122/* GDT_MPR, RN series (64-bit PCI), Fibre Channel */
 123#define PCI_DEVICE_ID_VORTEX_GDT7x19RN  0x260   /* GDT7519RN/GDT7619RN */
 124#define PCI_DEVICE_ID_VORTEX_GDT7x29RN  0x261   /* GDT7529RN/GDT7629RN */
 125#endif
 126
 127#ifndef PCI_DEVICE_ID_VORTEX_GDTMAXRP
 128/* GDT_MPR, last device ID */
 129#define PCI_DEVICE_ID_VORTEX_GDTMAXRP   0x2ff   
 130#endif
 131
 132#ifndef PCI_DEVICE_ID_VORTEX_GDTNEWRX
 133/* new GDT Rx Controller */
 134#define PCI_DEVICE_ID_VORTEX_GDTNEWRX   0x300
 135#endif
 136
 137#ifndef PCI_DEVICE_ID_VORTEX_GDTNEWRX2
 138/* new(2) GDT Rx Controller */
 139#define PCI_DEVICE_ID_VORTEX_GDTNEWRX2  0x301
 140#endif        
 141
 142#ifndef PCI_DEVICE_ID_INTEL_SRC
 143/* Intel Storage RAID Controller */
 144#define PCI_DEVICE_ID_INTEL_SRC         0x600
 145#endif
 146
 147#ifndef PCI_DEVICE_ID_INTEL_SRC_XSCALE
 148/* Intel Storage RAID Controller */
 149#define PCI_DEVICE_ID_INTEL_SRC_XSCALE  0x601
 150#endif
 151
 152/* limits */
 153#define GDTH_SCRATCH    PAGE_SIZE               /* 4KB scratch buffer */
 154#define GDTH_MAXCMDS    120
 155#define GDTH_MAXC_P_L   16                      /* max. cmds per lun */
 156#define GDTH_MAX_RAW    2                       /* max. cmds per raw device */
 157#define MAXOFFSETS      128
 158#define MAXHA           16
 159#define MAXID           127
 160#define MAXLUN          8
 161#define MAXBUS          6
 162#define MAX_EVENTS      100                     /* event buffer count */
 163#define MAX_RES_ARGS    40                      /* device reservation, 
 164                                                   must be a multiple of 4 */
 165#define MAXCYLS         1024
 166#define HEADS           64
 167#define SECS            32                      /* mapping 64*32 */
 168#define MEDHEADS        127
 169#define MEDSECS         63                      /* mapping 127*63 */
 170#define BIGHEADS        255
 171#define BIGSECS         63                      /* mapping 255*63 */
 172
 173/* special command ptr. */
 174#define UNUSED_CMND     ((Scsi_Cmnd *)-1)
 175#define INTERNAL_CMND   ((Scsi_Cmnd *)-2)
 176#define SCREEN_CMND     ((Scsi_Cmnd *)-3)
 177#define SPECIAL_SCP(p)  (p==UNUSED_CMND || p==INTERNAL_CMND || p==SCREEN_CMND)
 178
 179/* controller services */
 180#define SCSIRAWSERVICE  3
 181#define CACHESERVICE    9
 182#define SCREENSERVICE   11
 183
 184/* screenservice defines */
 185#define MSG_INV_HANDLE  -1                      /* special message handle */
 186#define MSGLEN          16                      /* size of message text */
 187#define MSG_SIZE        34                      /* size of message structure */
 188#define MSG_REQUEST     0                       /* async. event: message */
 189
 190/* cacheservice defines */
 191#define SECTOR_SIZE     0x200                   /* always 512 bytes per sec. */
 192
 193/* DPMEM constants */
 194#define DPMEM_MAGIC     0xC0FFEE11
 195#define IC_HEADER_BYTES 48
 196#define IC_QUEUE_BYTES  4
 197#define DPMEM_COMMAND_OFFSET    IC_HEADER_BYTES+IC_QUEUE_BYTES*MAXOFFSETS
 198
 199/* cluster_type constants */
 200#define CLUSTER_DRIVE         1
 201#define CLUSTER_MOUNTED       2
 202#define CLUSTER_RESERVED      4
 203#define CLUSTER_RESERVE_STATE (CLUSTER_DRIVE|CLUSTER_MOUNTED|CLUSTER_RESERVED)
 204
 205/* commands for all services, cache service */
 206#define GDT_INIT        0                       /* service initialization */
 207#define GDT_READ        1                       /* read command */
 208#define GDT_WRITE       2                       /* write command */
 209#define GDT_INFO        3                       /* information about devices */
 210#define GDT_FLUSH       4                       /* flush dirty cache buffers */
 211#define GDT_IOCTL       5                       /* ioctl command */
 212#define GDT_DEVTYPE     9                       /* additional information */
 213#define GDT_MOUNT       10                      /* mount cache device */
 214#define GDT_UNMOUNT     11                      /* unmount cache device */
 215#define GDT_SET_FEAT    12                      /* set feat. (scatter/gather) */
 216#define GDT_GET_FEAT    13                      /* get features */
 217#define GDT_WRITE_THR   16                      /* write through */
 218#define GDT_READ_THR    17                      /* read through */
 219#define GDT_EXT_INFO    18                      /* extended info */
 220#define GDT_RESET       19                      /* controller reset */
 221#define GDT_RESERVE_DRV 20                      /* reserve host drive */
 222#define GDT_RELEASE_DRV 21                      /* release host drive */
 223#define GDT_CLUST_INFO  22                      /* cluster info */
 224#define GDT_RW_ATTRIBS  23                      /* R/W attribs (write thru,..)*/
 225#define GDT_CLUST_RESET 24                      /* releases the cluster drives*/
 226#define GDT_FREEZE_IO   25                      /* freezes all IOs */
 227#define GDT_UNFREEZE_IO 26                      /* unfreezes all IOs */
 228#define GDT_X_INIT_HOST 29                      /* ext. init: 64 bit support */
 229#define GDT_X_INFO      30                      /* ext. info for drives>2TB */
 230
 231/* raw service commands */
 232#define GDT_RESERVE     14                      /* reserve dev. to raw serv. */
 233#define GDT_RELEASE     15                      /* release device */
 234#define GDT_RESERVE_ALL 16                      /* reserve all devices */
 235#define GDT_RELEASE_ALL 17                      /* release all devices */
 236#define GDT_RESET_BUS   18                      /* reset bus */
 237#define GDT_SCAN_START  19                      /* start device scan */
 238#define GDT_SCAN_END    20                      /* stop device scan */  
 239#define GDT_X_INIT_RAW  21                      /* ext. init: 64 bit support */
 240
 241/* screen service commands */
 242#define GDT_REALTIME    3                       /* realtime clock to screens. */
 243#define GDT_X_INIT_SCR  4                       /* ext. init: 64 bit support */
 244
 245/* IOCTL command defines */
 246#define SCSI_DR_INFO    0x00                    /* SCSI drive info */                   
 247#define SCSI_CHAN_CNT   0x05                    /* SCSI channel count */   
 248#define SCSI_DR_LIST    0x06                    /* SCSI drive list */
 249#define SCSI_DEF_CNT    0x15                    /* grown/primary defects */
 250#define DSK_STATISTICS  0x4b                    /* SCSI disk statistics */
 251#define IOCHAN_DESC     0x5d                    /* description of IO channel */
 252#define IOCHAN_RAW_DESC 0x5e                    /* description of raw IO chn. */
 253#define L_CTRL_PATTERN  0x20000000L             /* SCSI IOCTL mask */
 254#define ARRAY_INFO      0x12                    /* array drive info */
 255#define ARRAY_DRV_LIST  0x0f                    /* array drive list */
 256#define ARRAY_DRV_LIST2 0x34                    /* array drive list (new) */
 257#define LA_CTRL_PATTERN 0x10000000L             /* array IOCTL mask */
 258#define CACHE_DRV_CNT   0x01                    /* cache drive count */
 259#define CACHE_DRV_LIST  0x02                    /* cache drive list */
 260#define CACHE_INFO      0x04                    /* cache info */
 261#define CACHE_CONFIG    0x05                    /* cache configuration */
 262#define CACHE_DRV_INFO  0x07                    /* cache drive info */
 263#define BOARD_FEATURES  0x15                    /* controller features */
 264#define BOARD_INFO      0x28                    /* controller info */
 265#define SET_PERF_MODES  0x82                    /* set mode (coalescing,..) */
 266#define GET_PERF_MODES  0x83                    /* get mode */
 267#define CACHE_READ_OEM_STRING_RECORD 0x84       /* read OEM string record */ 
 268#define HOST_GET        0x10001L                /* get host drive list */
 269#define IO_CHANNEL      0x00020000L             /* default IO channel */
 270#define INVALID_CHANNEL 0x0000ffffL             /* invalid channel */
 271
 272/* service errors */
 273#define S_OK            1                       /* no error */
 274#define S_GENERR        6                       /* general error */
 275#define S_BSY           7                       /* controller busy */
 276#define S_CACHE_UNKNOWN 12                      /* cache serv.: drive unknown */
 277#define S_RAW_SCSI      12                      /* raw serv.: target error */
 278#define S_RAW_ILL       0xff                    /* raw serv.: illegal */
 279#define S_NOFUNC        -2                      /* unknown function */
 280#define S_CACHE_RESERV  -24                     /* cache: reserv. conflict */   
 281
 282/* timeout values */
 283#define INIT_RETRIES    100000                  /* 100000 * 1ms = 100s */
 284#define INIT_TIMEOUT    100000                  /* 100000 * 1ms = 100s */
 285#define POLL_TIMEOUT    10000                   /* 10000 * 1ms = 10s */
 286
 287/* priorities */
 288#define DEFAULT_PRI     0x20
 289#define IOCTL_PRI       0x10
 290#define HIGH_PRI        0x08
 291
 292/* data directions */
 293#define GDTH_DATA_IN    0x01000000L             /* data from target */
 294#define GDTH_DATA_OUT   0x00000000L             /* data to target */
 295
 296/* BMIC registers (EISA controllers) */
 297#define ID0REG          0x0c80                  /* board ID */
 298#define EINTENABREG     0x0c89                  /* interrupt enable */
 299#define SEMA0REG        0x0c8a                  /* command semaphore */
 300#define SEMA1REG        0x0c8b                  /* status semaphore */
 301#define LDOORREG        0x0c8d                  /* local doorbell */
 302#define EDENABREG       0x0c8e                  /* EISA system doorbell enab. */
 303#define EDOORREG        0x0c8f                  /* EISA system doorbell */
 304#define MAILBOXREG      0x0c90                  /* mailbox reg. (16 bytes) */
 305#define EISAREG         0x0cc0                  /* EISA configuration */
 306
 307/* DMA memory mappings */
 308#define GDTH_MAP_NONE   0
 309#define GDTH_MAP_SINGLE 1
 310#define GDTH_MAP_SG     2
 311#define GDTH_MAP_IOCTL  3 
 312
 313/* other defines */
 314#define LINUX_OS        8                       /* used for cache optim. */
 315#define SCATTER_GATHER  1                       /* s/g feature */
 316#define SECS32          0x1f                    /* round capacity */
 317#define BIOS_ID_OFFS    0x10                    /* offset contr-ID in ISABIOS */
 318#define LOCALBOARD      0                       /* board node always 0 */
 319#define ASYNCINDEX      0                       /* cmd index async. event */
 320#define SPEZINDEX       1                       /* cmd index unknown service */
 321#define COALINDEX       (GDTH_MAXCMDS + 2)
 322
 323/* features */
 324#define SCATTER_GATHER  1                       /* s/g feature */
 325#define GDT_WR_THROUGH  0x100                   /* WRITE_THROUGH supported */
 326#define GDT_64BIT       0x200                   /* 64bit / drv>2TB support */
 327
 328#include "gdth_ioctl.h"
 329
 330/* screenservice message */
 331typedef struct {                               
 332    ulong32     msg_handle;                     /* message handle */
 333    ulong32     msg_len;                        /* size of message */
 334    ulong32     msg_alen;                       /* answer length */
 335    unchar      msg_answer;                     /* answer flag */
 336    unchar      msg_ext;                        /* more messages */
 337    unchar      msg_reserved[2];
 338    char        msg_text[MSGLEN+2];             /* the message text */
 339} PACKED gdth_msg_str;
 340
 341
 342/* IOCTL data structures */
 343
 344/* Status coalescing buffer for returning multiple requests per interrupt */
 345typedef struct {
 346    ulong32     status;
 347    ulong32     ext_status;
 348    ulong32     info0;
 349    ulong32     info1;
 350} PACKED gdth_coal_status;
 351
 352/* performance mode data structure */
 353typedef struct {
 354    ulong32     version;            /* The version of this IOCTL structure. */
 355    ulong32     st_mode;            /* 0=dis., 1=st_buf_addr1 valid, 2=both  */
 356    ulong32     st_buff_addr1;      /* physical address of status buffer 1 */
 357    ulong32     st_buff_u_addr1;    /* reserved for 64 bit addressing */
 358    ulong32     st_buff_indx1;      /* reserved command idx. for this buffer */
 359    ulong32     st_buff_addr2;      /* physical address of status buffer 1 */
 360    ulong32     st_buff_u_addr2;    /* reserved for 64 bit addressing */
 361    ulong32     st_buff_indx2;      /* reserved command idx. for this buffer */
 362    ulong32     st_buff_size;       /* size of each buffer in bytes */
 363    ulong32     cmd_mode;           /* 0 = mode disabled, 1 = cmd_buff_addr1 */ 
 364    ulong32     cmd_buff_addr1;     /* physical address of cmd buffer 1 */   
 365    ulong32     cmd_buff_u_addr1;   /* reserved for 64 bit addressing */
 366    ulong32     cmd_buff_indx1;     /* cmd buf addr1 unique identifier */
 367    ulong32     cmd_buff_addr2;     /* physical address of cmd buffer 1 */   
 368    ulong32     cmd_buff_u_addr2;   /* reserved for 64 bit addressing */
 369    ulong32     cmd_buff_indx2;     /* cmd buf addr1 unique identifier */
 370    ulong32     cmd_buff_size;      /* size of each cmd bufer in bytes */
 371    ulong32     reserved1;
 372    ulong32     reserved2;
 373} PACKED gdth_perf_modes;
 374
 375/* SCSI drive info */
 376typedef struct {
 377    unchar      vendor[8];                      /* vendor string */
 378    unchar      product[16];                    /* product string */
 379    unchar      revision[4];                    /* revision */
 380    ulong32     sy_rate;                        /* current rate for sync. tr. */
 381    ulong32     sy_max_rate;                    /* max. rate for sync. tr. */
 382    ulong32     no_ldrive;                      /* belongs to this log. drv.*/
 383    ulong32     blkcnt;                         /* number of blocks */
 384    ushort      blksize;                        /* size of block in bytes */
 385    unchar      available;                      /* flag: access is available */
 386    unchar      init;                           /* medium is initialized */
 387    unchar      devtype;                        /* SCSI devicetype */
 388    unchar      rm_medium;                      /* medium is removable */
 389    unchar      wp_medium;                      /* medium is write protected */
 390    unchar      ansi;                           /* SCSI I/II or III? */
 391    unchar      protocol;                       /* same as ansi */
 392    unchar      sync;                           /* flag: sync. transfer enab. */
 393    unchar      disc;                           /* flag: disconnect enabled */
 394    unchar      queueing;                       /* flag: command queing enab. */
 395    unchar      cached;                         /* flag: caching enabled */
 396    unchar      target_id;                      /* target ID of device */
 397    unchar      lun;                            /* LUN id of device */
 398    unchar      orphan;                         /* flag: drive fragment */
 399    ulong32     last_error;                     /* sense key or drive state */
 400    ulong32     last_result;                    /* result of last command */
 401    ulong32     check_errors;                   /* err. in last surface check */
 402    unchar      percent;                        /* progress for surface check */
 403    unchar      last_check;                     /* IOCTRL operation */
 404    unchar      res[2];
 405    ulong32     flags;                          /* from 1.19/2.19: raw reserv.*/
 406    unchar      multi_bus;                      /* multi bus dev? (fibre ch.) */
 407    unchar      mb_status;                      /* status: available? */
 408    unchar      res2[2];
 409    unchar      mb_alt_status;                  /* status on second bus */
 410    unchar      mb_alt_bid;                     /* number of second bus */
 411    unchar      mb_alt_tid;                     /* target id on second bus */
 412    unchar      res3;
 413    unchar      fc_flag;                        /* from 1.22/2.22: info valid?*/
 414    unchar      res4;
 415    ushort      fc_frame_size;                  /* frame size (bytes) */
 416    char        wwn[8];                         /* world wide name */
 417} PACKED gdth_diskinfo_str;
 418
 419/* get SCSI channel count  */
 420typedef struct {
 421    ulong32     channel_no;                     /* number of channel */
 422    ulong32     drive_cnt;                      /* drive count */
 423    unchar      siop_id;                        /* SCSI processor ID */
 424    unchar      siop_state;                     /* SCSI processor state */ 
 425} PACKED gdth_getch_str;
 426
 427/* get SCSI drive numbers */
 428typedef struct {
 429    ulong32     sc_no;                          /* SCSI channel */
 430    ulong32     sc_cnt;                         /* sc_list[] elements */
 431    ulong32     sc_list[MAXID];                 /* minor device numbers */
 432} PACKED gdth_drlist_str;
 433
 434/* get grown/primary defect count */
 435typedef struct {
 436    unchar      sddc_type;                      /* 0x08: grown, 0x10: prim. */
 437    unchar      sddc_format;                    /* list entry format */
 438    unchar      sddc_len;                       /* list entry length */
 439    unchar      sddc_res;
 440    ulong32     sddc_cnt;                       /* entry count */
 441} PACKED gdth_defcnt_str;
 442
 443/* disk statistics */
 444typedef struct {
 445    ulong32     bid;                            /* SCSI channel */
 446    ulong32     first;                          /* first SCSI disk */
 447    ulong32     entries;                        /* number of elements */
 448    ulong32     count;                          /* (R) number of init. el. */
 449    ulong32     mon_time;                       /* time stamp */
 450    struct {
 451        unchar  tid;                            /* target ID */
 452        unchar  lun;                            /* LUN */
 453        unchar  res[2];
 454        ulong32 blk_size;                       /* block size in bytes */
 455        ulong32 rd_count;                       /* bytes read */
 456        ulong32 wr_count;                       /* bytes written */
 457        ulong32 rd_blk_count;                   /* blocks read */
 458        ulong32 wr_blk_count;                   /* blocks written */
 459        ulong32 retries;                        /* retries */
 460        ulong32 reassigns;                      /* reassigns */
 461    } PACKED list[1];
 462} PACKED gdth_dskstat_str;
 463
 464/* IO channel header */
 465typedef struct {
 466    ulong32     version;                        /* version (-1UL: newest) */
 467    unchar      list_entries;                   /* list entry count */
 468    unchar      first_chan;                     /* first channel number */
 469    unchar      last_chan;                      /* last channel number */
 470    unchar      chan_count;                     /* (R) channel count */
 471    ulong32     list_offset;                    /* offset of list[0] */
 472} PACKED gdth_iochan_header;
 473
 474/* get IO channel description */
 475typedef struct {
 476    gdth_iochan_header  hdr;
 477    struct {
 478        ulong32         address;                /* channel address */
 479        unchar          type;                   /* type (SCSI, FCAL) */
 480        unchar          local_no;               /* local number */
 481        ushort          features;               /* channel features */
 482    } PACKED list[MAXBUS];
 483} PACKED gdth_iochan_str;
 484
 485/* get raw IO channel description */
 486typedef struct {
 487    gdth_iochan_header  hdr;
 488    struct {
 489        unchar      proc_id;                    /* processor id */
 490        unchar      proc_defect;                /* defect ? */
 491        unchar      reserved[2];
 492    } PACKED list[MAXBUS];
 493} PACKED gdth_raw_iochan_str;
 494
 495/* array drive component */
 496typedef struct {
 497    ulong32     al_controller;                  /* controller ID */
 498    unchar      al_cache_drive;                 /* cache drive number */
 499    unchar      al_status;                      /* cache drive state */
 500    unchar      al_res[2];     
 501} PACKED gdth_arraycomp_str;
 502
 503/* array drive information */
 504typedef struct {
 505    unchar      ai_type;                        /* array type (RAID0,4,5) */
 506    unchar      ai_cache_drive_cnt;             /* active cachedrives */
 507    unchar      ai_state;                       /* array drive state */
 508    unchar      ai_master_cd;                   /* master cachedrive */
 509    ulong32     ai_master_controller;           /* ID of master controller */
 510    ulong32     ai_size;                        /* user capacity [sectors] */
 511    ulong32     ai_striping_size;               /* striping size [sectors] */
 512    ulong32     ai_secsize;                     /* sector size [bytes] */
 513    ulong32     ai_err_info;                    /* failed cache drive */
 514    unchar      ai_name[8];                     /* name of the array drive */
 515    unchar      ai_controller_cnt;              /* number of controllers */
 516    unchar      ai_removable;                   /* flag: removable */
 517    unchar      ai_write_protected;             /* flag: write protected */
 518    unchar      ai_devtype;                     /* type: always direct access */
 519    gdth_arraycomp_str  ai_drives[35];          /* drive components: */
 520    unchar      ai_drive_entries;               /* number of drive components */
 521    unchar      ai_protected;                   /* protection flag */
 522    unchar      ai_verify_state;                /* state of a parity verify */
 523    unchar      ai_ext_state;                   /* extended array drive state */
 524    unchar      ai_expand_state;                /* array expand state (>=2.18)*/
 525    unchar      ai_reserved[3];
 526} PACKED gdth_arrayinf_str;
 527
 528/* get array drive list */
 529typedef struct {
 530    ulong32     controller_no;                  /* controller no. */
 531    unchar      cd_handle;                      /* master cachedrive */
 532    unchar      is_arrayd;                      /* Flag: is array drive? */
 533    unchar      is_master;                      /* Flag: is array master? */
 534    unchar      is_parity;                      /* Flag: is parity drive? */
 535    unchar      is_hotfix;                      /* Flag: is hotfix drive? */
 536    unchar      res[3];
 537} PACKED gdth_alist_str;
 538
 539typedef struct {
 540    ulong32     entries_avail;                  /* allocated entries */
 541    ulong32     entries_init;                   /* returned entries */
 542    ulong32     first_entry;                    /* first entry number */
 543    ulong32     list_offset;                    /* offset of following list */
 544    gdth_alist_str list[1];                     /* list */
 545} PACKED gdth_arcdl_str;
 546
 547/* cache info/config IOCTL */
 548typedef struct {
 549    ulong32     version;                        /* firmware version */
 550    ushort      state;                          /* cache state (on/off) */
 551    ushort      strategy;                       /* cache strategy */
 552    ushort      write_back;                     /* write back state (on/off) */
 553    ushort      block_size;                     /* cache block size */
 554} PACKED gdth_cpar_str;
 555
 556typedef struct {
 557    ulong32     csize;                          /* cache size */
 558    ulong32     read_cnt;                       /* read/write counter */
 559    ulong32     write_cnt;
 560    ulong32     tr_hits;                        /* hits */
 561    ulong32     sec_hits;
 562    ulong32     sec_miss;                       /* misses */
 563} PACKED gdth_cstat_str;
 564
 565typedef struct {
 566    gdth_cpar_str   cpar;
 567    gdth_cstat_str  cstat;
 568} PACKED gdth_cinfo_str;
 569
 570/* cache drive info */
 571typedef struct {
 572    unchar      cd_name[8];                     /* cache drive name */
 573    ulong32     cd_devtype;                     /* SCSI devicetype */
 574    ulong32     cd_ldcnt;                       /* number of log. drives */
 575    ulong32     cd_last_error;                  /* last error */
 576    unchar      cd_initialized;                 /* drive is initialized */
 577    unchar      cd_removable;                   /* media is removable */
 578    unchar      cd_write_protected;             /* write protected */
 579    unchar      cd_flags;                       /* Pool Hot Fix? */
 580    ulong32     ld_blkcnt;                      /* number of blocks */
 581    ulong32     ld_blksize;                     /* blocksize */
 582    ulong32     ld_dcnt;                        /* number of disks */
 583    ulong32     ld_slave;                       /* log. drive index */
 584    ulong32     ld_dtype;                       /* type of logical drive */
 585    ulong32     ld_last_error;                  /* last error */
 586    unchar      ld_name[8];                     /* log. drive name */
 587    unchar      ld_error;                       /* error */
 588} PACKED gdth_cdrinfo_str;
 589
 590/* OEM string */
 591typedef struct {
 592    ulong32     ctl_version;
 593    ulong32     file_major_version;
 594    ulong32     file_minor_version;
 595    ulong32     buffer_size;
 596    ulong32     cpy_count;
 597    ulong32     ext_error;
 598    ulong32     oem_id;
 599    ulong32     board_id;
 600} PACKED gdth_oem_str_params;
 601
 602typedef struct {
 603    unchar      product_0_1_name[16];
 604    unchar      product_4_5_name[16];
 605    unchar      product_cluster_name[16];
 606    unchar      product_reserved[16];
 607    unchar      scsi_cluster_target_vendor_id[16];
 608    unchar      cluster_raid_fw_name[16];
 609    unchar      oem_brand_name[16];
 610    unchar      oem_raid_type[16];
 611    unchar      bios_type[13];
 612    unchar      bios_title[50];
 613    unchar      oem_company_name[37];
 614    ulong32     pci_id_1;
 615    ulong32     pci_id_2;
 616    unchar      validation_status[80];
 617    unchar      reserved_1[4];
 618    unchar      scsi_host_drive_inquiry_vendor_id[16];
 619    unchar      library_file_template[16];
 620    unchar      reserved_2[16];
 621    unchar      tool_name_1[32];
 622    unchar      tool_name_2[32];
 623    unchar      tool_name_3[32];
 624    unchar      oem_contact_1[84];
 625    unchar      oem_contact_2[84];
 626    unchar      oem_contact_3[84];
 627} PACKED gdth_oem_str;
 628
 629typedef struct {
 630    gdth_oem_str_params params;
 631    gdth_oem_str        text;
 632} PACKED gdth_oem_str_ioctl;
 633
 634/* board features */
 635typedef struct {
 636    unchar      chaining;                       /* Chaining supported */
 637    unchar      striping;                       /* Striping (RAID-0) supp. */
 638    unchar      mirroring;                      /* Mirroring (RAID-1) supp. */
 639    unchar      raid;                           /* RAID-4/5/10 supported */
 640} PACKED gdth_bfeat_str;
 641
 642/* board info IOCTL */
 643typedef struct {
 644    ulong32     ser_no;                         /* serial no. */
 645    unchar      oem_id[2];                      /* OEM ID */
 646    ushort      ep_flags;                       /* eprom flags */
 647    ulong32     proc_id;                        /* processor ID */
 648    ulong32     memsize;                        /* memory size (bytes) */
 649    unchar      mem_banks;                      /* memory banks */
 650    unchar      chan_type;                      /* channel type */
 651    unchar      chan_count;                     /* channel count */
 652    unchar      rdongle_pres;                   /* dongle present? */
 653    ulong32     epr_fw_ver;                     /* (eprom) firmware version */
 654    ulong32     upd_fw_ver;                     /* (update) firmware version */
 655    ulong32     upd_revision;                   /* update revision */
 656    char        type_string[16];                /* controller name */
 657    char        raid_string[16];                /* RAID firmware name */
 658    unchar      update_pres;                    /* update present? */
 659    unchar      xor_pres;                       /* XOR engine present? */
 660    unchar      prom_type;                      /* ROM type (eprom/flash) */
 661    unchar      prom_count;                     /* number of ROM devices */
 662    ulong32     dup_pres;                       /* duplexing module present? */
 663    ulong32     chan_pres;                      /* number of expansion chn. */
 664    ulong32     mem_pres;                       /* memory expansion inst. ? */
 665    unchar      ft_bus_system;                  /* fault bus supported? */
 666    unchar      subtype_valid;                  /* board_subtype valid? */
 667    unchar      board_subtype;                  /* subtype/hardware level */
 668    unchar      ramparity_pres;                 /* RAM parity check hardware? */
 669} PACKED gdth_binfo_str; 
 670
 671/* get host drive info */
 672typedef struct {
 673    char        name[8];                        /* host drive name */
 674    ulong32     size;                           /* size (sectors) */
 675    unchar      host_drive;                     /* host drive number */
 676    unchar      log_drive;                      /* log. drive (master) */
 677    unchar      reserved;
 678    unchar      rw_attribs;                     /* r/w attribs */
 679    ulong32     start_sec;                      /* start sector */
 680} PACKED gdth_hentry_str;
 681
 682typedef struct {
 683    ulong32     entries;                        /* entry count */
 684    ulong32     offset;                         /* offset of entries */
 685    unchar      secs_p_head;                    /* sectors/head */
 686    unchar      heads_p_cyl;                    /* heads/cylinder */
 687    unchar      reserved;
 688    unchar      clust_drvtype;                  /* cluster drive type */
 689    ulong32     location;                       /* controller number */
 690    gdth_hentry_str entry[MAX_HDRIVES];         /* entries */
 691} PACKED gdth_hget_str;    
 692
 693
 694/* DPRAM structures */
 695
 696/* interface area ISA/PCI */
 697typedef struct {
 698    unchar              S_Cmd_Indx;             /* special command */
 699    unchar volatile     S_Status;               /* status special command */
 700    ushort              reserved1;
 701    ulong32             S_Info[4];              /* add. info special command */
 702    unchar volatile     Sema0;                  /* command semaphore */
 703    unchar              reserved2[3];
 704    unchar              Cmd_Index;              /* command number */
 705    unchar              reserved3[3];
 706    ushort volatile     Status;                 /* command status */
 707    ushort              Service;                /* service(for async.events) */
 708    ulong32             Info[2];                /* additional info */
 709    struct {
 710        ushort          offset;                 /* command offs. in the DPRAM*/
 711        ushort          serv_id;                /* service */
 712    } PACKED comm_queue[MAXOFFSETS];            /* command queue */
 713    ulong32             bios_reserved[2];
 714    unchar              gdt_dpr_cmd[1];         /* commands */
 715} PACKED gdt_dpr_if;
 716
 717/* SRAM structure PCI controllers */
 718typedef struct {
 719    ulong32     magic;                          /* controller ID from BIOS */
 720    ushort      need_deinit;                    /* switch betw. BIOS/driver */
 721    unchar      switch_support;                 /* see need_deinit */
 722    unchar      padding[9];
 723    unchar      os_used[16];                    /* OS code per service */
 724    unchar      unused[28];
 725    unchar      fw_magic;                       /* contr. ID from firmware */
 726} PACKED gdt_pci_sram;
 727
 728/* SRAM structure EISA controllers (but NOT GDT3000/3020) */
 729typedef struct {
 730    unchar      os_used[16];                    /* OS code per service */
 731    ushort      need_deinit;                    /* switch betw. BIOS/driver */
 732    unchar      switch_support;                 /* see need_deinit */
 733    unchar      padding;
 734} PACKED gdt_eisa_sram;
 735
 736
 737/* DPRAM ISA controllers */
 738typedef struct {
 739    union {
 740        struct {
 741            unchar      bios_used[0x3c00-32];   /* 15KB - 32Bytes BIOS */
 742            ulong32     magic;                  /* controller (EISA) ID */
 743            ushort      need_deinit;            /* switch betw. BIOS/driver */
 744            unchar      switch_support;         /* see need_deinit */
 745            unchar      padding[9];
 746            unchar      os_used[16];            /* OS code per service */
 747        } PACKED dp_sram;
 748        unchar          bios_area[0x4000];      /* 16KB reserved for BIOS */
 749    } bu;
 750    union {
 751        gdt_dpr_if      ic;                     /* interface area */
 752        unchar          if_area[0x3000];        /* 12KB for interface */
 753    } u;
 754    struct {
 755        unchar          memlock;                /* write protection DPRAM */
 756        unchar          event;                  /* release event */
 757        unchar          irqen;                  /* board interrupts enable */
 758        unchar          irqdel;                 /* acknowledge board int. */
 759        unchar volatile Sema1;                  /* status semaphore */
 760        unchar          rq;                     /* IRQ/DRQ configuration */
 761    } PACKED io;
 762} PACKED gdt2_dpram_str;
 763
 764/* DPRAM PCI controllers */
 765typedef struct {
 766    union {
 767        gdt_dpr_if      ic;                     /* interface area */
 768        unchar          if_area[0xff0-sizeof(gdt_pci_sram)];
 769    } u;
 770    gdt_pci_sram        gdt6sr;                 /* SRAM structure */
 771    struct {
 772        unchar          unused0[1];
 773        unchar volatile Sema1;                  /* command semaphore */
 774        unchar          unused1[3];
 775        unchar          irqen;                  /* board interrupts enable */
 776        unchar          unused2[2];
 777        unchar          event;                  /* release event */
 778        unchar          unused3[3];
 779        unchar          irqdel;                 /* acknowledge board int. */
 780        unchar          unused4[3];
 781    } PACKED io;
 782} PACKED gdt6_dpram_str;
 783
 784/* PLX register structure (new PCI controllers) */
 785typedef struct {
 786    unchar              cfg_reg;        /* DPRAM cfg.(2:below 1MB,0:anywhere)*/
 787    unchar              unused1[0x3f];
 788    unchar volatile     sema0_reg;              /* command semaphore */
 789    unchar volatile     sema1_reg;              /* status semaphore */
 790    unchar              unused2[2];
 791    ushort volatile     status;                 /* command status */
 792    ushort              service;                /* service */
 793    ulong32             info[2];                /* additional info */
 794    unchar              unused3[0x10];
 795    unchar              ldoor_reg;              /* PCI to local doorbell */
 796    unchar              unused4[3];
 797    unchar volatile     edoor_reg;              /* local to PCI doorbell */
 798    unchar              unused5[3];
 799    unchar              control0;               /* control0 register(unused) */
 800    unchar              control1;               /* board interrupts enable */
 801    unchar              unused6[0x16];
 802} PACKED gdt6c_plx_regs;
 803
 804/* DPRAM new PCI controllers */
 805typedef struct {
 806    union {
 807        gdt_dpr_if      ic;                     /* interface area */
 808        unchar          if_area[0x4000-sizeof(gdt_pci_sram)];
 809    } u;
 810    gdt_pci_sram        gdt6sr;                 /* SRAM structure */
 811} PACKED gdt6c_dpram_str;
 812
 813/* i960 register structure (PCI MPR controllers) */
 814typedef struct {
 815    unchar              unused1[16];
 816    unchar volatile     sema0_reg;              /* command semaphore */
 817    unchar              unused2;
 818    unchar volatile     sema1_reg;              /* status semaphore */
 819    unchar              unused3;
 820    ushort volatile     status;                 /* command status */
 821    ushort              service;                /* service */
 822    ulong32             info[2];                /* additional info */
 823    unchar              ldoor_reg;              /* PCI to local doorbell */
 824    unchar              unused4[11];
 825    unchar volatile     edoor_reg;              /* local to PCI doorbell */
 826    unchar              unused5[7];
 827    unchar              edoor_en_reg;           /* board interrupts enable */
 828    unchar              unused6[27];
 829    ulong32             unused7[939];         
 830    ulong32             severity;       
 831    char                evt_str[256];           /* event string */
 832} PACKED gdt6m_i960_regs;
 833
 834/* DPRAM PCI MPR controllers */
 835typedef struct {
 836    gdt6m_i960_regs     i960r;                  /* 4KB i960 registers */
 837    union {
 838        gdt_dpr_if      ic;                     /* interface area */
 839        unchar          if_area[0x3000-sizeof(gdt_pci_sram)];
 840    } u;
 841    gdt_pci_sram        gdt6sr;                 /* SRAM structure */
 842} PACKED gdt6m_dpram_str;
 843
 844
 845/* PCI resources */
 846typedef struct {
 847    struct pci_dev      *pdev;
 848    ushort              vendor_id;              /* vendor (ICP, Intel, ..) */
 849    ushort              device_id;              /* device ID (0,..,9) */
 850    ushort              subdevice_id;           /* sub device ID */
 851    unchar              bus;                    /* PCI bus */
 852    unchar              device_fn;              /* PCI device/function no. */
 853    ulong               dpmem;                  /* DPRAM address */
 854    ulong               io;                     /* IO address */
 855    ulong               io_mm;                  /* IO address mem. mapped */
 856    unchar              irq;                    /* IRQ */
 857} gdth_pci_str;
 858
 859
 860/* controller information structure */
 861typedef struct {
 862    ushort              oem_id;                 /* OEM */
 863    ushort              type;                   /* controller class */
 864    ulong32             stype;                  /* subtype (PCI: device ID) */
 865    ushort              subdevice_id;           /* sub device ID (PCI) */
 866    ushort              fw_vers;                /* firmware version */
 867    ushort              cache_feat;             /* feat. cache serv. (s/g,..)*/
 868    ushort              raw_feat;               /* feat. raw service (s/g,..)*/
 869    ushort              screen_feat;            /* feat. raw service (s/g,..)*/
 870    ushort              bmic;                   /* BMIC address (EISA) */
 871    void                *brd;                   /* DPRAM address */
 872    ulong32             brd_phys;               /* slot number/BIOS address */
 873    gdt6c_plx_regs      *plx;                   /* PLX regs (new PCI contr.) */
 874    gdth_cmd_str        *pccb;                  /* address command structure */
 875    ulong32             ccb_phys;               /* phys. address */
 876#ifdef INT_COAL
 877    gdth_coal_status    *coal_stat;             /* buffer for coalescing int.*/
 878    ulong64             coal_stat_phys;         /* phys. address */
 879#endif
 880    char                *pscratch;              /* scratch (DMA) buffer */
 881    ulong64             scratch_phys;           /* phys. address */
 882    unchar              scratch_busy;           /* in use? */
 883    unchar              dma64_support;          /* 64-bit DMA supported? */
 884    gdth_msg_str        *pmsg;                  /* message buffer */
 885    ulong64             msg_phys;               /* phys. address */
 886    unchar              scan_mode;              /* current scan mode */
 887    unchar              irq;                    /* IRQ */
 888    unchar              drq;                    /* DRQ (ISA controllers) */
 889    ushort              status;                 /* command status */
 890    ushort              service;                /* service/firmware ver./.. */
 891    ulong32             info;
 892    ulong32             info2;                  /* additional info */
 893    Scsi_Cmnd           *req_first;             /* top of request queue */
 894    struct {
 895        unchar          present;                /* Flag: host drive present? */
 896        unchar          is_logdrv;              /* Flag: log. drive (master)? */
 897        unchar          is_arraydrv;            /* Flag: array drive? */
 898        unchar          is_master;              /* Flag: array drive master? */
 899        unchar          is_parity;              /* Flag: parity drive? */
 900        unchar          is_hotfix;              /* Flag: hotfix drive? */
 901        unchar          master_no;              /* number of master drive */
 902        unchar          lock;                   /* drive locked? (hot plug) */
 903        unchar          heads;                  /* mapping */
 904        unchar          secs;
 905        ushort          devtype;                /* further information */
 906        ulong64         size;                   /* capacity */
 907        unchar          ldr_no;                 /* log. drive no. */
 908        unchar          rw_attribs;             /* r/w attributes */
 909        unchar          cluster_type;           /* cluster properties */
 910        unchar          media_changed;          /* Flag:MOUNT/UNMOUNT occured */
 911        ulong32         start_sec;              /* start sector */
 912    } hdr[MAX_LDRIVES];                         /* host drives */
 913    struct {
 914        unchar          lock;                   /* channel locked? (hot plug) */
 915        unchar          pdev_cnt;               /* physical device count */
 916        unchar          local_no;               /* local channel number */
 917        unchar          io_cnt[MAXID];          /* current IO count */
 918        ulong32         address;                /* channel address */
 919        ulong32         id_list[MAXID];         /* IDs of the phys. devices */
 920    } raw[MAXBUS];                              /* SCSI channels */
 921    struct {
 922        Scsi_Cmnd       *cmnd;                  /* pending request */
 923        ushort          service;                /* service */
 924    } cmd_tab[GDTH_MAXCMDS];                    /* table of pend. requests */
 925    unchar              bus_cnt;                /* SCSI bus count */
 926    unchar              tid_cnt;                /* Target ID count */
 927    unchar              bus_id[MAXBUS];         /* IOP IDs */
 928    unchar              virt_bus;               /* number of virtual bus */
 929    unchar              more_proc;              /* more /proc info supported */
 930    ushort              cmd_cnt;                /* command count in DPRAM */
 931    ushort              cmd_len;                /* length of actual command */
 932    ushort              cmd_offs_dpmem;         /* actual offset in DPRAM */
 933    ushort              ic_all_size;            /* sizeof DPRAM interf. area */
 934    gdth_cpar_str       cpar;                   /* controller cache par. */
 935    gdth_bfeat_str      bfeat;                  /* controller features */
 936    gdth_binfo_str      binfo;                  /* controller info */
 937    gdth_evt_data       dvr;                    /* event structure */
 938    spinlock_t          smp_lock;
 939#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
 940    struct pci_dev      *pdev;
 941#endif
 942    char                oem_name[8];
 943#ifdef GDTH_DMA_STATISTICS
 944    ulong               dma32_cnt, dma64_cnt;   /* statistics: DMA buffer */
 945#endif
 946#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
 947    Scsi_Device         *sdev;
 948#else
 949    Scsi_Device         sdev;
 950#endif
 951} gdth_ha_str;
 952
 953/* structure for scsi_register(), SCSI bus != 0 */
 954typedef struct {
 955    ushort      hanum;
 956    ushort      busnum;
 957} gdth_num_str;
 958
 959/* structure for scsi_register() */
 960typedef struct {
 961    gdth_num_str        numext;                 /* must be the first element */
 962    gdth_ha_str         haext;
 963    gdth_cmd_str        cmdext;
 964} gdth_ext_str;
 965
 966
 967/* INQUIRY data format */
 968typedef struct {
 969    unchar      type_qual;
 970    unchar      modif_rmb;
 971    unchar      version;
 972    unchar      resp_aenc;
 973    unchar      add_length;
 974    unchar      reserved1;
 975    unchar      reserved2;
 976    unchar      misc;
 977    unchar      vendor[8];
 978    unchar      product[16];
 979    unchar      revision[4];
 980} PACKED gdth_inq_data;
 981
 982/* READ_CAPACITY data format */
 983typedef struct {
 984    ulong32     last_block_no;
 985    ulong32     block_length;
 986} PACKED gdth_rdcap_data;
 987
 988/* READ_CAPACITY (16) data format */
 989typedef struct {
 990    ulong64     last_block_no;
 991    ulong32     block_length;
 992} PACKED gdth_rdcap16_data;
 993
 994/* REQUEST_SENSE data format */
 995typedef struct {
 996    unchar      errorcode;
 997    unchar      segno;
 998    unchar      key;
 999    ulong32     info;
1000    unchar      add_length;

1001    ulong32     cmd_info;
1002    unchar      adsc;
1003    unchar      adsq;
1004    unchar      fruc;
1005    unchar      key_spec[3];
1006} PACKED gdth_sense_data;
1007
1008/* MODE_SENSE data format */
1009typedef struct {
1010    struct {
1011        unchar  data_length;
1012        unchar  med_type;
1013        unchar  dev_par;
1014        unchar  bd_length;
1015    } PACKED hd;
1016    struct {
1017        unchar  dens_code;
1018        unchar  block_count[3];
1019        unchar  reserved;
1020        unchar  block_length[3];
1021    } PACKED bd;
1022} PACKED gdth_modep_data;
1023
1024/* stack frame */
1025typedef struct {
1026    ulong       b[10];                          /* 32/64 bit compiler ! */
1027} PACKED gdth_stackframe;
1028
1029
1030/* function prototyping */
1031
1032int gdth_detect(Scsi_Host_Template *);
1033int gdth_release(struct Scsi_Host *);
1034int gdth_queuecommand(Scsi_Cmnd *,void (*done)(Scsi_Cmnd *));
1035const char *gdth_info(struct Scsi_Host *);
1036
1037#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
1038int gdth_bios_param(struct scsi_device *,struct block_device *,sector_t,int *);
1039int gdth_proc_info(struct Scsi_Host *, char *,char **,off_t,int,int);
1040#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
1041int gdth_bios_param(Disk *,kdev_t,int *);
1042int gdth_proc_info(char *,char **,off_t,int,int,int);
1043#else
1044int gdth_bios_param(Disk *,kdev_t,int *);
1045extern struct proc_dir_entry proc_scsi_gdth;
1046int gdth_proc_info(char *,char **,off_t,int,int,int);
1047int gdth_abort(Scsi_Cmnd *);
1048int gdth_reset(Scsi_Cmnd *,unsigned int); 
1049#define GDTH { proc_dir:        &proc_scsi_gdth,                 \
1050               proc_info:       gdth_proc_info,                  \
1051               name:            "GDT SCSI Disk Array Controller",\
1052               detect:          gdth_detect,                     \
1053               release:         gdth_release,                    \
1054               info:            gdth_info,                       \
1055               command:         NULL,                            \
1056               queuecommand:    gdth_queuecommand,               \
1057               eh_abort_handler: gdth_eh_abort,                  \
1058               eh_device_reset_handler: gdth_eh_device_reset,    \
1059               eh_bus_reset_handler: gdth_eh_bus_reset,          \
1060               eh_host_reset_handler: gdth_eh_host_reset,        \
1061               abort:           gdth_abort,                      \
1062               reset:           gdth_reset,                      \
1063               bios_param:      gdth_bios_param,                 \
1064               can_queue:       GDTH_MAXCMDS,                    \
1065               this_id:         -1,                              \
1066               sg_tablesize:    GDTH_MAXSG,                      \
1067               cmd_per_lun:     GDTH_MAXC_P_L,                   \
1068               present:         0,                               \
1069               unchecked_isa_dma: 1,                             \
1070               use_clustering:  ENABLE_CLUSTERING,               \
1071               use_new_eh_code: 1       /* use new error code */ }    
1072#endif
1073
1074int gdth_eh_abort(Scsi_Cmnd *scp);
1075int gdth_eh_device_reset(Scsi_Cmnd *scp);
1076int gdth_eh_bus_reset(Scsi_Cmnd *scp);
1077int gdth_eh_host_reset(Scsi_Cmnd *scp);
1078
1079#endif
1080