linux-old/drivers/net/wan/n2.c
<<
>>
Prefs
   1/*
   2 * SDL Inc. RISCom/N2 synchronous serial card driver for Linux
   3 *
   4 * Copyright (C) 1998-2003 Krzysztof Halasa <khc@pm.waw.pl>
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms of version 2 of the GNU General Public License
   8 * as published by the Free Software Foundation.
   9 *
  10 * For information see http://hq.pm.waw.pl/hdlc/
  11 *
  12 * Note: integrated CSU/DSU/DDS are not supported by this driver
  13 *
  14 * Sources of information:
  15 *    Hitachi HD64570 SCA User's Manual
  16 *    SDL Inc. PPP/HDLC/CISCO driver
  17 */
  18
  19#include <linux/module.h>
  20#include <linux/kernel.h>
  21#include <linux/slab.h>
  22#include <linux/types.h>
  23#include <linux/fcntl.h>
  24#include <linux/in.h>
  25#include <linux/string.h>
  26#include <linux/errno.h>
  27#include <linux/init.h>
  28#include <linux/ioport.h>
  29#include <linux/netdevice.h>
  30#include <linux/hdlc.h>
  31#include <asm/io.h>
  32#include "hd64570.h"
  33
  34
  35static const char* version = "SDL RISCom/N2 driver version: 1.14";
  36static const char* devname = "RISCom/N2";
  37
  38#undef DEBUG_PKT
  39#define DEBUG_RINGS
  40
  41#define USE_WINDOWSIZE 16384
  42#define USE_BUS16BITS 1
  43#define CLOCK_BASE 9830400      /* 9.8304 MHz */
  44#define MAX_PAGES      16       /* 16 RAM pages at max */
  45#define MAX_RAM_SIZE 0x80000    /* 512 KB */
  46#if MAX_RAM_SIZE > MAX_PAGES * USE_WINDOWSIZE
  47#undef MAX_RAM_SIZE
  48#define MAX_RAM_SIZE (MAX_PAGES * USE_WINDOWSIZE)
  49#endif
  50#define N2_IOPORTS 0x10
  51#define NEED_DETECT_RAM
  52#define MAX_TX_BUFFERS 10
  53
  54static char *hw = NULL; /* pointer to hw=xxx command line string */
  55
  56/* RISCom/N2 Board Registers */
  57
  58/* PC Control Register */
  59#define N2_PCR 0
  60#define PCR_RUNSCA 1     /* Run 64570 */
  61#define PCR_VPM    2     /* Enable VPM - needed if using RAM above 1 MB */
  62#define PCR_ENWIN  4     /* Open window */
  63#define PCR_BUS16  8     /* 16-bit bus */
  64
  65
  66/* Memory Base Address Register */
  67#define N2_BAR 2
  68
  69
  70/* Page Scan Register  */
  71#define N2_PSR 4
  72#define WIN16K       0x00
  73#define WIN32K       0x20
  74#define WIN64K       0x40
  75#define PSR_WINBITS  0x60
  76#define PSR_DMAEN    0x80
  77#define PSR_PAGEBITS 0x0F
  78
  79
  80/* Modem Control Reg */
  81#define N2_MCR 6
  82#define CLOCK_OUT_PORT1 0x80
  83#define CLOCK_OUT_PORT0 0x40
  84#define TX422_PORT1     0x20
  85#define TX422_PORT0     0x10
  86#define DSR_PORT1       0x08
  87#define DSR_PORT0       0x04
  88#define DTR_PORT1       0x02
  89#define DTR_PORT0       0x01
  90
  91
  92typedef struct port_s {
  93        hdlc_device hdlc;       /* HDLC device struct - must be first */
  94        struct card_s *card;
  95        spinlock_t lock;        /* TX lock */
  96        sync_serial_settings settings;
  97        int valid;              /* port enabled */
  98        int rxpart;             /* partial frame received, next frame invalid*/
  99        unsigned short encoding;
 100        unsigned short parity;
 101        u16 rxin;               /* rx ring buffer 'in' pointer */
 102        u16 txin;               /* tx ring buffer 'in' and 'last' pointers */
 103        u16 txlast;
 104        u8 rxs, txs, tmc;       /* SCA registers */
 105        u8 phy_node;            /* physical port # - 0 or 1 */
 106        u8 log_node;            /* logical port # */
 107}port_t;
 108
 109
 110
 111typedef struct card_s {
 112        u8 *winbase;            /* ISA window base address */
 113        u32 phy_winbase;        /* ISA physical base address */
 114        u32 ram_size;           /* number of bytes */
 115        u16 io;                 /* IO Base address */
 116        u16 buff_offset;        /* offset of first buffer of first channel */
 117        u16 rx_ring_buffers;    /* number of buffers in a ring */
 118        u16 tx_ring_buffers;
 119        u8 irq;                 /* IRQ (3-15) */
 120
 121        port_t ports[2];
 122        struct card_s *next_card;
 123}card_t;
 124
 125
 126static card_t *first_card;
 127static card_t **new_card = &first_card;
 128
 129
 130#define sca_reg(reg, card) (0x8000 | (card)->io | \
 131                            ((reg) & 0x0F) | (((reg) & 0xF0) << 6))
 132#define sca_in(reg, card)               inb(sca_reg(reg, card))
 133#define sca_out(value, reg, card)       outb(value, sca_reg(reg, card))
 134#define sca_inw(reg, card)              inw(sca_reg(reg, card))
 135#define sca_outw(value, reg, card)      outw(value, sca_reg(reg, card))
 136
 137#define port_to_card(port)              ((port)->card)
 138#define log_node(port)                  ((port)->log_node)
 139#define phy_node(port)                  ((port)->phy_node)
 140#define winsize(card)                   (USE_WINDOWSIZE)
 141#define winbase(card)                   ((card)->winbase)
 142#define get_port(card, port)            ((card)->ports[port].valid ? \
 143                                         &(card)->ports[port] : NULL)
 144
 145
 146
 147static __inline__ u8 sca_get_page(card_t *card)
 148{
 149        return inb(card->io + N2_PSR) & PSR_PAGEBITS;
 150}
 151
 152
 153static __inline__ void openwin(card_t *card, u8 page)
 154{
 155        u8 psr = inb(card->io + N2_PSR);
 156        outb((psr & ~PSR_PAGEBITS) | page, card->io + N2_PSR);
 157}
 158
 159
 160static __inline__ void close_windows(card_t *card)
 161{
 162        outb(inb(card->io + N2_PCR) & ~PCR_ENWIN, card->io + N2_PCR);
 163}
 164
 165
 166#include "hd6457x.c"
 167
 168
 169
 170static void n2_set_iface(port_t *port)
 171{
 172        card_t *card = port->card;
 173        int io = card->io;
 174        u8 mcr = inb(io + N2_MCR);
 175        u8 msci = get_msci(port);
 176        u8 rxs = port->rxs & CLK_BRG_MASK;
 177        u8 txs = port->txs & CLK_BRG_MASK;
 178
 179        switch(port->settings.clock_type) {
 180        case CLOCK_INT:
 181                mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0;
 182                rxs |= CLK_BRG_RX; /* BRG output */
 183                txs |= CLK_RXCLK_TX; /* RX clock */
 184                break;
 185
 186        case CLOCK_TXINT:
 187                mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0;
 188                rxs |= CLK_LINE_RX; /* RXC input */
 189                txs |= CLK_BRG_TX; /* BRG output */
 190                break;
 191
 192        case CLOCK_TXFROMRX:
 193                mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0;
 194                rxs |= CLK_LINE_RX; /* RXC input */
 195                txs |= CLK_RXCLK_TX; /* RX clock */
 196                break;
 197
 198        default:                /* Clock EXTernal */
 199                mcr &= port->phy_node ? ~CLOCK_OUT_PORT1 : ~CLOCK_OUT_PORT0;
 200                rxs |= CLK_LINE_RX; /* RXC input */
 201                txs |= CLK_LINE_TX; /* TXC input */
 202        }
 203
 204        outb(mcr, io + N2_MCR);
 205        port->rxs = rxs;
 206        port->txs = txs;
 207        sca_out(rxs, msci + RXS, card);
 208        sca_out(txs, msci + TXS, card);
 209        sca_set_port(port);
 210}
 211
 212
 213
 214static int n2_open(struct net_device *dev)
 215{
 216        hdlc_device *hdlc = dev_to_hdlc(dev);
 217        port_t *port = hdlc_to_port(hdlc);
 218        int io = port->card->io;
 219        u8 mcr = inb(io + N2_MCR) | (port->phy_node ? TX422_PORT1:TX422_PORT0);
 220
 221        int result = hdlc_open(hdlc);
 222        if (result)
 223                return result;
 224
 225        MOD_INC_USE_COUNT;
 226        mcr &= port->phy_node ? ~DTR_PORT1 : ~DTR_PORT0; /* set DTR ON */
 227        outb(mcr, io + N2_MCR);
 228
 229        outb(inb(io + N2_PCR) | PCR_ENWIN, io + N2_PCR); /* open window */
 230        outb(inb(io + N2_PSR) | PSR_DMAEN, io + N2_PSR); /* enable dma */
 231        sca_open(hdlc);
 232        n2_set_iface(port);
 233        return 0;
 234}
 235
 236
 237
 238static int n2_close(struct net_device *dev)
 239{
 240        hdlc_device *hdlc = dev_to_hdlc(dev);
 241        port_t *port = hdlc_to_port(hdlc);
 242        int io = port->card->io;
 243        u8 mcr = inb(io+N2_MCR) | (port->phy_node ? TX422_PORT1 : TX422_PORT0);
 244
 245        sca_close(hdlc);
 246        mcr |= port->phy_node ? DTR_PORT1 : DTR_PORT0; /* set DTR OFF */
 247        outb(mcr, io + N2_MCR);
 248        hdlc_close(hdlc);
 249        MOD_DEC_USE_COUNT;
 250        return 0;
 251}
 252
 253
 254
 255static int n2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 256{
 257        const size_t size = sizeof(sync_serial_settings);
 258        sync_serial_settings new_line, *line = ifr->ifr_settings.ifs_ifsu.sync;
 259        hdlc_device *hdlc = dev_to_hdlc(dev);
 260        port_t *port = hdlc_to_port(hdlc);
 261
 262#ifdef DEBUG_RINGS
 263        if (cmd == SIOCDEVPRIVATE) {
 264                sca_dump_rings(hdlc);
 265                return 0;
 266        }
 267#endif
 268        if (cmd != SIOCWANDEV)
 269                return hdlc_ioctl(dev, ifr, cmd);
 270
 271        switch(ifr->ifr_settings.type) {
 272        case IF_GET_IFACE:
 273                ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
 274                if (ifr->ifr_settings.size < size) {
 275                        ifr->ifr_settings.size = size; /* data size wanted */
 276                        return -ENOBUFS;
 277                }
 278                if (copy_to_user(line, &port->settings, size))
 279                        return -EFAULT;
 280                return 0;
 281
 282        case IF_IFACE_SYNC_SERIAL:
 283                if(!capable(CAP_NET_ADMIN))
 284                        return -EPERM;
 285
 286                if (copy_from_user(&new_line, line, size))
 287                        return -EFAULT;
 288
 289                if (new_line.clock_type != CLOCK_EXT &&
 290                    new_line.clock_type != CLOCK_TXFROMRX &&
 291                    new_line.clock_type != CLOCK_INT &&
 292                    new_line.clock_type != CLOCK_TXINT)
 293                return -EINVAL; /* No such clock setting */
 294
 295                if (new_line.loopback != 0 && new_line.loopback != 1)
 296                        return -EINVAL;
 297
 298                memcpy(&port->settings, &new_line, size); /* Update settings */
 299                n2_set_iface(port);
 300                return 0;
 301
 302        default:
 303                return hdlc_ioctl(dev, ifr, cmd);
 304        }
 305}
 306
 307
 308
 309static void n2_destroy_card(card_t *card)
 310{
 311        int cnt;
 312
 313        for (cnt = 0; cnt < 2; cnt++)
 314                if (card->ports[cnt].card)
 315                        unregister_hdlc_device(&card->ports[cnt].hdlc);
 316
 317        if (card->irq)
 318                free_irq(card->irq, card);
 319
 320        if (card->winbase) {
 321                iounmap(card->winbase);
 322                release_mem_region(card->phy_winbase, USE_WINDOWSIZE);
 323        }
 324
 325        if (card->io)
 326                release_region(card->io, N2_IOPORTS);
 327        kfree(card);
 328}
 329
 330
 331
 332static int __init n2_run(unsigned long io, unsigned long irq,
 333                         unsigned long winbase, long valid0, long valid1)
 334{
 335        card_t *card;
 336        u8 cnt, pcr;
 337        int i;
 338
 339        if (io < 0x200 || io > 0x3FF || (io % N2_IOPORTS) != 0) {
 340                printk(KERN_ERR "n2: invalid I/O port value\n");
 341                return -ENODEV;
 342        }
 343
 344        if (irq < 3 || irq > 15 || irq == 6) /* FIXME */ {
 345                printk(KERN_ERR "n2: invalid IRQ value\n");
 346                return -ENODEV;
 347        }
 348
 349        if (winbase < 0xA0000 || winbase > 0xFFFFF || (winbase & 0xFFF) != 0) {
 350                printk(KERN_ERR "n2: invalid RAM value\n");
 351                return -ENODEV;
 352        }
 353
 354        card = kmalloc(sizeof(card_t), GFP_KERNEL);
 355        if (card == NULL) {
 356                printk(KERN_ERR "n2: unable to allocate memory\n");
 357                return -ENOBUFS;
 358        }
 359        memset(card, 0, sizeof(card_t));
 360
 361        if (!request_region(io, N2_IOPORTS, devname)) {
 362                printk(KERN_ERR "n2: I/O port region in use\n");
 363                n2_destroy_card(card);
 364                return -EBUSY;
 365        }
 366        card->io = io;
 367
 368        if (request_irq(irq, &sca_intr, 0, devname, card)) {
 369                printk(KERN_ERR "n2: could not allocate IRQ\n");
 370                n2_destroy_card(card);
 371                return(-EBUSY);
 372        }
 373        card->irq = irq;
 374
 375        if (!request_mem_region(winbase, USE_WINDOWSIZE, devname)) {
 376                printk(KERN_ERR "n2: could not request RAM window\n");
 377                n2_destroy_card(card);
 378                return(-EBUSY);
 379        }
 380        card->phy_winbase = winbase;
 381        card->winbase = ioremap(winbase, USE_WINDOWSIZE);
 382
 383        outb(0, io + N2_PCR);
 384        outb(winbase >> 12, io + N2_BAR);
 385
 386        switch (USE_WINDOWSIZE) {
 387        case 16384:
 388                outb(WIN16K, io + N2_PSR);
 389                break;
 390
 391        case 32768:
 392                outb(WIN32K, io + N2_PSR);
 393                break;
 394
 395        case 65536:
 396                outb(WIN64K, io + N2_PSR);
 397                break;
 398
 399        default:
 400                printk(KERN_ERR "n2: invalid window size\n");
 401                n2_destroy_card(card);
 402                return -ENODEV;
 403        }
 404
 405        pcr = PCR_ENWIN | PCR_VPM | (USE_BUS16BITS ? PCR_BUS16 : 0);
 406        outb(pcr, io + N2_PCR);
 407
 408        card->ram_size = sca_detect_ram(card, card->winbase, MAX_RAM_SIZE);
 409
 410        /* number of TX + RX buffers for one port */
 411        i = card->ram_size / ((valid0 + valid1) * (sizeof(pkt_desc) +
 412                                                   HDLC_MAX_MRU));
 413
 414        card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
 415        card->rx_ring_buffers = i - card->tx_ring_buffers;
 416
 417        card->buff_offset = (valid0 + valid1) * sizeof(pkt_desc) *
 418                (card->tx_ring_buffers + card->rx_ring_buffers);
 419
 420        printk(KERN_INFO "n2: RISCom/N2 %u KB RAM, IRQ%u, "
 421               "using %u TX + %u RX packets rings\n", card->ram_size / 1024,
 422               card->irq, card->tx_ring_buffers, card->rx_ring_buffers);
 423
 424        if (card->tx_ring_buffers < 1) {
 425                printk(KERN_ERR "n2: RAM test failed\n");
 426                n2_destroy_card(card);
 427                return -EIO;
 428        }
 429
 430        pcr |= PCR_RUNSCA;              /* run SCA */
 431        outb(pcr, io + N2_PCR);
 432        outb(0, io + N2_MCR);
 433
 434        sca_init(card, 0);
 435        for (cnt = 0; cnt < 2; cnt++) {
 436                port_t *port = &card->ports[cnt];
 437                struct net_device *dev = hdlc_to_dev(&port->hdlc);
 438
 439                if ((cnt == 0 && !valid0) || (cnt == 1 && !valid1))
 440                        continue;
 441
 442                port->phy_node = cnt;
 443                port->valid = 1;
 444
 445                if ((cnt == 1) && valid0)
 446                        port->log_node = 1;
 447
 448                spin_lock_init(&port->lock);
 449                dev->irq = irq;
 450                dev->mem_start = winbase;
 451                dev->mem_end = winbase + USE_WINDOWSIZE - 1;
 452                dev->tx_queue_len = 50;
 453                dev->do_ioctl = n2_ioctl;
 454                dev->open = n2_open;
 455                dev->stop = n2_close;
 456                port->hdlc.attach = sca_attach;
 457                port->hdlc.xmit = sca_xmit;
 458                port->settings.clock_type = CLOCK_EXT;
 459
 460                if (register_hdlc_device(&port->hdlc)) {
 461                        printk(KERN_WARNING "n2: unable to register hdlc "
 462                               "device\n");
 463                        n2_destroy_card(card);
 464                        return -ENOBUFS;
 465                }
 466                port->card = card;
 467                sca_init_sync_port(port); /* Set up SCA memory */
 468
 469                printk(KERN_INFO "%s: RISCom/N2 node %d\n",
 470                       hdlc_to_name(&port->hdlc), port->phy_node);
 471        }
 472
 473        *new_card = card;
 474        new_card = &card->next_card;
 475
 476        return 0;
 477}
 478
 479
 480
 481static int __init n2_init(void)
 482{
 483        if (hw==NULL) {
 484#ifdef MODULE
 485                printk(KERN_INFO "n2: no card initialized\n");
 486#endif
 487                return -ENOSYS; /* no parameters specified, abort */
 488        }
 489
 490        printk(KERN_INFO "%s\n", version);
 491
 492        do {
 493                unsigned long io, irq, ram;
 494                long valid[2] = { 0, 0 }; /* Default = both ports disabled */
 495
 496                io = simple_strtoul(hw, &hw, 0);
 497
 498                if (*hw++ != ',')
 499                        break;
 500                irq = simple_strtoul(hw, &hw, 0);
 501
 502                if (*hw++ != ',')
 503                        break;
 504                ram = simple_strtoul(hw, &hw, 0);
 505
 506                if (*hw++ != ',')
 507                        break;
 508                while(1) {
 509                        if (*hw == '0' && !valid[0])
 510                                valid[0] = 1; /* Port 0 enabled */
 511                        else if (*hw == '1' && !valid[1])
 512                                valid[1] = 1; /* Port 1 enabled */
 513                        else
 514                                break;
 515                        hw++;
 516                }
 517
 518                if (!valid[0] && !valid[1])
 519                        break;  /* at least one port must be used */
 520
 521                if (*hw == ':' || *hw == '\x0')
 522                        n2_run(io, irq, ram, valid[0], valid[1]);
 523
 524                if (*hw == '\x0')
 525                        return first_card ? 0 : -ENOSYS;
 526        }while(*hw++ == ':');
 527
 528        printk(KERN_ERR "n2: invalid hardware parameters\n");
 529        return first_card ? 0 : -ENOSYS;
 530}
 531
 532
 533#ifndef MODULE
 534static int __init n2_setup(char *str)
 535{
 536        hw = str;
 537        return 1;
 538}
 539
 540__setup("n2=", n2_setup);
 541#endif
 542
 543
 544static void __exit n2_cleanup(void)
 545{
 546        card_t *card = first_card;
 547
 548        while (card) {
 549                card_t *ptr = card;
 550                card = card->next_card;
 551                n2_destroy_card(ptr);
 552        }
 553}
 554
 555
 556module_init(n2_init);
 557module_exit(n2_cleanup);
 558
 559MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
 560MODULE_DESCRIPTION("RISCom/N2 serial port driver");
 561MODULE_LICENSE("GPL v2");
 562MODULE_PARM(hw, "s");           /* hw=io,irq,ram,ports:io,irq,... */
 563EXPORT_NO_SYMBOLS;
 564
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.