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169#include <linux/module.h>
170#include <linux/init.h>
171#include <linux/ioport.h>
172#include <linux/pci.h>
173#include <linux/netdevice.h>
174#include <linux/etherdevice.h>
175#include <linux/delay.h>
176#include <linux/spinlock.h>
177#include <linux/tqueue.h>
178#include <linux/mii.h>
179
180#include "tlan.h"
181
182typedef u32 (TLanIntVectorFunc)( struct net_device *, u16 );
183
184
185
186static struct net_device *TLan_Eisa_Devices;
187
188static int TLanDevicesInstalled;
189
190
191static int aui[MAX_TLAN_BOARDS];
192static int duplex[MAX_TLAN_BOARDS];
193static int speed[MAX_TLAN_BOARDS];
194static int boards_found;
195
196MODULE_AUTHOR("Maintainer: Samuel Chessman <chessman@tux.org>");
197MODULE_DESCRIPTION("Driver for TI ThunderLAN based ethernet PCI adapters");
198MODULE_LICENSE("GPL");
199
200MODULE_PARM(aui, "1-" __MODULE_STRING(MAX_TLAN_BOARDS) "i");
201MODULE_PARM(duplex, "1-" __MODULE_STRING(MAX_TLAN_BOARDS) "i");
202MODULE_PARM(speed, "1-" __MODULE_STRING(MAX_TLAN_BOARDS) "i");
203MODULE_PARM(debug, "i");
204MODULE_PARM(bbuf, "i");
205MODULE_PARM_DESC(aui, "ThunderLAN use AUI port(s) (0-1)");
206MODULE_PARM_DESC(duplex, "ThunderLAN duplex setting(s) (0-default, 1-half, 2-full)");
207MODULE_PARM_DESC(speed, "ThunderLAN port speen setting(s) (0,10,100)");
208MODULE_PARM_DESC(debug, "ThunderLAN debug mask");
209MODULE_PARM_DESC(bbuf, "ThunderLAN use big buffer (0-1)");
210
211
212#undef MONITOR
213
214
215static int debug;
216
217static int bbuf;
218static u8 *TLanPadBuffer;
219static dma_addr_t TLanPadBufferDMA;
220static char TLanSignature[] = "TLAN";
221static const char tlan_banner[] = "ThunderLAN driver v1.15\n";
222static int tlan_have_pci;
223static int tlan_have_eisa;
224
225const char *media[] = {
226 "10BaseT-HD ", "10BaseT-FD ","100baseTx-HD ",
227 "100baseTx-FD", "100baseT4", 0
228};
229
230int media_map[] = { 0x0020, 0x0040, 0x0080, 0x0100, 0x0200,};
231
232static struct board {
233 const char *deviceLabel;
234 u32 flags;
235 u16 addrOfs;
236} board_info[] __devinitdata = {
237 { "Compaq Netelligent 10 T PCI UTP", TLAN_ADAPTER_ACTIVITY_LED, 0x83 },
238 { "Compaq Netelligent 10/100 TX PCI UTP", TLAN_ADAPTER_ACTIVITY_LED, 0x83 },
239 { "Compaq Integrated NetFlex-3/P", TLAN_ADAPTER_NONE, 0x83 },
240 { "Compaq NetFlex-3/P", TLAN_ADAPTER_UNMANAGED_PHY | TLAN_ADAPTER_BIT_RATE_PHY, 0x83 },
241 { "Compaq NetFlex-3/P", TLAN_ADAPTER_NONE, 0x83 },
242 { "Compaq Netelligent Integrated 10/100 TX UTP", TLAN_ADAPTER_ACTIVITY_LED, 0x83 },
243 { "Compaq Netelligent Dual 10/100 TX PCI UTP", TLAN_ADAPTER_NONE, 0x83 },
244 { "Compaq Netelligent 10/100 TX Embedded UTP", TLAN_ADAPTER_NONE, 0x83 },
245 { "Olicom OC-2183/2185", TLAN_ADAPTER_USE_INTERN_10, 0x83 },
246 { "Olicom OC-2325", TLAN_ADAPTER_UNMANAGED_PHY, 0xF8 },
247 { "Olicom OC-2326", TLAN_ADAPTER_USE_INTERN_10, 0xF8 },
248 { "Compaq Netelligent 10/100 TX UTP", TLAN_ADAPTER_ACTIVITY_LED, 0x83 },
249 { "Compaq Netelligent 10 T/2 PCI UTP/Coax", TLAN_ADAPTER_NONE, 0x83 },
250 { "Compaq NetFlex-3/E", TLAN_ADAPTER_ACTIVITY_LED |
251 TLAN_ADAPTER_UNMANAGED_PHY | TLAN_ADAPTER_BIT_RATE_PHY, 0x83 },
252 { "Compaq NetFlex-3/E", TLAN_ADAPTER_ACTIVITY_LED, 0x83 },
253};
254
255static struct pci_device_id tlan_pci_tbl[] __devinitdata = {
256 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_NETEL10,
257 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
258 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_NETEL100,
259 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
260 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_NETFLEX3I,
261 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
262 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_THUNDER,
263 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
264 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_NETFLEX3B,
265 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
266 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_NETEL100PI,
267 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
268 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_NETEL100D,
269 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6 },
270 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_NETEL100I,
271 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7 },
272 { PCI_VENDOR_ID_OLICOM, PCI_DEVICE_ID_OLICOM_OC2183,
273 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
274 { PCI_VENDOR_ID_OLICOM, PCI_DEVICE_ID_OLICOM_OC2325,
275 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9 },
276 { PCI_VENDOR_ID_OLICOM, PCI_DEVICE_ID_OLICOM_OC2326,
277 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10 },
278 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100,
279 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11 },
280 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_NETELLIGENT_10_T2,
281 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12 },
282 { 0,}
283};
284MODULE_DEVICE_TABLE(pci, tlan_pci_tbl);
285
286static void TLan_EisaProbe( void );
287static void TLan_Eisa_Cleanup( void );
288static int TLan_Init( struct net_device * );
289static int TLan_Open( struct net_device *dev );
290static int TLan_StartTx( struct sk_buff *, struct net_device *);
291static void TLan_HandleInterrupt( int, void *, struct pt_regs *);
292static int TLan_Close( struct net_device *);
293static struct net_device_stats *TLan_GetStats( struct net_device *);
294static void TLan_SetMulticastList( struct net_device *);
295static int TLan_ioctl( struct net_device *dev, struct ifreq *rq, int cmd);
296static int TLan_probe1( struct pci_dev *pdev, long ioaddr, int irq, int rev, const struct pci_device_id *ent);
297static void TLan_tx_timeout( struct net_device *dev);
298static int tlan_init_one( struct pci_dev *pdev, const struct pci_device_id *ent);
299
300static u32 TLan_HandleInvalid( struct net_device *, u16 );
301static u32 TLan_HandleTxEOF( struct net_device *, u16 );
302static u32 TLan_HandleStatOverflow( struct net_device *, u16 );
303static u32 TLan_HandleRxEOF( struct net_device *, u16 );
304static u32 TLan_HandleDummy( struct net_device *, u16 );
305static u32 TLan_HandleTxEOC( struct net_device *, u16 );
306static u32 TLan_HandleStatusCheck( struct net_device *, u16 );
307static u32 TLan_HandleRxEOC( struct net_device *, u16 );
308
309static void TLan_Timer( unsigned long );
310
311static void TLan_ResetLists( struct net_device * );
312static void TLan_FreeLists( struct net_device * );
313static void TLan_PrintDio( u16 );
314static void TLan_PrintList( TLanList *, char *, int );
315static void TLan_ReadAndClearStats( struct net_device *, int );
316static void TLan_ResetAdapter( struct net_device * );
317static void TLan_FinishReset( struct net_device * );
318static void TLan_SetMac( struct net_device *, int areg, char *mac );
319
320static void TLan_PhyPrint( struct net_device * );
321static void TLan_PhyDetect( struct net_device * );
322static void TLan_PhyPowerDown( struct net_device * );
323static void TLan_PhyPowerUp( struct net_device * );
324static void TLan_PhyReset( struct net_device * );
325static void TLan_PhyStartLink( struct net_device * );
326static void TLan_PhyFinishAutoNeg( struct net_device * );
327#ifdef MONITOR
328static void TLan_PhyMonitor( struct net_device * );
329#endif
330
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335
336
337
338static int TLan_MiiReadReg( struct net_device *, u16, u16, u16 * );
339static void TLan_MiiSendData( u16, u32, unsigned );
340static void TLan_MiiSync( u16 );
341static void TLan_MiiWriteReg( struct net_device *, u16, u16, u16 );
342
343static void TLan_EeSendStart( u16 );
344static int TLan_EeSendByte( u16, u8, int );
345static void TLan_EeReceiveByte( u16, u8 *, int );
346static int TLan_EeReadByte( struct net_device *, u8, u8 * );
347
348
349static void
350TLan_StoreSKB( struct tlan_list_tag *tag, struct sk_buff *skb)
351{
352 unsigned long addr = (unsigned long)skb;
353 tag->buffer[9].address = (u32)addr;
354 addr >>= 31;
355 addr >>= 1;
356 tag->buffer[8].address = (u32)addr;
357}
358
359static struct sk_buff *
360TLan_GetSKB( struct tlan_list_tag *tag)
361{
362 unsigned long addr = tag->buffer[8].address;
363 addr <<= 31;
364 addr <<= 1;
365 addr |= tag->buffer[9].address;
366 return (struct sk_buff *) addr;
367}
368
369
370static TLanIntVectorFunc *TLanIntVector[TLAN_INT_NUMBER_OF_INTS] = {
371 TLan_HandleInvalid,
372 TLan_HandleTxEOF,
373 TLan_HandleStatOverflow,
374 TLan_HandleRxEOF,
375 TLan_HandleDummy,
376 TLan_HandleTxEOC,
377 TLan_HandleStatusCheck,
378 TLan_HandleRxEOC
379};
380
381static inline void
382TLan_SetTimer( struct net_device *dev, u32 ticks, u32 type )
383{
384 TLanPrivateInfo *priv = dev->priv;
385 unsigned long flags = 0;
386
387 if (!in_irq())
388 spin_lock_irqsave(&priv->lock, flags);
389 if ( priv->timer.function != NULL &&
390 priv->timerType != TLAN_TIMER_ACTIVITY ) {
391 if (!in_irq())
392 spin_unlock_irqrestore(&priv->lock, flags);
393 return;
394 }
395 priv->timer.function = &TLan_Timer;
396 if (!in_irq())
397 spin_unlock_irqrestore(&priv->lock, flags);
398
399 priv->timer.data = (unsigned long) dev;
400 priv->timerSetAt = jiffies;
401 priv->timerType = type;
402 mod_timer(&priv->timer, jiffies + ticks);
403
404}
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437static void __devexit tlan_remove_one( struct pci_dev *pdev)
438{
439 struct net_device *dev = pci_get_drvdata( pdev );
440 TLanPrivateInfo *priv = dev->priv;
441
442 unregister_netdev( dev );
443
444 if ( priv->dmaStorage ) {
445 pci_free_consistent(priv->pciDev, priv->dmaSize, priv->dmaStorage, priv->dmaStorageDMA );
446 }
447
448 pci_release_regions(pdev);
449
450 kfree( dev );
451
452 pci_set_drvdata( pdev, NULL );
453}
454
455static struct pci_driver tlan_driver = {
456 .name = "tlan",
457 .id_table = tlan_pci_tbl,
458 .probe = tlan_init_one,
459 .remove = __devexit_p(tlan_remove_one),
460};
461
462static int __init tlan_probe(void)
463{
464 static int pad_allocated;
465
466 printk(KERN_INFO "%s", tlan_banner);
467
468 TLanPadBuffer = (u8 *) pci_alloc_consistent(NULL, TLAN_MIN_FRAME_SIZE, &TLanPadBufferDMA);
469
470 if (TLanPadBuffer == NULL) {
471 printk(KERN_ERR "TLAN: Could not allocate memory for pad buffer.\n");
472 return -ENOMEM;
473 }
474
475 memset(TLanPadBuffer, 0, TLAN_MIN_FRAME_SIZE);
476 pad_allocated = 1;
477
478 TLAN_DBG(TLAN_DEBUG_PROBE, "Starting PCI Probe....\n");
479
480
481
482 pci_register_driver(&tlan_driver);
483
484 TLAN_DBG(TLAN_DEBUG_PROBE, "Starting EISA Probe....\n");
485 TLan_EisaProbe();
486
487 printk(KERN_INFO "TLAN: %d device%s installed, PCI: %d EISA: %d\n",
488 TLanDevicesInstalled, TLanDevicesInstalled == 1 ? "" : "s",
489 tlan_have_pci, tlan_have_eisa);
490
491 if (TLanDevicesInstalled == 0) {
492 pci_unregister_driver(&tlan_driver);
493 pci_free_consistent(NULL, TLAN_MIN_FRAME_SIZE, TLanPadBuffer, TLanPadBufferDMA);
494 return -ENODEV;
495 }
496 return 0;
497}
498
499
500static int __devinit tlan_init_one( struct pci_dev *pdev,
501 const struct pci_device_id *ent)
502{
503 return TLan_probe1( pdev, -1, -1, 0, ent);
504}
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526static int __devinit TLan_probe1(struct pci_dev *pdev,
527 long ioaddr, int irq, int rev, const struct pci_device_id *ent )
528{
529
530 struct net_device *dev;
531 TLanPrivateInfo *priv;
532 u8 pci_rev;
533 u16 device_id;
534 int reg, rc = -ENODEV;
535
536 if (pdev) {
537 rc = pci_enable_device(pdev);
538 if (rc)
539 return rc;
540
541 rc = pci_request_regions(pdev, TLanSignature);
542 if (rc) {
543 printk(KERN_ERR "TLAN: Could not reserve IO regions\n");
544 goto err_out;
545 }
546 }
547
548 dev = alloc_etherdev(sizeof(TLanPrivateInfo));
549 if (dev == NULL) {
550 printk(KERN_ERR "TLAN: Could not allocate memory for device.\n");
551 rc = -ENOMEM;
552 goto err_out_regions;
553 }
554 SET_MODULE_OWNER(dev);
555
556 priv = dev->priv;
557
558 priv->pciDev = pdev;
559
560
561 if (pdev) {
562 u32 pci_io_base = 0;
563
564 priv->adapter = &board_info[ent->driver_data];
565
566 rc = pci_set_dma_mask(pdev, 0xFFFFFFFF);
567 if (rc) {
568 printk(KERN_ERR "TLAN: No suitable PCI mapping available.\n");
569 goto err_out_free_dev;
570 }
571
572 pci_read_config_byte ( pdev, PCI_REVISION_ID, &pci_rev);
573
574 for ( reg= 0; reg <= 5; reg ++ ) {
575 if (pci_resource_flags(pdev, reg) & IORESOURCE_IO) {
576 pci_io_base = pci_resource_start(pdev, reg);
577 TLAN_DBG( TLAN_DEBUG_GNRL, "IO mapping is available at %x.\n",
578 pci_io_base);
579 break;
580 }
581 }
582 if (!pci_io_base) {
583 printk(KERN_ERR "TLAN: No IO mappings available\n");
584 rc = -EIO;
585 goto err_out_free_dev;
586 }
587
588 dev->base_addr = pci_io_base;
589 dev->irq = pdev->irq;
590 priv->adapterRev = pci_rev;
591 pci_set_master(pdev);
592 pci_set_drvdata(pdev, dev);
593
594 } else {
595
596
597 device_id = inw(ioaddr + EISA_ID2);
598 priv->is_eisa = 1;
599 if (device_id == 0x20F1) {
600 priv->adapter = &board_info[13];
601 priv->adapterRev = 23;
602 } else {
603 priv->adapter = &board_info[14];
604 priv->adapterRev = 10;
605 }
606 dev->base_addr = ioaddr;
607 dev->irq = irq;
608 }
609
610
611 if (dev->mem_start) {
612 priv->aui = dev->mem_start & 0x01;
613 priv->duplex = ((dev->mem_start & 0x06) == 0x06) ? 0 : (dev->mem_start & 0x06) >> 1;
614 priv->speed = ((dev->mem_start & 0x18) == 0x18) ? 0 : (dev->mem_start & 0x18) >> 3;
615
616 if (priv->speed == 0x1) {
617 priv->speed = TLAN_SPEED_10;
618 } else if (priv->speed == 0x2) {
619 priv->speed = TLAN_SPEED_100;
620 }
621 debug = priv->debug = dev->mem_end;
622 } else {
623 priv->aui = aui[boards_found];
624 priv->speed = speed[boards_found];
625 priv->duplex = duplex[boards_found];
626 priv->debug = debug;
627 }
628
629
630
631 INIT_TQUEUE(&priv->tlan_tqueue, (void *)(void*)TLan_tx_timeout, dev);
632
633 spin_lock_init(&priv->lock);
634
635 rc = TLan_Init(dev);
636 if (rc) {
637 printk(KERN_ERR "TLAN: Could not set up device.\n");
638 goto err_out_free_dev;
639 }
640
641 rc = register_netdev(dev);
642 if (rc) {
643 printk(KERN_ERR "TLAN: Could not register device.\n");
644 goto err_out_uninit;
645 }
646
647
648 TLanDevicesInstalled++;
649 boards_found++;
650
651
652 if (pdev)
653 tlan_have_pci++;
654 else {
655 priv->nextDevice = TLan_Eisa_Devices;
656 TLan_Eisa_Devices = dev;
657 tlan_have_eisa++;
658 }
659
660 printk(KERN_INFO "TLAN: %s irq=%2d, io=%04x, %s, Rev. %d\n",
661 dev->name,
662 (int) dev->irq,
663 (int) dev->base_addr,
664 priv->adapter->deviceLabel,
665 priv->adapterRev);
666 return 0;
667
668err_out_uninit:
669 pci_free_consistent(priv->pciDev, priv->dmaSize, priv->dmaStorage,
670 priv->dmaStorageDMA );
671err_out_free_dev:
672 kfree(dev);
673err_out_regions:
674 if (pdev)
675 pci_release_regions(pdev);
676err_out:
677 if (pdev)
678 pci_disable_device(pdev);
679 return rc;
680}
681
682
683static void TLan_Eisa_Cleanup(void)
684{
685 struct net_device *dev;
686 TLanPrivateInfo *priv;
687
688 while( tlan_have_eisa ) {
689 dev = TLan_Eisa_Devices;
690 priv = dev->priv;
691 if (priv->dmaStorage) {
692 pci_free_consistent(priv->pciDev, priv->dmaSize, priv->dmaStorage, priv->dmaStorageDMA );
693 }
694 release_region( dev->base_addr, 0x10);
695 unregister_netdev( dev );
696 TLan_Eisa_Devices = priv->nextDevice;
697 kfree( dev );
698 tlan_have_eisa--;
699 }
700}
701
702
703static void __exit tlan_exit(void)
704{
705 pci_unregister_driver(&tlan_driver);
706
707 if (tlan_have_eisa)
708 TLan_Eisa_Cleanup();
709
710 pci_free_consistent(NULL, TLAN_MIN_FRAME_SIZE, TLanPadBuffer, TLanPadBufferDMA);
711
712}
713
714
715
716module_init(tlan_probe);
717module_exit(tlan_exit);
718
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733
734static void __init TLan_EisaProbe (void)
735{
736 long ioaddr;
737 int rc = -ENODEV;
738 int irq;
739 u16 device_id;
740
741 if (!EISA_bus) {
742 TLAN_DBG(TLAN_DEBUG_PROBE, "No EISA bus present\n");
743 return;
744 }
745
746
747 for (ioaddr = 0x1000; ioaddr < 0x9000; ioaddr += 0x1000) {
748
749 TLAN_DBG(TLAN_DEBUG_PROBE,"EISA_ID 0x%4x: 0x%4x\n", (int) ioaddr + 0xC80, inw(ioaddr + EISA_ID));
750 TLAN_DBG(TLAN_DEBUG_PROBE,"EISA_ID 0x%4x: 0x%4x\n", (int) ioaddr + 0xC82, inw(ioaddr + EISA_ID2));
751
752
753 TLAN_DBG(TLAN_DEBUG_PROBE, "Probing for EISA adapter at IO: 0x%4x : ",
754 (int) ioaddr);
755 if (request_region(ioaddr, 0x10, TLanSignature) == NULL)
756 goto out;
757
758 if (inw(ioaddr + EISA_ID) != 0x110E) {
759 release_region(ioaddr, 0x10);
760 goto out;
761 }
762
763 device_id = inw(ioaddr + EISA_ID2);
764 if (device_id != 0x20F1 && device_id != 0x40F1) {
765 release_region (ioaddr, 0x10);
766 goto out;
767 }
768
769 if (inb(ioaddr + EISA_CR) != 0x1) {
770 release_region (ioaddr, 0x10);
771 goto out2;
772 }
773
774 if (debug == 0x10)
775 printk("Found one\n");
776
777
778
779 switch (inb(ioaddr + 0xCC0)) {
780 case(0x10):
781 irq=5;
782 break;
783 case(0x20):
784 irq=9;
785 break;
786 case(0x40):
787 irq=10;
788 break;
789 case(0x80):
790 irq=11;
791 break;
792 default:
793 goto out;
794 }
795
796
797
798 rc = TLan_probe1( NULL, ioaddr, irq,
799 12, NULL);
800 continue;
801
802 out:
803 if (debug == 0x10)
804 printk("None found\n");
805 continue;
806
807 out2: if (debug == 0x10)
808 printk("Card found but it is not enabled, skipping\n");
809 continue;
810
811 }
812
813}
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836static int TLan_Init( struct net_device *dev )
837{
838 int dma_size;
839 int err;
840 int i;
841 TLanPrivateInfo *priv;
842
843 priv = dev->priv;
844
845 if ( bbuf ) {
846 dma_size = ( TLAN_NUM_RX_LISTS + TLAN_NUM_TX_LISTS )
847 * ( sizeof(TLanList) + TLAN_MAX_FRAME_SIZE );
848 } else {
849 dma_size = ( TLAN_NUM_RX_LISTS + TLAN_NUM_TX_LISTS )
850 * ( sizeof(TLanList) );
851 }
852 priv->dmaStorage = pci_alloc_consistent(priv->pciDev, dma_size, &priv->dmaStorageDMA);
853 priv->dmaSize = dma_size;
854
855 if ( priv->dmaStorage == NULL ) {
856 printk(KERN_ERR "TLAN: Could not allocate lists and buffers for %s.\n",
857 dev->name );
858 return -ENOMEM;
859 }
860 memset( priv->dmaStorage, 0, dma_size );
861 priv->rxList = (TLanList *)
862 ( ( ( (u32) priv->dmaStorage ) + 7 ) & 0xFFFFFFF8 );
863 priv->rxListDMA = ( ( ( (u32) priv->dmaStorageDMA ) + 7 ) & 0xFFFFFFF8 );
864 priv->txList = priv->rxList + TLAN_NUM_RX_LISTS;
865 priv->txListDMA = priv->rxListDMA + sizeof(TLanList) * TLAN_NUM_RX_LISTS;
866 if ( bbuf ) {
867 priv->rxBuffer = (u8 *) ( priv->txList + TLAN_NUM_TX_LISTS );
868 priv->rxBufferDMA =priv->txListDMA + sizeof(TLanList) * TLAN_NUM_TX_LISTS;
869 priv->txBuffer = priv->rxBuffer + ( TLAN_NUM_RX_LISTS * TLAN_MAX_FRAME_SIZE );
870 priv->txBufferDMA = priv->rxBufferDMA + ( TLAN_NUM_RX_LISTS * TLAN_MAX_FRAME_SIZE );
871 }
872
873 err = 0;
874 for ( i = 0; i < 6 ; i++ )
875 err |= TLan_EeReadByte( dev,
876 (u8) priv->adapter->addrOfs + i,
877 (u8 *) &dev->dev_addr[i] );
878 if ( err ) {
879 printk(KERN_ERR "TLAN: %s: Error reading MAC from eeprom: %d\n",
880 dev->name,
881 err );
882 }
883 dev->addr_len = 6;
884
885 netif_carrier_off(dev);
886
887
888 dev->open = &TLan_Open;
889 dev->hard_start_xmit = &TLan_StartTx;
890 dev->stop = &TLan_Close;
891 dev->get_stats = &TLan_GetStats;
892 dev->set_multicast_list = &TLan_SetMulticastList;
893 dev->do_ioctl = &TLan_ioctl;
894 dev->tx_timeout = &TLan_tx_timeout;
895 dev->watchdog_timeo = TX_TIMEOUT;
896
897 return 0;
898
899}
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921static int TLan_Open( struct net_device *dev )
922{
923 TLanPrivateInfo *priv = dev->priv;
924 int err;
925
926 priv->tlanRev = TLan_DioRead8( dev->base_addr, TLAN_DEF_REVISION );
927 err = request_irq( dev->irq, TLan_HandleInterrupt, SA_SHIRQ, TLanSignature, dev );
928
929 if ( err ) {
930 printk(KERN_ERR "TLAN: Cannot open %s because IRQ %d is already in use.\n", dev->name, dev->irq );
931 return err;
932 }
933
934 init_timer(&priv->timer);
935 netif_start_queue(dev);
936
937
938
939
940 TLan_ResetLists( dev );
941 TLan_ReadAndClearStats( dev, TLAN_IGNORE );
942 TLan_ResetAdapter( dev );
943
944 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Opened. TLAN Chip Rev: %x\n", dev->name, priv->tlanRev );
945
946 return 0;
947
948}
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967static int TLan_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
968{
969 TLanPrivateInfo *priv = dev->priv;
970 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&rq->ifr_data;
971 u32 phy = priv->phy[priv->phyNum];
972
973 if (!priv->phyOnline)
974 return -EAGAIN;
975
976 switch(cmd) {
977 case SIOCGMIIPHY:
978 case SIOCDEVPRIVATE:
979 data->phy_id = phy;
980
981
982 case SIOCGMIIREG:
983 case SIOCDEVPRIVATE+1:
984 TLan_MiiReadReg(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, &data->val_out);
985 return 0;
986
987
988 case SIOCSMIIREG:
989 case SIOCDEVPRIVATE+2:
990 if (!capable(CAP_NET_ADMIN))
991 return -EPERM;
992 TLan_MiiWriteReg(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
993 return 0;
994 default:
995 return -EOPNOTSUPP;
996 }
997}
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011static void TLan_tx_timeout(struct net_device *dev)
1012{
1013
1014 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Transmit timed out.\n", dev->name);
1015
1016
1017 TLan_FreeLists( dev );
1018 TLan_ResetLists( dev );
1019 TLan_ReadAndClearStats( dev, TLAN_IGNORE );
1020 TLan_ResetAdapter( dev );
1021 dev->trans_start = jiffies;
1022 netif_wake_queue( dev );
1023
1024}
1025
1026
1027
1028
1029
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1031
1032
1033
1034
1035
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1038
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1044
1045
1046
1047
1048
1049static int TLan_StartTx( struct sk_buff *skb, struct net_device *dev )
1050{
1051 TLanPrivateInfo *priv = dev->priv;
1052 TLanList *tail_list;
1053 dma_addr_t tail_list_phys;
1054 u8 *tail_buffer;
1055 int pad;
1056 unsigned long flags;
1057
1058 if ( ! priv->phyOnline ) {
1059 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: %s PHY is not ready\n", dev->name );
1060 dev_kfree_skb_any(skb);
1061 return 0;
1062 }
1063
1064 tail_list = priv->txList + priv->txTail;
1065 tail_list_phys = priv->txListDMA + sizeof(TLanList) * priv->txTail;
1066
1067 if ( tail_list->cStat != TLAN_CSTAT_UNUSED ) {
1068 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: %s is busy (Head=%d Tail=%d)\n", dev->name, priv->txHead, priv->txTail );
1069 netif_stop_queue(dev);
1070 priv->txBusyCount++;
1071 return 1;
1072 }
1073
1074 tail_list->forward = 0;
1075
1076 if ( bbuf ) {
1077 tail_buffer = priv->txBuffer + ( priv->txTail * TLAN_MAX_FRAME_SIZE );
1078 memcpy( tail_buffer, skb->data, skb->len );
1079 } else {
1080 tail_list->buffer[0].address = pci_map_single(priv->pciDev, skb->data, skb->len, PCI_DMA_TODEVICE);
1081 TLan_StoreSKB(tail_list, skb);
1082 }
1083
1084 pad = TLAN_MIN_FRAME_SIZE - skb->len;
1085
1086 if ( pad > 0 ) {
1087 tail_list->frameSize = (u16) skb->len + pad;
1088 tail_list->buffer[0].count = (u32) skb->len;
1089 tail_list->buffer[1].count = TLAN_LAST_BUFFER | (u32) pad;
1090 tail_list->buffer[1].address = TLanPadBufferDMA;
1091 } else {
1092 tail_list->frameSize = (u16) skb->len;
1093 tail_list->buffer[0].count = TLAN_LAST_BUFFER | (u32) skb->len;
1094 tail_list->buffer[1].count = 0;
1095 tail_list->buffer[1].address = 0;
1096 }
1097
1098 spin_lock_irqsave(&priv->lock, flags);
1099 tail_list->cStat = TLAN_CSTAT_READY;
1100 if ( ! priv->txInProgress ) {
1101 priv->txInProgress = 1;
1102 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: Starting TX on buffer %d\n", priv->txTail );
1103 outl( tail_list_phys, dev->base_addr + TLAN_CH_PARM );
1104 outl( TLAN_HC_GO, dev->base_addr + TLAN_HOST_CMD );
1105 } else {
1106 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: Adding buffer %d to TX channel\n", priv->txTail );
1107 if ( priv->txTail == 0 ) {
1108 ( priv->txList + ( TLAN_NUM_TX_LISTS - 1 ) )->forward = tail_list_phys;
1109 } else {
1110 ( priv->txList + ( priv->txTail - 1 ) )->forward = tail_list_phys;
1111 }
1112 }
1113 spin_unlock_irqrestore(&priv->lock, flags);
1114
1115 CIRC_INC( priv->txTail, TLAN_NUM_TX_LISTS );
1116
1117 if ( bbuf )
1118 dev_kfree_skb_any(skb);
1119
1120 dev->trans_start = jiffies;
1121 return 0;
1122
1123}
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
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1141
1142
1143
1144
1145
1146
1147
1148
1149static void TLan_HandleInterrupt(int irq, void *dev_id, struct pt_regs *regs)
1150{
1151 u32 ack;
1152 struct net_device *dev;
1153 u32 host_cmd;
1154 u16 host_int;
1155 int type;
1156 TLanPrivateInfo *priv;
1157
1158 dev = dev_id;
1159 priv = dev->priv;
1160
1161 spin_lock(&priv->lock);
1162
1163 host_int = inw( dev->base_addr + TLAN_HOST_INT );
1164 outw( host_int, dev->base_addr + TLAN_HOST_INT );
1165
1166 type = ( host_int & TLAN_HI_IT_MASK ) >> 2;
1167
1168 ack = TLanIntVector[type]( dev, host_int );
1169
1170 if ( ack ) {
1171 host_cmd = TLAN_HC_ACK | ack | ( type << 18 );
1172 outl( host_cmd, dev->base_addr + TLAN_HOST_CMD );
1173 }
1174
1175 spin_unlock(&priv->lock);
1176
1177}
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197static int TLan_Close(struct net_device *dev)
1198{
1199 TLanPrivateInfo *priv = dev->priv;
1200
1201 netif_stop_queue(dev);
1202 priv->neg_be_verbose = 0;
1203
1204 TLan_ReadAndClearStats( dev, TLAN_RECORD );
1205 outl( TLAN_HC_AD_RST, dev->base_addr + TLAN_HOST_CMD );
1206 if ( priv->timer.function != NULL ) {
1207 del_timer_sync( &priv->timer );
1208 priv->timer.function = NULL;
1209 }
1210
1211 free_irq( dev->irq, dev );
1212 TLan_FreeLists( dev );
1213 TLAN_DBG( TLAN_DEBUG_GNRL, "Device %s closed.\n", dev->name );
1214
1215 return 0;
1216
1217}
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237static struct net_device_stats *TLan_GetStats( struct net_device *dev )
1238{
1239 TLanPrivateInfo *priv = dev->priv;
1240 int i;
1241
1242
1243 TLan_ReadAndClearStats( dev, TLAN_RECORD );
1244
1245 TLAN_DBG( TLAN_DEBUG_RX, "RECEIVE: %s EOC count = %d\n", dev->name, priv->rxEocCount );
1246 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: %s Busy count = %d\n", dev->name, priv->txBusyCount );
1247 if ( debug & TLAN_DEBUG_GNRL ) {
1248 TLan_PrintDio( dev->base_addr );
1249 TLan_PhyPrint( dev );
1250 }
1251 if ( debug & TLAN_DEBUG_LIST ) {
1252 for ( i = 0; i < TLAN_NUM_RX_LISTS; i++ )
1253 TLan_PrintList( priv->rxList + i, "RX", i );
1254 for ( i = 0; i < TLAN_NUM_TX_LISTS; i++ )
1255 TLan_PrintList( priv->txList + i, "TX", i );
1256 }
1257
1258 return ( &( (TLanPrivateInfo *) dev->priv )->stats );
1259
1260}
1261
1262
1263
1264
1265
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1272
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1274
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1279
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1281
1282
1283
1284
1285static void TLan_SetMulticastList( struct net_device *dev )
1286{
1287 struct dev_mc_list *dmi = dev->mc_list;
1288 u32 hash1 = 0;
1289 u32 hash2 = 0;
1290 int i;
1291 u32 offset;
1292 u8 tmp;
1293
1294 if ( dev->flags & IFF_PROMISC ) {
1295 tmp = TLan_DioRead8( dev->base_addr, TLAN_NET_CMD );
1296 TLan_DioWrite8( dev->base_addr, TLAN_NET_CMD, tmp | TLAN_NET_CMD_CAF );
1297 } else {
1298 tmp = TLan_DioRead8( dev->base_addr, TLAN_NET_CMD );
1299 TLan_DioWrite8( dev->base_addr, TLAN_NET_CMD, tmp & ~TLAN_NET_CMD_CAF );
1300 if ( dev->flags & IFF_ALLMULTI ) {
1301 for ( i = 0; i < 3; i++ )
1302 TLan_SetMac( dev, i + 1, NULL );
1303 TLan_DioWrite32( dev->base_addr, TLAN_HASH_1, 0xFFFFFFFF );
1304 TLan_DioWrite32( dev->base_addr, TLAN_HASH_2, 0xFFFFFFFF );
1305 } else {
1306 for ( i = 0; i < dev->mc_count; i++ ) {
1307 if ( i < 3 ) {
1308 TLan_SetMac( dev, i + 1, (char *) &dmi->dmi_addr );
1309 } else {
1310 offset = TLan_HashFunc( (u8 *) &dmi->dmi_addr );
1311 if ( offset < 32 )
1312 hash1 |= ( 1 << offset );
1313 else
1314 hash2 |= ( 1 << ( offset - 32 ) );
1315 }
1316 dmi = dmi->next;
1317 }
1318 for ( ; i < 3; i++ )
1319 TLan_SetMac( dev, i + 1, NULL );
1320 TLan_DioWrite32( dev->base_addr, TLAN_HASH_1, hash1 );
1321 TLan_DioWrite32( dev->base_addr, TLAN_HASH_2, hash2 );
1322 }
1323 }
1324
1325}
1326
1327
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1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359u32 TLan_HandleInvalid( struct net_device *dev, u16 host_int )
1360{
1361
1362 return 0;
1363
1364}
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
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1385
1386
1387
1388
1389
1390
1391u32 TLan_HandleTxEOF( struct net_device *dev, u16 host_int )
1392{
1393 TLanPrivateInfo *priv = dev->priv;
1394 int eoc = 0;
1395 TLanList *head_list;
1396 dma_addr_t head_list_phys;
1397 u32 ack = 0;
1398 u16 tmpCStat;
1399
1400 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: Handling TX EOF (Head=%d Tail=%d)\n", priv->txHead, priv->txTail );
1401 head_list = priv->txList + priv->txHead;
1402
1403 while (((tmpCStat = head_list->cStat ) & TLAN_CSTAT_FRM_CMP) && (ack < 255)) {
1404 ack++;
1405 if ( ! bbuf ) {
1406 struct sk_buff *skb = TLan_GetSKB(head_list);
1407 pci_unmap_single(priv->pciDev, head_list->buffer[0].address, skb->len, PCI_DMA_TODEVICE);
1408 dev_kfree_skb_any(skb);
1409 head_list->buffer[8].address = 0;
1410 head_list->buffer[9].address = 0;
1411 }
1412
1413 if ( tmpCStat & TLAN_CSTAT_EOC )
1414 eoc = 1;
1415
1416 priv->stats.tx_bytes += head_list->frameSize;
1417
1418 head_list->cStat = TLAN_CSTAT_UNUSED;
1419 netif_start_queue(dev);
1420 CIRC_INC( priv->txHead, TLAN_NUM_TX_LISTS );
1421 head_list = priv->txList + priv->txHead;
1422 }
1423
1424 if (!ack)
1425 printk(KERN_INFO "TLAN: Received interrupt for uncompleted TX frame.\n");
1426
1427 if ( eoc ) {
1428 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: Handling TX EOC (Head=%d Tail=%d)\n", priv->txHead, priv->txTail );
1429 head_list = priv->txList + priv->txHead;
1430 head_list_phys = priv->txListDMA + sizeof(TLanList) * priv->txHead;
1431 if ( ( head_list->cStat & TLAN_CSTAT_READY ) == TLAN_CSTAT_READY ) {
1432 outl(head_list_phys, dev->base_addr + TLAN_CH_PARM );
1433 ack |= TLAN_HC_GO;
1434 } else {
1435 priv->txInProgress = 0;
1436 }
1437 }
1438
1439 if ( priv->adapter->flags & TLAN_ADAPTER_ACTIVITY_LED ) {
1440 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK | TLAN_LED_ACT );
1441 if ( priv->timer.function == NULL ) {
1442 priv->timer.function = &TLan_Timer;
1443 priv->timer.data = (unsigned long) dev;
1444 priv->timer.expires = jiffies + TLAN_TIMER_ACT_DELAY;
1445 priv->timerSetAt = jiffies;
1446 priv->timerType = TLAN_TIMER_ACTIVITY;
1447 add_timer(&priv->timer);
1448 } else if ( priv->timerType == TLAN_TIMER_ACTIVITY ) {
1449 priv->timerSetAt = jiffies;
1450 }
1451 }
1452
1453 return ack;
1454
1455}
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477u32 TLan_HandleStatOverflow( struct net_device *dev, u16 host_int )
1478{
1479 TLan_ReadAndClearStats( dev, TLAN_RECORD );
1480
1481 return 1;
1482
1483}
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513u32 TLan_HandleRxEOF( struct net_device *dev, u16 host_int )
1514{
1515 TLanPrivateInfo *priv = dev->priv;
1516 u32 ack = 0;
1517 int eoc = 0;
1518 u8 *head_buffer;
1519 TLanList *head_list;
1520 struct sk_buff *skb;
1521 TLanList *tail_list;
1522 void *t;
1523 u32 frameSize;
1524 u16 tmpCStat;
1525 dma_addr_t head_list_phys;
1526
1527 TLAN_DBG( TLAN_DEBUG_RX, "RECEIVE: Handling RX EOF (Head=%d Tail=%d)\n", priv->rxHead, priv->rxTail );
1528 head_list = priv->rxList + priv->rxHead;
1529 head_list_phys = priv->rxListDMA + sizeof(TLanList) * priv->rxHead;
1530
1531 while (((tmpCStat = head_list->cStat) & TLAN_CSTAT_FRM_CMP) && (ack < 255)) {
1532 frameSize = head_list->frameSize;
1533 ack++;
1534 if (tmpCStat & TLAN_CSTAT_EOC)
1535 eoc = 1;
1536
1537 if (bbuf) {
1538 skb = dev_alloc_skb(frameSize + 7);
1539 if (skb == NULL)
1540 printk(KERN_INFO "TLAN: Couldn't allocate memory for received data.\n");
1541 else {
1542 head_buffer = priv->rxBuffer + (priv->rxHead * TLAN_MAX_FRAME_SIZE);
1543 skb->dev = dev;
1544 skb_reserve(skb, 2);
1545 t = (void *) skb_put(skb, frameSize);
1546
1547 priv->stats.rx_bytes += head_list->frameSize;
1548
1549 memcpy( t, head_buffer, frameSize );
1550 skb->protocol = eth_type_trans( skb, dev );
1551 netif_rx( skb );
1552 }
1553 } else {
1554 struct sk_buff *new_skb;
1555
1556
1557
1558
1559
1560
1561
1562 new_skb = dev_alloc_skb( TLAN_MAX_FRAME_SIZE + 7 );
1563
1564 if ( new_skb != NULL ) {
1565 skb = TLan_GetSKB(head_list);
1566 pci_unmap_single(priv->pciDev, head_list->buffer[0].address, TLAN_MAX_FRAME_SIZE, PCI_DMA_FROMDEVICE);
1567 skb_trim( skb, frameSize );
1568
1569 priv->stats.rx_bytes += frameSize;
1570
1571 skb->protocol = eth_type_trans( skb, dev );
1572 netif_rx( skb );
1573
1574 new_skb->dev = dev;
1575 skb_reserve( new_skb, 2 );
1576 t = (void *) skb_put( new_skb, TLAN_MAX_FRAME_SIZE );
1577 head_list->buffer[0].address = pci_map_single(priv->pciDev, new_skb->data, TLAN_MAX_FRAME_SIZE, PCI_DMA_FROMDEVICE);
1578 head_list->buffer[8].address = (u32) t;
1579 TLan_StoreSKB(head_list, new_skb);
1580 } else
1581 printk(KERN_WARNING "TLAN: Couldn't allocate memory for received data.\n" );
1582 }
1583
1584 head_list->forward = 0;
1585 head_list->cStat = 0;
1586 tail_list = priv->rxList + priv->rxTail;
1587 tail_list->forward = head_list_phys;
1588
1589 CIRC_INC( priv->rxHead, TLAN_NUM_RX_LISTS );
1590 CIRC_INC( priv->rxTail, TLAN_NUM_RX_LISTS );
1591 head_list = priv->rxList + priv->rxHead;
1592 head_list_phys = priv->rxListDMA + sizeof(TLanList) * priv->rxHead;
1593 }
1594
1595 if (!ack)
1596 printk(KERN_INFO "TLAN: Received interrupt for uncompleted RX frame.\n");
1597
1598
1599
1600
1601 if ( eoc ) {
1602 TLAN_DBG( TLAN_DEBUG_RX, "RECEIVE: Handling RX EOC (Head=%d Tail=%d)\n", priv->rxHead, priv->rxTail );
1603 head_list = priv->rxList + priv->rxHead;
1604 head_list_phys = priv->rxListDMA + sizeof(TLanList) * priv->rxHead;
1605 outl(head_list_phys, dev->base_addr + TLAN_CH_PARM );
1606 ack |= TLAN_HC_GO | TLAN_HC_RT;
1607 priv->rxEocCount++;
1608 }
1609
1610 if ( priv->adapter->flags & TLAN_ADAPTER_ACTIVITY_LED ) {
1611 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK | TLAN_LED_ACT );
1612 if ( priv->timer.function == NULL ) {
1613 priv->timer.function = &TLan_Timer;
1614 priv->timer.data = (unsigned long) dev;
1615 priv->timer.expires = jiffies + TLAN_TIMER_ACT_DELAY;
1616 priv->timerSetAt = jiffies;
1617 priv->timerType = TLAN_TIMER_ACTIVITY;
1618 add_timer(&priv->timer);
1619 } else if ( priv->timerType == TLAN_TIMER_ACTIVITY ) {
1620 priv->timerSetAt = jiffies;
1621 }
1622 }
1623
1624 dev->last_rx = jiffies;
1625
1626 return ack;
1627
1628}
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
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1647
1648
1649
1650u32 TLan_HandleDummy( struct net_device *dev, u16 host_int )
1651{
1652 printk( "TLAN: Test interrupt on %s.\n", dev->name );
1653 return 1;
1654
1655}
1656
1657
1658
1659
1660
1661
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1664
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1679
1680u32 TLan_HandleTxEOC( struct net_device *dev, u16 host_int )
1681{
1682 TLanPrivateInfo *priv = dev->priv;
1683 TLanList *head_list;
1684 dma_addr_t head_list_phys;
1685 u32 ack = 1;
1686
1687 host_int = 0;
1688 if ( priv->tlanRev < 0x30 ) {
1689 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: Handling TX EOC (Head=%d Tail=%d) -- IRQ\n", priv->txHead, priv->txTail );
1690 head_list = priv->txList + priv->txHead;
1691 head_list_phys = priv->txListDMA + sizeof(TLanList) * priv->txHead;
1692 if ( ( head_list->cStat & TLAN_CSTAT_READY ) == TLAN_CSTAT_READY ) {
1693 netif_stop_queue(dev);
1694 outl( head_list_phys, dev->base_addr + TLAN_CH_PARM );
1695 ack |= TLAN_HC_GO;
1696 } else {
1697 priv->txInProgress = 0;
1698 }
1699 }
1700
1701 return ack;
1702
1703}
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
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1720
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1722
1723
1724
1725
1726
1727
1728u32 TLan_HandleStatusCheck( struct net_device *dev, u16 host_int )
1729{
1730 TLanPrivateInfo *priv = dev->priv;
1731 u32 ack;
1732 u32 error;
1733 u8 net_sts;
1734 u32 phy;
1735 u16 tlphy_ctl;
1736 u16 tlphy_sts;
1737
1738 ack = 1;
1739 if ( host_int & TLAN_HI_IV_MASK ) {
1740 netif_stop_queue( dev );
1741 error = inl( dev->base_addr + TLAN_CH_PARM );
1742 printk( "TLAN: %s: Adaptor Error = 0x%x\n", dev->name, error );
1743 TLan_ReadAndClearStats( dev, TLAN_RECORD );
1744 outl( TLAN_HC_AD_RST, dev->base_addr + TLAN_HOST_CMD );
1745
1746 schedule_task(&priv->tlan_tqueue);
1747
1748 netif_wake_queue(dev);
1749 ack = 0;
1750 } else {
1751 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Status Check\n", dev->name );
1752 phy = priv->phy[priv->phyNum];
1753
1754 net_sts = TLan_DioRead8( dev->base_addr, TLAN_NET_STS );
1755 if ( net_sts ) {
1756 TLan_DioWrite8( dev->base_addr, TLAN_NET_STS, net_sts );
1757 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Net_Sts = %x\n", dev->name, (unsigned) net_sts );
1758 }
1759 if ( ( net_sts & TLAN_NET_STS_MIRQ ) && ( priv->phyNum == 0 ) ) {
1760 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_STS, &tlphy_sts );
1761 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_CTL, &tlphy_ctl );
1762 if ( ! ( tlphy_sts & TLAN_TS_POLOK ) && ! ( tlphy_ctl & TLAN_TC_SWAPOL ) ) {
1763 tlphy_ctl |= TLAN_TC_SWAPOL;
1764 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tlphy_ctl);
1765 } else if ( ( tlphy_sts & TLAN_TS_POLOK ) && ( tlphy_ctl & TLAN_TC_SWAPOL ) ) {
1766 tlphy_ctl &= ~TLAN_TC_SWAPOL;
1767 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tlphy_ctl);
1768 }
1769
1770 if (debug) {
1771 TLan_PhyPrint( dev );
1772 }
1773 }
1774 }
1775
1776 return ack;
1777
1778}
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
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1794
1795
1796
1797
1798
1799
1800
1801
1802
1803u32 TLan_HandleRxEOC( struct net_device *dev, u16 host_int )
1804{
1805 TLanPrivateInfo *priv = dev->priv;
1806 dma_addr_t head_list_phys;
1807 u32 ack = 1;
1808
1809 if ( priv->tlanRev < 0x30 ) {
1810 TLAN_DBG( TLAN_DEBUG_RX, "RECEIVE: Handling RX EOC (Head=%d Tail=%d) -- IRQ\n", priv->rxHead, priv->rxTail );
1811 head_list_phys = priv->rxListDMA + sizeof(TLanList) * priv->rxHead;
1812 outl( head_list_phys, dev->base_addr + TLAN_CH_PARM );
1813 ack |= TLAN_HC_GO | TLAN_HC_RT;
1814 priv->rxEocCount++;
1815 }
1816
1817 return ack;
1818
1819}
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
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1854
1855
1856
1857
1858
1859
1860
1861
1862
1863void TLan_Timer( unsigned long data )
1864{
1865 struct net_device *dev = (struct net_device *) data;
1866 TLanPrivateInfo *priv = dev->priv;
1867 u32 elapsed;
1868 unsigned long flags = 0;
1869
1870 priv->timer.function = NULL;
1871
1872 switch ( priv->timerType ) {
1873#ifdef MONITOR
1874 case TLAN_TIMER_LINK_BEAT:
1875 TLan_PhyMonitor( dev );
1876 break;
1877#endif
1878 case TLAN_TIMER_PHY_PDOWN:
1879 TLan_PhyPowerDown( dev );
1880 break;
1881 case TLAN_TIMER_PHY_PUP:
1882 TLan_PhyPowerUp( dev );
1883 break;
1884 case TLAN_TIMER_PHY_RESET:
1885 TLan_PhyReset( dev );
1886 break;
1887 case TLAN_TIMER_PHY_START_LINK:
1888 TLan_PhyStartLink( dev );
1889 break;
1890 case TLAN_TIMER_PHY_FINISH_AN:
1891 TLan_PhyFinishAutoNeg( dev );
1892 break;
1893 case TLAN_TIMER_FINISH_RESET:
1894 TLan_FinishReset( dev );
1895 break;
1896 case TLAN_TIMER_ACTIVITY:
1897 spin_lock_irqsave(&priv->lock, flags);
1898 if ( priv->timer.function == NULL ) {
1899 elapsed = jiffies - priv->timerSetAt;
1900 if ( elapsed >= TLAN_TIMER_ACT_DELAY ) {
1901 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK );
1902 } else {
1903 priv->timer.function = &TLan_Timer;
1904 priv->timer.expires = priv->timerSetAt + TLAN_TIMER_ACT_DELAY;
1905 spin_unlock_irqrestore(&priv->lock, flags);
1906 add_timer( &priv->timer );
1907 break;
1908 }
1909 }
1910 spin_unlock_irqrestore(&priv->lock, flags);
1911 break;
1912 default:
1913 break;
1914 }
1915
1916}
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944void TLan_ResetLists( struct net_device *dev )
1945{
1946 TLanPrivateInfo *priv = dev->priv;
1947 int i;
1948 TLanList *list;
1949 dma_addr_t list_phys;
1950 struct sk_buff *skb;
1951 void *t = NULL;
1952
1953 priv->txHead = 0;
1954 priv->txTail = 0;
1955 for ( i = 0; i < TLAN_NUM_TX_LISTS; i++ ) {
1956 list = priv->txList + i;
1957 list->cStat = TLAN_CSTAT_UNUSED;
1958 if ( bbuf ) {
1959 list->buffer[0].address = priv->txBufferDMA + ( i * TLAN_MAX_FRAME_SIZE );
1960 } else {
1961 list->buffer[0].address = 0;
1962 }
1963 list->buffer[2].count = 0;
1964 list->buffer[2].address = 0;
1965 list->buffer[8].address = 0;
1966 list->buffer[9].address = 0;
1967 }
1968
1969 priv->rxHead = 0;
1970 priv->rxTail = TLAN_NUM_RX_LISTS - 1;
1971 for ( i = 0; i < TLAN_NUM_RX_LISTS; i++ ) {
1972 list = priv->rxList + i;
1973 list_phys = priv->rxListDMA + sizeof(TLanList) * i;
1974 list->cStat = TLAN_CSTAT_READY;
1975 list->frameSize = TLAN_MAX_FRAME_SIZE;
1976 list->buffer[0].count = TLAN_MAX_FRAME_SIZE | TLAN_LAST_BUFFER;
1977 if ( bbuf ) {
1978 list->buffer[0].address = priv->rxBufferDMA + ( i * TLAN_MAX_FRAME_SIZE );
1979 } else {
1980 skb = dev_alloc_skb( TLAN_MAX_FRAME_SIZE + 7 );
1981 if ( skb == NULL ) {
1982 printk( "TLAN: Couldn't allocate memory for received data.\n" );
1983
1984 } else {
1985 skb->dev = dev;
1986 skb_reserve( skb, 2 );
1987 t = (void *) skb_put( skb, TLAN_MAX_FRAME_SIZE );
1988 }
1989 list->buffer[0].address = pci_map_single(priv->pciDev, t, TLAN_MAX_FRAME_SIZE, PCI_DMA_FROMDEVICE);
1990 list->buffer[8].address = (u32) t;
1991 TLan_StoreSKB(list, skb);
1992 }
1993 list->buffer[1].count = 0;
1994 list->buffer[1].address = 0;
1995 if ( i < TLAN_NUM_RX_LISTS - 1 )
1996 list->forward = list_phys + sizeof(TLanList);
1997 else
1998 list->forward = 0;
1999 }
2000
2001}
2002
2003
2004void TLan_FreeLists( struct net_device *dev )
2005{
2006 TLanPrivateInfo *priv = dev->priv;
2007 int i;
2008 TLanList *list;
2009 struct sk_buff *skb;
2010
2011 if ( ! bbuf ) {
2012 for ( i = 0; i < TLAN_NUM_TX_LISTS; i++ ) {
2013 list = priv->txList + i;
2014 skb = TLan_GetSKB(list);
2015 if ( skb ) {
2016 pci_unmap_single(priv->pciDev, list->buffer[0].address, skb->len, PCI_DMA_TODEVICE);
2017 dev_kfree_skb_any( skb );
2018 list->buffer[8].address = 0;
2019 list->buffer[9].address = 0;
2020 }
2021 }
2022
2023 for ( i = 0; i < TLAN_NUM_RX_LISTS; i++ ) {
2024 list = priv->rxList + i;
2025 skb = TLan_GetSKB(list);
2026 if ( skb ) {
2027 pci_unmap_single(priv->pciDev, list->buffer[0].address, TLAN_MAX_FRAME_SIZE, PCI_DMA_FROMDEVICE);
2028 dev_kfree_skb_any( skb );
2029 list->buffer[8].address = 0;
2030 list->buffer[9].address = 0;
2031 }
2032 }
2033 }
2034}
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053void TLan_PrintDio( u16 io_base )
2054{
2055 u32 data0, data1;
2056 int i;
2057
2058 printk( "TLAN: Contents of internal registers for io base 0x%04hx.\n", io_base );
2059 printk( "TLAN: Off. +0 +4\n" );
2060 for ( i = 0; i < 0x4C; i+= 8 ) {
2061 data0 = TLan_DioRead32( io_base, i );
2062 data1 = TLan_DioRead32( io_base, i + 0x4 );
2063 printk( "TLAN: 0x%02x 0x%08x 0x%08x\n", i, data0, data1 );
2064 }
2065
2066}
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088void TLan_PrintList( TLanList *list, char *type, int num)
2089{
2090 int i;
2091
2092 printk( "TLAN: %s List %d at 0x%08x\n", type, num, (u32) list );
2093 printk( "TLAN: Forward = 0x%08x\n", list->forward );
2094 printk( "TLAN: CSTAT = 0x%04hx\n", list->cStat );
2095 printk( "TLAN: Frame Size = 0x%04hx\n", list->frameSize );
2096
2097 for ( i = 0; i < 2; i++ ) {
2098 printk( "TLAN: Buffer[%d].count, addr = 0x%08x, 0x%08x\n", i, list->buffer[i].count, list->buffer[i].address );
2099 }
2100
2101}
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124void TLan_ReadAndClearStats( struct net_device *dev, int record )
2125{
2126 TLanPrivateInfo *priv = dev->priv;
2127 u32 tx_good, tx_under;
2128 u32 rx_good, rx_over;
2129 u32 def_tx, crc, code;
2130 u32 multi_col, single_col;
2131 u32 excess_col, late_col, loss;
2132
2133 outw( TLAN_GOOD_TX_FRMS, dev->base_addr + TLAN_DIO_ADR );
2134 tx_good = inb( dev->base_addr + TLAN_DIO_DATA );
2135 tx_good += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8;
2136 tx_good += inb( dev->base_addr + TLAN_DIO_DATA + 2 ) << 16;
2137 tx_under = inb( dev->base_addr + TLAN_DIO_DATA + 3 );
2138
2139 outw( TLAN_GOOD_RX_FRMS, dev->base_addr + TLAN_DIO_ADR );
2140 rx_good = inb( dev->base_addr + TLAN_DIO_DATA );
2141 rx_good += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8;
2142 rx_good += inb( dev->base_addr + TLAN_DIO_DATA + 2 ) << 16;
2143 rx_over = inb( dev->base_addr + TLAN_DIO_DATA + 3 );
2144
2145 outw( TLAN_DEFERRED_TX, dev->base_addr + TLAN_DIO_ADR );
2146 def_tx = inb( dev->base_addr + TLAN_DIO_DATA );
2147 def_tx += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8;
2148 crc = inb( dev->base_addr + TLAN_DIO_DATA + 2 );
2149 code = inb( dev->base_addr + TLAN_DIO_DATA + 3 );
2150
2151 outw( TLAN_MULTICOL_FRMS, dev->base_addr + TLAN_DIO_ADR );
2152 multi_col = inb( dev->base_addr + TLAN_DIO_DATA );
2153 multi_col += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8;
2154 single_col = inb( dev->base_addr + TLAN_DIO_DATA + 2 );
2155 single_col += inb( dev->base_addr + TLAN_DIO_DATA + 3 ) << 8;
2156
2157 outw( TLAN_EXCESSCOL_FRMS, dev->base_addr + TLAN_DIO_ADR );
2158 excess_col = inb( dev->base_addr + TLAN_DIO_DATA );
2159 late_col = inb( dev->base_addr + TLAN_DIO_DATA + 1 );
2160 loss = inb( dev->base_addr + TLAN_DIO_DATA + 2 );
2161
2162 if ( record ) {
2163 priv->stats.rx_packets += rx_good;
2164 priv->stats.rx_errors += rx_over + crc + code;
2165 priv->stats.tx_packets += tx_good;
2166 priv->stats.tx_errors += tx_under + loss;
2167 priv->stats.collisions += multi_col + single_col + excess_col + late_col;
2168
2169 priv->stats.rx_over_errors += rx_over;
2170 priv->stats.rx_crc_errors += crc;
2171 priv->stats.rx_frame_errors += code;
2172
2173 priv->stats.tx_aborted_errors += tx_under;
2174 priv->stats.tx_carrier_errors += loss;
2175 }
2176
2177}
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199void
2200TLan_ResetAdapter( struct net_device *dev )
2201{
2202 TLanPrivateInfo *priv = dev->priv;
2203 int i;
2204 u32 addr;
2205 u32 data;
2206 u8 data8;
2207
2208 priv->tlanFullDuplex = FALSE;
2209 priv->phyOnline=0;
2210 netif_carrier_off(dev);
2211
2212
2213
2214 data = inl(dev->base_addr + TLAN_HOST_CMD);
2215 data |= TLAN_HC_AD_RST;
2216 outl(data, dev->base_addr + TLAN_HOST_CMD);
2217
2218 udelay(1000);
2219
2220
2221
2222 data = inl(dev->base_addr + TLAN_HOST_CMD);
2223 data |= TLAN_HC_INT_OFF;
2224 outl(data, dev->base_addr + TLAN_HOST_CMD);
2225
2226
2227
2228 for ( i = TLAN_AREG_0; i <= TLAN_HASH_2; i += 4 ) {
2229 TLan_DioWrite32( dev->base_addr, (u16) i, 0 );
2230 }
2231
2232
2233
2234 data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | TLAN_NET_CFG_PHY_EN;
2235 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, (u16) data );
2236
2237
2238
2239 outl( TLAN_HC_LD_TMR | 0x3f, dev->base_addr + TLAN_HOST_CMD );
2240 outl( TLAN_HC_LD_THR | 0x9, dev->base_addr + TLAN_HOST_CMD );
2241
2242
2243
2244 outw( TLAN_NET_SIO, dev->base_addr + TLAN_DIO_ADR );
2245 addr = dev->base_addr + TLAN_DIO_DATA + TLAN_NET_SIO;
2246 TLan_SetBit( TLAN_NET_SIO_NMRST, addr );
2247
2248
2249
2250 if ( priv->tlanRev >= 0x30 ) {
2251 data8 = TLAN_ID_TX_EOC | TLAN_ID_RX_EOC;
2252 TLan_DioWrite8( dev->base_addr, TLAN_INT_DIS, data8 );
2253 }
2254 TLan_PhyDetect( dev );
2255 data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN;
2256
2257 if ( priv->adapter->flags & TLAN_ADAPTER_BIT_RATE_PHY ) {
2258 data |= TLAN_NET_CFG_BIT;
2259 if ( priv->aui == 1 ) {
2260 TLan_DioWrite8( dev->base_addr, TLAN_ACOMMIT, 0x0a );
2261 } else if ( priv->duplex == TLAN_DUPLEX_FULL ) {
2262 TLan_DioWrite8( dev->base_addr, TLAN_ACOMMIT, 0x00 );
2263 priv->tlanFullDuplex = TRUE;
2264 } else {
2265 TLan_DioWrite8( dev->base_addr, TLAN_ACOMMIT, 0x08 );
2266 }
2267 }
2268
2269 if ( priv->phyNum == 0 ) {
2270 data |= TLAN_NET_CFG_PHY_EN;
2271 }
2272 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, (u16) data );
2273
2274 if ( priv->adapter->flags & TLAN_ADAPTER_UNMANAGED_PHY ) {
2275 TLan_FinishReset( dev );
2276 } else {
2277 TLan_PhyPowerDown( dev );
2278 }
2279
2280}
2281
2282
2283
2284
2285void
2286TLan_FinishReset( struct net_device *dev )
2287{
2288 TLanPrivateInfo *priv = dev->priv;
2289 u8 data;
2290 u32 phy;
2291 u8 sio;
2292 u16 status;
2293 u16 partner;
2294 u16 tlphy_ctl;
2295 u16 tlphy_par;
2296 u16 tlphy_id1, tlphy_id2;
2297 int i;
2298
2299 phy = priv->phy[priv->phyNum];
2300
2301 data = TLAN_NET_CMD_NRESET | TLAN_NET_CMD_NWRAP;
2302 if ( priv->tlanFullDuplex ) {
2303 data |= TLAN_NET_CMD_DUPLEX;
2304 }
2305 TLan_DioWrite8( dev->base_addr, TLAN_NET_CMD, data );
2306 data = TLAN_NET_MASK_MASK4 | TLAN_NET_MASK_MASK5;
2307 if ( priv->phyNum == 0 ) {
2308 data |= TLAN_NET_MASK_MASK7;
2309 }
2310 TLan_DioWrite8( dev->base_addr, TLAN_NET_MASK, data );
2311 TLan_DioWrite16( dev->base_addr, TLAN_MAX_RX, ((1536)+7)&~7 );
2312 TLan_MiiReadReg( dev, phy, MII_GEN_ID_HI, &tlphy_id1 );
2313 TLan_MiiReadReg( dev, phy, MII_GEN_ID_LO, &tlphy_id2 );
2314
2315 if ( ( priv->adapter->flags & TLAN_ADAPTER_UNMANAGED_PHY ) || ( priv->aui ) ) {
2316 status = MII_GS_LINK;
2317 printk( "TLAN: %s: Link forced.\n", dev->name );
2318 } else {
2319 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
2320 udelay( 1000 );
2321 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
2322 if ( (status & MII_GS_LINK) &&
2323 (tlphy_id1 == NAT_SEM_ID1) &&
2324 (tlphy_id2 == NAT_SEM_ID2) ) {
2325 TLan_MiiReadReg( dev, phy, MII_AN_LPA, &partner );
2326 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_PAR, &tlphy_par );
2327
2328 printk( "TLAN: %s: Link active with ", dev->name );
2329 if (!(tlphy_par & TLAN_PHY_AN_EN_STAT)) {
2330 printk( "forced 10%sMbps %s-Duplex\n",
2331 tlphy_par & TLAN_PHY_SPEED_100 ? "" : "0",
2332 tlphy_par & TLAN_PHY_DUPLEX_FULL ? "Full" : "Half");
2333 } else {
2334 printk( "AutoNegotiation enabled, at 10%sMbps %s-Duplex\n",
2335 tlphy_par & TLAN_PHY_SPEED_100 ? "" : "0",
2336 tlphy_par & TLAN_PHY_DUPLEX_FULL ? "Full" : "Half");
2337 printk("TLAN: Partner capability: ");
2338 for (i = 5; i <= 10; i++)
2339 if (partner & (1<<i))
2340 printk("%s",media[i-5]);
2341 printk("\n");
2342 }
2343
2344 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK );
2345#ifdef MONITOR
2346
2347 priv->link = 1;
2348
2349 TLan_SetTimer( dev, (10*HZ), TLAN_TIMER_LINK_BEAT );
2350#endif
2351 } else if (status & MII_GS_LINK) {
2352 printk( "TLAN: %s: Link active\n", dev->name );
2353 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK );
2354 }
2355 }
2356
2357 if ( priv->phyNum == 0 ) {
2358 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_CTL, &tlphy_ctl );
2359 tlphy_ctl |= TLAN_TC_INTEN;
2360 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tlphy_ctl );
2361 sio = TLan_DioRead8( dev->base_addr, TLAN_NET_SIO );
2362 sio |= TLAN_NET_SIO_MINTEN;
2363 TLan_DioWrite8( dev->base_addr, TLAN_NET_SIO, sio );
2364 }
2365
2366 if ( status & MII_GS_LINK ) {
2367 TLan_SetMac( dev, 0, dev->dev_addr );
2368 priv->phyOnline = 1;
2369 outb( ( TLAN_HC_INT_ON >> 8 ), dev->base_addr + TLAN_HOST_CMD + 1 );
2370 if ( debug >= 1 && debug != TLAN_DEBUG_PROBE ) {
2371 outb( ( TLAN_HC_REQ_INT >> 8 ), dev->base_addr + TLAN_HOST_CMD + 1 );
2372 }
2373 outl( priv->rxListDMA, dev->base_addr + TLAN_CH_PARM );
2374 outl( TLAN_HC_GO | TLAN_HC_RT, dev->base_addr + TLAN_HOST_CMD );
2375 netif_carrier_on(dev);
2376 } else {
2377 printk( "TLAN: %s: Link inactive, will retry in 10 secs...\n", dev->name );
2378 TLan_SetTimer( dev, (10*HZ), TLAN_TIMER_FINISH_RESET );
2379 return;
2380 }
2381
2382}
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408void TLan_SetMac( struct net_device *dev, int areg, char *mac )
2409{
2410 int i;
2411
2412 areg *= 6;
2413
2414 if ( mac != NULL ) {
2415 for ( i = 0; i < 6; i++ )
2416 TLan_DioWrite8( dev->base_addr, TLAN_AREG_0 + areg + i, mac[i] );
2417 } else {
2418 for ( i = 0; i < 6; i++ )
2419 TLan_DioWrite8( dev->base_addr, TLAN_AREG_0 + areg + i, 0 );
2420 }
2421
2422}
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450void TLan_PhyPrint( struct net_device *dev )
2451{
2452 TLanPrivateInfo *priv = dev->priv;
2453 u16 i, data0, data1, data2, data3, phy;
2454
2455 phy = priv->phy[priv->phyNum];
2456
2457 if ( priv->adapter->flags & TLAN_ADAPTER_UNMANAGED_PHY ) {
2458 printk( "TLAN: Device %s, Unmanaged PHY.\n", dev->name );
2459 } else if ( phy <= TLAN_PHY_MAX_ADDR ) {
2460 printk( "TLAN: Device %s, PHY 0x%02x.\n", dev->name, phy );
2461 printk( "TLAN: Off. +0 +1 +2 +3 \n" );
2462 for ( i = 0; i < 0x20; i+= 4 ) {
2463 printk( "TLAN: 0x%02x", i );
2464 TLan_MiiReadReg( dev, phy, i, &data0 );
2465 printk( " 0x%04hx", data0 );
2466 TLan_MiiReadReg( dev, phy, i + 1, &data1 );
2467 printk( " 0x%04hx", data1 );
2468 TLan_MiiReadReg( dev, phy, i + 2, &data2 );
2469 printk( " 0x%04hx", data2 );
2470 TLan_MiiReadReg( dev, phy, i + 3, &data3 );
2471 printk( " 0x%04hx\n", data3 );
2472 }
2473 } else {
2474 printk( "TLAN: Device %s, Invalid PHY.\n", dev->name );
2475 }
2476
2477}
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499void TLan_PhyDetect( struct net_device *dev )
2500{
2501 TLanPrivateInfo *priv = dev->priv;
2502 u16 control;
2503 u16 hi;
2504 u16 lo;
2505 u32 phy;
2506
2507 if ( priv->adapter->flags & TLAN_ADAPTER_UNMANAGED_PHY ) {
2508 priv->phyNum = 0xFFFF;
2509 return;
2510 }
2511
2512 TLan_MiiReadReg( dev, TLAN_PHY_MAX_ADDR, MII_GEN_ID_HI, &hi );
2513
2514 if ( hi != 0xFFFF ) {
2515 priv->phy[0] = TLAN_PHY_MAX_ADDR;
2516 } else {
2517 priv->phy[0] = TLAN_PHY_NONE;
2518 }
2519
2520 priv->phy[1] = TLAN_PHY_NONE;
2521 for ( phy = 0; phy <= TLAN_PHY_MAX_ADDR; phy++ ) {
2522 TLan_MiiReadReg( dev, phy, MII_GEN_CTL, &control );
2523 TLan_MiiReadReg( dev, phy, MII_GEN_ID_HI, &hi );
2524 TLan_MiiReadReg( dev, phy, MII_GEN_ID_LO, &lo );
2525 if ( ( control != 0xFFFF ) || ( hi != 0xFFFF ) || ( lo != 0xFFFF ) ) {
2526 TLAN_DBG( TLAN_DEBUG_GNRL, "PHY found at %02x %04x %04x %04x\n", phy, control, hi, lo );
2527 if ( ( priv->phy[1] == TLAN_PHY_NONE ) && ( phy != TLAN_PHY_MAX_ADDR ) ) {
2528 priv->phy[1] = phy;
2529 }
2530 }
2531 }
2532
2533 if ( priv->phy[1] != TLAN_PHY_NONE ) {
2534 priv->phyNum = 1;
2535 } else if ( priv->phy[0] != TLAN_PHY_NONE ) {
2536 priv->phyNum = 0;
2537 } else {
2538 printk( "TLAN: Cannot initialize device, no PHY was found!\n" );
2539 }
2540
2541}
2542
2543
2544
2545
2546void TLan_PhyPowerDown( struct net_device *dev )
2547{
2548 TLanPrivateInfo *priv = dev->priv;
2549 u16 value;
2550
2551 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Powering down PHY(s).\n", dev->name );
2552 value = MII_GC_PDOWN | MII_GC_LOOPBK | MII_GC_ISOLATE;
2553 TLan_MiiSync( dev->base_addr );
2554 TLan_MiiWriteReg( dev, priv->phy[priv->phyNum], MII_GEN_CTL, value );
2555 if ( ( priv->phyNum == 0 ) && ( priv->phy[1] != TLAN_PHY_NONE ) && ( ! ( priv->adapter->flags & TLAN_ADAPTER_USE_INTERN_10 ) ) ) {
2556 TLan_MiiSync( dev->base_addr );
2557 TLan_MiiWriteReg( dev, priv->phy[1], MII_GEN_CTL, value );
2558 }
2559
2560
2561
2562
2563
2564 TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_PUP );
2565
2566}
2567
2568
2569
2570
2571void TLan_PhyPowerUp( struct net_device *dev )
2572{
2573 TLanPrivateInfo *priv = dev->priv;
2574 u16 value;
2575
2576 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Powering up PHY.\n", dev->name );
2577 TLan_MiiSync( dev->base_addr );
2578 value = MII_GC_LOOPBK;
2579 TLan_MiiWriteReg( dev, priv->phy[priv->phyNum], MII_GEN_CTL, value );
2580 TLan_MiiSync(dev->base_addr);
2581
2582
2583
2584
2585 TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_RESET );
2586
2587}
2588
2589
2590
2591
2592void TLan_PhyReset( struct net_device *dev )
2593{
2594 TLanPrivateInfo *priv = dev->priv;
2595 u16 phy;
2596 u16 value;
2597
2598 phy = priv->phy[priv->phyNum];
2599
2600 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Reseting PHY.\n", dev->name );
2601 TLan_MiiSync( dev->base_addr );
2602 value = MII_GC_LOOPBK | MII_GC_RESET;
2603 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, value );
2604 TLan_MiiReadReg( dev, phy, MII_GEN_CTL, &value );
2605 while ( value & MII_GC_RESET ) {
2606 TLan_MiiReadReg( dev, phy, MII_GEN_CTL, &value );
2607 }
2608
2609
2610
2611
2612
2613 TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_START_LINK );
2614
2615}
2616
2617
2618
2619
2620void TLan_PhyStartLink( struct net_device *dev )
2621{
2622 TLanPrivateInfo *priv = dev->priv;
2623 u16 ability;
2624 u16 control;
2625 u16 data;
2626 u16 phy;
2627 u16 status;
2628 u16 tctl;
2629
2630 phy = priv->phy[priv->phyNum];
2631 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Trying to activate link.\n", dev->name );
2632 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
2633 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &ability );
2634
2635 if ( ( status & MII_GS_AUTONEG ) &&
2636 ( ! priv->aui ) ) {
2637 ability = status >> 11;
2638 if ( priv->speed == TLAN_SPEED_10 &&
2639 priv->duplex == TLAN_DUPLEX_HALF) {
2640 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x0000);
2641 } else if ( priv->speed == TLAN_SPEED_10 &&
2642 priv->duplex == TLAN_DUPLEX_FULL) {
2643 priv->tlanFullDuplex = TRUE;
2644 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x0100);
2645 } else if ( priv->speed == TLAN_SPEED_100 &&
2646 priv->duplex == TLAN_DUPLEX_HALF) {
2647 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x2000);
2648 } else if ( priv->speed == TLAN_SPEED_100 &&
2649 priv->duplex == TLAN_DUPLEX_FULL) {
2650 priv->tlanFullDuplex = TRUE;
2651 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x2100);
2652 } else {
2653
2654
2655 TLan_MiiWriteReg( dev, phy, MII_AN_ADV, (ability << 5) | 1);
2656
2657 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x1000 );
2658
2659 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x1200 );
2660
2661
2662
2663
2664
2665 printk( "TLAN: %s: Starting autonegotiation.\n", dev->name );
2666 TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_PHY_FINISH_AN );
2667 return;
2668 }
2669
2670 }
2671
2672 if ( ( priv->aui ) && ( priv->phyNum != 0 ) ) {
2673 priv->phyNum = 0;
2674 data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | TLAN_NET_CFG_PHY_EN;
2675 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, data );
2676 TLan_SetTimer( dev, (40*HZ/1000), TLAN_TIMER_PHY_PDOWN );
2677 return;
2678 } else if ( priv->phyNum == 0 ) {
2679 control = 0;
2680 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_CTL, &tctl );
2681 if ( priv->aui ) {
2682 tctl |= TLAN_TC_AUISEL;
2683 } else {
2684 tctl &= ~TLAN_TC_AUISEL;
2685 if ( priv->duplex == TLAN_DUPLEX_FULL ) {
2686 control |= MII_GC_DUPLEX;
2687 priv->tlanFullDuplex = TRUE;
2688 }
2689 if ( priv->speed == TLAN_SPEED_100 ) {
2690 control |= MII_GC_SPEEDSEL;
2691 }
2692 }
2693 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, control );
2694 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tctl );
2695 }
2696
2697
2698
2699
2700 TLan_SetTimer( dev, (4*HZ), TLAN_TIMER_FINISH_RESET );
2701
2702}
2703
2704
2705
2706
2707void TLan_PhyFinishAutoNeg( struct net_device *dev )
2708{
2709 TLanPrivateInfo *priv = dev->priv;
2710 u16 an_adv;
2711 u16 an_lpa;
2712 u16 data;
2713 u16 mode;
2714 u16 phy;
2715 u16 status;
2716
2717 phy = priv->phy[priv->phyNum];
2718
2719 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
2720 udelay( 1000 );
2721 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
2722
2723 if ( ! ( status & MII_GS_AUTOCMPLT ) ) {
2724
2725
2726
2727 if (!priv->neg_be_verbose++) {
2728 printk(KERN_INFO "TLAN: Giving autonegotiation more time.\n");
2729 printk(KERN_INFO "TLAN: Please check that your adapter has\n");
2730 printk(KERN_INFO "TLAN: been properly connected to a HUB or Switch.\n");
2731 printk(KERN_INFO "TLAN: Trying to establish link in the background...\n");
2732 }
2733 TLan_SetTimer( dev, (8*HZ), TLAN_TIMER_PHY_FINISH_AN );
2734 return;
2735 }
2736
2737 printk( "TLAN: %s: Autonegotiation complete.\n", dev->name );
2738 TLan_MiiReadReg( dev, phy, MII_AN_ADV, &an_adv );
2739 TLan_MiiReadReg( dev, phy, MII_AN_LPA, &an_lpa );
2740 mode = an_adv & an_lpa & 0x03E0;
2741 if ( mode & 0x0100 ) {
2742 priv->tlanFullDuplex = TRUE;
2743 } else if ( ! ( mode & 0x0080 ) && ( mode & 0x0040 ) ) {
2744 priv->tlanFullDuplex = TRUE;
2745 }
2746
2747 if ( ( ! ( mode & 0x0180 ) ) && ( priv->adapter->flags & TLAN_ADAPTER_USE_INTERN_10 ) && ( priv->phyNum != 0 ) ) {
2748 priv->phyNum = 0;
2749 data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | TLAN_NET_CFG_PHY_EN;
2750 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, data );
2751 TLan_SetTimer( dev, (400*HZ/1000), TLAN_TIMER_PHY_PDOWN );
2752 return;
2753 }
2754
2755 if ( priv->phyNum == 0 ) {
2756 if ( ( priv->duplex == TLAN_DUPLEX_FULL ) || ( an_adv & an_lpa & 0x0040 ) ) {
2757 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, MII_GC_AUTOENB | MII_GC_DUPLEX );
2758 printk( "TLAN: Starting internal PHY with FULL-DUPLEX\n" );
2759 } else {
2760 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, MII_GC_AUTOENB );
2761 printk( "TLAN: Starting internal PHY with HALF-DUPLEX\n" );
2762 }
2763 }
2764
2765
2766
2767 TLan_SetTimer( dev, (HZ/10), TLAN_TIMER_FINISH_RESET );
2768
2769}
2770
2771#ifdef MONITOR
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791void TLan_PhyMonitor( struct net_device *dev )
2792{
2793 TLanPrivateInfo *priv = dev->priv;
2794 u16 phy;
2795 u16 phy_status;
2796
2797 phy = priv->phy[priv->phyNum];
2798
2799
2800 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &phy_status );
2801
2802
2803 if (!(phy_status & MII_GS_LINK)) {
2804 if (priv->link) {
2805 priv->link = 0;
2806 printk(KERN_DEBUG "TLAN: %s has lost link\n", dev->name);
2807 dev->flags &= ~IFF_RUNNING;
2808 TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT );
2809 return;
2810 }
2811 }
2812
2813
2814 if ((phy_status & MII_GS_LINK) && !priv->link) {
2815 priv->link = 1;
2816 printk(KERN_DEBUG "TLAN: %s has reestablished link\n", dev->name);
2817 dev->flags |= IFF_RUNNING;
2818 }
2819
2820
2821 TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT );
2822}
2823
2824#endif
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863int TLan_MiiReadReg( struct net_device *dev, u16 phy, u16 reg, u16 *val )
2864{
2865 u8 nack;
2866 u16 sio, tmp;
2867 u32 i;
2868 int err;
2869 int minten;
2870 TLanPrivateInfo *priv = dev->priv;
2871 unsigned long flags = 0;
2872
2873 err = FALSE;
2874 outw(TLAN_NET_SIO, dev->base_addr + TLAN_DIO_ADR);
2875 sio = dev->base_addr + TLAN_DIO_DATA + TLAN_NET_SIO;
2876
2877 if (!in_irq())
2878 spin_lock_irqsave(&priv->lock, flags);
2879
2880 TLan_MiiSync(dev->base_addr);
2881
2882 minten = TLan_GetBit( TLAN_NET_SIO_MINTEN, sio );
2883 if ( minten )
2884 TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio);
2885
2886 TLan_MiiSendData( dev->base_addr, 0x1, 2 );
2887 TLan_MiiSendData( dev->base_addr, 0x2, 2 );
2888 TLan_MiiSendData( dev->base_addr, phy, 5 );
2889 TLan_MiiSendData( dev->base_addr, reg, 5 );
2890
2891
2892 TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio);
2893
2894 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
2895 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
2896 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
2897
2898 nack = TLan_GetBit(TLAN_NET_SIO_MDATA, sio);
2899 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
2900 if (nack) {
2901 for (i = 0; i < 16; i++) {
2902 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
2903 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
2904 }
2905 tmp = 0xffff;
2906 err = TRUE;
2907 } else {
2908 for (tmp = 0, i = 0x8000; i; i >>= 1) {
2909 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
2910 if (TLan_GetBit(TLAN_NET_SIO_MDATA, sio))
2911 tmp |= i;
2912 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
2913 }
2914 }
2915
2916
2917 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
2918 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
2919
2920 if ( minten )
2921 TLan_SetBit(TLAN_NET_SIO_MINTEN, sio);
2922
2923 *val = tmp;
2924
2925 if (!in_irq())
2926 spin_unlock_irqrestore(&priv->lock, flags);
2927
2928 return err;
2929
2930}
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953void TLan_MiiSendData( u16 base_port, u32 data, unsigned num_bits )
2954{
2955 u16 sio;
2956 u32 i;
2957
2958 if ( num_bits == 0 )
2959 return;
2960
2961 outw( TLAN_NET_SIO, base_port + TLAN_DIO_ADR );
2962 sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
2963 TLan_SetBit( TLAN_NET_SIO_MTXEN, sio );
2964
2965 for ( i = ( 0x1 << ( num_bits - 1 ) ); i; i >>= 1 ) {
2966 TLan_ClearBit( TLAN_NET_SIO_MCLK, sio );
2967 (void) TLan_GetBit( TLAN_NET_SIO_MCLK, sio );
2968 if ( data & i )
2969 TLan_SetBit( TLAN_NET_SIO_MDATA, sio );
2970 else
2971 TLan_ClearBit( TLAN_NET_SIO_MDATA, sio );
2972 TLan_SetBit( TLAN_NET_SIO_MCLK, sio );
2973 (void) TLan_GetBit( TLAN_NET_SIO_MCLK, sio );
2974 }
2975
2976}
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995void TLan_MiiSync( u16 base_port )
2996{
2997 int i;
2998 u16 sio;
2999
3000 outw( TLAN_NET_SIO, base_port + TLAN_DIO_ADR );
3001 sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
3002
3003 TLan_ClearBit( TLAN_NET_SIO_MTXEN, sio );
3004 for ( i = 0; i < 32; i++ ) {
3005 TLan_ClearBit( TLAN_NET_SIO_MCLK, sio );
3006 TLan_SetBit( TLAN_NET_SIO_MCLK, sio );
3007 }
3008
3009}
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034void TLan_MiiWriteReg( struct net_device *dev, u16 phy, u16 reg, u16 val )
3035{
3036 u16 sio;
3037 int minten;
3038 unsigned long flags = 0;
3039 TLanPrivateInfo *priv = dev->priv;
3040
3041 outw(TLAN_NET_SIO, dev->base_addr + TLAN_DIO_ADR);
3042 sio = dev->base_addr + TLAN_DIO_DATA + TLAN_NET_SIO;
3043
3044 if (!in_irq())
3045 spin_lock_irqsave(&priv->lock, flags);
3046
3047 TLan_MiiSync( dev->base_addr );
3048
3049 minten = TLan_GetBit( TLAN_NET_SIO_MINTEN, sio );
3050 if ( minten )
3051 TLan_ClearBit( TLAN_NET_SIO_MINTEN, sio );
3052
3053 TLan_MiiSendData( dev->base_addr, 0x1, 2 );
3054 TLan_MiiSendData( dev->base_addr, 0x1, 2 );
3055 TLan_MiiSendData( dev->base_addr, phy, 5 );
3056 TLan_MiiSendData( dev->base_addr, reg, 5 );
3057
3058 TLan_MiiSendData( dev->base_addr, 0x2, 2 );
3059 TLan_MiiSendData( dev->base_addr, val, 16 );
3060
3061 TLan_ClearBit( TLAN_NET_SIO_MCLK, sio );
3062 TLan_SetBit( TLAN_NET_SIO_MCLK, sio );
3063
3064 if ( minten )
3065 TLan_SetBit( TLAN_NET_SIO_MINTEN, sio );
3066
3067 if (!in_irq())
3068 spin_unlock_irqrestore(&priv->lock, flags);
3069
3070}
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104void TLan_EeSendStart( u16 io_base )
3105{
3106 u16 sio;
3107
3108 outw( TLAN_NET_SIO, io_base + TLAN_DIO_ADR );
3109 sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
3110
3111 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3112 TLan_SetBit( TLAN_NET_SIO_EDATA, sio );
3113 TLan_SetBit( TLAN_NET_SIO_ETXEN, sio );
3114 TLan_ClearBit( TLAN_NET_SIO_EDATA, sio );
3115 TLan_ClearBit( TLAN_NET_SIO_ECLOK, sio );
3116
3117}
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144int TLan_EeSendByte( u16 io_base, u8 data, int stop )
3145{
3146 int err;
3147 u8 place;
3148 u16 sio;
3149
3150 outw( TLAN_NET_SIO, io_base + TLAN_DIO_ADR );
3151 sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
3152
3153
3154 for ( place = 0x80; place != 0; place >>= 1 ) {
3155 if ( place & data )
3156 TLan_SetBit( TLAN_NET_SIO_EDATA, sio );
3157 else
3158 TLan_ClearBit( TLAN_NET_SIO_EDATA, sio );
3159 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3160 TLan_ClearBit( TLAN_NET_SIO_ECLOK, sio );
3161 }
3162 TLan_ClearBit( TLAN_NET_SIO_ETXEN, sio );
3163 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3164 err = TLan_GetBit( TLAN_NET_SIO_EDATA, sio );
3165 TLan_ClearBit( TLAN_NET_SIO_ECLOK, sio );
3166 TLan_SetBit( TLAN_NET_SIO_ETXEN, sio );
3167
3168 if ( ( ! err ) && stop ) {
3169 TLan_ClearBit( TLAN_NET_SIO_EDATA, sio );
3170 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3171 TLan_SetBit( TLAN_NET_SIO_EDATA, sio );
3172 }
3173
3174 return ( err );
3175
3176}
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205void TLan_EeReceiveByte( u16 io_base, u8 *data, int stop )
3206{
3207 u8 place;
3208 u16 sio;
3209
3210 outw( TLAN_NET_SIO, io_base + TLAN_DIO_ADR );
3211 sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
3212 *data = 0;
3213
3214
3215 TLan_ClearBit( TLAN_NET_SIO_ETXEN, sio );
3216 for ( place = 0x80; place; place >>= 1 ) {
3217 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3218 if ( TLan_GetBit( TLAN_NET_SIO_EDATA, sio ) )
3219 *data |= place;
3220 TLan_ClearBit( TLAN_NET_SIO_ECLOK, sio );
3221 }
3222
3223 TLan_SetBit( TLAN_NET_SIO_ETXEN, sio );
3224 if ( ! stop ) {
3225 TLan_ClearBit( TLAN_NET_SIO_EDATA, sio );
3226 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3227 TLan_ClearBit( TLAN_NET_SIO_ECLOK, sio );
3228 } else {
3229 TLan_SetBit( TLAN_NET_SIO_EDATA, sio );
3230 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3231 TLan_ClearBit( TLAN_NET_SIO_ECLOK, sio );
3232 TLan_ClearBit( TLAN_NET_SIO_EDATA, sio );
3233 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3234 TLan_SetBit( TLAN_NET_SIO_EDATA, sio );
3235 }
3236
3237}
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263int TLan_EeReadByte( struct net_device *dev, u8 ee_addr, u8 *data )
3264{
3265 int err;
3266 TLanPrivateInfo *priv = dev->priv;
3267 unsigned long flags = 0;
3268 int ret=0;
3269
3270 spin_lock_irqsave(&priv->lock, flags);
3271
3272 TLan_EeSendStart( dev->base_addr );
3273 err = TLan_EeSendByte( dev->base_addr, 0xA0, TLAN_EEPROM_ACK );
3274 if (err)
3275 {
3276 ret=1;
3277 goto fail;
3278 }
3279 err = TLan_EeSendByte( dev->base_addr, ee_addr, TLAN_EEPROM_ACK );
3280 if (err)
3281 {
3282 ret=2;
3283 goto fail;
3284 }
3285 TLan_EeSendStart( dev->base_addr );
3286 err = TLan_EeSendByte( dev->base_addr, 0xA1, TLAN_EEPROM_ACK );
3287 if (err)
3288 {
3289 ret=3;
3290 goto fail;
3291 }
3292 TLan_EeReceiveByte( dev->base_addr, data, TLAN_EEPROM_STOP );
3293fail:
3294 spin_unlock_irqrestore(&priv->lock, flags);
3295
3296 return ret;
3297
3298}
3299
3300
3301
3302