1/****************************************************************************** 2 * 3 * (C)Copyright 1998,1999 SysKonnect, 4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * The information in this file is provided "AS IS" without warranty. 12 * 13 ******************************************************************************/ 14 15#ifndef _SKFBI_H_ 16#define _SKFBI_H_ 17 18#ifdef SYNC 19#define exist_board_far exist_board 20#define get_board_para_far get_board_para 21#endif 22 23/* 24 * physical address offset + IO-Port base address 25 */ 26#ifndef PCI 27#define ADDR(a) ((a)+smc->hw.iop) 28#define ADDRS(smc,a) ((a)+(smc)->hw.iop) 29#endif 30 31/* 32 * FDDI-Fx (x := {I(SA), E(ISA), M(CA), P(CI)}) 33 * address calculation & function defines 34 */ 35 36#ifdef EISA 37 38/* 39 * Configuration PROM: !! all 8-Bit IO's !! 40 * |<- MAC-Address ->| 41 * /-+--+--+--+--+-//-+--+--+--+--+-//-+--+--+--+--+-//-+--+--+--+--+-/ 42 * val: |PROD_ID0..3| | free | |00|00|5A|40| |nn|mm|00|00| 43 * /-+--+--+--+--+-//-+--+--+--+--+-//-+--+--+--+--+-//-+--+--+--+--+-/ 44 * IO- ^ ^ ^ ^ ^ 45 * port 0C80 0C83 0C88 0C90 0C98 46 * | \ 47 * | \ 48 * | \______________________________________________ 49 * EISA Expansion Board Product ID: \ 50 * BIT: |7 6 5 4 3 2 1 0| \ 51 * | PROD_ID0 | PROD_ID1 | PROD_ID2 | PROD_ID3 | 52 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 53 * |0| MAN_C0 | MAN_C1 | MAN_C2 | PROD1 | PROD0 | REV1 | REV0 | 54 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 55 * ^=reserved | product numb. | revision numb | 56 * MAN_Cx = compressed manufacterer code (x:=0..2) 57 * ASCII : 'A'..'Z' : 0x41..0x5A -> compr.(c-0x40) : 0x01..0x1A (5Bits!) 58 */ 59 60#ifndef MULT_OEM 61#ifndef OEM_CONCEPT 62#define MAN_C0 ('S'-0x40) 63#define MAN_C1 ('K'-0x40) 64#define MAN_C2 ('D'-0x40) 65#define PROD_ID0 (u_char)((MAN_C0<<2) | (MAN_C1>>3)) 66#define PROD_ID1 (u_char)(((MAN_C1<<5) & 0xff) | MAN_C2) 67#define PROD_ID2 (u_char)(1) /* prod. nr. */ 68#define PROD_ID3 (u_char)(0) /* rev. nr. */ 69 70#ifndef OEM_USER_DATA 71#define OEM_USER_DATA "SK-NET FDDI V2.0 Userdata" 72#endif 73#else /* OEM_CONCEPT */ 74 75/* MAN_C(0|1|2) no longer present (ra). */ 76#define PROD_ID0 (u_char)OEM_PROD_ID0 77#define PROD_ID1 (u_char)OEM_PROD_ID1 78#define PROD_ID2 (u_char)OEM_PROD_ID2 79#define PROD_ID3 (u_char)OEM_PROD_ID3 80#endif /* OEM_CONCEPT */ 81 82#define SKLOGO PROD_ID0, PROD_ID1, PROD_ID2, PROD_ID3 83#endif /* MULT_OEM */ 84 85#define SADDRL (0) /* start address SKLOGO */ 86#define SA_MAC (0x10) /* start addr. MAC_AD within the PROM */ 87#define PRA_OFF (4) 88#define SA_PMD_TYPE (8) /* start addr. PMD-Type */ 89 90#define SKFDDI_PSZ 32 /* address PROM size */ 91 92/* 93 * address transmission from logical to physical offset address on board 94 */ 95#define FMA(a) (0x0400|((a)<<1)) /* FORMAC+ (r/w) */ 96#define P1A(a) (0x0800|((a)<<1)) /* PLC1 (r/w) */ 97#define P2A(a) (0x0840|((a)<<1)) /* PLC2 (r/w) */ 98#define TIA(a) (0x0880|((a)<<1)) /* Timer (r/w) */ 99#define PRA(a) (0x0c80| (a)) /* configuration PROM */ 100#define C0A(a) (0x0c84| (a)) /* config. RAM */ 101#define C1A(a) (0x0ca0| (a)) /* IRQ-, DMA-nr., EPROM type */ 102#define C2A(a) (0x0ca4| (a)) /* EPROM and PAGE selector */ 103 104#define CONF C0A(0) /* config RAM (card enable bit port) */ 105#define PGRA C2A(0) /* Flash page register */ 106#define CDID PRA(0) /* Card ID I/O port addr. offset */ 107 108 109/* 110 * physical address offset + slot specific IO-Port base address 111 */ 112#define FM_A(a) (FMA(a)+smc->hw.iop) /* FORMAC Plus physical addr */ 113#define P1_A(a) (P1A(a)+smc->hw.iop) /* PLC1 (r/w) */ 114#define P2_A(a) (P2A(a)+smc->hw.iop) /* PLC2 (r/w) */ 115#define TI_A(a) (TIA(a)+smc->hw.iop) /* Timer (r/w) */ 116#define PR_A(a) (PRA(a)+smc->hw.iop) /* config. PROM */ 117#define C0_A(a) (C0A(a)+smc->hw.iop) /* config. RAM */ 118#define C1_A(a) (C1A(a)+smc->hw.iop) /* config. RAM */ 119#define C2_A(a) (C2A(a)+smc->hw.iop) /* config. RAM */ 120 121 122#define CSRA 0x0008 /* control/status register address (r/w) */ 123#define ISRA 0x0008 /* int. source register address (upper 8Bits) */ 124#define PLC1I 0x001a /* clear PLC1 interrupt (write only) */ 125#define PLC2I 0x0020 /* clear PLC2 interrupt (write only) */ 126#define CSFA 0x001c /* control/status FIFO BUSY flags (read only) */ 127#define RQAA 0x001c /* Request reg. (write only) */ 128#define WCTA 0x001e /* word counter (r/w) */ 129#define FFLAG 0x005e /* FLAG/V_FULL (FIFO almost full, write only)*/ 130 131#define CSR_A (CSRA+smc->hw.iop) /* control/status register address (r/w) */ 132#ifdef UNIX 133#define CSR_AS(smc) (CSRA+(smc)->hw.iop) /* control/status register address (r/w) */ 134#endif 135#define ISR_A (ISRA+smc->hw.iop) /* int. source register address (upper 8Bits) */ 136#define PLC1_I (PLC1I+smc->hw.iop) /* clear PLC1 internupt (write only) */ 137#define PLC2_I (PLC2I+smc->hw.iop) /* clear PLC2 interrupt (write only) */ 138#define CSF_A (CSFA+smc->hw.iop) /* control/status FIFO BUSY flags (r/w) */ 139#define RQA_A (RQAA+smc->hw.iop) /* Request reg. (write only) */ 140#define WCT_A (WCTA+smc->hw.iop) /* word counter (r/w) */ 141#define FFLAG_A (FFLAG+smc->hw.iop) /* FLAG/V_FULL (FIFO almost full, write only)*/ 142 143/* 144 * control/status register CSRA bits 145 */ 146/* write */ 147#define CS_CRESET 0x01 /* Card reset (0=reset) */ 148#define CS_RESET_FIFO 0x02 /* FIFO reset (0=reset) */ 149#define CS_IMSK 0x04 /* enable IRQ (1=enable, 0=disable) */ 150#define CS_EN_IRQ_TC 0x08 /* enable IRQ from transfer counter */ 151#define CS_BYPASS 0x20 /* bypass switch (0=remove, 1=insert)*/ 152#define CS_LED_0 0x40 /* switch LED 0 */ 153#define CS_LED_1 0x80 /* switch LED 1 */ 154/* read */ 155#define CS_BYSTAT 0x40 /* 0=Bypass exist, 1= ..not */ 156#define CS_SAS 0x80 /* single attachement station (=1) */ 157 158/* 159 * control/status register CSFA bits (FIFO) 160 */ 161#define CSF_MUX0 0x01 162#define CSF_MUX1 0x02 163#define CSF_HSREQ0 0x04 164#define CSF_HSREQ1 0x08 165#define CSF_HSREQ2 0x10 166#define CSF_BUSY_DMA 0x40 167#define CSF_BUSY_FIFO 0x80 168 169/* 170 * Interrupt source register ISRA (upper 8 data bits) read only & low activ. 171 */ 172#define IS_MINTR1 0x0100 /* FORMAC ST1U/L & ~IMSK1U/L*/ 173#define IS_MINTR2 0x0200 /* FORMAC ST2U/L & ~IMSK2U/L*/ 174#define IS_PLINT1 0x0400 /* PLC1 */ 175#define IS_PLINT2 0x0800 /* PLC2 */ 176#define IS_TIMINT 0x1000 /* Timer 82C54-2 */ 177#define IS_TC 0x2000 /* transf. counter */ 178 179#define ALL_IRSR (IS_MINTR1|IS_MINTR2|IS_PLINT1|IS_PLINT2|IS_TIMINT|IS_TC) 180 181/* 182 * CONFIG<0> RAM (C0_A()) 183 */ 184#define CFG_CARD_EN 0x01 /* card enable */ 185 186/* 187 * CONFIG<1> RAM (C1_A()) 188 */ 189#define CFG_IRQ_SEL 0x03 /* IRQ select (4 nr.) */ 190#define CFG_IRQ_TT 0x04 /* IRQ trigger type (LEVEL/EDGE) */ 191#define CFG_DRQ_SEL 0x18 /* DMA requ. (4 nr.) */ 192#define CFG_BOOT_EN 0x20 /* 0=BOOT-, 1=Application Software */ 193#define CFG_PROG_EN 0x40 /* V_Prog for FLASH_PROM (1=on) */ 194 195/* 196 * CONFIG<2> RAM (C2_A()) 197 */ 198#define CFG_EPROM_SEL 0x0f /* FPROM start address selection */ 199#define CFG_PAGE 0xf0 /* FPROM page selection */ 200 201 202#define READ_PROM(a) ((u_char)inp(a)) 203#define GET_PAGE(i) outp(C2_A(0),((int)(i)<<4) | (inp(C2_A(0)) & ~CFG_PAGE)) 204#define FPROM_SW() (inp(C1_A(0)) & CFG_BOOT_EN) 205 206#define MAX_PAGES 16 /* 16 pages */ 207#define MAX_FADDR 0x2000 /* 8K per page */ 208#define VPP_ON() outp(C1_A(0),inp(C1_A(0)) | CFG_PROG_EN) 209#define VPP_OFF() outp(C1_A(0),inp(C1_A(0)) & ~CFG_PROG_EN) 210 211#define DMA_BUSY() (inpw(CSF_A) & CSF_BUSY_DMA) 212#define FIFO_BUSY() (inpw(CSF_A) & CSF_BUSY_FIFO) 213#define DMA_FIFO_BUSY() (inpw(CSF_A) & (CSF_BUSY_DMA | CSF_BUSY_FIFO)) 214#define BUS_CHECK() 215 216#ifdef UNISYS 217/* For UNISYS use another macro with drv_usecewait function */ 218#define CHECK_DMA() {u_long k = 1000000; \ 219 while (k && (DMA_BUSY())) { k--; drv_usecwait(20); } \ 220 if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; } 221#else 222#define CHECK_DMA() {u_long k = 1000000 ;\ 223 while (k && (DMA_BUSY())) k-- ;\ 224 if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; } 225#endif 226 227#define CHECK_FIFO() {u_long k = 1000000 ;\ 228 while (k && (FIFO_BUSY())) k-- ;\ 229 if (!k) SMT_PANIC(smc,HWM_E0019,HWM_E0019_MSG) ; } 230 231#define CHECK_DMA_FIFO() {u_long k = 1000000 ;\ 232 while (k && (DMA_FIFO_BUSY())) k-- ;\ 233 if (!k) SMT_PANIC(smc,HWM_E0004,HWM_E0004_MSG) ; } 234 235#define GET_ISR() ~inpw(ISR_A) 236#define CHECK_ISR() ~inpw(ISR_A) 237 238#ifndef UNIX 239#ifndef WINNT 240#define CLI_FBI() outpw(CSR_A,(inpw(CSR_A)&\ 241 (CS_CRESET|CS_BYPASS))|CS_RESET_FIFO|smc->hw.led) 242#else /* WINNT */ 243#define CLI_FBI() outpw(CSR_A,(l_inpw(CSR_A)&\ 244 (CS_CRESET|CS_BYPASS))|CS_RESET_FIFO|smc->hw.led) 245#endif /* WINNT */ 246#else /* UNIX */ 247#define CLI_FBI(smc) outpw(CSR_AS(smc),(inpw(CSR_AS(smc))&\ 248 (CS_CRESET|CS_BYPASS))|CS_RESET_FIFO|(smc)->hw.led) 249#endif 250 251#ifndef UNIX 252#define STI_FBI() outpw(CSR_A,(inpw(CSR_A)&\ 253 (CS_CRESET|CS_BYPASS|CS_RESET_FIFO))|CS_IMSK|smc->hw.led) 254#else 255#define STI_FBI(smc) outpw(CSR_AS(smc),(inpw(CSR_AS(smc))&\ 256 (CS_CRESET|CS_BYPASS|CS_RESET_FIFO))|CS_IMSK|(smc)->hw.led) 257#endif 258 259/* EISA DMA Controller */ 260#define DMA_WRITE_SINGLE_MASK_BIT_M 0x0a /* Master DMA Controller */ 261#define DMA_WRITE_SINGLE_MASK_BIT_S 0xd4 /* Slave DMA Controller */ 262#define DMA_CLEAR_BYTE_POINTER_M 0x0c 263#define DMA_CLEAR_BYTE_POINTER_S 0xd8 264 265#endif /* EISA */ 266 267#ifdef MCA 268 269/* 270 * POS Register: !! all I/O's are 8-Bit !! 271 */ 272#define POS_SYS_SETUP 0x94 /* system setup register */ 273#define POS_SYSTEM 0xff /* system mode */ 274 275#define POS_CHANNEL_POS 0x96 /* register slot ID */ 276#define POS_CHANNEL_BIT 0x08 /* mask for -"- */ 277 278#define POS_BASE 0x100 /* POS base address */ 279#define POS_ID_LOW POS_BASE /* card ID low */ 280#define POS_ID_HIGH (POS_BASE+1) /* card ID high */ 281#define POS_102 (POS_BASE+2) /* card en., arbitration level .. */ 282#define POS_103 (POS_BASE+3) /* FPROM addr, page */ 283#define POS_104 (POS_BASE+4) /* I/O, IRQ */ 284#define POS_105 (POS_BASE+5) /* POS_CHCK */ 285#define POS_106 (POS_BASE+6) /* to read VPD */ 286#define POS_107 (POS_BASE+7) /* added without function */ 287 288/* FM1 card IDs */ 289#define FM1_CARD_ID0 0x83 290#define FM1_CARD_ID1 0 291 292#define FM1_IBM_ID0 0x9c 293#define FM1_IBM_ID1 0x8f 294 295 296/* FM2 card IDs */ 297#define FM2_CARD_ID0 0xab 298#define FM2_CARD_ID1 0 299 300#define FM2_IBM_ID0 0x7e 301#define FM2_IBM_ID1 0x8f 302 303/* Board revision. */ 304#define FM1_REV 0 305#define FM2_REV 1 306 307#define MAX_SLOT 8 308 309/* 310 * POS_102 311 */ 312#define POS_CARD_EN 0x01 /* card enable =1 */ 313#define POS_SDAT_EN 0x02 /* enable 32-bit streaming data mode */ 314#define POS_EN_CHKINT 0x04 /* enable int. from check line asserted */ 315#define POS_EN_BUS_ERR 0x08 /* enable int. on invalid busmaster transf. */ 316#define POS_FAIRNESS 0x10 /* fairnes on =1 */ 317/* attention: arbitration level used with bit 0 POS 105 */ 318#define POS_LARBIT 0xe0 /* arbitration level (0,0,0)->level = 0x8 319 (1,1,1)->level = 0xf */ 320/* 321 * POS_103 322 */ 323#define POS_PAGE 0x07 /* FPROM page selection */ 324#define POS_BOOT_EN 0x08 /* boot PROM enable =1 */ 325#define POS_MSEL 0x70 /* memory start address for FPROM mapping */ 326#define PROG_EN 0x80 /* FM1: Vpp prog on/off */ 327#define POS_SDR 0x80 /* FM2: Streaming data bit */ 328 329/* 330 * POS_104 331 */ 332#define POS_IOSEL 0x3f /* selected I/O base address */ 333#define POS_IRQSEL 0xc0 /* selected interrupt */ 334 335/* 336 * POS_105 337 */ 338#define POS_CHCK 0x80 339#define POS_SYNC_ERR 0x20 /* FM2: synchronous error reporting */ 340#define POS_PAR_DATA 0x10 /* FM2: data parity enable bit */ 341#define POS_PAR_ADDR 0x08 /* FM2: address parity enable bit */ 342#define POS_IRQHSEL 0x02 /* FM2: Highest bit for IRQ_selection */ 343#define POS_HARBIT 0x01 /* Highest bit in Bus arbitration selection */ 344 345#define SA_MAC (0) /* start addr. MAC_AD within the PROM */ 346#define PRA_OFF (0) 347#define SA_PMD_TYPE (8) /* start addr. PMD-Type */ 348 349/* 350 * address transmission from logical to physical offset address on board 351 */ 352#define FMA(a) (0x0100|((a)<<1)) /* FORMAC+ (r/w) */ 353#define P2(a) (0x00c0|((a)<<1)) /* PLC2 (r/w) (DAS) */ 354#define P1(a) (0x0080|((a)<<1)) /* PLC1 (r/w) */ 355#define TI(a) (0x0060|((a)<<1)) /* Timer (r/w) */ 356#define PR(a) (0x0040|((a)<<1)) /* configuration PROM */ 357#define CS(a) (0x0020| (a)) /* control/status */ 358#define FF(a) (0x0010|((a)<<1)) /* FIFO ASIC */ 359#define CT(a) (0x0000|((a)<<1)) /* counter */ 360 361/* 362 * counter 363 */ 364#define ACLA CT(0) /* address counter low */ 365#define ACHA CT(1) /* address counter high */ 366#define BCN CT(2) /* byte counter */ 367#define MUX CT(3) /* MUX-register */ 368#define WCN CT(0x08) /* word counter */ 369#define FFLG CT(0x09) /* FIFO Flags */ 370 371/* 372 * test/control register (FM2 only) 373 */ 374#define CNT_TST 0x018 /* Counter test control register */ 375#define CNT_STP 0x01a /* Counter test step reg. (8 Bit) */ 376 377/* 378 * CS register (read only) 379 */ 380#define CSRA CS(0) /* control/status register address */ 381#define CSFA CS(2) /* control/status FIFO BUSY ... */ 382#define ISRA CS(4) /* first int. source register address */ 383#define ISR2 CS(6) /* second int. source register address */ 384#define LEDR CS(0x0c) /* LED register r/w */ 385#define CSIL CS(0x10) /* I/O mapped POS_ID_low (100) */ 386#define CSIH CS(0x12) /* - " - POS_ID_HIGH (101) */ 387#define CSA CS(0x14) /* - " - POS_102 */ 388#define CSM CS(0x0e) /* - " - POS_103 */ 389#define CSM_FM1 CS(0x16) /* - " - POS_103 (copy in FM1) */ 390#define CSI CS(0x18) /* - " - POS_104 */ 391#define CSS CS(0x1a) /* - " - POS_105 */ 392#define CSP_06 CS(0x1c) /* - " - POS_106 */ 393#define WDOG_ST 0x1c /* Watchdog status (FM2 only) */ 394#define WDOG_EN 0x1c /* Watchdog enabling (FM2 only, 8Bit) */ 395#define WDOG_DIS 0x1e /* Watchdog disabling (FM2 only, 8Bit) */ 396 397#define PGRA CSM /* Flash page register */ 398 399 400#define WCTA FF(0) /* word counter */ 401#define FFLAG FF(1) /* FLAG/V_FULL (FIFO almost full, write only)*/ 402 403/* 404 * Timer register (FM2 only) 405 */ 406#define RTM_CNT 0x28 /* RTM Counter */ 407#define TI_DIV 0x60 /* Timer Prescaler */ 408#define TI_CH1 0x62 /* Timer channel 1 counter */ 409#define TI_STOP 0x64 /* Stop timer on channel 1 */ 410#define TI_STRT 0x66 /* Start timer on channel 1 */ 411#define TI_INI2 0x68 /* Timer: Bus master preemption */ 412#define TI_CNT2 0x6a /* Timer */ 413#define TI_INI3 0x6c /* Timer: Streaming data */ 414#define TI_CNT3 0x6e /* Timer */ 415#define WDOG_LO 0x70 /* Watchdog counter low */ 416#define WDOG_HI 0x72 /* Watchdog counter high */ 417#define RTM_PRE 0x74 /* restr. token prescaler */ 418#define RTM_TIM 0x76 /* restr. token timer */ 419 420/* 421 * Recommended Timeout values (for FM2 timer only) 422 */ 423#define TOUT_BM_PRE 188 /* 3.76 usec */ 424#define TOUT_S_DAT 374 /* 7.48 usec */ 425 426/* 427 * CS register (write only) 428 */ 429#define HSR(p) CS(0x18|(p)) /* Host request register */ 430 431#define RTM_PUT 0x36 /* restr. token counter write */ 432#define RTM_GET 0x28 /* - " - clear */ 433#define RTM_CLEAR 0x34 /* - " - read */ 434 435/* 436 * BCN Bit definitions 437 */ 438#define BCN_BUSY 0x8000 /* DMA Busy flag */ 439#define BCN_AZERO 0x4000 /* Almost zero flag (BCN < 4) */ 440#define BCN_STREAM 0x2000 /* Allow streaming data (BCN >= 8) */ 441 442/* 443 * WCN Bit definitions 444 */ 445#define WCN_ZERO 0x2000 /* Zero flag (counted to zero) */ 446#define WCN_AZERO 0x1000 /* Almost zero flag (BCN < 4) */ 447 448/* 449 * CNT_TST Bit definitions 450 */ 451#define CNT_MODE 0x01 /* Go into test mode */ 452#define CNT_D32 0x02 /* 16/32 BIT test mode */ 453 454/* 455 * FIFO Flag FIFO Flags/Vfull register 456 */ 457#define FF_VFULL 0x003f /* V_full value mask */ 458#define FFLG_FULL 0x2000 /* FULL flag */ 459#define FFLG_A_FULL 0x1000 /* Almost full flag */ 460#define FFLG_VFULL 0x0800 /* V_full Flag */ 461#define FFLG_A_EMP 0x0400 /* almost empty flag */ 462#define FFLG_EMP 0x0200 /* empty flag */ 463#define FFLG_T_EMP 0x0100 /* totally empty flag */ 464 465/* 466 * WDOG Watchdog status register 467 */ 468#define WDOG_ALM 0x01 /* Watchdog alarm Bit */ 469#define WDOG_ACT 0x02 /* Watchdog active Bit */ 470 471/* 472 * CS(0) CONTROLS 473 */ 474#define CS_CRESET 0x0001 475#define FIFO_RST 0x0002 476#define CS_IMSK 0x0004 477#define EN_IRQ_CHCK 0x0008 478#define EN_IRQ_TOKEN 0x0010 479#define EN_IRQ_TC 0x0020 480#define TOKEN_STATUS 0x0040 481#define RTM_CHANGE 0x0080 482 483#define CS_SAS 0x0100 484#define CS_BYSTAT 0x0200 /* bypass connected (0=conn.) */ 485#define CS_BYPASS 0x0400 /* bypass on/off indication */ 486 487/* 488 * CS(2) FIFOSTAT 489 */ 490#define HSREQ 0x0007 491#define BIGDIR 0x0008 492#define CSF_BUSY_FIFO 0x0010 493#define CSF_BUSY_DMA 0x0020 494#define SLOT_32 0x0040 495 496#define LED_0 0x0001 497#define LED_1 0x0002 498#define LED_2 0x0100 499 500#define MAX_PAGES 8 /* pages */ 501#define MAX_FADDR 0x4000 /* 16K per page */ 502 503/* 504 * IRQ = ISRA || ISR2 ; 505 * 506 * ISRA = IRQ_OTH_EN && (IS_LAN | IS_BUS) ; 507 * ISR2 = IRQ_TC_EN && IS_TC ; 508 * 509 * IS_LAN = (IS_MINTR1 | IS_MINTR2 | IS_PLINT1 | IS_PLINT2 | IS_TIMINT) || 510 * (IRQ_EN_TOKEN && IS_TOKEN) ; 511 * IS_BUS = IRQ_CHCK_EN && (IS_BUSERR | IS_CHCK_L) ; 512 */ 513/* 514 * ISRA !!! activ high !!! 515 */ 516#define IS_MINTR1 0x0001 /* FORMAC ST1U/L & ~IMSK1U/L*/ 517#define IS_MINTR2 0x0002 /* FORMAC ST2U/L & ~IMSK2U/L*/ 518#define IS_PLINT1 0x0004 /* PLC1 */ 519#define IS_PLINT2 0x0008 /* PLC2 */ 520#define IS_TIMINT 0x0010 /* Timer 82C54-2 */ 521#define IS_TOKEN 0x0020 /* restrictet token monitoring */ 522#define IS_CHCK_L 0x0040 /* check line asserted */ 523#define IS_BUSERR 0x0080 /* bus error */ 524/* 525 * ISR2 526 */ 527#define IS_TC 0x0001 /* terminal count irq */ 528#define IS_SFDBKRTN 0x0002 /* selected feedback return */ 529#define IS_D16 0x0004 /* DS16 */ 530#define IS_D32 0x0008 /* DS32 */ 531#define IS_DPEI 0x0010 /* Data Parity Indication */ 532 533#define ALL_IRSR 0x00ff 534 535#define FM_A(a) ADDR(FMA(a)) /* FORMAC Plus physical addr */ 536#define P1_A(a) ADDR(P1(a)) /* PLC1 (r/w) */ 537#define P2_A(a) ADDR(P2(a)) /* PLC2 (r/w) (DAS) */ 538#define TI_A(a) ADDR(TI(a)) /* Timer (r/w) FM1 only! */ 539#define PR_A(a) ADDR(PR(a)) /* config. PROM */ 540#define CS_A(a) ADDR(CS(a)) /* control/status */ 541 542#define ISR1_A ADDR(ISRA) /* first int. source register address */ 543#define ISR2_A ADDR(ISR2) /* second -"- */ 544#define CSR_A ADDR(CSRA) /* control/status register address */ 545#define CSF_A ADDR(CSFA) /* control/status FIFO BUSY flags (r/w) */ 546 547#define CSIL_A ADDR(CSIL) /* I/O mapped POS_ID_low (102) */ 548#define CSIH_A ADDR(CSIH) /* - " - POS_ID_HIGH (101) */ 549#define CSA_A ADDR(CSA) /* - " - POS_102 */ 550#define CSI_A ADDR(CSI) /* - " - POS_104 */ 551#define CSM_A ADDR(CSM) /* - " - POS_103 */ 552#define CSM_FM1_A ADDR(CSM_FM1) /* - " - POS_103 (2nd copy, FM1) */ 553#define CSP_06_A ADDR(CSP_06) /* - " - POS_106 */ 554 555#define WCT_A ADDR(WCTA) /* word counter (r/w) */ 556#define FFLAG_A ADDR(FFLAG) /* FLAG/V_FULL (FIFO almost full, write only)*/ 557 558#define ACL_A ADDR(ACLA) /* address counter low */ 559#define ACH_A ADDR(ACHA) /* address counter high */ 560#define BCN_A ADDR(BCN) /* byte counter */ 561#define MUX_A ADDR(MUX) /* MUX-register */ 562 563#define ISR_A ADDR(ISRA) /* Interrupt Source Register */ 564#define FIFO_RESET_A ADDR(FIFO_RESET) /* reset the FIFO */ 565#define FIFO_EN_A ADDR(FIFO_EN) /* enable the FIFO */ 566 567#define WDOG_EN_A ADDR(WDOG_EN) /* reset and start the WDOG */ 568#define WDOG_DIS_A ADDR(WDOG_DIS) /* disable the WDOG */ 569/* 570 * all control reg. (read!) are 8 bit (except PAGE_RG_A and LEDR_A) 571 */ 572#define HSR_A(p) ADDR(HSR(p)) /* Host request register */ 573 574#define STAT_BYP 0 /* bypass station */ 575#define STAT_INS 2 /* insert station */ 576#define BYPASS(o) CS(0x10|(o)) /* o=STAT_BYP || STAT_INS */ 577 578#define IRQ_TC_EN CS(0x0b) /* enable/disable IRQ on TC */ 579#define IRQ_TC_DIS CS(0x0a) 580#define IRQ_TOKEN_EN CS(9) /* enable/disable IRQ on restr. Token */ 581#define IRQ_TOKEN_DIS CS(8) 582#define IRQ_CHCK_EN CS(7) /* -"- IRQ after CHCK line */ 583#define IRQ_CHCK_DIS CS(6) 584#define IRQ_OTH_EN CS(5) /* -"- other IRQ's */ 585#define IRQ_OTH_DIS CS(4) 586#define FIFO_EN CS(3) /* disable (reset), enable FIFO */ 587#define FIFO_RESET CS(2) 588#define CARD_EN CS(1) /* disable (reset), enable card */ 589#define CARD_DIS CS(0) 590 591#define LEDR_A ADDR(LEDR) /* D0=green, D1=yellow, D8=L2 */ 592#define PAGE_RG_A ADDR(CSM) /* D<2..0> */ 593#define IRQ_CHCK_EN_A ADDR(IRQ_CHCK_EN) 594#define IRQ_CHCK_DIS_A ADDR(IRQ_CHCK_DIS) 595 596#define GET_PAGE(bank) outpw(PAGE_RG_A,(inpw(PAGE_RG_A) &\ 597 (~POS_PAGE)) |(int) (bank)) 598#define VPP_ON() if (smc->hw.rev == FM1_REV) { \ 599 outpw(PAGE_RG_A, \ 600 (inpw(PAGE_RG_A) & POS_PAGE) | PROG_EN); \ 601 } 602#define VPP_OFF() if (smc->hw.rev == FM1_REV) { \ 603 outpw(PAGE_RG_A,(inpw(PAGE_RG_A) & POS_PAGE)); \ 604 } 605 606#define SKFDDI_PSZ 16 /* address PROM size */ 607 608#define READ_PROM(a) ((u_char)inp(a)) 609 610#define GET_ISR() ~inpw(ISR1_A) 611#ifndef TCI 612#define CHECK_ISR() ~inpw(ISR1_A) 613#define CHECK_ISR_SMP(iop) ~inpw((iop)+ISRA) 614#else 615#define CHECK_ISR() (~inpw(ISR1_A) | ~inpw(ISR2_A)) 616#define CHECK_ISR_SMP(iop) (~inpw((iop)+ISRA) | ~inpw((iop)+ISR2)) 617#endif 618 619#define DMA_BUSY() (inpw(CSF_A) & CSF_BUSY_DMA) 620#define FIFO_BUSY() (inpw(CSF_A) & CSF_BUSY_FIFO) 621#define DMA_FIFO_BUSY() (inpw(CSF_A) & (CSF_BUSY_DMA | CSF_BUSY_FIFO)) 622#define BUS_CHECK() { int i ; \ 623 if ((i = GET_ISR()) & IS_BUSERR) \ 624 SMT_PANIC(smc,HWM_E0020,HWM_E0020_MSG) ; \ 625 if (i & IS_CHCK_L) \ 626 SMT_PANIC(smc,HWM_E0014,HWM_E0014_MSG) ; \ 627 } 628 629#define CHECK_DMA() { u_long k = 10000 ; \ 630 while (k && (DMA_BUSY())) { \ 631 k-- ; \ 632 BUS_CHECK() ; \ 633 } \ 634 if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; } 635 636#define CHECK_FIFO() {u_long k = 1000000 ;\ 637 while (k && (FIFO_BUSY())) k-- ;\ 638 if (!k) SMT_PANIC(smc,HWM_E0019,HWM_E0019_MSG) ; } 639 640#define CHECK_DMA_FIFO() {u_long k = 1000000 ;\ 641 while (k && (DMA_FIFO_BUSY())) { \ 642 k-- ;\ 643 BUS_CHECK() ; \ 644 } \ 645 if (!k) SMT_PANIC(smc,HWM_E0004,HWM_E0004_MSG) ; } 646 647#ifndef UNIX 648#define CLI_FBI() outp(ADDR(IRQ_OTH_DIS),0) 649#else 650#define CLI_FBI(smc) outp(ADDRS((smc),IRQ_OTH_DIS),0) 651#endif 652 653#ifndef TCI 654#define CLI_FBI_SMP(iop) outp((iop)+IRQ_OTH_DIS,0) 655#else 656#define CLI_FBI_SMP(iop) outp((iop)+IRQ_OTH_DIS,0) ;\ 657 outp((iop)+IRQ_TC_DIS,0) 658#endif 659 660#ifndef UNIX 661#define STI_FBI() outp(ADDR(IRQ_OTH_EN),0) 662#else 663#define STI_FBI(smc) outp(ADDRS((smc),IRQ_OTH_EN),0) 664#endif 665 666/* 667 * Terminal count primitives 668 */ 669#define CLI_TCI(smc) outp(ADDRS((smc),IRQ_TC_DIS),0) 670#define STI_TCI(smc) outp(ADDRS((smc),IRQ_TC_EN),0) 671#define CHECK_TC(smc,k) {(k) = 10000 ;\ 672 while ((k) && (~inpw(ISR2_A) & IS_TC)) (k)-- ;\ 673 if (!k) SMT_PANIC(smc,HWM_E0018,HWM_E0018_MSG) ; } 674 675#endif /* MCA */ 676 677#ifdef ISA 678 679/* 680 * address transmission from logic NPADDR6-0 to physical offset address on board 681 */ 682#define FMA(a) (0x8000|(((a)&0x07)<<1)|(((a)&0x78)<<7)) /* FORMAC+ (r/w) */ 683#define PRA(a) (0x1000|(((a)&0x07)<<1)|(((a)&0x18)<<7)) /* PROM (read only)*/ 684#define P1A(a) (0x4000|(((a)&0x07)<<1)|(((a)&0x18)<<7)) /* PLC1 (r/w) */ 685#define P2A(a) (0x5000|(((a)&0x07)<<1)|(((a)&0x18)<<7)) /* PLC2 (r/w) */ 686#define TIA(a) (0x6000|(((a)&0x03)<<1)) /* Timer (r/w) */ 687 688#define ISRA 0x0000 /* int. source register address (read only) */ 689#define ACLA 0x0000 /* address counter low address (write only) */ 690#define ACHA 0x0002 /* address counter high address (write only) */ 691#define TRCA 0x0004 /* transfer counter address (write only) */ 692#define PGRA 0x0006 /* page register address (write only) */ 693#define RQAA 0x2000 /* Request reg. (write only) */ 694#define CSRA 0x3000 /* control/status register address (r/w) */ 695 696/* 697 * physical address offset + IO-Port base address 698 */ 699#define FM_A(a) (FMA(a)+smc->hw.iop) /* FORMAC Plus physical addr */ 700#define PR_A(a) (PRA(a)+smc->hw.iop) /* PROM (read only)*/ 701#define P1_A(a) (P1A(a)+smc->hw.iop) /* PLC1 (r/w) */ 702#define P2_A(a) (P2A(a)+smc->hw.iop) /* PLC2 (r/w) */ 703#define TI_A(a) (TIA(a)+smc->hw.iop) /* Timer (r/w) */ 704 705#define ISR_A (0x0000+smc->hw.iop) /* int. source register address (read only) */ 706#define ACL_A (0x0000+smc->hw.iop) /* address counter low address (write only) */ 707#define ACH_A (0x0002+smc->hw.iop) /* address counter high address (write only)*/ 708#define TRC_A (0x0004+smc->hw.iop) /* transfer counter address (write only) */ 709#define PGR_A (0x0006+smc->hw.iop) /* page register address (write only) */ 710#define RQA_A (0x2000+smc->hw.iop) /* Request reg. (write only) */ 711#define CSR_A (0x3000+smc->hw.iop) /* control/status register address (r/w) */ 712#ifdef UNIX 713#define CSR_AS(smc) (0x3000+(smc)->hw.iop) /* control/status register address */ 714#endif 715#define PLC1_I (0x3400+smc->hw.iop) /* clear PLC1 interrupt bit */ 716#define PLC2_I (0x3800+smc->hw.iop) /* clear PLC2 interrupt bit */ 717 718#ifndef MULT_OEM 719#ifndef OEM_CONCEPT 720#define SKLOGO_STR "SKFDDI" 721#else /* OEM_CONCEPT */ 722#define SKLOGO_STR OEM_FDDI_LOGO 723#endif /* OEM_CONCEPT */ 724#endif /* MULT_OEM */ 725#define SADDRL (24) /* start address SKLOGO */ 726#define SA_MAC (0) /* start addr. MAC_AD within the PROM */ 727#define PRA_OFF (0) 728#define SA_PMD_TYPE (8) /* start addr. PMD-Type */ 729 730#define CDID (PRA(SADDRL)) /* Card ID int/O port addr. offset */ 731#define NEXT_CDID ((PRA(SADDRL+1)) - CDID) 732 733#define SKFDDI_PSZ 32 /* address PROM size */ 734 735#define READ_PROM(a) ((u_char)inpw(a)) 736#define GET_PAGE(i) outpw(PGR_A,(int)(i)) 737 738#define MAX_PAGES 16 /* 16 pages */ 739#define MAX_FADDR 0x2000 /* 8K per page */ 740#define VPP_OFF() outpw(CSR_A,(inpw(CSR_A) & (CS_CRESET|CS_BYPASS))) 741#define VPP_ON() outpw(CSR_A,(inpw(CSR_A) & (CS_CRESET|CS_BYPASS)) | \ 742 CS_VPPSW) 743 744/* 745 * control/status register CSRA bits (log. addr: 0x3000) 746 */ 747/* write */ 748#define CS_CRESET 0x01 /* Card reset (0=reset) */ 749#define CS_IMSK 0x02 /* enable IRQ (1=enable, 0=disable) */ 750#define CS_RESINT1 0x04 /* PLINT1 reset */ 751#define CS_VPPSW 0x10 /* 12V power switch (0=off, 1=on) */ 752#define CS_BYPASS 0x20 /* bypass switch (0=remove, 1=insert)*/ 753#define CS_RESINT2 0x40 /* PLINT2 reset */ 754/* read */ 755#define CS_BUSY 0x04 /* master transfer activ (=1) */ 756#define CS_SW_EPROM 0x08 /* 0=Application Soft. 1=BOOT-EPROM */ 757#define CS_BYSTAT 0x40 /* 0=Bypass exist, 1= ..not */ 758#define CS_SAS 0x80 /* single attachement station (=1) */ 759 760/* 761 * Interrupt source register ISRA (log. addr: 0x0000) read only & low activ. 762 */ 763#define IS_MINTR1 0x01 /* FORMAC ST1U/L && ~IMSK1U/L*/ 764#define IS_MINTR2 0x02 /* FORMAC ST2U/L && ~IMSK2U/L*/ 765#define IS_PLINT1 0x04 /* PLC1 */ 766#define IS_PLINT2 0x08 /* PLC2 */ 767#define IS_TIMINT 0x10 /* Timer 82C54-2 */ 768 769#define ALL_IRSR (IS_MINTR1|IS_MINTR2|IS_PLINT1|IS_PLINT2|IS_TIMINT) 770 771#define FPROM_SW() (inpw(CSR_A)&CS_SW_EPROM) 772#define DMA_BUSY() (inpw(CSR_A)&CS_BUSY) 773#define CHECK_FIFO() 774#define BUS_CHECK() 775 776/* 777 * set Host Request register (wr.) 778 */ 779#define SET_HRQ(qup) outpw(RQA_A+((qup)<<1),0) 780 781#ifndef UNIX 782#ifndef WINNT 783#define CLI_FBI() outpw(CSR_A,(inpw(CSR_A)&(CS_CRESET|CS_BYPASS|CS_VPPSW))) 784#else 785#define CLI_FBI() outpw(CSR_A,(l_inpw(CSR_A) & \ 786 (CS_CRESET|CS_BYPASS|CS_VPPSW))) 787#endif 788#else 789#define CLI_FBI(smc) outpw(CSR_AS(smc),(inpw(CSR_AS(smc))& \ 790 (CS_CRESET|CS_BYPASS|CS_VPPSW))) 791#endif 792 793#ifndef UNIX 794#define STI_FBI() outpw(CSR_A,(inpw(CSR_A) & \ 795 (CS_CRESET|CS_BYPASS|CS_VPPSW)) | CS_IMSK) 796#else 797#define STI_FBI(smc) outpw(CSR_AS(smc),(inpw(CSR_AS(smc)) & \ 798 (CS_CRESET|CS_BYPASS|CS_VPPSW)) | CS_IMSK) 799#endif 800 801#define CHECK_DMA() {unsigned k = 10000 ;\ 802 while (k && (DMA_BUSY())) k-- ;\ 803 if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; } 804 805#define GET_ISR() ~inpw(ISR_A) 806 807#endif /* ISA */ 808 809/*--------------------------------------------------------------------------*/ 810#ifdef PCI 811 812/* 813 * (DV) = only defined for Da Vinci 814 * (ML) = only defined for Monalisa 815 */ 816 817/* 818 * Configuration Space header 819 */ 820#define PCI_VENDOR_ID 0x00 /* 16 bit Vendor ID */ 821#define PCI_DEVICE_ID 0x02 /* 16 bit Device ID */ 822#define PCI_COMMAND 0x04 /* 16 bit Command */ 823#define PCI_STATUS 0x06 /* 16 bit Status */ 824#define PCI_REV_ID 0x08 /* 8 bit Revision ID */ 825#define PCI_CLASS_CODE 0x09 /* 24 bit Class Code */ 826#define PCI_CACHE_LSZ 0x0c /* 8 bit Cache Line Size */ 827#define PCI_LAT_TIM 0x0d /* 8 bit Latency Timer */ 828#define PCI_HEADER_T 0x0e /* 8 bit Header Type */ 829#define PCI_BIST 0x0f /* 8 bit Built-in selftest */ 830#define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */ 831#define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */ 832/* Byte 18..2b: Reserved */ 833#define PCI_SUB_VID 0x2c /* 16 bit Subsystem Vendor ID */ 834#define PCI_SUB_ID 0x2e /* 16 bit Subsystem ID */ 835#define PCI_BASE_ROM 0x30 /* 32 bit Expansion ROM Base Address */ 836/* Byte 34..33: Reserved */ 837#define PCI_CAP_PTR 0x34 /* 8 bit (ML) Capabilities Ptr */ 838/* Byte 35..3b: Reserved */ 839#define PCI_IRQ_LINE 0x3c /* 8 bit Interrupt Line */ 840#define PCI_IRQ_PIN 0x3d /* 8 bit Interrupt Pin */ 841#define PCI_MIN_GNT 0x3e /* 8 bit Min_Gnt */ 842#define PCI_MAX_LAT 0x3f /* 8 bit Max_Lat */ 843/* Device Dependent Region */ 844#define PCI_OUR_REG 0x40 /* 32 bit (DV) Our Register */ 845#define PCI_OUR_REG_1 0x40 /* 32 bit (ML) Our Register 1 */ 846#define PCI_OUR_REG_2 0x44 /* 32 bit (ML) Our Register 2 */ 847/* Power Management Region */ 848#define PCI_PM_CAP_ID 0x48 /* 8 bit (ML) Power Management Cap. ID */ 849#define PCI_PM_NITEM 0x49 /* 8 bit (ML) Next Item Ptr */ 850#define PCI_PM_CAP_REG 0x4a /* 16 bit (ML) Power Management Capabilities */ 851#define PCI_PM_CTL_STS 0x4c /* 16 bit (ML) Power Manag. Control/Status */ 852/* Byte 0x4e: Reserved */ 853#define PCI_PM_DAT_REG 0x4f /* 8 bit (ML) Power Manag. Data Register */ 854/* VPD Region */ 855#define PCI_VPD_CAP_ID 0x50 /* 8 bit (ML) VPD Cap. ID */ 856#define PCI_VPD_NITEM 0x51 /* 8 bit (ML) Next Item Ptr */ 857#define PCI_VPD_ADR_REG 0x52 /* 16 bit (ML) VPD Address Register */ 858#define PCI_VPD_DAT_REG 0x54 /* 32 bit (ML) VPD Data Register */ 859/* Byte 58..ff: Reserved */ 860 861/* 862 * I2C Address (PCI Config) 863 * 864 * Note: The temperature and voltage sensors are relocated on a different 865 * I2C bus. 866 */ 867#define I2C_ADDR_VPD 0xA0 /* I2C address for the VPD EEPROM */ 868 869/* 870 * Define Bits and Values of the registers 871 */ 872/* PCI_VENDOR_ID 16 bit Vendor ID */ 873/* PCI_DEVICE_ID 16 bit Device ID */ 874/* Values for Vendor ID and Device ID shall be patched into the code */ 875/* PCI_COMMAND 16 bit Command */ 876#define PCI_FBTEN 0x0200 /* Bit 9: Fast Back-To-Back enable */ 877#define PCI_SERREN 0x0100 /* Bit 8: SERR enable */ 878#define PCI_ADSTEP 0x0080 /* Bit 7: Address Stepping */ 879#define PCI_PERREN 0x0040 /* Bit 6: Parity Report Response enable */ 880#define PCI_VGA_SNOOP 0x0020 /* Bit 5: VGA palette snoop */ 881#define PCI_MWIEN 0x0010 /* Bit 4: Memory write an inv cycl ena */ 882#define PCI_SCYCEN 0x0008 /* Bit 3: Special Cycle enable */ 883#define PCI_BMEN 0x0004 /* Bit 2: Bus Master enable */ 884#define PCI_MEMEN 0x0002 /* Bit 1: Memory Space Access enable */ 885#define PCI_IOEN 0x0001 /* Bit 0: IO Space Access enable */ 886 887/* PCI_STATUS 16 bit Status */ 888#define PCI_PERR 0x8000 /* Bit 15: Parity Error */ 889#define PCI_SERR 0x4000 /* Bit 14: Signaled SERR */ 890#define PCI_RMABORT 0x2000 /* Bit 13: Received Master Abort */ 891#define PCI_RTABORT 0x1000 /* Bit 12: Received Target Abort */ 892#define PCI_STABORT 0x0800 /* Bit 11: Sent Target Abort */ 893#define PCI_DEVSEL 0x0600 /* Bit 10..9: DEVSEL Timing */ 894#define PCI_DEV_FAST (0<<9) /* fast */ 895#define PCI_DEV_MEDIUM (1<<9) /* medium */ 896#define PCI_DEV_SLOW (2<<9) /* slow */ 897#define PCI_DATAPERR 0x0100 /* Bit 8: DATA Parity error detected */ 898#define PCI_FB2BCAP 0x0080 /* Bit 7: Fast Back-to-Back Capability */ 899#define PCI_UDF 0x0040 /* Bit 6: User Defined Features */ 900#define PCI_66MHZCAP 0x0020 /* Bit 5: 66 MHz PCI bus clock capable */ 901#define PCI_NEWCAP 0x0010 /* Bit 4: New cap. list implemented */ 902 903#define PCI_ERRBITS (PCI_PERR|PCI_SERR|PCI_RMABORT|PCI_STABORT|PCI_DATAPERR) 904 905/* PCI_REV_ID 8 bit Revision ID */ 906/* PCI_CLASS_CODE 24 bit Class Code */ 907/* Byte 2: Base Class (02) */ 908/* Byte 1: SubClass (02) */ 909/* Byte 0: Programming Interface (00) */ 910 911/* PCI_CACHE_LSZ 8 bit Cache Line Size */ 912/* Possible values: 0,2,4,8,16 */ 913 914/* PCI_LAT_TIM 8 bit Latency Timer */ 915 916/* PCI_HEADER_T 8 bit Header Type */ 917#define PCI_HD_MF_DEV 0x80 /* Bit 7: 0= single, 1= multi-func dev */ 918#define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout 0= normal */ 919 920/* PCI_BIST 8 bit Built-in selftest */ 921#define PCI_BIST_CAP 0x80 /* Bit 7: BIST Capable */ 922#define PCI_BIST_ST 0x40 /* Bit 6: Start BIST */ 923#define PCI_BIST_RET 0x0f /* Bit 3..0: Completion Code */ 924 925/* PCI_BASE_1ST 32 bit 1st Base address */ 926#define PCI_MEMSIZE 0x800L /* use 2 kB Memory Base */ 927#define PCI_MEMBASE_BITS 0xfffff800L /* Bit 31..11: Memory Base Address */ 928#define PCI_MEMSIZE_BIIS 0x000007f0L /* Bit 10..4: Memory Size Req. */ 929#define PCI_PREFEN 0x00000008L /* Bit 3: Prefetchable */ 930#define PCI_MEM_TYP 0x00000006L /* Bit 2..1: Memory Type */ 931#define PCI_MEM32BIT (0<<1) /* Base addr anywhere in 32 Bit range */ 932#define PCI_MEM1M (1<<1) /* Base addr below 1 MegaByte */ 933#define PCI_MEM64BIT (2<<1) /* Base addr anywhere in 64 Bit range */ 934#define PCI_MEMSPACE 0x00000001L /* Bit 0: Memory Space Indic. */ 935 936/* PCI_BASE_2ND 32 bit 2nd Base address */ 937#define PCI_IOBASE 0xffffff00L /* Bit 31..8: I/O Base address */ 938#define PCI_IOSIZE 0x000000fcL /* Bit 7..2: I/O Size Requirements */ 939#define PCI_IOSPACE 0x00000001L /* Bit 0: I/O Space Indicator */ 940 941/* PCI_SUB_VID 16 bit Subsystem Vendor ID */ 942/* PCI_SUB_ID 16 bit Subsystem ID */ 943 944/* PCI_BASE_ROM 32 bit Expansion ROM Base Address */ 945#define PCI_ROMBASE 0xfffe0000L /* Bit 31..17: ROM BASE address (1st) */ 946#define PCI_ROMBASZ 0x0001c000L /* Bit 16..14: Treat as BASE or SIZE */ 947#define PCI_ROMSIZE 0x00003800L /* Bit 13..11: ROM Size Requirements */ 948#define PCI_ROMEN 0x00000001L /* Bit 0: Address Decode enable */ 949 950/* PCI_CAP_PTR 8 bit New Capabilities Pointers */ 951/* PCI_IRQ_LINE 8 bit Interrupt Line */ 952/* PCI_IRQ_PIN 8 bit Interrupt Pin */ 953/* PCI_MIN_GNT 8 bit Min_Gnt */ 954/* PCI_MAX_LAT 8 bit Max_Lat */ 955/* Device Dependent Region */ 956/* PCI_OUR_REG (DV) 32 bit Our Register */ 957/* PCI_OUR_REG_1 (ML) 32 bit Our Register 1 */ 958 /* Bit 31..29: reserved */ 959#define PCI_PATCH_DIR (3L<<27) /*(DV) Bit 28..27: Ext Patchs direction */ 960#define PCI_PATCH_DIR_0 (1L<<27) /*(DV) Type of the pins EXT_PATCHS<1..0> */ 961#define PCI_PATCH_DIR_1 (1L<<28) /* 0 = input */ 962 /* 1 = output */ 963#define PCI_EXT_PATCHS (3L<<25) /*(DV) Bit 26..25: Extended Patches */ 964#define PCI_EXT_PATCH_0 (1L<<25) /*(DV) */ 965#define PCI_EXT_PATCH_1 (1L<<26) /* CLK for MicroWire (ML) */ 966#define PCI_VIO (1L<<25) /*(ML) */ 967#define PCI_EN_BOOT (1L<<24) /* Bit 24: Enable BOOT via ROM */ 968 /* 1 = Don't boot with ROM */ 969 /* 0 = Boot with ROM */ 970#define PCI_EN_IO (1L<<23) /* Bit 23: Mapping to IO space */ 971#define PCI_EN_FPROM (1L<<22) /* Bit 22: FLASH mapped to mem? */ 972 /* 1 = Map Flash to Memory */ 973 /* 0 = Disable all addr. decoding */ 974#define PCI_PAGESIZE (3L<<20) /* Bit 21..20: FLASH Page Size */ 975#define PCI_PAGE_16 (0L<<20) /* 16 k pages */ 976#define PCI_PAGE_32K (1L<<20) /* 32 k pages */ 977#define PCI_PAGE_64K (2L<<20) /* 64 k pages */ 978#define PCI_PAGE_128K (3L<<20) /* 128 k pages */ 979 /* Bit 19: reserved (ML) and (DV) */ 980#define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */ 981 /* Bit 15: reserved */ 982#define PCI_FORCE_BE (1L<<14) /* Bit 14: Assert all BEs on MR */ 983#define PCI_DIS_MRL (1L<<13) /* Bit 13: Disable Mem R Line */ 984#define PCI_DIS_MRM (1L<<12) /* Bit 12: Disable Mem R multip */ 985#define PCI_DIS_MWI (1L<<11) /* Bit 11: Disable Mem W & inv */ 986#define PCI_DISC_CLS (1L<<10) /* Bit 10: Disc: cacheLsz bound */ 987#define PCI_BURST_DIS (1L<<9) /* Bit 9: Burst Disable */ 988#define PCI_BYTE_SWAP (1L<<8) /*(DV) Bit 8: Byte Swap in DATA */ 989#define PCI_SKEW_DAS (0xfL<<4) /* Bit 7..4: Skew Ctrl, DAS Ext */ 990#define PCI_SKEW_BASE (0xfL<<0) /* Bit 3..0: Skew Ctrl, Base */ 991 992/* PCI_OUR_REG_2 (ML) 32 bit Our Register 2 (Monalisa only) */ 993#define PCI_VPD_WR_TH (0xffL<<24) /* Bit 24..31 VPD Write Threshold */ 994#define PCI_DEV_SEL (0x7fL<<17) /* Bit 17..23 EEPROM Device Select */ 995#define PCI_VPD_ROM_SZ (7L<<14) /* Bit 14..16 VPD ROM Size */ 996 /* Bit 12..13 reserved */ 997#define PCI_PATCH_DIR2 (0xfL<<8) /* Bit 8..11 Ext Patchs dir 2..5 */ 998#define PCI_PATCH_DIR_2 (1L<<8) /* Bit 8 CS for MicroWire */ 999#define PCI_PATCH_DIR_3 (1L<<9) 1000#define PCI_PATCH_DIR_4 (1L<<10)
1001#define PCI_PATCH_DIR_5 (1L<<11) 1002#define PCI_EXT_PATCHS2 (0xfL<<4) /* Bit 4..7 Extended Patches */ 1003#define PCI_EXT_PATCH_2 (1L<<4) /* Bit 4 CS for MicroWire */ 1004#define PCI_EXT_PATCH_3 (1L<<5) 1005#define PCI_EXT_PATCH_4 (1L<<6) 1006#define PCI_EXT_PATCH_5 (1L<<7) 1007#define PCI_EN_DUMMY_RD (1L<<3) /* Bit 3 Enable Dummy Read */ 1008#define PCI_REV_DESC (1L<<2) /* Bit 2 Reverse Desc. Bytes */ 1009#define PCI_USEADDR64 (1L<<1) /* Bit 1 Use 64 Bit Addresse */ 1010#define PCI_USEDATA64 (1L<<0) /* Bit 0 Use 64 Bit Data bus ext*/ 1011 1012/* Power Management Region */ 1013/* PCI_PM_CAP_ID 8 bit (ML) Power Management Cap. ID */ 1014/* PCI_PM_NITEM 8 bit (ML) Next Item Ptr */ 1015/* PCI_PM_CAP_REG 16 bit (ML) Power Management Capabilities*/ 1016#define PCI_PME_SUP (0x1f<<11) /* Bit 11..15 PM Manag. Event Support*/ 1017#define PCI_PM_D2_SUB (1<<10) /* Bit 10 D2 Support Bit */ 1018#define PCI_PM_D1_SUB (1<<9) /* Bit 9 D1 Support Bit */ 1019 /* Bit 6..8 reserved */ 1020#define PCI_PM_DSI (1<<5) /* Bit 5 Device Specific Init.*/ 1021#define PCI_PM_APS (1<<4) /* Bit 4 Auxialiary Power Src */ 1022#define PCI_PME_CLOCK (1<<3) /* Bit 3 PM Event Clock */ 1023#define PCI_PM_VER (7<<0) /* Bit 0..2 PM PCI Spec. version */ 1024 1025/* PCI_PM_CTL_STS 16 bit (ML) Power Manag. Control/Status */ 1026#define PCI_PME_STATUS (1<<15) /* Bit 15 PFA doesn't sup. PME#*/ 1027#define PCI_PM_DAT_SCL (3<<13) /* Bit 13..14 dat reg Scaling factor */ 1028#define PCI_PM_DAT_SEL (0xf<<9) /* Bit 9..12 PM data selector field */ 1029 /* Bit 7.. 2 reserved */ 1030#define PCI_PM_STATE (3<<0) /* Bit 0.. 1 Power Management State */ 1031#define PCI_PM_STATE_D0 (0<<0) /* D0: Operational (default) */ 1032#define PCI_PM_STATE_D1 (1<<0) /* D1: not supported */ 1033#define PCI_PM_STATE_D2 (2<<0) /* D2: not supported */ 1034#define PCI_PM_STATE_D3 (3<<0) /* D3: HOT, Power Down and Reset */ 1035 1036/* PCI_PM_DAT_REG 8 bit (ML) Power Manag. Data Register */ 1037/* VPD Region */ 1038/* PCI_VPD_CAP_ID 8 bit (ML) VPD Cap. ID */ 1039/* PCI_VPD_NITEM 8 bit (ML) Next Item Ptr */ 1040/* PCI_VPD_ADR_REG 16 bit (ML) VPD Address Register */ 1041#define PCI_VPD_FLAG (1<<15) /* Bit 15 starts VPD rd/wd cycle*/ 1042 1043/* PCI_VPD_DAT_REG 32 bit (ML) VPD Data Register */ 1044 1045/* 1046 * Control Register File: 1047 * Bank 0 1048 */ 1049#define B0_RAP 0x0000 /* 8 bit register address port */ 1050 /* 0x0001 - 0x0003: reserved */ 1051#define B0_CTRL 0x0004 /* 8 bit control register */ 1052#define B0_DAS 0x0005 /* 8 Bit control register (DAS) */ 1053#define B0_LED 0x0006 /* 8 Bit LED register */ 1054#define B0_TST_CTRL 0x0007 /* 8 bit test control register */ 1055#define B0_ISRC 0x0008 /* 32 bit Interrupt source register */ 1056#define B0_IMSK 0x000c /* 32 bit Interrupt mask register */ 1057 1058/* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */ 1059#define B0_CMDREG1 0x0010 /* write command reg 1 instruction */ 1060#define B0_CMDREG2 0x0014 /* write command reg 2 instruction */ 1061#define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */ 1062#define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */ 1063#define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */ 1064#define B0_ST2L 0x001c /* read lower 16-bit of status reg 2 */ 1065 1066#define B0_MARR 0x0020 /* r/w the memory read addr register */ 1067#define B0_MARW 0x0024 /* r/w the memory write addr register*/ 1068#define B0_MDRU 0x0028 /* r/w upper 16-bit of mem. data reg */ 1069#define B0_MDRL 0x002c /* r/w lower 16-bit of mem. data reg */ 1070 1071#define B0_MDREG3 0x0030 /* r/w Mode Register 3 */ 1072#define B0_ST3U 0x0034 /* read upper 16-bit of status reg 3 */ 1073#define B0_ST3L 0x0038 /* read lower 16-bit of status reg 3 */ 1074#define B0_IMSK3U 0x003c /* r/w upper 16-bit of IMSK reg 3 */ 1075#define B0_IMSK3L 0x0040 /* r/w lower 16-bit of IMSK reg 3 */ 1076#define B0_IVR 0x0044 /* read Interrupt Vector register */ 1077#define B0_IMR 0x0048 /* r/w Interrupt mask register */ 1078/* 0x4c Hidden */ 1079 1080#define B0_CNTRL_A 0x0050 /* control register A (r/w) */ 1081#define B0_CNTRL_B 0x0054 /* control register B (r/w) */ 1082#define B0_INTR_MASK 0x0058 /* interrupt mask (r/w) */ 1083#define B0_XMIT_VECTOR 0x005c /* transmit vector register (r/w) */ 1084 1085#define B0_STATUS_A 0x0060 /* status register A (read only) */ 1086#define B0_STATUS_B 0x0064 /* status register B (read only) */ 1087#define B0_CNTRL_C 0x0068 /* control register C (r/w) */ 1088#define B0_MDREG1 0x006c /* r/w Mode Register 1 */ 1089 1090#define B0_R1_CSR 0x0070 /* 32 bit BMU control/status reg (rec q 1) */ 1091#define B0_R2_CSR 0x0074 /* 32 bit BMU control/status reg (rec q 2)(DV)*/ 1092#define B0_XA_CSR 0x0078 /* 32 bit BMU control/status reg (a xmit q) */ 1093#define B0_XS_CSR 0x007c /* 32 bit BMU control/status reg (s xmit q) */ 1094 1095/* 1096 * Bank 1 1097 * - completely empty (this is the RAP Block window) 1098 * Note: if RAP = 1 this page is reserved 1099 */ 1100 1101/* 1102 * Bank 2 1103 */ 1104#define B2_MAC_0 0x0100 /* 8 bit MAC address Byte 0 */ 1105#define B2_MAC_1 0x0101 /* 8 bit MAC address Byte 1 */ 1106#define B2_MAC_2 0x0102 /* 8 bit MAC address Byte 2 */ 1107#define B2_MAC_3 0x0103 /* 8 bit MAC address Byte 3 */ 1108#define B2_MAC_4 0x0104 /* 8 bit MAC address Byte 4 */ 1109#define B2_MAC_5 0x0105 /* 8 bit MAC address Byte 5 */ 1110#define B2_MAC_6 0x0106 /* 8 bit MAC address Byte 6 (== 0) (DV) */ 1111#define B2_MAC_7 0x0107 /* 8 bit MAC address Byte 7 (== 0) (DV) */ 1112 1113#define B2_CONN_TYP 0x0108 /* 8 bit Connector type */ 1114#define B2_PMD_TYP 0x0109 /* 8 bit PMD type */ 1115 /* 0x010a - 0x010b: reserved */ 1116 /* Eprom registers are currently of no use */ 1117#define B2_E_0 0x010c /* 8 bit EPROM Byte 0 */ 1118#define B2_E_1 0x010d /* 8 bit EPROM Byte 1 */ 1119#define B2_E_2 0x010e /* 8 bit EPROM Byte 2 */ 1120#define B2_E_3 0x010f /* 8 bit EPROM Byte 3 */ 1121#define B2_FAR 0x0110 /* 32 bit Flash-Prom Address Register/Counter */ 1122#define B2_FDP 0x0114 /* 8 bit Flash-Prom Data Port */ 1123 /* 0x0115 - 0x0117: reserved */ 1124#define B2_LD_CRTL 0x0118 /* 8 bit loader control */ 1125#define B2_LD_TEST 0x0119 /* 8 bit loader test */ 1126 /* 0x011a - 0x011f: reserved */ 1127#define B2_TI_INI 0x0120 /* 32 bit Timer init value */ 1128#define B2_TI_VAL 0x0124 /* 32 bit Timer value */ 1129#define B2_TI_CRTL 0x0128 /* 8 bit Timer control */ 1130#define B2_TI_TEST 0x0129 /* 8 Bit Timer Test */ 1131 /* 0x012a - 0x012f: reserved */ 1132#define B2_WDOG_INI 0x0130 /* 32 bit Watchdog init value */ 1133#define B2_WDOG_VAL 0x0134 /* 32 bit Watchdog value */ 1134#define B2_WDOG_CRTL 0x0138 /* 8 bit Watchdog control */ 1135#define B2_WDOG_TEST 0x0139 /* 8 Bit Watchdog Test */ 1136 /* 0x013a - 0x013f: reserved */ 1137#define B2_RTM_INI 0x0140 /* 32 bit RTM init value */ 1138#define B2_RTM_VAL 0x0144 /* 32 bit RTM value */ 1139#define B2_RTM_CRTL 0x0148 /* 8 bit RTM control */ 1140#define B2_RTM_TEST 0x0149 /* 8 Bit RTM Test */ 1141 1142#define B2_TOK_COUNT 0x014c /* (ML) 32 bit Token Counter */ 1143#define B2_DESC_ADDR_H 0x0150 /* (ML) 32 bit Desciptor Base Addr Reg High */ 1144#define B2_CTRL_2 0x0154 /* (ML) 8 bit Control Register 2 */ 1145#define B2_IFACE_REG 0x0155 /* (ML) 8 bit Interface Register */ 1146 /* 0x0156: reserved */ 1147#define B2_TST_CTRL_2 0x0157 /* (ML) 8 bit Test Control Register 2 */ 1148#define B2_I2C_CTRL 0x0158 /* (ML) 32 bit I2C Control Register */ 1149#define B2_I2C_DATA 0x015c /* (ML) 32 bit I2C Data Register */ 1150 1151#define B2_IRQ_MOD_INI 0x0160 /* (ML) 32 bit IRQ Moderation Timer Init Reg. */ 1152#define B2_IRQ_MOD_VAL 0x0164 /* (ML) 32 bit IRQ Moderation Timer Value */ 1153#define B2_IRQ_MOD_CTRL 0x0168 /* (ML) 8 bit IRQ Moderation Timer Control */ 1154#define B2_IRQ_MOD_TEST 0x0169 /* (ML) 8 bit IRQ Moderation Timer Test */ 1155 /* 0x016a - 0x017f: reserved */ 1156 1157/* 1158 * Bank 3 1159 */ 1160/* 1161 * This is a copy of the Configuration register file (lower half) 1162 */ 1163#define B3_CFG_SPC 0x180 1164 1165/* 1166 * Bank 4 1167 */ 1168#define B4_R1_D 0x0200 /* 4*32 bit current receive Descriptor */ 1169#define B4_R1_DA 0x0210 /* 32 bit current rec desc address */ 1170#define B4_R1_AC 0x0214 /* 32 bit current receive Address Count */ 1171#define B4_R1_BC 0x0218 /* 32 bit current receive Byte Counter */ 1172#define B4_R1_CSR 0x021c /* 32 bit BMU Control/Status Register */ 1173#define B4_R1_F 0x0220 /* 32 bit flag register */ 1174#define B4_R1_T1 0x0224 /* 32 bit Test Register 1 */ 1175#define B4_R1_T1_TR 0x0224 /* 8 bit Test Register 1 TR */ 1176#define B4_R1_T1_WR 0x0225 /* 8 bit Test Register 1 WR */ 1177#define B4_R1_T1_RD 0x0226 /* 8 bit Test Register 1 RD */ 1178#define B4_R1_T1_SV 0x0227 /* 8 bit Test Register 1 SV */ 1179#define B4_R1_T2 0x0228 /* 32 bit Test Register 2 */ 1180#define B4_R1_T3 0x022c /* 32 bit Test Register 3 */ 1181#define B4_R1_DA_H 0x0230 /* (ML) 32 bit Curr Rx Desc Address High */ 1182#define B4_R1_AC_H 0x0234 /* (ML) 32 bit Curr Addr Counter High dword */ 1183 /* 0x0238 - 0x023f: reserved */ 1184 /* Receive queue 2 is removed on Monalisa */ 1185#define B4_R2_D 0x0240 /* 4*32 bit current receive Descriptor (q2) */ 1186#define B4_R2_DA 0x0250 /* 32 bit current rec desc address (q2) */ 1187#define B4_R2_AC 0x0254 /* 32 bit current receive Address Count (q2) */ 1188#define B4_R2_BC 0x0258 /* 32 bit current receive Byte Counter (q2) */ 1189#define B4_R2_CSR 0x025c /* 32 bit BMU Control/Status Register (q2) */ 1190#define B4_R2_F 0x0260 /* 32 bit flag register (q2) */ 1191#define B4_R2_T1 0x0264 /* 32 bit Test Register 1 (q2) */ 1192#define B4_R2_T1_TR 0x0264 /* 8 bit Test Register 1 TR (q2) */ 1193#define B4_R2_T1_WR 0x0265 /* 8 bit Test Register 1 WR (q2) */ 1194#define B4_R2_T1_RD 0x0266 /* 8 bit Test Register 1 RD (q2) */ 1195#define B4_R2_T1_SV 0x0267 /* 8 bit Test Register 1 SV (q2) */ 1196#define B4_R2_T2 0x0268 /* 32 bit Test Register 2 (q2) */ 1197#define B4_R2_T3 0x026c /* 32 bit Test Register 3 (q2) */ 1198 /* 0x0270 - 0x027c: reserved */ 1199 1200/* 1201 * Bank 5 1202 */ 1203#define B5_XA_D 0x0280 /* 4*32 bit current transmit Descriptor (xa) */ 1204#define B5_XA_DA 0x0290 /* 32 bit current tx desc address (xa) */ 1205#define B5_XA_AC 0x0294 /* 32 bit current tx Address Count (xa) */ 1206#define B5_XA_BC 0x0298 /* 32 bit current tx Byte Counter (xa) */ 1207#define B5_XA_CSR 0x029c /* 32 bit BMU Control/Status Register (xa) */ 1208#define B5_XA_F 0x02a0 /* 32 bit flag register (xa) */ 1209#define B5_XA_T1 0x02a4 /* 32 bit Test Register 1 (xa) */ 1210#define B5_XA_T1_TR 0x02a4 /* 8 bit Test Register 1 TR (xa) */ 1211#define B5_XA_T1_WR 0x02a5 /* 8 bit Test Register 1 WR (xa) */ 1212#define B5_XA_T1_RD 0x02a6 /* 8 bit Test Register 1 RD (xa) */ 1213#define B5_XA_T1_SV 0x02a7 /* 8 bit Test Register 1 SV (xa) */ 1214#define B5_XA_T2 0x02a8 /* 32 bit Test Register 2 (xa) */ 1215#define B5_XA_T3 0x02ac /* 32 bit Test Register 3 (xa) */ 1216#define B5_XA_DA_H 0x02b0 /* (ML) 32 bit Curr Tx Desc Address High */ 1217#define B5_XA_AC_H 0x02b4 /* (ML) 32 bit Curr Addr Counter High dword */ 1218 /* 0x02b8 - 0x02bc: reserved */ 1219#define B5_XS_D 0x02c0 /* 4*32 bit current transmit Descriptor (xs) */ 1220#define B5_XS_DA 0x02d0 /* 32 bit current tx desc address (xs) */ 1221#define B5_XS_AC 0x02d4 /* 32 bit current transmit Address Count(xs) */ 1222#define B5_XS_BC 0x02d8 /* 32 bit current transmit Byte Counter (xs) */ 1223#define B5_XS_CSR 0x02dc /* 32 bit BMU Control/Status Register (xs) */ 1224#define B5_XS_F 0x02e0 /* 32 bit flag register (xs) */ 1225#define B5_XS_T1 0x02e4 /* 32 bit Test Register 1 (xs) */ 1226#define B5_XS_T1_TR 0x02e4 /* 8 bit Test Register 1 TR (xs) */ 1227#define B5_XS_T1_WR 0x02e5 /* 8 bit Test Register 1 WR (xs) */ 1228#define B5_XS_T1_RD 0x02e6 /* 8 bit Test Register 1 RD (xs) */ 1229#define B5_XS_T1_SV 0x02e7 /* 8 bit Test Register 1 SV (xs) */ 1230#define B5_XS_T2 0x02e8 /* 32 bit Test Register 2 (xs) */ 1231#define B5_XS_T3 0x02ec /* 32 bit Test Register 3 (xs) */ 1232#define B5_XS_DA_H 0x02f0 /* (ML) 32 bit Curr Tx Desc Address High */ 1233#define B5_XS_AC_H 0x02f4 /* (ML) 32 bit Curr Addr Counter High dword */ 1234 /* 0x02f8 - 0x02fc: reserved */ 1235 1236/* 1237 * Bank 6 1238 */ 1239/* External PLC-S registers (SN2 compatibility for DV) */ 1240/* External registers (ML) */ 1241#define B6_EXT_REG 0x300 1242 1243/* 1244 * Bank 7 1245 */ 1246/* DAS PLC-S Registers */ 1247 1248/* 1249 * Bank 8 - 15 1250 */ 1251/* IFCP registers */ 1252 1253/*---------------------------------------------------------------------------*/ 1254/* Definitions of the Bits in the registers */ 1255 1256/* B0_RAP 16 bit register address port */ 1257#define RAP_RAP 0x0f /* Bit 3..0: 0 = block0, .., f = block15 */ 1258 1259/* B0_CTRL 8 bit control register */ 1260#define CTRL_FDDI_CLR (1<<7) /* Bit 7: (ML) Clear FDDI Reset */ 1261#define CTRL_FDDI_SET (1<<6) /* Bit 6: (ML) Set FDDI Reset */ 1262#define CTRL_HPI_CLR (1<<5) /* Bit 5: Clear HPI SM reset */ 1263#define CTRL_HPI_SET (1<<4) /* Bit 4: Set HPI SM reset */ 1264#define CTRL_MRST_CLR (1<<3) /* Bit 3: Clear Master reset */ 1265#define CTRL_MRST_SET (1<<2) /* Bit 2: Set Master reset */ 1266#define CTRL_RST_CLR (1<<1) /* Bit 1: Clear Software reset */ 1267#define CTRL_RST_SET (1<<0) /* Bit 0: Set Software reset */ 1268 1269/* B0_DAS 8 Bit control register (DAS) */ 1270#define BUS_CLOCK (1<<7) /* Bit 7: (ML) Bus Clock 0/1 = 33/66MHz */ 1271#define BUS_SLOT_SZ (1<<6) /* Bit 6: (ML) Slot Size 0/1 = 32/64 bit slot*/ 1272 /* Bit 5..4: reserved */ 1273#define DAS_AVAIL (1<<3) /* Bit 3: 1 = DAS, 0 = SAS */ 1274#define DAS_BYP_ST (1<<2) /* Bit 2: 1 = avail,SAS, 0 = not avail */ 1275#define DAS_BYP_INS (1<<1) /* Bit 1: 1 = insert Bypass */ 1276#define DAS_BYP_RMV (1<<0) /* Bit 0: 1 = remove Bypass */ 1277 1278/* B0_LED 8 Bit LED register */ 1279 /* Bit 7..6: reserved */ 1280#define LED_2_ON (1<<5) /* Bit 5: 1 = switch LED_2 on (left,gn)*/ 1281#define LED_2_OFF (1<<4) /* Bit 4: 1 = switch LED_2 off */ 1282#define LED_1_ON (1<<3) /* Bit 3: 1 = switch LED_1 on (mid,yel)*/ 1283#define LED_1_OFF (1<<2) /* Bit 2: 1 = switch LED_1 off */ 1284#define LED_0_ON (1<<1) /* Bit 1: 1 = switch LED_0 on (rght,gn)*/ 1285#define LED_0_OFF (1<<0) /* Bit 0: 1 = switch LED_0 off */ 1286/* This hardware defines are very ugly therefore we define some others */ 1287 1288#define LED_GA_ON LED_2_ON /* S port = A port */ 1289#define LED_GA_OFF LED_2_OFF /* S port = A port */ 1290#define LED_MY_ON LED_1_ON 1291#define LED_MY_OFF LED_1_OFF 1292#define LED_GB_ON LED_0_ON 1293#define LED_GB_OFF LED_0_OFF 1294 1295/* B0_TST_CTRL 8 bit test control register */ 1296#define TST_FRC_DPERR_MR (1<<7) /* Bit 7: force DATAPERR on MST RE. */ 1297#define TST_FRC_DPERR_MW (1<<6) /* Bit 6: force DATAPERR on MST WR. */ 1298#define TST_FRC_DPERR_TR (1<<5) /* Bit 5: force DATAPERR on TRG RE. */ 1299#define TST_FRC_DPERR_TW (1<<4) /* Bit 4: force DATAPERR on TRG WR. */ 1300#define TST_FRC_APERR_M (1<<3) /* Bit 3: force ADDRPERR on MST */ 1301#define TST_FRC_APERR_T (1<<2) /* Bit 2: force ADDRPERR on TRG */ 1302#define TST_CFG_WRITE_ON (1<<1) /* Bit 1: ena configuration reg. WR */ 1303#define TST_CFG_WRITE_OFF (1<<0) /* Bit 0: dis configuration reg. WR */ 1304 1305/* B0_ISRC 32 bit Interrupt source register */ 1306 /* Bit 31..28: reserved */ 1307#define IS_I2C_READY (1L<<27) /* Bit 27: (ML) IRQ on end of I2C tx */ 1308#define IS_IRQ_SW (1L<<26) /* Bit 26: (ML) SW forced IRQ */ 1309#define IS_EXT_REG (1L<<25) /* Bit 25: (ML) IRQ from external reg*/ 1310#define IS_IRQ_STAT (1L<<24) /* Bit 24: IRQ status execption */ 1311 /* PERR, RMABORT, RTABORT DATAPERR */ 1312#define IS_IRQ_MST_ERR (1L<<23) /* Bit 23: IRQ master error */ 1313 /* RMABORT, RTABORT, DATAPERR */ 1314#define IS_TIMINT (1L<<22) /* Bit 22: IRQ_TIMER */ 1315#define IS_TOKEN (1L<<21) /* Bit 21: IRQ_RTM */ 1316/* 1317 * Note: The DAS is our First Port (!=PA) 1318 */ 1319#define IS_PLINT1 (1L<<20) /* Bit 20: IRQ_PHY_DAS */ 1320#define IS_PLINT2 (1L<<19) /* Bit 19: IRQ_IFCP_4 */ 1321#define IS_MINTR3 (1L<<18) /* Bit 18: IRQ_IFCP_3/IRQ_PHY */ 1322#define IS_MINTR2 (1L<<17) /* Bit 17: IRQ_IFCP_2/IRQ_MAC_2 */ 1323#define IS_MINTR1 (1L<<16) /* Bit 16: IRQ_IFCP_1/IRQ_MAC_1 */ 1324/* Receive Queue 1 */ 1325#define IS_R1_P (1L<<15) /* Bit 15: Parity Error (q1) */ 1326#define IS_R1_B (1L<<14) /* Bit 14: End of Buffer (q1) */ 1327#define IS_R1_F (1L<<13) /* Bit 13: End of Frame (q1) */ 1328#define IS_R1_C (1L<<12) /* Bit 12: Encoding Error (q1) */ 1329/* Receive Queue 2 */ 1330#define IS_R2_P (1L<<11) /* Bit 11: (DV) Parity Error (q2) */ 1331#define IS_R2_B (1L<<10) /* Bit 10: (DV) End of Buffer (q2) */ 1332#define IS_R2_F (1L<<9) /* Bit 9: (DV) End of Frame (q2) */ 1333#define IS_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */ 1334/* Asynchronous Transmit queue */ 1335 /* Bit 7: reserved */ 1336#define IS_XA_B (1L<<6) /* Bit 6: End of Buffer (xa) */ 1337#define IS_XA_F (1L<<5) /* Bit 5: End of Frame (xa) */ 1338#define IS_XA_C (1L<<4) /* Bit 4: Encoding Error (xa) */ 1339/* Synchronous Transmit queue */ 1340 /* Bit 3: reserved */ 1341#define IS_XS_B (1L<<2) /* Bit 2: End of Buffer (xs) */ 1342#define IS_XS_F (1L<<1) /* Bit 1: End of Frame (xs) */ 1343#define IS_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */ 1344 1345/* 1346 * Define all valid interrupt source Bits from GET_ISR () 1347 */ 1348#define ALL_IRSR 0x01ffff77L /* (DV) */ 1349#define ALL_IRSR_ML 0x0ffff077L /* (ML) */ 1350 1351 1352/* B0_IMSK 32 bit Interrupt mask register */ 1353/* 1354 * The Bit definnition of this register are the same as of the interrupt 1355 * source register. These definition are directly derived from the Hardware 1356 * spec. 1357 */ 1358 /* Bit 31..28: reserved */ 1359#define IRQ_I2C_READY (1L<<27) /* Bit 27: (ML) IRQ on end of I2C tx */ 1360#define IRQ_SW (1L<<26) /* Bit 26: (ML) SW forced IRQ */ 1361#define IRQ_EXT_REG (1L<<25) /* Bit 25: (ML) IRQ from external reg*/ 1362#define IRQ_STAT (1L<<24) /* Bit 24: IRQ status execption */ 1363 /* PERR, RMABORT, RTABORT DATAPERR */ 1364#define IRQ_MST_ERR (1L<<23) /* Bit 23: IRQ master error */ 1365 /* RMABORT, RTABORT, DATAPERR */ 1366#define IRQ_TIMER (1L<<22) /* Bit 22: IRQ_TIMER */ 1367#define IRQ_RTM (1L<<21) /* Bit 21: IRQ_RTM */ 1368#define IRQ_DAS (1L<<20) /* Bit 20: IRQ_PHY_DAS */ 1369#define IRQ_IFCP_4 (1L<<19) /* Bit 19: IRQ_IFCP_4 */ 1370#define IRQ_IFCP_3 (1L<<18) /* Bit 18: IRQ_IFCP_3/IRQ_PHY */ 1371#define IRQ_IFCP_2 (1L<<17) /* Bit 17: IRQ_IFCP_2/IRQ_MAC_2 */ 1372#define IRQ_IFCP_1 (1L<<16) /* Bit 16: IRQ_IFCP_1/IRQ_MAC_1 */ 1373/* Receive Queue 1 */ 1374#define IRQ_R1_P (1L<<15) /* Bit 15: Parity Error (q1) */ 1375#define IRQ_R1_B (1L<<14) /* Bit 14: End of Buffer (q1) */ 1376#define IRQ_R1_F (1L<<13) /* Bit 13: End of Frame (q1) */ 1377#define IRQ_R1_C (1L<<12) /* Bit 12: Encoding Error (q1) */ 1378/* Receive Queue 2 */ 1379#define IRQ_R2_P (1L<<11) /* Bit 11: (DV) Parity Error (q2) */ 1380#define IRQ_R2_B (1L<<10) /* Bit 10: (DV) End of Buffer (q2) */ 1381#define IRQ_R2_F (1L<<9) /* Bit 9: (DV) End of Frame (q2) */ 1382#define IRQ_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */ 1383/* Asynchronous Transmit queue */ 1384 /* Bit 7: reserved */ 1385#define IRQ_XA_B (1L<<6) /* Bit 6: End of Buffer (xa) */ 1386#define IRQ_XA_F (1L<<5) /* Bit 5: End of Frame (xa) */ 1387#define IRQ_XA_C (1L<<4) /* Bit 4: Encoding Error (xa) */ 1388/* Synchronous Transmit queue */ 1389 /* Bit 3: reserved */ 1390#define IRQ_XS_B (1L<<2) /* Bit 2: End of Buffer (xs) */ 1391#define IRQ_XS_F (1L<<1) /* Bit 1: End of Frame (xs) */ 1392#define IRQ_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */ 1393 1394/* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */ 1395/* B0_R1_CSR 32 bit BMU control/status reg (rec q 1 ) */ 1396/* B0_R2_CSR 32 bit BMU control/status reg (rec q 2 ) */ 1397/* B0_XA_CSR 32 bit BMU control/status reg (a xmit q ) */ 1398/* B0_XS_CSR 32 bit BMU control/status reg (s xmit q ) */ 1399/* The registers are the same as B4_R1_CSR, B4_R2_CSR, B5_Xa_CSR, B5_XS_CSR */ 1400 1401/* B2_MAC_0 8 bit MAC address Byte 0 */ 1402/* B2_MAC_1 8 bit MAC address Byte 1 */ 1403/* B2_MAC_2 8 bit MAC address Byte 2 */ 1404/* B2_MAC_3 8 bit MAC address Byte 3 */ 1405/* B2_MAC_4 8 bit MAC address Byte 4 */ 1406/* B2_MAC_5 8 bit MAC address Byte 5 */ 1407/* B2_MAC_6 8 bit MAC address Byte 6 (== 0) (DV) */ 1408/* B2_MAC_7 8 bit MAC address Byte 7 (== 0) (DV) */ 1409 1410/* B2_CONN_TYP 8 bit Connector type */ 1411/* B2_PMD_TYP 8 bit PMD type */ 1412/* Values of connector and PMD type comply to SysKonnect internal std */ 1413 1414/* The EPROM register are currently of no use */ 1415/* B2_E_0 8 bit EPROM Byte 0 */ 1416/* B2_E_1 8 bit EPROM Byte 1 */ 1417/* B2_E_2 8 bit EPROM Byte 2 */ 1418/* B2_E_3 8 bit EPROM Byte 3 */ 1419 1420/* B2_FAR 32 bit Flash-Prom Address Register/Counter */ 1421#define FAR_ADDR 0x1ffffL /* Bit 16..0: FPROM Address mask */ 1422 1423/* B2_FDP 8 bit Flash-Prom Data Port */ 1424 1425/* B2_LD_CRTL 8 bit loader control */ 1426/* Bits are currently reserved */ 1427 1428/* B2_LD_TEST 8 bit loader test */ 1429#define LD_T_ON (1<<3) /* Bit 3: Loader Testmode on */ 1430#define LD_T_OFF (1<<2) /* Bit 2: Loader Testmode off */ 1431#define LD_T_STEP (1<<1) /* Bit 1: Decrement FPROM addr. Counter */ 1432#define LD_START (1<<0) /* Bit 0: Start loading FPROM */ 1433 1434/* B2_TI_INI 32 bit Timer init value */ 1435/* B2_TI_VAL 32 bit Timer value */ 1436/* B2_TI_CRTL 8 bit Timer control */ 1437/* B2_TI_TEST 8 Bit Timer Test */ 1438/* B2_WDOG_INI 32 bit Watchdog init value */ 1439/* B2_WDOG_VAL 32 bit Watchdog value */ 1440/* B2_WDOG_CRTL 8 bit Watchdog control */ 1441/* B2_WDOG_TEST 8 Bit Watchdog Test */ 1442/* B2_RTM_INI 32 bit RTM init value */ 1443/* B2_RTM_VAL 32 bit RTM value */ 1444/* B2_RTM_CRTL 8 bit RTM control */ 1445/* B2_RTM_TEST 8 Bit RTM Test */ 1446/* B2_<TIM>_CRTL 8 bit <TIM> control */ 1447/* B2_IRQ_MOD_INI 32 bit IRQ Moderation Timer Init Reg. (ML) */ 1448/* B2_IRQ_MOD_VAL 32 bit IRQ Moderation Timer Value (ML) */ 1449/* B2_IRQ_MOD_CTRL 8 bit IRQ Moderation Timer Control (ML) */ 1450/* B2_IRQ_MOD_TEST 8 bit IRQ Moderation Timer Test (ML) */ 1451#define GET_TOK_CT (1<<4) /* Bit 4: Get the Token Counter (RTM) */ 1452#define TIM_RES_TOK (1<<3) /* Bit 3: RTM Status: 1 == restricted */ 1453#define TIM_ALARM (1<<3) /* Bit 3: Timer Alarm (WDOG) */ 1454#define TIM_START (1<<2) /* Bit 2: Start Timer (TI,WDOG,RTM,IRQ_MOD)*/ 1455#define TIM_STOP (1<<1) /* Bit 1: Stop Timer (TI,WDOG,RTM,IRQ_MOD) */ 1456#define TIM_CL_IRQ (1<<0) /* Bit 0: Clear Timer IRQ (TI,WDOG,RTM) */ 1457/* B2_<TIM>_TEST 8 Bit <TIM> Test */ 1458#define TIM_T_ON (1<<2) /* Bit 2: Test mode on (TI,WDOG,RTM,IRQ_MOD) */ 1459#define TIM_T_OFF (1<<1) /* Bit 1: Test mode off (TI,WDOG,RTM,IRQ_MOD) */ 1460#define TIM_T_STEP (1<<0) /* Bit 0: Test step (TI,WDOG,RTM,IRQ_MOD) */ 1461 1462/* B2_TOK_COUNT 0x014c (ML) 32 bit Token Counter */ 1463/* B2_DESC_ADDR_H 0x0150 (ML) 32 bit Desciptor Base Addr Reg High */ 1464/* B2_CTRL_2 0x0154 (ML) 8 bit Control Register 2 */ 1465 /* Bit 7..5: reserved */ 1466#define CTRL_CL_I2C_IRQ (1<<4) /* Bit 4: Clear I2C IRQ */ 1467#define CTRL_ST_SW_IRQ (1<<3) /* Bit 3: Set IRQ SW Request */ 1468#define CTRL_CL_SW_IRQ (1<<2) /* Bit 2: Clear IRQ SW Request */ 1469#define CTRL_STOP_DONE (1<<1) /* Bit 1: Stop Master is finished */ 1470#define CTRL_STOP_MAST (1<<0) /* Bit 0: Command Bit to stop the master*/ 1471 1472/* B2_IFACE_REG 0x0155 (ML) 8 bit Interface Register */ 1473 /* Bit 7..3: reserved */ 1474#define IF_I2C_DATA_DIR (1<<2) /* Bit 2: direction of IF_I2C_DATA*/ 1475#define IF_I2C_DATA (1<<1) /* Bit 1: I2C Data Port */ 1476#define IF_I2C_CLK (1<<0) /* Bit 0: I2C Clock Port */ 1477 1478 /* 0x0156: reserved */ 1479/* B2_TST_CTRL_2 0x0157 (ML) 8 bit Test Control Register 2 */ 1480 /* Bit 7..4: reserved */ 1481 /* force the following error on */ 1482 /* the next master read/write */ 1483#define TST_FRC_DPERR_MR64 (1<<3) /* Bit 3: DataPERR RD 64 */ 1484#define TST_FRC_DPERR_MW64 (1<<2) /* Bit 2: DataPERR WR 64 */ 1485#define TST_FRC_APERR_1M64 (1<<1) /* Bit 1: AddrPERR on 1. phase */ 1486#define TST_FRC_APERR_2M64 (1<<0) /* Bit 0: AddrPERR on 2. phase */ 1487 1488/* B2_I2C_CTRL 0x0158 (ML) 32 bit I2C Control Register */ 1489#define I2C_FLAG (1L<<31) /* Bit 31: Start read/write if WR */ 1490#define I2C_ADDR (0x7fffL<<16) /* Bit 30..16: Addr to be read/written*/ 1491#define I2C_DEV_SEL (0x7fL<<9) /* Bit 9..15: I2C Device Select */ 1492 /* Bit 5.. 8: reserved */ 1493#define I2C_BURST_LEN (1L<<4) /* Bit 4 Burst Len, 1/4 bytes */ 1494#define I2C_DEV_SIZE (7L<<1) /* Bit 1.. 3: I2C Device Size */ 1495#define I2C_025K_DEV (0L<<1) /* 0: 256 Bytes or smaller*/ 1496#define I2C_05K_DEV (1L<<1) /* 1: 512 Bytes */ 1497#define I2C_1K_DEV (2L<<1) /* 2: 1024 Bytes */ 1498#define I2C_2K_DEV (3L<<1) /* 3: 2048 Bytes */ 1499#define I2C_4K_DEV (4L<<1) /* 4: 4096 Bytes */ 1500#define I2C_8K_DEV (5L<<1) /* 5: 8192 Bytes */ 1501#define I2C_16K_DEV (6L<<1) /* 6: 16384 Bytes */ 1502#define I2C_32K_DEV (7L<<1) /* 7: 32768 Bytes */ 1503#define I2C_STOP_BIT (1<<0) /* Bit 0: Interrupt I2C transfer */ 1504 1505/* 1506 * I2C Addresses 1507 * 1508 * The temperature sensor and the voltage sensor are on the same I2C bus. 1509 * Note: The voltage sensor (Micorwire) will be selected by PCI_EXT_PATCH_1 1510 * in PCI_OUR_REG 1. 1511 */ 1512#define I2C_ADDR_TEMP 0x90 /* I2C Address Temperature Sensor */ 1513 1514/* B2_I2C_DATA 0x015c (ML) 32 bit I2C Data Register */ 1515 1516/* B4_R1_D 4*32 bit current receive Descriptor (q1) */ 1517/* B4_R1_DA 32 bit current rec desc address (q1) */ 1518/* B4_R1_AC 32 bit current receive Address Count (q1) */ 1519/* B4_R1_BC 32 bit current receive Byte Counter (q1) */ 1520/* B4_R1_CSR 32 bit BMU Control/Status Register (q1) */ 1521/* B4_R1_F 32 bit flag register (q1) */ 1522/* B4_R1_T1 32 bit Test Register 1 (q1) */ 1523/* B4_R1_T2 32 bit Test Register 2 (q1) */ 1524/* B4_R1_T3 32 bit Test Register 3 (q1) */ 1525/* B4_R2_D 4*32 bit current receive Descriptor (q2) */ 1526/* B4_R2_DA 32 bit current rec desc address (q2) */ 1527/* B4_R2_AC 32 bit current receive Address Count (q2) */ 1528/* B4_R2_BC 32 bit current receive Byte Counter (q2) */ 1529/* B4_R2_CSR 32 bit BMU Control/Status Register (q2) */ 1530/* B4_R2_F 32 bit flag register (q2) */ 1531/* B4_R2_T1 32 bit Test Register 1 (q2) */ 1532/* B4_R2_T2 32 bit Test Register 2 (q2) */ 1533/* B4_R2_T3 32 bit Test Register 3 (q2) */ 1534/* B5_XA_D 4*32 bit current receive Descriptor (xa) */ 1535/* B5_XA_DA 32 bit current rec desc address (xa) */ 1536/* B5_XA_AC 32 bit current receive Address Count (xa) */ 1537/* B5_XA_BC 32 bit current receive Byte Counter (xa) */ 1538/* B5_XA_CSR 32 bit BMU Control/Status Register (xa) */ 1539/* B5_XA_F 32 bit flag register (xa) */ 1540/* B5_XA_T1 32 bit Test Register 1 (xa) */ 1541/* B5_XA_T2 32 bit Test Register 2 (xa) */ 1542/* B5_XA_T3 32 bit Test Register 3 (xa) */ 1543/* B5_XS_D 4*32 bit current receive Descriptor (xs) */ 1544/* B5_XS_DA 32 bit current rec desc address (xs) */ 1545/* B5_XS_AC 32 bit current receive Address Count (xs) */ 1546/* B5_XS_BC 32 bit current receive Byte Counter (xs) */ 1547/* B5_XS_CSR 32 bit BMU Control/Status Register (xs) */ 1548/* B5_XS_F 32 bit flag register (xs) */ 1549/* B5_XS_T1 32 bit Test Register 1 (xs) */ 1550/* B5_XS_T2 32 bit Test Register 2 (xs) */ 1551/* B5_XS_T3 32 bit Test Register 3 (xs) */ 1552/* B5_<xx>_CSR 32 bit BMU Control/Status Register (xx) */ 1553#define CSR_DESC_CLEAR (1L<<21) /* Bit 21: Clear Reset for Descr */ 1554#define CSR_DESC_SET (1L<<20) /* Bit 20: Set Reset for Descr */ 1555#define CSR_FIFO_CLEAR (1L<<19) /* Bit 19: Clear Reset for FIFO */ 1556#define CSR_FIFO_SET (1L<<18) /* Bit 18: Set Reset for FIFO */ 1557#define CSR_HPI_RUN (1L<<17) /* Bit 17: Release HPI SM */ 1558#define CSR_HPI_RST (1L<<16) /* Bit 16: Reset HPI SM to Idle */ 1559#define CSR_SV_RUN (1L<<15) /* Bit 15: Release Supervisor SM */ 1560#define CSR_SV_RST (1L<<14) /* Bit 14: Reset Supervisor SM */ 1561#define CSR_DREAD_RUN (1L<<13) /* Bit 13: Release Descr Read SM */ 1562#define CSR_DREAD_RST (1L<<12) /* Bit 12: Reset Descr Read SM */ 1563#define CSR_DWRITE_RUN (1L<<11) /* Bit 11: Rel. Descr Write SM */ 1564#define CSR_DWRITE_RST (1L<<10) /* Bit 10: Reset Descr Write SM */ 1565#define CSR_TRANS_RUN (1L<<9) /* Bit 9: Release Transfer SM */ 1566#define CSR_TRANS_RST (1L<<8) /* Bit 8: Reset Transfer SM */ 1567 /* Bit 7..5: reserved */ 1568#define CSR_START (1L<<4) /* Bit 4: Start Rec/Xmit Queue */ 1569#define CSR_IRQ_CL_P (1L<<3) /* Bit 3: Clear Parity IRQ, Rcv */ 1570#define CSR_IRQ_CL_B (1L<<2) /* Bit 2: Clear EOB IRQ */ 1571#define CSR_IRQ_CL_F (1L<<1) /* Bit 1: Clear EOF IRQ */ 1572#define CSR_IRQ_CL_C (1L<<0) /* Bit 0: Clear ERR IRQ */ 1573 1574#define CSR_SET_RESET (CSR_DESC_SET|CSR_FIFO_SET|CSR_HPI_RST|CSR_SV_RST|\ 1575 CSR_DREAD_RST|CSR_DWRITE_RST|CSR_TRANS_RST) 1576#define CSR_CLR_RESET (CSR_DESC_CLEAR|CSR_FIFO_CLEAR|CSR_HPI_RUN|CSR_SV_RUN|\ 1577 CSR_DREAD_RUN|CSR_DWRITE_RUN|CSR_TRANS_RUN) 1578 1579 1580/* B5_<xx>_F 32 bit flag register (xx) */ 1581 /* Bit 28..31: reserved */ 1582#define F_ALM_FULL (1L<<27) /* Bit 27: (ML) FIFO almost full */ 1583#define F_FIFO_EOF (1L<<26) /* Bit 26: (ML) Fag bit in FIFO */ 1584#define F_WM_REACHED (1L<<25) /* Bit 25: (ML) Watermark reached */ 1585#define F_UP_DW_USED (1L<<24) /* Bit 24: (ML) Upper Dword used (bug)*/ 1586 /* Bit 23: reserved */ 1587#define F_FIFO_LEVEL (0x1fL<<16) /* Bit 16..22:(ML) # of Qwords in FIFO*/ 1588 /* Bit 8..15: reserved */ 1589#define F_ML_WATER_M 0x0000ffL /* Bit 0.. 7:(ML) Watermark */ 1590#define FLAG_WATER 0x00001fL /* Bit 4..0:(DV) Level of req data tr.*/ 1591 1592/* B5_<xx>_T1 32 bit Test Register 1 (xx) */ 1593/* Holds four State Machine control Bytes */ 1594#define SM_CRTL_SV (0xffL<<24) /* Bit 31..24: Control Supervisor SM */ 1595#define SM_CRTL_RD (0xffL<<16) /* Bit 23..16: Control Read Desc SM */ 1596#define SM_CRTL_WR (0xffL<<8) /* Bit 15..8: Control Write Desc SM */ 1597#define SM_CRTL_TR (0xffL<<0) /* Bit 7..0: Control Transfer SM */ 1598 1599/* B4_<xx>_T1_TR 8 bit Test Register 1 TR (xx) */ 1600/* B4_<xx>_T1_WR 8 bit Test Register 1 WR (xx) */ 1601/* B4_<xx>_T1_RD 8 bit Test Register 1 RD (xx) */ 1602/* B4_<xx>_T1_SV 8 bit Test Register 1 SV (xx) */ 1603/* The control status byte of each machine looks like ... */ 1604#define SM_STATE 0xf0 /* Bit 7..4: State which shall be loaded */ 1605#define SM_LOAD 0x08 /* Bit 3: Load the SM with SM_STATE */ 1606#define SM_TEST_ON 0x04 /* Bit 2: Switch on SM Test Mode */ 1607#define SM_TEST_OFF 0x02 /* Bit 1: Go off the Test Mode */ 1608#define SM_STEP 0x01 /* Bit 0: Step the State Machine */ 1609 1610/* The coding of the states */ 1611#define SM_SV_IDLE 0x0 /* Supervisor Idle Tr/Re */ 1612#define SM_SV_RES_START 0x1 /* Supervisor Res_Start Tr/Re */ 1613#define SM_SV_GET_DESC 0x3 /* Supervisor Get_Desc Tr/Re */ 1614#define SM_SV_CHECK 0x2 /* Supervisor Check Tr/Re */ 1615#define SM_SV_MOV_DATA 0x6 /* Supervisor Move_Data Tr/Re */ 1616#define SM_SV_PUT_DESC 0x7 /* Supervisor Put_Desc Tr/Re */ 1617#define SM_SV_SET_IRQ 0x5 /* Supervisor Set_Irq Tr/Re */ 1618 1619#define SM_RD_IDLE 0x0 /* Read Desc. Idle Tr/Re */ 1620#define SM_RD_LOAD 0x1 /* Read Desc. Load Tr/Re */ 1621#define SM_RD_WAIT_TC 0x3 /* Read Desc. Wait_TC Tr/Re */ 1622#define SM_RD_RST_EOF 0x6 /* Read Desc. Reset_EOF Re */ 1623#define SM_RD_WDONE_R 0x2 /* Read Desc. Wait_Done Re */ 1624#define SM_RD_WDONE_T 0x4 /* Read Desc. Wait_Done Tr */ 1625 1626#define SM_TR_IDLE 0x0 /* Trans. Data Idle Tr/Re */ 1627#define SM_TR_LOAD 0x3 /* Trans. Data Load Tr/Re */ 1628#define SM_TR_LOAD_R_ML 0x1 /* Trans. Data Load /Re (ML) */ 1629#define SM_TR_WAIT_TC 0x2 /* Trans. Data Wait_TC Tr/Re */ 1630#define SM_TR_WDONE 0x4 /* Trans. Data Wait_Done Tr/Re */ 1631 1632#define SM_WR_IDLE 0x0 /* Write Desc. Idle Tr/Re */ 1633#define SM_WR_ABLEN 0x1 /* Write Desc. Act_Buf_Length Tr/Re */ 1634#define SM_WR_LD_A4 0x2 /* Write Desc. Load_A4 Re */ 1635#define SM_WR_RES_OWN 0x2 /* Write Desc. Res_OWN Tr */ 1636#define SM_WR_WAIT_EOF 0x3 /* Write Desc. Wait_EOF Re */ 1637#define SM_WR_LD_N2C_R 0x4 /* Write Desc. Load_N2C Re */ 1638#define SM_WR_WAIT_TC_R 0x5 /* Write Desc. Wait_TC Re */ 1639#define SM_WR_WAIT_TC4 0x6 /* Write Desc. Wait_TC4 Re */ 1640#define SM_WR_LD_A_T 0x6 /* Write Desc. Load_A Tr */ 1641#define SM_WR_LD_A_R 0x7 /* Write Desc. Load_A Re */ 1642#define SM_WR_WAIT_TC_T 0x7 /* Write Desc. Wait_TC Tr */ 1643#define SM_WR_LD_N2C_T 0xc /* Write Desc. Load_N2C Tr */ 1644#define SM_WR_WDONE_T 0x9 /* Write Desc. Wait_Done Tr */ 1645#define SM_WR_WDONE_R 0xc /* Write Desc. Wait_Done Re */ 1646#define SM_WR_LD_D_AD 0xe /* Write Desc. Load_Dumr_A Re (ML) */ 1647#define SM_WR_WAIT_D_TC 0xf /* Write Desc. Wait_Dumr_TC Re (ML) */ 1648 1649/* B5_<xx>_T2 32 bit Test Register 2 (xx) */ 1650/* Note: This register is only defined for the transmit queues */ 1651 /* Bit 31..8: reserved */ 1652#define AC_TEST_ON (1<<7) /* Bit 7: Address Counter Test Mode on */ 1653#define AC_TEST_OFF (1<<6) /* Bit 6: Address Counter Test Mode off*/ 1654#define BC_TEST_ON (1<<5) /* Bit 5: Byte Counter Test Mode on */ 1655#define BC_TEST_OFF (1<<4) /* Bit 4: Byte Counter Test Mode off */ 1656#define TEST_STEP04 (1<<3) /* Bit 3: Inc AC/Dec BC by 4 */ 1657#define TEST_STEP03 (1<<2) /* Bit 2: Inc AC/Dec BC by 3 */ 1658#define TEST_STEP02 (1<<1) /* Bit 1: Inc AC/Dec BC by 2 */ 1659#define TEST_STEP01 (1<<0) /* Bit 0: Inc AC/Dec BC by 1 */ 1660 1661/* B5_<xx>_T3 32 bit Test Register 3 (xx) */ 1662/* Note: This register is only defined for the transmit queues */ 1663 /* Bit 31..8: reserved */ 1664#define T3_MUX_2 (1<<7) /* Bit 7: (ML) Mux position MSB */ 1665#define T3_VRAM_2 (1<<6) /* Bit 6: (ML) Virtual RAM buffer addr MSB */ 1666#define T3_LOOP (1<<5) /* Bit 5: Set Loopback (Xmit) */ 1667#define T3_UNLOOP (1<<4) /* Bit 4: Unset Loopback (Xmit) */ 1668#define T3_MUX (3<<2) /* Bit 3..2: Mux position */ 1669#define T3_VRAM (3<<0) /* Bit 1..0: Virtual RAM buffer Address */ 1670 1671/* PCI card IDs */ 1672/* 1673 * Note: The following 4 byte definitions shall not be used! Use OEM Concept! 1674 */ 1675#define PCI_VEND_ID0 0x48 /* PCI vendor ID (SysKonnect) */ 1676#define PCI_VEND_ID1 0x11 /* PCI vendor ID (SysKonnect) */ 1677 /* (High byte) */ 1678#define PCI_DEV_ID0 0x00 /* PCI device ID */ 1679#define PCI_DEV_ID1 0x40 /* PCI device ID (High byte) */ 1680 1681/*#define PCI_CLASS 0x02*/ /* PCI class code: network device */ 1682#define PCI_NW_CLASS 0x02 /* PCI class code: network device */ 1683#define PCI_SUB_CLASS 0x02 /* PCI subclass ID: FDDI device */ 1684#define PCI_PROG_INTFC 0x00 /* PCI programming Interface (=0) */ 1685 1686/* 1687 * address transmission from logical to physical offset address on board 1688 */ 1689#define FMA(a) (0x0400|((a)<<2)) /* FORMAC+ (r/w) (SN3) */ 1690#define P1(a) (0x0380|((a)<<2)) /* PLC1 (r/w) (DAS) */ 1691#define P2(a) (0x0600|((a)<<2)) /* PLC2 (r/w) (covered by the SN3) */ 1692#define PRA(a) (B2_MAC_0 + (a)) /* configuration PROM (MAC address) */ 1693 1694/* 1695 * FlashProm specification 1696 */ 1697#define MAX_PAGES 0x20000L /* Every byte has a single page */ 1698#define MAX_FADDR 1 /* 1 byte per page */ 1699 1700/* 1701 * Receive / Transmit Buffer Control word 1702 */ 1703#define BMU_OWN (1UL<<31) /* OWN bit: 0 == host, 1 == adapter */ 1704#define BMU_STF (1L<<30) /* Start of Frame ? */ 1705#define BMU_EOF (1L<<29) /* End of Frame ? */ 1706#define BMU_EN_IRQ_EOB (1L<<28) /* Enable "End of Buffer" IRQ */ 1707#define BMU_EN_IRQ_EOF (1L<<27) /* Enable "End of Frame" IRQ */ 1708#define BMU_DEV_0 (1L<<26) /* RX: don't transfer to system mem */ 1709#define BMU_SMT_TX (1L<<25) /* TX: if set, buffer type SMT_MBuf */ 1710#define BMU_ST_BUF (1L<<25) /* RX: copy of start of frame */ 1711#define BMU_UNUSED (1L<<24) /* Set if the Descr is curr unused */ 1712#define BMU_SW (3L<<24) /* 2 Bits reserved for SW usage */ 1713#define BMU_CHECK 0x00550000L /* To identify the control word */ 1714#define BMU_BBC 0x0000FFFFL /* R/T Buffer Byte Count */ 1715 1716/* 1717 * physical address offset + IO-Port base address 1718 */ 1719#ifdef MEM_MAPPED_IO 1720#define ADDR(a) (char far *) smc->hw.iop+(a) 1721#define ADDRS(smc,a) (char far *) (smc)->hw.iop+(a) 1722#else 1723#define ADDR(a) (((a)>>7) ? (outp(smc->hw.iop+B0_RAP,(a)>>7), \ 1724 (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \ 1725 (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) 1726#define ADDRS(smc,a) (((a)>>7) ? (outp((smc)->hw.iop+B0_RAP,(a)>>7), \ 1727 ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \ 1728 ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) 1729#endif 1730 1731/* 1732 * Define a macro to access the configuration space 1733 */ 1734#define PCI_C(a) ADDR(B3_CFG_SPC + (a)) /* PCI Config Space */ 1735 1736#define EXT_R(a) ADDR(B6_EXT_REG + (a)) /* External Registers */ 1737 1738/* 1739 * Define some values needed for the MAC address (PROM) 1740 */ 1741#define SA_MAC (0) /* start addr. MAC_AD within the PROM */ 1742#define PRA_OFF (0) /* offset correction when 4th byte reading */ 1743 1744#define SKFDDI_PSZ 8 /* address PROM size */ 1745 1746#define FM_A(a) ADDR(FMA(a)) /* FORMAC Plus physical addr */ 1747#define P1_A(a) ADDR(P1(a)) /* PLC1 (r/w) */ 1748#define P2_A(a) ADDR(P2(a)) /* PLC2 (r/w) (DAS) */ 1749#define PR_A(a) ADDR(PRA(a)) /* config. PROM (MAC address) */ 1750 1751/* 1752 * Macro to read the PROM 1753 */ 1754#define READ_PROM(a) ((u_char)inp(a)) 1755 1756#define GET_PAGE(bank) outpd(ADDR(B2_FAR),bank) 1757#define VPP_ON() 1758#define VPP_OFF() 1759 1760/* 1761 * Note: Values of the Interrupt Source Register are defined above 1762 */ 1763#define ISR_A ADDR(B0_ISRC) 1764#define GET_ISR() inpd(ISR_A) 1765#define GET_ISR_SMP(iop) inpd((iop)+B0_ISRC) 1766#define CHECK_ISR() (inpd(ISR_A) & inpd(ADDR(B0_IMSK))) 1767#define CHECK_ISR_SMP(iop) (inpd((iop)+B0_ISRC) & inpd((iop)+B0_IMSK)) 1768 1769#define BUS_CHECK() 1770 1771/* 1772 * CLI_FBI: Disable Board Interrupts 1773 * STI_FBI: Enable Board Interrupts 1774 */ 1775#ifndef UNIX 1776#define CLI_FBI() outpd(ADDR(B0_IMSK),0) 1777#else 1778#define CLI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),0) 1779#endif 1780 1781#ifndef UNIX 1782#define STI_FBI() outpd(ADDR(B0_IMSK),smc->hw.is_imask) 1783#else 1784#define STI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),(smc)->hw.is_imask) 1785#endif 1786 1787#define CLI_FBI_SMP(iop) outpd((iop)+B0_IMSK,0) 1788#define STI_FBI_SMP(smc,iop) outpd((iop)+B0_IMSK,(smc)->hw.is_imask) 1789 1790#endif /* PCI */ 1791/*--------------------------------------------------------------------------*/ 1792 1793/* 1794 * 12 bit transfer (dword) counter: 1795 * (ISA: 2*trc = number of byte) 1796 * (EISA: 4*trc = number of byte) 1797 * (MCA: 4*trc = number of byte) 1798 */ 1799#define MAX_TRANS (0x0fff) 1800 1801/* 1802 * PC PIC 1803 */ 1804#define MST_8259 (0x20) 1805#define SLV_8259 (0xA0) 1806 1807#define TPS (18) /* ticks per second */ 1808 1809/* 1810 * error timer defs 1811 */ 1812#define TN (4) /* number of supported timer = TN+1 */ 1813#define SNPPND_TIME (5) /* buffer memory access over mem. data reg. */ 1814 1815#define MAC_AD 0x405a0000 1816 1817#define MODR1 FM_A(FM_MDREG1) /* mode register 1 */ 1818#define MODR2 FM_A(FM_MDREG2) /* mode register 2 */ 1819 1820#define CMDR1 FM_A(FM_CMDREG1) /* command register 1 */ 1821#define CMDR2 FM_A(FM_CMDREG2) /* command register 2 */ 1822 1823 1824/* 1825 * function defines 1826 */ 1827#define CLEAR(io,mask) outpw((io),inpw(io)&(~(mask))) 1828#define SET(io,mask) outpw((io),inpw(io)|(mask)) 1829#define GET(io,mask) (inpw(io)&(mask)) 1830#define SETMASK(io,val,mask) outpw((io),(inpw(io) & ~(mask)) | (val)) 1831 1832/* 1833 * PHY Port A (PA) = PLC 1 1834 * With SuperNet 3 PHY-A and PHY S are identical. 1835 */ 1836#define PLC(np,reg) (((np) == PA) ? P2_A(reg) : P1_A(reg)) 1837 1838/* 1839 * set memory address register for write and read 1840 */ 1841#define MARW(ma) outpw(FM_A(FM_MARW),(unsigned int)(ma)) 1842#define MARR(ma) outpw(FM_A(FM_MARR),(unsigned int)(ma)) 1843 1844/* 1845 * read/write from/to memory data register 1846 */ 1847/* write double word */ 1848#define MDRW(dd) outpw(FM_A(FM_MDRU),(unsigned int)((dd)>>16)) ;\ 1849 outpw(FM_A(FM_MDRL),(unsigned int)(dd)) 1850 1851#ifndef WINNT 1852/* read double word */ 1853#define MDRR() (((long)inpw(FM_A(FM_MDRU))<<16) + inpw(FM_A(FM_MDRL))) 1854 1855/* read FORMAC+ 32-bit status register */ 1856#define GET_ST1() (((long)inpw(FM_A(FM_ST1U))<<16) + inpw(FM_A(FM_ST1L))) 1857#define GET_ST2() (((long)inpw(FM_A(FM_ST2U))<<16) + inpw(FM_A(FM_ST2L))) 1858#ifdef SUPERNET_3 1859#define GET_ST3() (((long)inpw(FM_A(FM_ST3U))<<16) + inpw(FM_A(FM_ST3L))) 1860#endif 1861#else 1862/* read double word */ 1863#define MDRR() inp2w((FM_A(FM_MDRU)),(FM_A(FM_MDRL))) 1864 1865/* read FORMAC+ 32-bit status register */ 1866#define GET_ST1() inp2w((FM_A(FM_ST1U)),(FM_A(FM_ST1L))) 1867#define GET_ST2() inp2w((FM_A(FM_ST2U)),(FM_A(FM_ST2L))) 1868#ifdef SUPERNET_3 1869#define GET_ST3() inp2w((FM_A(FM_ST3U)),(FM_A(FM_ST3L))) 1870#endif 1871#endif 1872 1873/* Special timer macro for 82c54 */ 1874 /* timer access over data bus bit 8..15 */ 1875#define OUT_82c54_TIMER(port,val) outpw(TI_A(port),(val)<<8) 1876#define IN_82c54_TIMER(port) ((inpw(TI_A(port))>>8) & 0xff) 1877 1878 1879#ifdef DEBUG 1880#define DB_MAC(mac,st) {if (debug_mac & 0x1)\ 1881 printf("M") ;\ 1882 if (debug_mac & 0x2)\ 1883 printf("\tMAC %d status 0x%08lx\n",mac,st) ;\ 1884 if (debug_mac & 0x4)\ 1885 dp_mac(mac,st) ;\ 1886} 1887 1888#define DB_PLC(p,iev) { if (debug_plc & 0x1)\ 1889 printf("P") ;\ 1890 if (debug_plc & 0x2)\ 1891 printf("\tPLC %s Int 0x%04x\n", \ 1892 (p == PA) ? "A" : "B", iev) ;\ 1893 if (debug_plc & 0x4)\ 1894 dp_plc(p,iev) ;\ 1895} 1896 1897#define DB_TIMER() { if (debug_timer & 0x1)\ 1898 printf("T") ;\ 1899 if (debug_timer & 0x2)\ 1900 printf("\tTimer ISR\n") ;\ 1901} 1902 1903#else /* no DEBUG */ 1904 1905#define DB_MAC(mac,st) 1906#define DB_PLC(p,iev) 1907#define DB_TIMER() 1908 1909#endif /* no DEBUG */ 1910 1911#define INC_PTR(sp,cp,ep) if (++cp == ep) cp = sp 1912/* 1913 * timer defs 1914 */ 1915#define COUNT(t) ((t)<<6) /* counter */ 1916#define RW_OP(o) ((o)<<4) /* read/write operation */ 1917#define TMODE(m) ((m)<<1) /* timer mode */ 1918 1919#endif 1920