LXR linux-old/arch/sh64/mach-cayman/setup.c

   1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * arch/sh64/mach-cayman/setup.c
   7 *
   8 * SH5 Cayman support
   9 *
  10 * This file handles the architecture-dependent parts of initialization
  11 *
  12 * Copyright David J. Mckay.
  13 * Needs major work!
  14 *
  15 * benedict.gaster@superh.com:   3rd May 2002
  16 *    Added support for ramdisk, removing statically linked romfs at the same time.
  17 *
  18 * lethal@linux-sh.org:          15th May 2003
  19 *    Use the generic procfs cpuinfo interface, just return a valid board name.
  20 */
  21
  22#include <linux/stddef.h>
  23#include <linux/init.h>
  24#include <linux/config.h>
  25#include <linux/mm.h>
  26#include <linux/bootmem.h>
  27#include <linux/delay.h>
  28#include <linux/kernel.h>
  29#include <linux/seq_file.h>
  30#include <asm/processor.h>
  31#include <asm/platform.h>
  32#include <asm/io.h>
  33#include <asm/irq.h>
  34#include <asm/page.h>
  35
  36#define RES_COUNT(res) ((sizeof((res))/sizeof(struct resource)))
  37
  38/*
  39 * Platform Dependent Interrupt Priorities.
  40 */
  41
  42/* Using defaults defined in irq.h */
  43#define RES NO_PRIORITY         /* Disabled */
  44#define IR0 IRL0_PRIORITY       /* IRLs */
  45#define IR1 IRL1_PRIORITY
  46#define IR2 IRL2_PRIORITY
  47#define IR3 IRL3_PRIORITY
  48#define PCA INTA_PRIORITY       /* PCI Ints */
  49#define PCB INTB_PRIORITY
  50#define PCC INTC_PRIORITY
  51#define PCD INTD_PRIORITY
  52#define SER TOP_PRIORITY
  53#define ERR TOP_PRIORITY
  54#define PW0 TOP_PRIORITY
  55#define PW1 TOP_PRIORITY
  56#define PW2 TOP_PRIORITY
  57#define PW3 TOP_PRIORITY
  58#define DM0 NO_PRIORITY         /* DMA Ints */
  59#define DM1 NO_PRIORITY
  60#define DM2 NO_PRIORITY
  61#define DM3 NO_PRIORITY
  62#define DAE NO_PRIORITY
  63#define TU0 TIMER_PRIORITY      /* TMU Ints */
  64#define TU1 NO_PRIORITY
  65#define TU2 NO_PRIORITY
  66#define TI2 NO_PRIORITY
  67#define ATI NO_PRIORITY         /* RTC Ints */
  68#define PRI NO_PRIORITY
  69#define CUI RTC_PRIORITY
  70#define ERI SCIF_PRIORITY       /* SCIF Ints */
  71#define RXI SCIF_PRIORITY
  72#define BRI SCIF_PRIORITY
  73#define TXI SCIF_PRIORITY
  74#define ITI TOP_PRIORITY        /* WDT Ints */
  75
  76/* Setup for the SMSC FDC37C935 */
  77#define SMSC_SUPERIO_BASE       0x04000000
  78#define SMSC_CONFIG_PORT_ADDR   0x3f0
  79#define SMSC_INDEX_PORT_ADDR    SMSC_CONFIG_PORT_ADDR
  80#define SMSC_DATA_PORT_ADDR     0x3f1
  81
  82#define SMSC_ENTER_CONFIG_KEY   0x55
  83#define SMSC_EXIT_CONFIG_KEY    0xaa
  84
  85#define SMCS_LOGICAL_DEV_INDEX  0x07
  86#define SMSC_DEVICE_ID_INDEX    0x20
  87#define SMSC_DEVICE_REV_INDEX   0x21
  88#define SMSC_ACTIVATE_INDEX     0x30
  89#define SMSC_PRIMARY_INT_INDEX  0x70
  90#define SMSC_SECONDARY_INT_INDEX 0x72
  91
  92#define SMSC_KEYBOARD_DEVICE 7
  93
  94#define SMSC_SUPERIO_READ_INDEXED(index) ({ \
  95        outb((index), SMSC_INDEX_PORT_ADDR); \
  96        inb(SMSC_DATA_PORT_ADDR); })
  97#define SMSC_SUPERIO_WRITE_INDEXED(val, index) ({ \
  98        outb((index), SMSC_INDEX_PORT_ADDR); \
  99        outb((val),   SMSC_DATA_PORT_ADDR); })
 100
 101unsigned long smsc_superio_virt;
 102
 103/*
 104 * Platform dependent structures: maps and parms block.
 105 */
 106struct resource io_resources[] = {
 107        /* To be updated with external devices */
 108};
 109
 110struct resource kram_resources[] = {
 111        { "Kernel code", 0, 0 },        /* These must be last in the array */
 112        { "Kernel data", 0, 0 }         /* These must be last in the array */
 113};
 114
 115struct resource xram_resources[] = {
 116        /* To be updated with external devices */
 117};
 118
 119struct resource rom_resources[] = {
 120        /* To be updated with external devices */
 121};
 122
 123struct sh64_platform platform_parms = {
 124        .readonly_rootfs =      1,
 125        .initial_root_dev =     0x0100,
 126        .loader_type =          1,
 127        .io_res_p =             io_resources,
 128        .io_res_count =         RES_COUNT(io_resources),
 129        .kram_res_p =           kram_resources,
 130        .kram_res_count =       RES_COUNT(kram_resources),
 131        .xram_res_p =           xram_resources,
 132        .xram_res_count =       RES_COUNT(xram_resources),
 133        .rom_res_p =            rom_resources,
 134        .rom_res_count =        RES_COUNT(rom_resources),
 135};
 136
 137int platform_int_priority[NR_INTC_IRQS] = {
 138        IR0, IR1, IR2, IR3, PCA, PCB, PCC, PCD, /* IRQ  0- 7 */
 139        RES, RES, RES, RES, SER, ERR, PW3, PW2, /* IRQ  8-15 */
 140        PW1, PW0, DM0, DM1, DM2, DM3, DAE, RES, /* IRQ 16-23 */
 141        RES, RES, RES, RES, RES, RES, RES, RES, /* IRQ 24-31 */
 142        TU0, TU1, TU2, TI2, ATI, PRI, CUI, ERI, /* IRQ 32-39 */
 143        RXI, BRI, TXI, RES, RES, RES, RES, RES, /* IRQ 40-47 */
 144        RES, RES, RES, RES, RES, RES, RES, RES, /* IRQ 48-55 */
 145        RES, RES, RES, RES, RES, RES, RES, ITI, /* IRQ 56-63 */
 146};
 147
 148static int __init smsc_superio_setup(void)
 149{
 150        unsigned char devid, devrev;
 151
 152        smsc_superio_virt = onchip_remap(SMSC_SUPERIO_BASE, 1024, "SMSC SuperIO");
 153        if (!smsc_superio_virt) {
 154                panic("Unable to remap SMSC SuperIO\n");
 155        }
 156
 157        /* Initially the chip is in run state */
 158        /* Put it into configuration state */
 159        outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
 160        outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
 161
 162        /* Read device ID info */
 163        devid = SMSC_SUPERIO_READ_INDEXED(SMSC_DEVICE_ID_INDEX);
 164        devrev = SMSC_SUPERIO_READ_INDEXED(SMSC_DEVICE_REV_INDEX);
 165        printk("SMSC SuperIO devid %02x rev %02x\n", devid, devrev);
 166
 167        /* Select the keyboard device */
 168        SMSC_SUPERIO_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX);
 169
 170        /* enable it */
 171        SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);     
 172
 173        /* Select the interrupts */
 174        /* On a PC keyboard is IRQ1, mouse is IRQ12 */
 175        SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_PRIMARY_INT_INDEX);
 176        SMSC_SUPERIO_WRITE_INDEXED(12, SMSC_SECONDARY_INT_INDEX);
 177
 178        /* Exit the configuraton state */
 179        outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
 180
 181        return 0;
 182}
 183
 184/* This is grotty, but, because kernel is always referenced on the link line
 185 * before any devices, this is safe.
 186 */
 187__initcall(smsc_superio_setup);
 188
 189void __init platform_setup(void)
 190{
 191        /* Cayman platform leaves the decision to head.S, for now */
 192        platform_parms.fpu_flags = fpu_in_use;
 193}
 194
 195void __init platform_monitor(void)
 196{
 197        /* Nothing yet .. */
 198}
 199
 200void __init platform_reserve(void)
 201{
 202        /* Nothing yet .. */
 203}
 204
 205const char *get_system_type(void)
 206{
 207        return "Hitachi Cayman";
 208}
 209
 210