LXR linux-old/arch/mips/vr41xx/common/pciu.h

   1/*
   2 * arch/mips/vr41xx/common/pciu.h
   3 *
   4 * Include file for PCI Control Unit of the NEC VR4100 series.
   5 *
   6 * Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com>
   7 *
   8 * 2002-2003 (c) MontaVista, Software, Inc. This file is licensed under
   9 * the terms of the GNU General Public License version 2. This program
  10 * is licensed "as is" without any warranty of any kind, whether express
  11 * or implied.
  12 */
  13/*
  14 * Changes:
  15 *  MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
  16 *  - New creation, NEC VR4122 and VR4131 are supported.
  17 */
  18#ifndef __VR41XX_PCIU_H
  19#define __VR41XX_PCIU_H
  20
  21#include <linux/config.h>
  22#include <asm/addrspace.h>
  23
  24#define BIT(x)  (1U << (x))
  25
  26#define PCIMMAW1REG                     KSEG1ADDR(0x0f000c00)
  27#define PCIMMAW2REG                     KSEG1ADDR(0x0f000c04)
  28#define PCITAW1REG                      KSEG1ADDR(0x0f000c08)
  29#define PCITAW2REG                      KSEG1ADDR(0x0f000c0c)
  30#define PCIMIOAWREG                     KSEG1ADDR(0x0f000c10)
  31#define INTERNAL_BUS_BASE_ADDRESS       0xff000000U
  32#define ADDRESS_MASK                    0x000fe000U
  33#define PCI_ACCESS_ENABLE               BIT(12)
  34#define PCI_ADDRESS_SETTING             0x000000ffU
  35
  36#define PCICONFDREG                     KSEG1ADDR(0x0f000c14)
  37#define PCICONFAREG                     KSEG1ADDR(0x0f000c18)
  38#define PCIMAILREG                      KSEG1ADDR(0x0f000c1c)
  39
  40#define BUSERRADREG                     KSEG1ADDR(0x0f000c24)
  41#define ERROR_ADDRESS                   0xfffffffcU
  42
  43#define INTCNTSTAREG                    KSEG1ADDR(0x0f000c28)
  44#define MABTCLR                         BIT(31)
  45#define TRDYCLR                         BIT(30)
  46#define PARCLR                          BIT(29)
  47#define MBCLR                           BIT(28)
  48#define SERRCLR                         BIT(27)
  49
  50#define PCIEXACCREG                     KSEG1ADDR(0x0f000c2c)
  51#define UNLOCK                          BIT(1)
  52#define EAREQ                           BIT(0)
  53
  54#define PCIRECONTREG                    KSEG1ADDR(0x0f000c30)
  55#define RTRYCNT                         0xffU
  56
  57#define PCIENREG                        KSEG1ADDR(0x0f000c34)
  58#define CONFIG_DONE                     BIT(2)
  59
  60#define PCICLKSELREG                    KSEG1ADDR(0x0f000c38)
  61#define EQUAL_VTCLOCK                   0x2U
  62#define HALF_VTCLOCK                    0x0U
  63#define QUARTER_VTCLOCK                 0x1U
  64
  65#define PCITRDYVREG                     KSEG1ADDR(0x0f000c3c)
  66
  67#define PCICLKRUNREG                    KSEG1ADDR(0x0f000c60)
  68
  69#define VENDORIDREG                     KSEG1ADDR(0x0f000d00)
  70
  71#define MPCIINTREG                      KSEG1ADDR(0x0f0000b2)
  72
  73#define MAX_PCI_CLOCK                   33333333
  74
  75static inline int pciu_read_config_byte(int where, uint8_t *val)
  76{
  77        uint32_t data;
  78
  79        if (where > 0xff)
  80                return PCIBIOS_BAD_REGISTER_NUMBER;
  81
  82        data = readl(VENDORIDREG + (where & 0xfc));
  83        *val = (uint8_t)(data >> ((where & 3) << 3));
  84
  85        return PCIBIOS_SUCCESSFUL;
  86}
  87
  88static inline int pciu_read_config_word(int where, uint16_t *val)
  89{
  90        uint32_t data;
  91
  92        if (where > 0xff || (where & 1))
  93                return PCIBIOS_BAD_REGISTER_NUMBER;
  94
  95        data = readl(VENDORIDREG + (where & 0xfc));
  96        *val = (uint16_t)(data >> ((where & 2) << 3));
  97
  98        return PCIBIOS_SUCCESSFUL;
  99}
 100
 101static inline int pciu_read_config_dword(int where, uint32_t *val)
 102{
 103        if (where > 0xff || (where & 3))
 104                return PCIBIOS_BAD_REGISTER_NUMBER;
 105
 106        *val = readl(VENDORIDREG + where);
 107
 108        return PCIBIOS_SUCCESSFUL;
 109}
 110
 111static inline int pciu_write_config_byte(int where, uint8_t val)
 112{
 113        uint32_t data;
 114        int shift;
 115
 116        if (where > 0xff)
 117                return PCIBIOS_BAD_REGISTER_NUMBER;
 118
 119        data = readl(VENDORIDREG + (where & 0xfc));
 120        shift = (where & 3) << 3;
 121        data &= ~(0xffU << shift);
 122        data |= (uint32_t)val << shift;
 123        writel(data, VENDORIDREG + (where & 0xfc));
 124
 125        return 0;
 126}
 127
 128static inline int pciu_write_config_word(int where, uint16_t val)
 129{
 130        uint32_t data;
 131        int shift;
 132
 133        if (where > 0xff || (where & 1))
 134                return PCIBIOS_BAD_REGISTER_NUMBER;
 135
 136        data = readl(VENDORIDREG + (where & 0xfc));
 137        shift = (where & 2) << 3;
 138        data &= ~(0xffffU << shift);
 139        data |= (uint32_t)val << shift;
 140        writel(data, VENDORIDREG + (where & 0xfc));
 141
 142        return 0;
 143}
 144
 145static inline int pciu_write_config_dword(int where, uint32_t val)
 146{
 147        if (where > 0xff || (where & 3))
 148                return PCIBIOS_BAD_REGISTER_NUMBER;
 149
 150        writel(val, VENDORIDREG + where);
 151
 152        return 0;
 153}
 154
 155#endif /* __VR41XX_PCIU_H */
 156