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13#include <linux/config.h>
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/sched.h>
17#include <linux/mm.h>
18
19#include <asm/page.h>
20#include <asm/pgtable.h>
21#include <asm/mmu_context.h>
22#include <asm/system.h>
23#include <asm/isadep.h>
24#include <asm/io.h>
25#include <asm/bootinfo.h>
26#include <asm/cpu.h>
27
28#undef DEBUG_TLB
29
30extern char except_vec0_r2300;
31
32
33#define BARRIER \
34 __asm__ __volatile__( \
35 ".set push\n\t" \
36 ".set noreorder\n\t" \
37 "nop\n\t" \
38 ".set pop\n\t")
39
40int r3k_have_wired_reg;
41
42
43void local_flush_tlb_all(void)
44{
45 unsigned long flags;
46 unsigned long old_ctx;
47 int entry;
48
49#ifdef DEBUG_TLB
50 printk("[tlball]");
51#endif
52
53 local_irq_save(flags);
54 old_ctx = read_c0_entryhi() & ASID_MASK;
55 write_c0_entrylo0(0);
56 entry = r3k_have_wired_reg ? read_c0_wired() : 8;
57 for (; entry < current_cpu_data.tlbsize; entry++) {
58 write_c0_index(entry << 8);
59 write_c0_entryhi((entry | 0x80000) << 12);
60 BARRIER;
61 tlb_write_indexed();
62 }
63 write_c0_entryhi(old_ctx);
64 local_irq_restore(flags);
65}
66
67void local_flush_tlb_mm(struct mm_struct *mm)
68{
69 int cpu = smp_processor_id();
70
71 if (cpu_context(cpu, mm) != 0) {
72#ifdef DEBUG_TLB
73 printk("[tlbmm<%lu>]", (unsigned long)cpu_context(cpu, mm));
74#endif
75 drop_mmu_context(mm, cpu);
76 }
77}
78
79void local_flush_tlb_range(struct mm_struct *mm, unsigned long start,
80 unsigned long end)
81{
82 int cpu = smp_processor_id();
83
84 if (cpu_context(cpu, mm) != 0) {
85 unsigned long flags;
86 int size;
87
88#ifdef DEBUG_TLB
89 printk("[tlbrange<%lu,0x%08lx,0x%08lx>]",
90 cpu_asid(cpu, mm), start, end);
91#endif
92 local_irq_save(flags);
93 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
94 if (size <= current_cpu_data.tlbsize) {
95 int oldpid = read_c0_entryhi() & ASID_MASK;
96 int newpid = cpu_asid(cpu, mm);
97
98 start &= PAGE_MASK;
99 end += PAGE_SIZE - 1;
100 end &= PAGE_MASK;
101 while (start < end) {
102 int idx;
103
104 write_c0_entryhi(start | newpid);
105 start += PAGE_SIZE;
106 tlb_probe();
107 idx = read_c0_index();
108 write_c0_entrylo0(0);
109 write_c0_entryhi(KSEG0);
110 if (idx < 0)
111 continue;
112 tlb_write_indexed();
113 }
114 write_c0_entryhi(oldpid);
115 } else {
116 drop_mmu_context(mm, cpu);
117 }
118 local_irq_restore(flags);
119 }
120}
121
122void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
123{
124 int cpu = smp_processor_id();
125
126 if (!vma || cpu_context(cpu, vma->vm_mm) != 0) {
127 unsigned long flags;
128 int oldpid, newpid, idx;
129
130#ifdef DEBUG_TLB
131 printk("[tlbpage<%lu,0x%08lx>]", cpu_context(cpu, vma->vm_mm), page);
132#endif
133 newpid = cpu_asid(cpu, vma->vm_mm);
134 page &= PAGE_MASK;
135 local_irq_save(flags);
136 oldpid = read_c0_entryhi() & ASID_MASK;
137 write_c0_entryhi(page | newpid);
138 BARRIER;
139 tlb_probe();
140 idx = read_c0_index();
141 write_c0_entrylo0(0);
142 write_c0_entryhi(KSEG0);
143 if (idx < 0)
144 goto finish;
145 tlb_write_indexed();
146
147finish:
148 write_c0_entryhi(oldpid);
149 local_irq_restore(flags);
150 }
151}
152
153void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
154{
155 unsigned long flags;
156 int idx, pid;
157
158
159
160
161 if (current->active_mm != vma->vm_mm)
162 return;
163
164 pid = read_c0_entryhi() & ASID_MASK;
165
166#ifdef DEBUG_TLB
167 if ((pid != cpu_asid(cpu, vma->vm_mm)) || (cpu_context(cpu, vma->vm_mm) == 0)) {
168 printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%lu tlbpid=%d\n",
169 (cpu_context(cpu, vma->vm_mm)), pid);
170 }
171#endif
172
173 local_irq_save(flags);
174 address &= PAGE_MASK;
175 write_c0_entryhi(address | pid);
176 BARRIER;
177 tlb_probe();
178 idx = read_c0_index();
179 write_c0_entrylo0(pte_val(pte));
180 write_c0_entryhi(address | pid);
181 if (idx < 0) {
182 tlb_write_random();
183 } else {
184 tlb_write_indexed();
185 }
186 write_c0_entryhi(pid);
187 local_irq_restore(flags);
188}
189
190void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
191 unsigned long entryhi, unsigned long pagemask)
192{
193 unsigned long flags;
194 unsigned long old_ctx;
195 static unsigned long wired = 0;
196
197 if (r3k_have_wired_reg) {
198 unsigned long old_pagemask;
199 unsigned long w;
200
201#ifdef DEBUG_TLB
202 printk("[tlbwired<entry lo0 %8x, hi %8x\n, pagemask %8x>]\n",
203 entrylo0, entryhi, pagemask);
204#endif
205
206 local_irq_save(flags);
207
208 old_ctx = read_c0_entryhi() & ASID_MASK;
209 old_pagemask = read_c0_pagemask();
210 w = read_c0_wired();
211 write_c0_wired(w + 1);
212 if (read_c0_wired() != w + 1) {
213 printk("[tlbwired] No WIRED reg?\n");
214 return;
215 }
216 write_c0_index(w << 8);
217 write_c0_pagemask(pagemask);
218 write_c0_entryhi(entryhi);
219 write_c0_entrylo0(entrylo0);
220 BARRIER;
221 tlb_write_indexed();
222
223 write_c0_entryhi(old_ctx);
224 write_c0_pagemask(old_pagemask);
225 local_flush_tlb_all();
226 local_irq_restore(flags);
227
228 } else if (wired < 8) {
229#ifdef DEBUG_TLB
230 printk("[tlbwired<entry lo0 %8x, hi %8x\n>]\n",
231 entrylo0, entryhi);
232#endif
233
234 local_irq_save(flags);
235 old_ctx = read_c0_entryhi() & ASID_MASK;
236 write_c0_entrylo0(entrylo0);
237 write_c0_entryhi(entryhi);
238 write_c0_index(wired);
239 wired++;
240 tlb_write_indexed();
241 write_c0_entryhi(old_ctx);
242 local_flush_tlb_all();
243 local_irq_restore(flags);
244 }
245}
246
247void __init r3k_tlb_init(void)
248{
249 local_flush_tlb_all();
250 memcpy((void *)KSEG0, &except_vec0_r2300, 0x80);
251 flush_icache_range(KSEG0, KSEG0 + 0x80);
252}
253
