LXR linux-old/arch/ia64/mm/tlb.c

   1/*
   2 * TLB support routines.
   3 *
   4 * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
   5 *      David Mosberger-Tang <davidm@hpl.hp.com>
   6 *
   7 * 08/02/00 A. Mallick <asit.k.mallick@intel.com>
   8 *              Modified RID allocation for SMP
   9 *          Goutham Rao <goutham.rao@intel.com>
  10 *              IPI based ptc implementation and A-step IPI implementation.
  11 */
  12#include <linux/config.h>
  13#include <linux/init.h>
  14#include <linux/kernel.h>
  15#include <linux/sched.h>
  16#include <linux/smp.h>
  17#include <linux/mm.h>
  18
  19#include <asm/delay.h>
  20#include <asm/mmu_context.h>
  21#include <asm/pgalloc.h>
  22#include <asm/pal.h>
  23
  24static struct {
  25        unsigned long mask;     /* mask of supported purge page-sizes */
  26        unsigned long max_bits; /* log2() of largest supported purge page-size */
  27} purge;
  28
  29struct ia64_ctx ia64_ctx = {
  30        .lock =         SPIN_LOCK_UNLOCKED,
  31        .next =         1,
  32        .limit =        (1 << 15) - 1,          /* start out with the safe (architected) limit */
  33        .max_ctx =      ~0U
  34};
  35
  36/*
  37 * Acquire the ia64_ctx.lock before calling this function!
  38 */
  39void
  40wrap_mmu_context (struct mm_struct *mm)
  41{
  42        unsigned long tsk_context, max_ctx = ia64_ctx.max_ctx;
  43        struct task_struct *tsk;
  44        int i;
  45
  46        if (ia64_ctx.next > max_ctx)
  47                ia64_ctx.next = 300;    /* skip daemons */
  48        ia64_ctx.limit = max_ctx + 1;
  49
  50        /*
  51         * Scan all the task's mm->context and set proper safe range
  52         */
  53
  54        read_lock(&tasklist_lock);
  55  repeat:
  56        for_each_task(tsk) {
  57                if (!tsk->mm)
  58                        continue;
  59                tsk_context = tsk->mm->context;
  60                if (tsk_context == ia64_ctx.next) {
  61                        if (++ia64_ctx.next >= ia64_ctx.limit) {
  62                                /* empty range: reset the range limit and start over */
  63                                if (ia64_ctx.next > max_ctx)
  64                                        ia64_ctx.next = 300;
  65                                ia64_ctx.limit = max_ctx + 1;
  66                                goto repeat;
  67                        }
  68                }
  69                if ((tsk_context > ia64_ctx.next) && (tsk_context < ia64_ctx.limit))
  70                        ia64_ctx.limit = tsk_context;
  71        }
  72        read_unlock(&tasklist_lock);
  73        /*
  74         * Can't call flush_tlb_all() here because of race condition with scheduler [EF]
  75         * and because interrupts are disabled during context switch.
  76         */
  77        for (i = 0; i < NR_CPUS; ++i)
  78                if (cpu_online(i) && (i != smp_processor_id()))
  79                        cpu_data(i)->need_tlb_flush = 1;
  80        local_flush_tlb_all();
  81}
  82
  83void
  84ia64_global_tlb_purge (unsigned long start, unsigned long end, unsigned long nbits)
  85{
  86        static spinlock_t ptcg_lock = SPIN_LOCK_UNLOCKED;
  87
  88        /* HW requires global serialization of ptc.ga.  */
  89        spin_lock(&ptcg_lock);
  90        {
  91                do {
  92                        /*
  93                         * Flush ALAT entries also.
  94                         */
  95                        asm volatile ("ptc.ga %0,%1;;srlz.i;;" :: "r"(start), "r"(nbits<<2)
  96                                      : "memory");
  97                        start += (1UL << nbits);
  98                } while (start < end);
  99        }
 100        spin_unlock(&ptcg_lock);
 101}
 102
 103void
 104local_flush_tlb_all (void)
 105{
 106        unsigned long i, j, flags, count0, count1, stride0, stride1, addr;
 107
 108        addr    = local_cpu_data->ptce_base;
 109        count0  = local_cpu_data->ptce_count[0];
 110        count1  = local_cpu_data->ptce_count[1];
 111        stride0 = local_cpu_data->ptce_stride[0];
 112        stride1 = local_cpu_data->ptce_stride[1];
 113
 114        local_irq_save(flags);
 115        for (i = 0; i < count0; ++i) {
 116                for (j = 0; j < count1; ++j) {
 117                        asm volatile ("ptc.e %0" :: "r"(addr));
 118                        addr += stride1;
 119                }
 120                addr += stride0;
 121        }
 122        local_irq_restore(flags);
 123        ia64_insn_group_barrier();
 124        ia64_srlz_i();                  /* srlz.i implies srlz.d */
 125        ia64_insn_group_barrier();
 126}
 127
 128void
 129flush_tlb_range (struct mm_struct *mm, unsigned long start, unsigned long end)
 130{
 131        unsigned long size = end - start;
 132        unsigned long nbits;
 133
 134        if (mm != current->active_mm) {
 135                /* this does happen, but perhaps it's not worth optimizing for? */
 136#ifdef CONFIG_SMP
 137                flush_tlb_all();
 138#else
 139                mm->context = 0;
 140#endif
 141                return;
 142        }
 143
 144        nbits = ia64_fls(size + 0xfff);
 145        while (unlikely (((1UL << nbits) & purge.mask) == 0) && (nbits < purge.max_bits))
 146                ++nbits;
 147        if (nbits > purge.max_bits)
 148                nbits = purge.max_bits;
 149        start &= ~((1UL << nbits) - 1);
 150
 151# ifdef CONFIG_SMP
 152        platform_global_tlb_purge(start, end, nbits);
 153# else
 154        do {
 155                asm volatile ("ptc.l %0,%1" :: "r"(start), "r"(nbits<<2) : "memory");
 156                start += (1UL << nbits);
 157        } while (start < end);
 158# endif
 159
 160        ia64_insn_group_barrier();
 161        ia64_srlz_i();                  /* srlz.i implies srlz.d */
 162        ia64_insn_group_barrier();
 163}
 164
 165void __init
 166ia64_tlb_init (void)
 167{
 168        ia64_ptce_info_t ptce_info;
 169        unsigned long tr_pgbits;
 170        long status;
 171
 172        if ((status = ia64_pal_vm_page_size(&tr_pgbits, &purge.mask)) != 0) {
 173                printk(KERN_ERR "PAL_VM_PAGE_SIZE failed with status=%ld;"
 174                       "defaulting to architected purge page-sizes.\n", status);
 175                purge.mask = 0x115557000;
 176        }
 177        purge.max_bits = ia64_fls(purge.mask);
 178
 179        ia64_get_ptce(&ptce_info);
 180        local_cpu_data->ptce_base = ptce_info.base;
 181        local_cpu_data->ptce_count[0] = ptce_info.count[0];
 182        local_cpu_data->ptce_count[1] = ptce_info.count[1];
 183        local_cpu_data->ptce_stride[0] = ptce_info.stride[0];
 184        local_cpu_data->ptce_stride[1] = ptce_info.stride[1];
 185
 186        local_flush_tlb_all();          /* nuke left overs from bootstrapping... */
 187}
 188