1#ifndef __ASM_APICDEF_H
2#define __ASM_APICDEF_H
3
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9
10
11#define APIC_DEFAULT_PHYS_BASE 0xfee00000
12
13#define APIC_ID 0x20
14#define APIC_ID_MASK (0x0F<<24)
15#define GET_APIC_ID(x) (((x)>>24)&0x0F)
16#define APIC_LVR 0x30
17#define APIC_LVR_MASK 0xFF00FF
18#define GET_APIC_VERSION(x) ((x)&0xFF)
19#define GET_APIC_MAXLVT(x) (((x)>>16)&0xFF)
20#define APIC_INTEGRATED(x) ((x)&0xF0)
21#define APIC_XAPIC_SUPPORT(x) ((x)>=0x14)
22#define APIC_TASKPRI 0x80
23#define APIC_TPRI_MASK 0xFF
24#define APIC_ARBPRI 0x90
25#define APIC_ARBPRI_MASK 0xFF
26#define APIC_PROCPRI 0xA0
27#define APIC_EOI 0xB0
28#define APIC_EIO_ACK 0x0
29#define APIC_RRR 0xC0
30#define APIC_LDR 0xD0
31#define APIC_LDR_MASK (0xFF<<24)
32#define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFF)
33#define SET_APIC_LOGICAL_ID(x) (((x)<<24))
34#define APIC_ALL_CPUS 0xFF
35#define APIC_DFR 0xE0
36#define APIC_DFR_CLUSTER 0x0FFFFFFFul
37#define APIC_DFR_FLAT 0xFFFFFFFFul
38#define APIC_SPIV 0xF0
39#define APIC_SPIV_FOCUS_DISABLED (1<<9)
40#define APIC_SPIV_APIC_ENABLED (1<<8)
41#define APIC_ISR 0x100
42#define APIC_TMR 0x180
43#define APIC_IRR 0x200
44#define APIC_ESR 0x280
45#define APIC_ESR_SEND_CS 0x00001
46#define APIC_ESR_RECV_CS 0x00002
47#define APIC_ESR_SEND_ACC 0x00004
48#define APIC_ESR_RECV_ACC 0x00008
49#define APIC_ESR_SENDILL 0x00020
50#define APIC_ESR_RECVILL 0x00040
51#define APIC_ESR_ILLREGA 0x00080
52#define APIC_ICR 0x300
53#define APIC_DEST_SELF 0x40000
54#define APIC_DEST_ALLINC 0x80000
55#define APIC_DEST_ALLBUT 0xC0000
56#define APIC_ICR_RR_MASK 0x30000
57#define APIC_ICR_RR_INVALID 0x00000
58#define APIC_ICR_RR_INPROG 0x10000
59#define APIC_ICR_RR_VALID 0x20000
60#define APIC_INT_LEVELTRIG 0x08000
61#define APIC_INT_ASSERT 0x04000
62#define APIC_ICR_BUSY 0x01000
63#define APIC_DEST_PHYSICAL 0x00000
64#define APIC_DEST_LOGICAL 0x00800
65#define APIC_DM_FIXED 0x00000
66#define APIC_DM_LOWEST 0x00100
67#define APIC_DM_SMI 0x00200
68#define APIC_DM_REMRD 0x00300
69#define APIC_DM_NMI 0x00400
70#define APIC_DM_INIT 0x00500
71#define APIC_DM_STARTUP 0x00600
72#define APIC_DM_EXTINT 0x00700
73#define APIC_VECTOR_MASK 0x000FF
74#define APIC_ICR2 0x310
75#define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF)
76#define SET_APIC_DEST_FIELD(x) ((x)<<24)
77#define APIC_LVTT 0x320
78#define APIC_LVTPC 0x340
79#define APIC_LVT0 0x350
80#define APIC_LVT_TIMER_BASE_MASK (0x3<<18)
81#define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3)
82#define SET_APIC_TIMER_BASE(x) (((x)<<18))
83#define APIC_TIMER_BASE_CLKIN 0x0
84#define APIC_TIMER_BASE_TMBASE 0x1
85#define APIC_TIMER_BASE_DIV 0x2
86#define APIC_LVT_TIMER_PERIODIC (1<<17)
87#define APIC_LVT_MASKED (1<<16)
88#define APIC_LVT_LEVEL_TRIGGER (1<<15)
89#define APIC_LVT_REMOTE_IRR (1<<14)
90#define APIC_INPUT_POLARITY (1<<13)
91#define APIC_SEND_PENDING (1<<12)
92#define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
93#define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8))
94#define APIC_MODE_FIXED 0x0
95#define APIC_MODE_NMI 0x4
96#define APIC_MODE_EXINT 0x7
97#define APIC_LVT1 0x360
98#define APIC_LVTERR 0x370
99#define APIC_TMICT 0x380
100#define APIC_TMCCT 0x390
101#define APIC_TDCR 0x3E0
102#define APIC_TDR_DIV_TMBASE (1<<2)
103#define APIC_TDR_DIV_1 0xB
104#define APIC_TDR_DIV_2 0x0
105#define APIC_TDR_DIV_4 0x1
106#define APIC_TDR_DIV_8 0x2
107#define APIC_TDR_DIV_16 0x3
108#define APIC_TDR_DIV_32 0x8
109#define APIC_TDR_DIV_64 0x9
110#define APIC_TDR_DIV_128 0xA
111
112#define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
113
114#ifdef CONFIG_X86_CLUSTERED_APIC
115#define MAX_IO_APICS 32
116#else
117#define MAX_IO_APICS 8
118#endif
119
120
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122
123
124
125#define APIC_BROADCAST_ID_XAPIC (0xFF)
126#define APIC_BROADCAST_ID_APIC (0x0F)
127
128
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132
133
134#define u32 unsigned int
135
136#define lapic ((volatile struct local_apic *)APIC_BASE)
137
138struct local_apic {
139
140 struct { u32 __reserved[4]; } __reserved_01;
141
142 struct { u32 __reserved[4]; } __reserved_02;
143
144 struct {
145 u32 __reserved_1 : 24,
146 phys_apic_id : 4,
147 __reserved_2 : 4;
148 u32 __reserved[3];
149 } id;
150
151 const
152 struct {
153 u32 version : 8,
154 __reserved_1 : 8,
155 max_lvt : 8,
156 __reserved_2 : 8;
157 u32 __reserved[3];
158 } version;
159
160 struct { u32 __reserved[4]; } __reserved_03;
161
162 struct { u32 __reserved[4]; } __reserved_04;
163
164 struct { u32 __reserved[4]; } __reserved_05;
165
166 struct { u32 __reserved[4]; } __reserved_06;
167
168 struct {
169 u32 priority : 8,
170 __reserved_1 : 24;
171 u32 __reserved_2[3];
172 } tpr;
173
174 const
175 struct {
176 u32 priority : 8,
177 __reserved_1 : 24;
178 u32 __reserved_2[3];
179 } apr;
180
181 const
182 struct {
183 u32 priority : 8,
184 __reserved_1 : 24;
185 u32 __reserved_2[3];
186 } ppr;
187
188 struct {
189 u32 eoi;
190 u32 __reserved[3];
191 } eoi;
192
193 struct { u32 __reserved[4]; } __reserved_07;
194
195 struct {
196 u32 __reserved_1 : 24,
197 logical_dest : 8;
198 u32 __reserved_2[3];
199 } ldr;
200
201 struct {
202 u32 __reserved_1 : 28,
203 model : 4;
204 u32 __reserved_2[3];
205 } dfr;
206
207 struct {
208 u32 spurious_vector : 8,
209 apic_enabled : 1,
210 focus_cpu : 1,
211 __reserved_2 : 22;
212 u32 __reserved_3[3];
213 } svr;
214
215 struct {
216 u32 bitfield;
217 u32 __reserved[3];
218 } isr [8];
219
220 struct {
221 u32 bitfield;
222 u32 __reserved[3];
223 } tmr [8];
224
225 struct {
226 u32 bitfield;
227 u32 __reserved[3];
228 } irr [8];
229
230 union {
231 struct {
232 u32 send_cs_error : 1,
233 receive_cs_error : 1,
234 send_accept_error : 1,
235 receive_accept_error : 1,
236 __reserved_1 : 1,
237 send_illegal_vector : 1,
238 receive_illegal_vector : 1,
239 illegal_register_address : 1,
240 __reserved_2 : 24;
241 u32 __reserved_3[3];
242 } error_bits;
243 struct {
244 u32 errors;
245 u32 __reserved_3[3];
246 } all_errors;
247 } esr;
248
249 struct { u32 __reserved[4]; } __reserved_08;
250
251 struct { u32 __reserved[4]; } __reserved_09;
252
253 struct { u32 __reserved[4]; } __reserved_10;
254
255 struct { u32 __reserved[4]; } __reserved_11;
256
257 struct { u32 __reserved[4]; } __reserved_12;
258
259 struct { u32 __reserved[4]; } __reserved_13;
260
261 struct { u32 __reserved[4]; } __reserved_14;
262
263 struct {
264 u32 vector : 8,
265 delivery_mode : 3,
266 destination_mode : 1,
267 delivery_status : 1,
268 __reserved_1 : 1,
269 level : 1,
270 trigger : 1,
271 __reserved_2 : 2,
272 shorthand : 2,
273 __reserved_3 : 12;
274 u32 __reserved_4[3];
275 } icr1;
276
277 struct {
278 union {
279 u32 __reserved_1 : 24,
280 phys_dest : 4,
281 __reserved_2 : 4;
282 u32 __reserved_3 : 24,
283 logical_dest : 8;
284 } dest;
285 u32 __reserved_4[3];
286 } icr2;
287
288 struct {
289 u32 vector : 8,
290 __reserved_1 : 4,
291 delivery_status : 1,
292 __reserved_2 : 3,
293 mask : 1,
294 timer_mode : 1,
295 __reserved_3 : 14;
296 u32 __reserved_4[3];
297 } lvt_timer;
298
299 struct { u32 __reserved[4]; } __reserved_15;
300
301 struct {
302 u32 vector : 8,
303 delivery_mode : 3,
304 __reserved_1 : 1,
305 delivery_status : 1,
306 __reserved_2 : 3,
307 mask : 1,
308 __reserved_3 : 15;
309 u32 __reserved_4[3];
310 } lvt_pc;
311
312 struct {
313 u32 vector : 8,
314 delivery_mode : 3,
315 __reserved_1 : 1,
316 delivery_status : 1,
317 polarity : 1,
318 remote_irr : 1,
319 trigger : 1,
320 mask : 1,
321 __reserved_2 : 15;
322 u32 __reserved_3[3];
323 } lvt_lint0;
324
325 struct {
326 u32 vector : 8,
327 delivery_mode : 3,
328 __reserved_1 : 1,
329 delivery_status : 1,
330 polarity : 1,
331 remote_irr : 1,
332 trigger : 1,
333 mask : 1,
334 __reserved_2 : 15;
335 u32 __reserved_3[3];
336 } lvt_lint1;
337
338 struct {
339 u32 vector : 8,
340 __reserved_1 : 4,
341 delivery_status : 1,
342 __reserved_2 : 3,
343 mask : 1,
344 __reserved_3 : 15;
345 u32 __reserved_4[3];
346 } lvt_error;
347
348 struct {
349 u32 initial_count;
350 u32 __reserved_2[3];
351 } timer_icr;
352
353 const
354 struct {
355 u32 curr_count;
356 u32 __reserved_2[3];
357 } timer_ccr;
358
359 struct { u32 __reserved[4]; } __reserved_16;
360
361 struct { u32 __reserved[4]; } __reserved_17;
362
363 struct { u32 __reserved[4]; } __reserved_18;
364
365 struct { u32 __reserved[4]; } __reserved_19;
366
367 struct {
368 u32 divisor : 4,
369 __reserved_1 : 28;
370 u32 __reserved_2[3];
371 } timer_dcr;
372
373 struct { u32 __reserved[4]; } __reserved_20;
374
375} __attribute__ ((packed));
376
377#undef u32
378
379#endif
380
