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43static char ixj_c_rcsid[] = "$Id: ixj.c,v 4.7 2001/08/13 06:19:33 craigs Exp $";
44static char ixj_c_revision[] = "$Revision: 4.7 $";
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246#include "ixj-ver.h"
247
248#define PERFMON_STATS
249#define IXJDEBUG 0
250#define MAXRINGS 5
251
252#include <linux/module.h>
253
254#include <linux/init.h>
255#include <linux/sched.h>
256#include <linux/kernel.h>
257#include <linux/fs.h>
258#include <linux/errno.h>
259#include <linux/slab.h>
260#include <linux/mm.h>
261#include <linux/ioport.h>
262#include <linux/interrupt.h>
263#include <linux/tqueue.h>
264#include <linux/proc_fs.h>
265#include <linux/poll.h>
266#include <linux/timer.h>
267#include <linux/delay.h>
268#include <linux/pci.h>
269
270#include <asm/io.h>
271#include <asm/segment.h>
272#include <asm/uaccess.h>
273
274#include <linux/isapnp.h>
275
276#include "ixj.h"
277
278#define TYPE(dev) (MINOR(dev) >> 4)
279#define NUM(dev) (MINOR(dev) & 0xf)
280
281static int ixjdebug;
282static int hertz = HZ;
283static int samplerate = 100;
284
285MODULE_PARM(ixjdebug, "i");
286
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305#ifdef IXJ_DYN_ALLOC
306
307static IXJ *ixj[IXJMAX];
308#define get_ixj(b) ixj[(b)]
309
310
311
312
313
314static IXJ *ixj_alloc()
315{
316 for(cnt=0; cnt<IXJMAX; cnt++)
317 {
318 if(ixj[cnt] == NULL || !ixj[cnt]->DSPbase)
319 {
320 j = kmalloc(sizeof(IXJ), GFP_KERNEL);
321 if (j == NULL)
322 return NULL;
323 ixj[cnt] = j;
324 return j;
325 }
326 }
327 return NULL;
328}
329
330static void ixj_fsk_free(IXJ *j)
331{
332 if(j->fskdata != NULL) {
333 kfree(j->fskdata);
334 j->fskdata = NULL;
335 }
336}
337
338static void ixj_fsk_alloc(IXJ *j)
339{
340 if(!j->fskdata) {
341 j->fskdata = kmalloc(8000, GFP_KERNEL);
342 if (!j->fskdata) {
343 if(ixjdebug & 0x0200) {
344 printk("IXJ phone%d - allocate failed\n", j->board);
345 }
346 return;
347 } else {
348 j->fsksize = 8000;
349 if(ixjdebug & 0x0200) {
350 printk("IXJ phone%d - allocate succeded\n", j->board);
351 }
352 }
353 }
354}
355
356#else
357
358static IXJ ixj[IXJMAX];
359#define get_ixj(b) (&ixj[(b)])
360
361
362
363
364
365static IXJ *ixj_alloc(void)
366{
367 int cnt;
368 for(cnt=0; cnt<IXJMAX; cnt++)
369 {
370 if(!ixj[cnt].DSPbase)
371 {
372 return &ixj[cnt];
373 }
374 }
375 return NULL;
376}
377
378static inline void ixj_fsk_free(IXJ *j) {;}
379
380static inline void ixj_fsk_alloc(IXJ *j)
381{
382 j->fsksize = 8000;
383}
384
385#endif
386
387#ifdef PERFMON_STATS
388#define ixj_perfmon(x) ((x)++)
389#else
390#define ixj_perfmon(x) do { } while(0)
391#endif
392
393static int ixj_convert_loaded;
394
395static int ixj_WriteDSPCommand(unsigned short, IXJ *j);
396
397
398
399
400
401
402
403
404static int Stub(IXJ * J, unsigned long arg)
405{
406 return 0;
407}
408
409static IXJ_REGFUNC ixj_DownloadG729 = &Stub;
410static IXJ_REGFUNC ixj_DownloadTS85 = &Stub;
411static IXJ_REGFUNC ixj_PreRead = &Stub;
412static IXJ_REGFUNC ixj_PostRead = &Stub;
413static IXJ_REGFUNC ixj_PreWrite = &Stub;
414static IXJ_REGFUNC ixj_PostWrite = &Stub;
415static IXJ_REGFUNC ixj_PreIoctl = &Stub;
416static IXJ_REGFUNC ixj_PostIoctl = &Stub;
417
418static void ixj_read_frame(IXJ *j);
419static void ixj_write_frame(IXJ *j);
420static void ixj_init_timer(IXJ *j);
421static void ixj_add_timer(IXJ * j);
422static void ixj_timeout(unsigned long ptr);
423static int read_filters(IXJ *j);
424static int LineMonitor(IXJ *j);
425static int ixj_fasync(int fd, struct file *, int mode);
426static int ixj_set_port(IXJ *j, int arg);
427static int ixj_set_pots(IXJ *j, int arg);
428static int ixj_hookstate(IXJ *j);
429static int ixj_record_start(IXJ *j);
430static void ixj_record_stop(IXJ *j);
431static void set_rec_volume(IXJ *j, int volume);
432static int get_rec_volume(IXJ *j);
433static int set_rec_codec(IXJ *j, int rate);
434static void ixj_vad(IXJ *j, int arg);
435static int ixj_play_start(IXJ *j);
436static void ixj_play_stop(IXJ *j);
437static int ixj_set_tone_on(unsigned short arg, IXJ *j);
438static int ixj_set_tone_off(unsigned short, IXJ *j);
439static int ixj_play_tone(IXJ *j, char tone);
440static void ixj_aec_start(IXJ *j, int level);
441static int idle(IXJ *j);
442static void ixj_ring_on(IXJ *j);
443static void ixj_ring_off(IXJ *j);
444static void aec_stop(IXJ *j);
445static void ixj_ringback(IXJ *j);
446static void ixj_busytone(IXJ *j);
447static void ixj_dialtone(IXJ *j);
448static void ixj_cpt_stop(IXJ *j);
449static char daa_int_read(IXJ *j);
450static char daa_CR_read(IXJ *j, int cr);
451static int daa_set_mode(IXJ *j, int mode);
452static int ixj_linetest(IXJ *j);
453static int ixj_daa_write(IXJ *j);
454static int ixj_daa_cid_read(IXJ *j);
455static void DAA_Coeff_US(IXJ *j);
456static void DAA_Coeff_UK(IXJ *j);
457static void DAA_Coeff_France(IXJ *j);
458static void DAA_Coeff_Germany(IXJ *j);
459static void DAA_Coeff_Australia(IXJ *j);
460static void DAA_Coeff_Japan(IXJ *j);
461static int ixj_init_filter(IXJ *j, IXJ_FILTER * jf);
462static int ixj_init_filter_raw(IXJ *j, IXJ_FILTER_RAW * jfr);
463static int ixj_init_tone(IXJ *j, IXJ_TONE * ti);
464static int ixj_build_cadence(IXJ *j, IXJ_CADENCE * cp);
465static int ixj_build_filter_cadence(IXJ *j, IXJ_FILTER_CADENCE * cp);
466
467static int SCI_Control(IXJ *j, int control);
468static int SCI_Prepare(IXJ *j);
469static int SCI_WaitHighSCI(IXJ *j);
470static int SCI_WaitLowSCI(IXJ *j);
471static DWORD PCIEE_GetSerialNumber(WORD wAddress);
472static int ixj_PCcontrol_wait(IXJ *j);
473static void ixj_pre_cid(IXJ *j);
474static void ixj_write_cid(IXJ *j);
475static void ixj_write_cid_bit(IXJ *j, int bit);
476static int set_base_frame(IXJ *j, int size);
477static int set_play_codec(IXJ *j, int rate);
478static void set_rec_depth(IXJ *j, int depth);
479static int ixj_mixer(long val, IXJ *j);
480
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494
495static inline void ixj_read_HSR(IXJ *j)
496{
497 j->hsr.bytes.low = inb_p(j->DSPbase + 8);
498 j->hsr.bytes.high = inb_p(j->DSPbase + 9);
499}
500
501static inline int IsControlReady(IXJ *j)
502{
503 ixj_read_HSR(j);
504 return j->hsr.bits.controlrdy ? 1 : 0;
505}
506
507static inline int IsPCControlReady(IXJ *j)
508{
509 j->pccr1.byte = inb_p(j->XILINXbase + 3);
510 return j->pccr1.bits.crr ? 1 : 0;
511}
512
513static inline int IsStatusReady(IXJ *j)
514{
515 ixj_read_HSR(j);
516 return j->hsr.bits.statusrdy ? 1 : 0;
517}
518
519static inline int IsRxReady(IXJ *j)
520{
521 ixj_read_HSR(j);
522 ixj_perfmon(j->rxreadycheck);
523 return j->hsr.bits.rxrdy ? 1 : 0;
524}
525
526static inline int IsTxReady(IXJ *j)
527{
528 ixj_read_HSR(j);
529 ixj_perfmon(j->txreadycheck);
530 return j->hsr.bits.txrdy ? 1 : 0;
531}
532
533static inline void set_play_volume(IXJ *j, int volume)
534{
535 if (ixjdebug & 0x0002)
536 printk(KERN_INFO "IXJ: /dev/phone%d Setting Play Volume to 0x%4.4x\n", j->board, volume);
537 ixj_WriteDSPCommand(0xCF02, j);
538 ixj_WriteDSPCommand(volume, j);
539}
540
541static int set_play_volume_linear(IXJ *j, int volume)
542{
543 int newvolume, dspplaymax;
544
545 if (ixjdebug & 0x0002)
546 printk(KERN_INFO "IXJ: /dev/phone %d Setting Linear Play Volume to 0x%4.4x\n", j->board, volume);
547 if(volume > 100 || volume < 0) {
548 return -1;
549 }
550
551
552 switch (j->cardtype) {
553 case QTI_PHONEJACK:
554 dspplaymax = 0x380;
555 break;
556 case QTI_LINEJACK:
557 if(j->port == PORT_PSTN) {
558 dspplaymax = 0x48;
559 } else {
560 dspplaymax = 0x100;
561 }
562 break;
563 case QTI_PHONEJACK_LITE:
564 dspplaymax = 0x380;
565 break;
566 case QTI_PHONEJACK_PCI:
567 dspplaymax = 0x6C;
568 break;
569 case QTI_PHONECARD:
570 dspplaymax = 0x50;
571 break;
572 default:
573 return -1;
574 }
575 newvolume = (dspplaymax * volume) / 100;
576 set_play_volume(j, newvolume);
577 return 0;
578}
579
580static inline void set_play_depth(IXJ *j, int depth)
581{
582 if (depth > 60)
583 depth = 60;
584 if (depth < 0)
585 depth = 0;
586 ixj_WriteDSPCommand(0x5280 + depth, j);
587}
588
589static inline int get_play_volume(IXJ *j)
590{
591 ixj_WriteDSPCommand(0xCF00, j);
592 return j->ssr.high << 8 | j->ssr.low;
593}
594
595static int get_play_volume_linear(IXJ *j)
596{
597 int volume, newvolume, dspplaymax;
598
599
600 switch (j->cardtype) {
601 case QTI_PHONEJACK:
602 dspplaymax = 0x380;
603 break;
604 case QTI_LINEJACK:
605 if(j->port == PORT_PSTN) {
606 dspplaymax = 0x48;
607 } else {
608 dspplaymax = 0x100;
609 }
610 break;
611 case QTI_PHONEJACK_LITE:
612 dspplaymax = 0x380;
613 break;
614 case QTI_PHONEJACK_PCI:
615 dspplaymax = 0x6C;
616 break;
617 case QTI_PHONECARD:
618 dspplaymax = 100;
619 break;
620 default:
621 return -1;
622 }
623 volume = get_play_volume(j);
624 newvolume = (volume * 100) / dspplaymax;
625 if(newvolume > 100)
626 newvolume = 100;
627 return newvolume;
628}
629
630static inline BYTE SLIC_GetState(IXJ *j)
631{
632 if (j->cardtype == QTI_PHONECARD) {
633 j->pccr1.byte = 0;
634 j->psccr.bits.dev = 3;
635 j->psccr.bits.rw = 1;
636 outw_p(j->psccr.byte << 8, j->XILINXbase + 0x00);
637 ixj_PCcontrol_wait(j);
638 j->pslic.byte = inw_p(j->XILINXbase + 0x00) & 0xFF;
639 ixj_PCcontrol_wait(j);
640 if (j->pslic.bits.powerdown)
641 return PLD_SLIC_STATE_OC;
642 else if (!j->pslic.bits.ring0 && !j->pslic.bits.ring1)
643 return PLD_SLIC_STATE_ACTIVE;
644 else
645 return PLD_SLIC_STATE_RINGING;
646 } else {
647 j->pld_slicr.byte = inb_p(j->XILINXbase + 0x01);
648 }
649 return j->pld_slicr.bits.state;
650}
651
652static BOOL SLIC_SetState(BYTE byState, IXJ *j)
653{
654 BOOL fRetVal = FALSE;
655
656 if (j->cardtype == QTI_PHONECARD) {
657 if (j->flags.pcmciasct) {
658 switch (byState) {
659 case PLD_SLIC_STATE_TIPOPEN:
660 case PLD_SLIC_STATE_OC:
661 j->pslic.bits.powerdown = 1;
662 j->pslic.bits.ring0 = j->pslic.bits.ring1 = 0;
663 fRetVal = TRUE;
664 break;
665 case PLD_SLIC_STATE_RINGING:
666 if (j->readers || j->writers) {
667 j->pslic.bits.powerdown = 0;
668 j->pslic.bits.ring0 = 1;
669 j->pslic.bits.ring1 = 0;
670 fRetVal = TRUE;
671 }
672 break;
673 case PLD_SLIC_STATE_OHT:
674
675 case PLD_SLIC_STATE_STANDBY:
676 case PLD_SLIC_STATE_ACTIVE:
677 if (j->readers || j->writers) {
678 j->pslic.bits.powerdown = 0;
679 } else {
680 j->pslic.bits.powerdown = 1;
681 }
682 j->pslic.bits.ring0 = j->pslic.bits.ring1 = 0;
683 fRetVal = TRUE;
684 break;
685 case PLD_SLIC_STATE_APR:
686
687 case PLD_SLIC_STATE_OHTPR:
688
689 default:
690 fRetVal = FALSE;
691 break;
692 }
693 j->psccr.bits.dev = 3;
694 j->psccr.bits.rw = 0;
695 outw_p(j->psccr.byte << 8 | j->pslic.byte, j->XILINXbase + 0x00);
696 ixj_PCcontrol_wait(j);
697 }
698 } else {
699
700 switch (byState) {
701 case PLD_SLIC_STATE_OC:
702 j->pld_slicw.bits.c1 = 0;
703 j->pld_slicw.bits.c2 = 0;
704 j->pld_slicw.bits.c3 = 0;
705 j->pld_slicw.bits.b2en = 0;
706 outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
707 fRetVal = TRUE;
708 break;
709 case PLD_SLIC_STATE_RINGING:
710 j->pld_slicw.bits.c1 = 1;
711 j->pld_slicw.bits.c2 = 0;
712 j->pld_slicw.bits.c3 = 0;
713 j->pld_slicw.bits.b2en = 1;
714 outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
715 fRetVal = TRUE;
716 break;
717 case PLD_SLIC_STATE_ACTIVE:
718 j->pld_slicw.bits.c1 = 0;
719 j->pld_slicw.bits.c2 = 1;
720 j->pld_slicw.bits.c3 = 0;
721 j->pld_slicw.bits.b2en = 0;
722 outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
723 fRetVal = TRUE;
724 break;
725 case PLD_SLIC_STATE_OHT:
726
727 j->pld_slicw.bits.c1 = 1;
728 j->pld_slicw.bits.c2 = 1;
729 j->pld_slicw.bits.c3 = 0;
730 j->pld_slicw.bits.b2en = 0;
731 outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
732 fRetVal = TRUE;
733 break;
734 case PLD_SLIC_STATE_TIPOPEN:
735 j->pld_slicw.bits.c1 = 0;
736 j->pld_slicw.bits.c2 = 0;
737 j->pld_slicw.bits.c3 = 1;
738 j->pld_slicw.bits.b2en = 0;
739 outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
740 fRetVal = TRUE;
741 break;
742 case PLD_SLIC_STATE_STANDBY:
743 j->pld_slicw.bits.c1 = 1;
744 j->pld_slicw.bits.c2 = 0;
745 j->pld_slicw.bits.c3 = 1;
746 j->pld_slicw.bits.b2en = 1;
747 outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
748 fRetVal = TRUE;
749 break;
750 case PLD_SLIC_STATE_APR:
751
752 j->pld_slicw.bits.c1 = 0;
753 j->pld_slicw.bits.c2 = 1;
754 j->pld_slicw.bits.c3 = 1;
755 j->pld_slicw.bits.b2en = 0;
756 outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
757 fRetVal = TRUE;
758 break;
759 case PLD_SLIC_STATE_OHTPR:
760
761 j->pld_slicw.bits.c1 = 1;
762 j->pld_slicw.bits.c2 = 1;
763 j->pld_slicw.bits.c3 = 1;
764 j->pld_slicw.bits.b2en = 0;
765 outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
766 fRetVal = TRUE;
767 break;
768 default:
769 fRetVal = FALSE;
770 break;
771 }
772 }
773
774 return fRetVal;
775}
776
777static int ixj_wink(IXJ *j)
778{
779 BYTE slicnow;
780
781 slicnow = SLIC_GetState(j);
782
783 j->pots_winkstart = jiffies;
784 SLIC_SetState(PLD_SLIC_STATE_OC, j);
785
786 while (time_before(jiffies, j->pots_winkstart + j->winktime)) {
787 set_current_state(TASK_INTERRUPTIBLE);
788 schedule_timeout(1);
789 }
790
791 SLIC_SetState(slicnow, j);
792 return 0;
793}
794
795static int ixj_register(int index, IXJ_REGFUNC regfunc)
796{
797 int cnt;
798 int retval = 0;
799 switch (index) {
800 case G729LOADER:
801 ixj_DownloadG729 = regfunc;
802 for (cnt = 0; cnt < IXJMAX; cnt++) {
803 IXJ *j = get_ixj(cnt);
804 while(test_and_set_bit(cnt, (void *)&j->busyflags) != 0) {
805 set_current_state(TASK_INTERRUPTIBLE);
806 schedule_timeout(1);
807 }
808 ixj_DownloadG729(j, 0L);
809 clear_bit(cnt, &j->busyflags);
810 }
811 break;
812 case TS85LOADER:
813 ixj_DownloadTS85 = regfunc;
814 for (cnt = 0; cnt < IXJMAX; cnt++) {
815 IXJ *j = get_ixj(cnt);
816 while(test_and_set_bit(cnt, (void *)&j->busyflags) != 0) {
817 set_current_state(TASK_INTERRUPTIBLE);
818 schedule_timeout(1);
819 }
820 ixj_DownloadTS85(j, 0L);
821 clear_bit(cnt, &j->busyflags);
822 }
823 break;
824 case PRE_READ:
825 ixj_PreRead = regfunc;
826 break;
827 case POST_READ:
828 ixj_PostRead = regfunc;
829 break;
830 case PRE_WRITE:
831 ixj_PreWrite = regfunc;
832 break;
833 case POST_WRITE:
834 ixj_PostWrite = regfunc;
835 break;
836 case PRE_IOCTL:
837 ixj_PreIoctl = regfunc;
838 break;
839 case POST_IOCTL:
840 ixj_PostIoctl = regfunc;
841 break;
842 default:
843 retval = 1;
844 }
845 return retval;
846}
847
848EXPORT_SYMBOL(ixj_register);
849
850static int ixj_unregister(int index)
851{
852 int retval = 0;
853 switch (index) {
854 case G729LOADER:
855 ixj_DownloadG729 = &Stub;
856 break;
857 case TS85LOADER:
858 ixj_DownloadTS85 = &Stub;
859 break;
860 case PRE_READ:
861 ixj_PreRead = &Stub;
862 break;
863 case POST_READ:
864 ixj_PostRead = &Stub;
865 break;
866 case PRE_WRITE:
867 ixj_PreWrite = &Stub;
868 break;
869 case POST_WRITE:
870 ixj_PostWrite = &Stub;
871 break;
872 case PRE_IOCTL:
873 ixj_PreIoctl = &Stub;
874 break;
875 case POST_IOCTL:
876 ixj_PostIoctl = &Stub;
877 break;
878 default:
879 retval = 1;
880 }
881 return retval;
882}
883
884EXPORT_SYMBOL(ixj_unregister);
885
886static void ixj_init_timer(IXJ *j)
887{
888 init_timer(&j->timer);
889 j->timer.function = ixj_timeout;
890 j->timer.data = (unsigned long)j;
891}
892
893static void ixj_add_timer(IXJ *j)
894{
895 j->timer.expires = jiffies + (hertz / samplerate);
896 add_timer(&j->timer);
897}
898
899static void ixj_tone_timeout(IXJ *j)
900{
901 IXJ_TONE ti;
902
903 j->tone_state++;
904 if (j->tone_state == 3) {
905 j->tone_state = 0;
906 if (j->cadence_t) {
907 j->tone_cadence_state++;
908 if (j->tone_cadence_state >= j->cadence_t->elements_used) {
909 switch (j->cadence_t->termination) {
910 case PLAY_ONCE:
911 ixj_cpt_stop(j);
912 break;
913 case REPEAT_LAST_ELEMENT:
914 j->tone_cadence_state--;
915 ixj_play_tone(j, j->cadence_t->ce[j->tone_cadence_state].index);
916 break;
917 case REPEAT_ALL:
918 j->tone_cadence_state = 0;
919 if (j->cadence_t->ce[j->tone_cadence_state].freq0) {
920 ti.tone_index = j->cadence_t->ce[j->tone_cadence_state].index;
921 ti.freq0 = j->cadence_t->ce[j->tone_cadence_state].freq0;
922 ti.gain0 = j->cadence_t->ce[j->tone_cadence_state].gain0;
923 ti.freq1 = j->cadence_t->ce[j->tone_cadence_state].freq1;
924 ti.gain1 = j->cadence_t->ce[j->tone_cadence_state].gain1;
925 ixj_init_tone(j, &ti);
926 }
927 ixj_set_tone_on(j->cadence_t->ce[0].tone_on_time, j);
928 ixj_set_tone_off(j->cadence_t->ce[0].tone_off_time, j);
929 ixj_play_tone(j, j->cadence_t->ce[0].index);
930 break;
931 }
932 } else {
933 if (j->cadence_t->ce[j->tone_cadence_state].gain0) {
934 ti.tone_index = j->cadence_t->ce[j->tone_cadence_state].index;
935 ti.freq0 = j->cadence_t->ce[j->tone_cadence_state].freq0;
936 ti.gain0 = j->cadence_t->ce[j->tone_cadence_state].gain0;
937 ti.freq1 = j->cadence_t->ce[j->tone_cadence_state].freq1;
938 ti.gain1 = j->cadence_t->ce[j->tone_cadence_state].gain1;
939 ixj_init_tone(j, &ti);
940 }
941 ixj_set_tone_on(j->cadence_t->ce[j->tone_cadence_state].tone_on_time, j);
942 ixj_set_tone_off(j->cadence_t->ce[j->tone_cadence_state].tone_off_time, j);
943 ixj_play_tone(j, j->cadence_t->ce[j->tone_cadence_state].index);
944 }
945 }
946 }
947}
948
949static inline void ixj_kill_fasync(IXJ *j, IXJ_SIGEVENT event, int dir)
950{
951 if(j->ixj_signals[event]) {
952 if(ixjdebug & 0x0100)
953 printk("Sending signal for event %d\n", event);
954
955
956 kill_fasync(&(j->async_queue), j->ixj_signals[event], dir);
957 }
958}
959
960static void ixj_pstn_state(IXJ *j)
961{
962 int var;
963 union XOPXR0 XR0, daaint;
964
965 var = 10;
966
967 XR0.reg = j->m_DAAShadowRegs.XOP_REGS.XOP.xr0.reg;
968 daaint.reg = 0;
969 XR0.bitreg.RMR = j->m_DAAShadowRegs.SOP_REGS.SOP.cr1.bitreg.RMR;
970
971 j->pld_scrr.byte = inb_p(j->XILINXbase);
972 if (j->pld_scrr.bits.daaflag) {
973 daa_int_read(j);
974 if(j->m_DAAShadowRegs.XOP_REGS.XOP.xr0.bitreg.RING) {
975 if(time_after(jiffies, j->pstn_sleeptil) && !(j->flags.pots_pstn && j->hookstate)) {
976 daaint.bitreg.RING = 1;
977 if(ixjdebug & 0x0008) {
978 printk(KERN_INFO "IXJ DAA Ring Interrupt /dev/phone%d at %ld\n", j->board, jiffies);
979 }
980 } else {
981 daa_set_mode(j, SOP_PU_RESET);
982 }
983 }
984 if(j->m_DAAShadowRegs.XOP_REGS.XOP.xr0.bitreg.Caller_ID) {
985 daaint.bitreg.Caller_ID = 1;
986 j->pstn_cid_intr = 1;
987 j->pstn_cid_received = jiffies;
988 if(ixjdebug & 0x0008) {
989 printk(KERN_INFO "IXJ DAA Caller_ID Interrupt /dev/phone%d at %ld\n", j->board, jiffies);
990 }
991 }
992 if(j->m_DAAShadowRegs.XOP_REGS.XOP.xr0.bitreg.Cadence) {
993 daaint.bitreg.Cadence = 1;
994 if(ixjdebug & 0x0008) {
995 printk(KERN_INFO "IXJ DAA Cadence Interrupt /dev/phone%d at %ld\n", j->board, jiffies);
996 }
997 }
998 if(j->m_DAAShadowRegs.XOP_REGS.XOP.xr0.bitreg.VDD_OK != XR0.bitreg.VDD_OK) {
999 daaint.bitreg.VDD_OK = 1;
1000 daaint.bitreg.SI_0 = j->m_DAAShadowRegs.XOP_REGS.XOP.xr0.bitreg.VDD_OK;
1001 }
1002 }
1003 daa_CR_read(j, 1);
1004 if(j->m_DAAShadowRegs.SOP_REGS.SOP.cr1.bitreg.RMR != XR0.bitreg.RMR && time_after(jiffies, j->pstn_sleeptil) && !(j->flags.pots_pstn && j->hookstate)) {
1005 daaint.bitreg.RMR = 1;
1006 daaint.bitreg.SI_1 = j->m_DAAShadowRegs.SOP_REGS.SOP.cr1.bitreg.RMR;
1007 if(ixjdebug & 0x0008) {
1008 printk(KERN_INFO "IXJ DAA RMR /dev/phone%d was %s for %ld\n", j->board, XR0.bitreg.RMR?"on":"off", jiffies - j->pstn_last_rmr);
1009 }
1010 j->pstn_prev_rmr = j->pstn_last_rmr;
1011 j->pstn_last_rmr = jiffies;
1012 }
1013 switch(j->daa_mode) {
1014 case SOP_PU_SLEEP:
1015 if (daaint.bitreg.RING) {
1016 if (!j->flags.pstn_ringing) {
1017 if (j->daa_mode != SOP_PU_RINGING) {
1018 j->pstn_ring_int = jiffies;
1019 daa_set_mode(j, SOP_PU_RINGING);
1020 }
1021 }
1022 }
1023 break;
1024 case SOP_PU_RINGING:
1025 if (daaint.bitreg.RMR) {
1026 if (ixjdebug & 0x0008) {
1027 printk(KERN_INFO "IXJ Ring Cadence a state = %d /dev/phone%d at %ld\n", j->cadence_f[4].state, j->board, jiffies);
1028 }
1029 if (daaint.bitreg.SI_1) {
1030 j->flags.pstn_rmr = 1;
1031 j->pstn_ring_start = jiffies;
1032 j->pstn_ring_stop = 0;
1033 j->ex.bits.pstn_ring = 0;
1034 if (j->cadence_f[4].state == 0) {
1035 j->cadence_f[4].state = 1;
1036 j->cadence_f[4].on1min = jiffies + (long)((j->cadence_f[4].on1 * hertz * (100 - var)) / 10000);
1037 j->cadence_f[4].on1dot = jiffies + (long)((j->cadence_f[4].on1 * hertz * (100)) / 10000);
1038 j->cadence_f[4].on1max = jiffies + (long)((j->cadence_f[4].on1 * hertz * (100 + var)) / 10000);
1039 } else if (j->cadence_f[4].state == 2) {
1040 if((time_after(jiffies, j->cadence_f[4].off1min) &&
1041 time_before(jiffies, j->cadence_f[4].off1max))) {
1042 if (j->cadence_f[4].on2) {
1043 j->cadence_f[4].state = 3;
1044 j->cadence_f[4].on2min = jiffies + (long)((j->cadence_f[4].on2 * (hertz * (100 - var)) / 10000));
1045 j->cadence_f[4].on2dot = jiffies + (long)((j->cadence_f[4].on2 * (hertz * (100)) / 10000));
1046 j->cadence_f[4].on2max = jiffies + (long)((j->cadence_f[4].on2 * (hertz * (100 + var)) / 10000));
1047 } else {
1048 j->cadence_f[4].state = 7;
1049 }
1050 } else {
1051 if (ixjdebug & 0x0008) {
1052 printk(KERN_INFO "IXJ Ring Cadence fail state = %d /dev/phone%d at %ld should be %d\n",
1053 j->cadence_f[4].state, j->board, jiffies - j->pstn_prev_rmr,
1054 j->cadence_f[4].off1);
1055 }
1056 j->cadence_f[4].state = 0;
1057 }
1058 } else if (j->cadence_f[4].state == 4) {
1059 if((time_after(jiffies, j->cadence_f[4].off2min) &&
1060 time_before(jiffies, j->cadence_f[4].off2max))) {
1061 if (j->cadence_f[4].on3) {
1062 j->cadence_f[4].state = 5;
1063 j->cadence_f[4].on3min = jiffies + (long)((j->cadence_f[4].on3 * (hertz * (100 - var)) / 10000));
1064 j->cadence_f[4].on3dot = jiffies + (long)((j->cadence_f[4].on3 * (hertz * (100)) / 10000));
1065 j->cadence_f[4].on3max = jiffies + (long)((j->cadence_f[4].on3 * (hertz * (100 + var)) / 10000));
1066 } else {
1067 j->cadence_f[4].state = 7;
1068 }
1069 } else {
1070 if (ixjdebug & 0x0008) {
1071 printk(KERN_INFO "IXJ Ring Cadence fail state = %d /dev/phone%d at %ld should be %d\n",
1072 j->cadence_f[4].state, j->board, jiffies - j->pstn_prev_rmr,
1073 j->cadence_f[4].off2);
1074 }
1075 j->cadence_f[4].state = 0;
1076 }
1077 } else if (j->cadence_f[4].state == 6) {
1078 if((time_after(jiffies, j->cadence_f[4].off3min) &&
1079 time_before(jiffies, j->cadence_f[4].off3max))) {
1080 j->cadence_f[4].state = 7;
1081 } else {
1082 if (ixjdebug & 0x0008) {
1083 printk(KERN_INFO "IXJ Ring Cadence fail state = %d /dev/phone%d at %ld should be %d\n",
1084 j->cadence_f[4].state, j->board, jiffies - j->pstn_prev_rmr,
1085 j->cadence_f[4].off3);
1086 }
1087 j->cadence_f[4].state = 0;
1088 }
1089 } else {
1090 j->cadence_f[4].state = 0;
1091 }
1092 } else {
1093 j->pstn_ring_start = 0;
1094 j->pstn_ring_stop = jiffies;
1095 if (j->cadence_f[4].state == 1) {
1096 if(!j->cadence_f[4].on1) {
1097 j->cadence_f[4].state = 7;
1098 } else if((time_after(jiffies, j->cadence_f[4].on1min) &&
1099 time_before(jiffies, j->cadence_f[4].on1max))) {
1100 if (j->cadence_f[4].off1) {
1101 j->cadence_f[4].state = 2;
1102 j->cadence_f[4].off1min = jiffies + (long)((j->cadence_f[4].off1 * (hertz * (100 - var)) / 10000));
1103 j->cadence_f[4].off1dot = jiffies + (long)((j->cadence_f[4].off1 * (hertz * (100)) / 10000));
1104 j->cadence_f[4].off1max = jiffies + (long)((j->cadence_f[4].off1 * (hertz * (100 + var)) / 10000));
1105 } else {
1106 j->cadence_f[4].state = 7;
1107 }
1108 } else {
1109 if (ixjdebug & 0x0008) {
1110 printk(KERN_INFO "IXJ Ring Cadence fail state = %d /dev/phone%d at %ld should be %d\n",
1111 j->cadence_f[4].state, j->board, jiffies - j->pstn_prev_rmr,
1112 j->cadence_f[4].on1);
1113 }
1114 j->cadence_f[4].state = 0;
1115 }
1116 } else if (j->cadence_f[4].state == 3) {
1117 if((time_after(jiffies, j->cadence_f[4].on2min) &&
1118 time_before(jiffies, j->cadence_f[4].on2max))) {
1119 if (j->cadence_f[4].off2) {
1120 j->cadence_f[4].state = 4;
1121 j->cadence_f[4].off2min = jiffies + (long)((j->cadence_f[4].off2 * (hertz * (100 - var)) / 10000));
1122 j->cadence_f[4].off2dot = jiffies + (long)((j->cadence_f[4].off2 * (hertz * (100)) / 10000));
1123 j->cadence_f[4].off2max = jiffies + (long)((j->cadence_f[4].off2 * (hertz * (100 + var)) / 10000));
1124 } else {
1125 j->cadence_f[4].state = 7;
1126 }
1127 } else {
1128 if (ixjdebug & 0x0008) {
1129 printk(KERN_INFO "IXJ Ring Cadence fail state = %d /dev/phone%d at %ld should be %d\n",
1130 j->cadence_f[4].state, j->board, jiffies - j->pstn_prev_rmr,
1131 j->cadence_f[4].on2);
1132 }
1133 j->cadence_f[4].state = 0;
1134 }
1135 } else if (j->cadence_f[4].state == 5) {
1136 if((time_after(jiffies, j->cadence_f[4].on3min) &&
1137 time_before(jiffies, j->cadence_f[4].on3max))) {
1138 if (j->cadence_f[4].off3) {
1139 j->cadence_f[4].state = 6;
1140 j->cadence_f[4].off3min = jiffies + (long)((j->cadence_f[4].off3 * (hertz * (100 - var)) / 10000));
1141 j->cadence_f[4].off3dot = jiffies + (long)((j->cadence_f[4].off3 * (hertz * (100)) / 10000));
1142 j->cadence_f[4].off3max = jiffies + (long)((j->cadence_f[4].off3 * (hertz * (100 + var)) / 10000));
1143 } else {
1144 j->cadence_f[4].state = 7;
1145 }
1146 } else {
1147 j->cadence_f[4].state = 0;
1148 }
1149 } else {
1150 if (ixjdebug & 0x0008) {
1151 printk(KERN_INFO "IXJ Ring Cadence fail state = %d /dev/phone%d at %ld should be %d\n",
1152 j->cadence_f[4].state, j->board, jiffies - j->pstn_prev_rmr,
1153 j->cadence_f[4].on3);
1154 }
1155 j->cadence_f[4].state = 0;
1156 }
1157 }
1158 if (ixjdebug & 0x0010) {
1159 printk(KERN_INFO "IXJ Ring Cadence b state = %d /dev/phone%d at %ld\n", j->cadence_f[4].state, j->board, jiffies);
1160 }
1161 if (ixjdebug & 0x0010) {
1162 switch(j->cadence_f[4].state) {
1163 case 1:
1164 printk(KERN_INFO "IXJ /dev/phone%d Next Ring Cadence state at %u min %ld - %ld - max %ld\n", j->board,
1165 j->cadence_f[4].on1, j->cadence_f[4].on1min, j->cadence_f[4].on1dot, j->cadence_f[4].on1max);
1166 break;
1167 case 2:
1168 printk(KERN_INFO "IXJ /dev/phone%d Next Ring Cadence state at %u min %ld - %ld - max %ld\n", j->board,
1169 j->cadence_f[4].off1, j->cadence_f[4].off1min, j->cadence_f[4].off1dot, j->cadence_f[4].off1max);
1170 break;
1171 case 3:
1172 printk(KERN_INFO "IXJ /dev/phone%d Next Ring Cadence state at %u min %ld - %ld - max %ld\n", j->board,
1173 j->cadence_f[4].on2, j->cadence_f[4].on2min, j->cadence_f[4].on2dot, j->cadence_f[4].on2max);
1174 break;
1175 case 4:
1176 printk(KERN_INFO "IXJ /dev/phone%d Next Ring Cadence state at %u min %ld - %ld - max %ld\n", j->board,
1177 j->cadence_f[4].off2, j->cadence_f[4].off2min, j->cadence_f[4].off2dot, j->cadence_f[4].off2max);
1178 break;
1179 case 5:
1180 printk(KERN_INFO "IXJ /dev/phone%d Next Ring Cadence state at %u min %ld - %ld - max %ld\n", j->board,
1181 j->cadence_f[4].on3, j->cadence_f[4].on3min, j->cadence_f[4].on3dot, j->cadence_f[4].on3max);
1182 break;
1183 case 6:
1184 printk(KERN_INFO "IXJ /dev/phone%d Next Ring Cadence state at %u min %ld - %ld - max %ld\n", j->board,
1185 j->cadence_f[4].off3, j->cadence_f[4].off3min, j->cadence_f[4].off3dot, j->cadence_f[4].off3max);
1186 break;
1187 }
1188 }
1189 }
1190 if (j->cadence_f[4].state == 7) {
1191 j->cadence_f[4].state = 0;
1192 j->pstn_ring_stop = jiffies;
1193 j->ex.bits.pstn_ring = 1;
1194 ixj_kill_fasync(j, SIG_PSTN_RING, POLL_IN);
1195 if(ixjdebug & 0x0008) {
1196 printk(KERN_INFO "IXJ Ring int set /dev/phone%d at %ld\n", j->board, jiffies);
1197 }
1198 }
1199 if((j->pstn_ring_int != 0 && time_after(jiffies, j->pstn_ring_int + (hertz * 5)) && !j->flags.pstn_rmr) ||
1200 (j->pstn_ring_stop != 0 && time_after(jiffies, j->pstn_ring_stop + (hertz * 5)))) {
1201 if(ixjdebug & 0x0008) {
1202 printk("IXJ DAA no ring in 5 seconds /dev/phone%d at %ld\n", j->board, jiffies);
1203 printk("IXJ DAA pstn ring int /dev/phone%d at %ld\n", j->board, j->pstn_ring_int);
1204 printk("IXJ DAA pstn ring stop /dev/phone%d at %ld\n", j->board, j->pstn_ring_stop);
1205 }
1206 j->pstn_ring_stop = j->pstn_ring_int = 0;
1207 daa_set_mode(j, SOP_PU_SLEEP);
1208 }
1209 outb_p(j->pld_scrw.byte, j->XILINXbase);
1210 if (j->pstn_cid_intr && time_after(jiffies, j->pstn_cid_received + hertz)) {
1211 ixj_daa_cid_read(j);
1212 j->ex.bits.caller_id = 1;
1213 ixj_kill_fasync(j, SIG_CALLER_ID, POLL_IN);
1214 j->pstn_cid_intr = 0;
1215 }
1216 if (daaint.bitreg.Cadence) {
1217 if(ixjdebug & 0x0008) {
1218 printk("IXJ DAA Cadence interrupt going to sleep /dev/phone%d\n", j->board);
1219 }
1220 daa_set_mode(j, SOP_PU_SLEEP);
1221 j->ex.bits.pstn_ring = 0;
1222 }
1223 break;
1224 case SOP_PU_CONVERSATION:
1225 if (daaint.bitreg.VDD_OK) {
1226 if(!daaint.bitreg.SI_0) {
1227 if (!j->pstn_winkstart) {
1228 if(ixjdebug & 0x0008) {
1229 printk("IXJ DAA possible wink /dev/phone%d %ld\n", j->board, jiffies);
1230 }
1231 j->pstn_winkstart = jiffies;
1232 }
1233 } else {
1234 if (j->pstn_winkstart) {
1235 if(ixjdebug & 0x0008) {
1236 printk("IXJ DAA possible wink end /dev/phone%d %ld\n", j->board, jiffies);
1237 }
1238 j->pstn_winkstart = 0;
1239 }
1240 }
1241 }
1242 if (j->pstn_winkstart && time_after(jiffies, j->pstn_winkstart + ((hertz * j->winktime) / 1000))) {
1243 if(ixjdebug & 0x0008) {
1244 printk("IXJ DAA wink detected going to sleep /dev/phone%d %ld\n", j->board, jiffies);
1245 }
1246 daa_set_mode(j, SOP_PU_SLEEP);
1247 j->pstn_winkstart = 0;
1248 j->ex.bits.pstn_wink = 1;
1249 ixj_kill_fasync(j, SIG_PSTN_WINK, POLL_IN);
1250 }
1251 break;
1252 }
1253}
1254
1255static void ixj_timeout(unsigned long ptr)
1256{
1257 int board;
1258 unsigned long jifon;
1259 IXJ *j = (IXJ *)ptr;
1260 board = j->board;
1261
1262 if (j->DSPbase && atomic_read(&j->DSPWrite) == 0 && test_and_set_bit(board, (void *)&j->busyflags) == 0) {
1263 ixj_perfmon(j->timerchecks);
1264 j->hookstate = ixj_hookstate(j);
1265 if (j->tone_state) {
1266 if (!(j->hookstate)) {
1267 ixj_cpt_stop(j);
1268 if (j->m_hook) {
1269 j->m_hook = 0;
1270 j->ex.bits.hookstate = 1;
1271 ixj_kill_fasync(j, SIG_HOOKSTATE, POLL_IN);
1272 }
1273 clear_bit(board, &j->busyflags);
1274 ixj_add_timer(j);
1275 return;
1276 }
1277 if (j->tone_state == 1)
1278 jifon = ((hertz * j->tone_on_time) * 25 / 100000);
1279 else
1280 jifon = ((hertz * j->tone_on_time) * 25 / 100000) + ((hertz * j->tone_off_time) * 25 / 100000);
1281 if (time_before(jiffies, j->tone_start_jif + jifon)) {
1282 if (j->tone_state == 1) {
1283 ixj_play_tone(j, j->tone_index);
1284 if (j->dsp.low == 0x20) {
1285 clear_bit(board, &j->busyflags);
1286 ixj_add_timer(j);
1287 return;
1288 }
1289 } else {
1290 ixj_play_tone(j, 0);
1291 if (j->dsp.low == 0x20) {
1292 clear_bit(board, &j->busyflags);
1293 ixj_add_timer(j);
1294 return;
1295 }
1296 }
1297 } else {
1298 ixj_tone_timeout(j);
1299 if (j->flags.dialtone) {
1300 ixj_dialtone(j);
1301 }
1302 if (j->flags.busytone) {
1303 ixj_busytone(j);
1304 if (j->dsp.low == 0x20) {
1305 clear_bit(board, &j->busyflags);
1306 ixj_add_timer(j);
1307 return;
1308 }
1309 }
1310 if (j->flags.ringback) {
1311 ixj_ringback(j);
1312 if (j->dsp.low == 0x20) {
1313 clear_bit(board, &j->busyflags);
1314 ixj_add_timer(j);
1315 return;
1316 }
1317 }
1318 if (!j->tone_state) {
1319 ixj_cpt_stop(j);
1320 }
1321 }
1322 }
1323 if (!(j->tone_state && j->dsp.low == 0x20)) {
1324 if (IsRxReady(j)) {
1325 ixj_read_frame(j);
1326 }
1327 if (IsTxReady(j)) {
1328 ixj_write_frame(j);
1329 }
1330 }
1331 if (j->flags.cringing) {
1332 if (j->hookstate & 1) {
1333 j->flags.cringing = 0;
1334 ixj_ring_off(j);
1335 } else if(j->cadence_f[5].enable && ((!j->cadence_f[5].en_filter) || (j->cadence_f[5].en_filter && j->flags.firstring))) {
1336 switch(j->cadence_f[5].state) {
1337 case 0:
1338 j->cadence_f[5].on1dot = jiffies + (long)((j->cadence_f[5].on1 * (hertz * 100) / 10000));
1339 if (time_before(jiffies, j->cadence_f[5].on1dot)) {
1340 if(ixjdebug & 0x0004) {
1341 printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1342 }
1343 ixj_ring_on(j);
1344 }
1345 j->cadence_f[5].state = 1;
1346 break;
1347 case 1:
1348 if (time_after(jiffies, j->cadence_f[5].on1dot)) {
1349 j->cadence_f[5].off1dot = jiffies + (long)((j->cadence_f[5].off1 * (hertz * 100) / 10000));
1350 if(ixjdebug & 0x0004) {
1351 printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1352 }
1353 ixj_ring_off(j);
1354 j->cadence_f[5].state = 2;
1355 }
1356 break;
1357 case 2:
1358 if (time_after(jiffies, j->cadence_f[5].off1dot)) {
1359 if(ixjdebug & 0x0004) {
1360 printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1361 }
1362 ixj_ring_on(j);
1363 if (j->cadence_f[5].on2) {
1364 j->cadence_f[5].on2dot = jiffies + (long)((j->cadence_f[5].on2 * (hertz * 100) / 10000));
1365 j->cadence_f[5].state = 3;
1366 } else {
1367 j->cadence_f[5].state = 7;
1368 }
1369 }
1370 break;
1371 case 3:
1372 if (time_after(jiffies, j->cadence_f[5].on2dot)) {
1373 if(ixjdebug & 0x0004) {
1374 printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1375 }
1376 ixj_ring_off(j);
1377 if (j->cadence_f[5].off2) {
1378 j->cadence_f[5].off2dot = jiffies + (long)((j->cadence_f[5].off2 * (hertz * 100) / 10000));
1379 j->cadence_f[5].state = 4;
1380 } else {
1381 j->cadence_f[5].state = 7;
1382 }
1383 }
1384 break;
1385 case 4:
1386 if (time_after(jiffies, j->cadence_f[5].off2dot)) {
1387 if(ixjdebug & 0x0004) {
1388 printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1389 }
1390 ixj_ring_on(j);
1391 if (j->cadence_f[5].on3) {
1392 j->cadence_f[5].on3dot = jiffies + (long)((j->cadence_f[5].on3 * (hertz * 100) / 10000));
1393 j->cadence_f[5].state = 5;
1394 } else {
1395 j->cadence_f[5].state = 7;
1396 }
1397 }
1398 break;
1399 case 5:
1400 if (time_after(jiffies, j->cadence_f[5].on3dot)) {
1401 if(ixjdebug & 0x0004) {
1402 printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1403 }
1404 ixj_ring_off(j);
1405 if (j->cadence_f[5].off3) {
1406 j->cadence_f[5].off3dot = jiffies + (long)((j->cadence_f[5].off3 * (hertz * 100) / 10000));
1407 j->cadence_f[5].state = 6;
1408 } else {
1409 j->cadence_f[5].state = 7;
1410 }
1411 }
1412 break;
1413 case 6:
1414 if (time_after(jiffies, j->cadence_f[5].off3dot)) {
1415 if(ixjdebug & 0x0004) {
1416 printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1417 }
1418 j->cadence_f[5].state = 7;
1419 }
1420 break;
1421 case 7:
1422 if(ixjdebug & 0x0004) {
1423 printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1424 }
1425 j->flags.cidring = 1;
1426 j->cadence_f[5].state = 0;
1427 break;
1428 }
1429 if (j->flags.cidring && !j->flags.cidsent) {
1430 j->flags.cidsent = 1;
1431 if(j->fskdcnt) {
1432 SLIC_SetState(PLD_SLIC_STATE_OHT, j);
1433 ixj_pre_cid(j);
1434 }
1435 j->flags.cidring = 0;
1436 }
1437 clear_bit(board, &j->busyflags);
1438 ixj_add_timer(j);
1439 return;
1440 } else {
1441 if (time_after(jiffies, j->ring_cadence_jif + (hertz / 2))) {
1442 if (j->flags.cidring && !j->flags.cidsent) {
1443 j->flags.cidsent = 1;
1444 if(j->fskdcnt) {
1445 SLIC_SetState(PLD_SLIC_STATE_OHT, j);
1446 ixj_pre_cid(j);
1447 }
1448 j->flags.cidring = 0;
1449 }
1450 j->ring_cadence_t--;
1451 if (j->ring_cadence_t == -1)
1452 j->ring_cadence_t = 15;
1453 j->ring_cadence_jif = jiffies;
1454
1455 if (j->ring_cadence & 1 << j->ring_cadence_t) {
1456 if(j->flags.cidsent && j->cadence_f[5].en_filter)
1457 j->flags.firstring = 1;
1458 else
1459 ixj_ring_on(j);
1460 } else {
1461 ixj_ring_off(j);
1462 if(!j->flags.cidsent)
1463 j->flags.cidring = 1;
1464 }
1465 }
1466 clear_bit(board, &j->busyflags);
1467 ixj_add_timer(j);
1468 return;
1469 }
1470 }
1471 if (!j->flags.ringing) {
1472 if (j->hookstate) {
1473 if (j->dsp.low != 0x20 &&
1474 SLIC_GetState(j) != PLD_SLIC_STATE_ACTIVE) {
1475 SLIC_SetState(PLD_SLIC_STATE_ACTIVE, j);
1476 }
1477 LineMonitor(j);
1478 read_filters(j);
1479 ixj_WriteDSPCommand(0x511B, j);
1480 j->proc_load = j->ssr.high << 8 | j->ssr.low;
1481 if (!j->m_hook && (j->hookstate & 1)) {
1482 j->m_hook = j->ex.bits.hookstate = 1;
1483 ixj_kill_fasync(j, SIG_HOOKSTATE, POLL_IN);
1484 }
1485 } else {
1486 if (j->ex.bits.dtmf_ready) {
1487 j->dtmf_wp = j->dtmf_rp = j->ex.bits.dtmf_ready = 0;
1488 }
1489 if (j->m_hook) {
1490 j->m_hook = 0;
1491 j->ex.bits.hookstate = 1;
1492 ixj_kill_fasync(j, SIG_HOOKSTATE, POLL_IN);
1493 }
1494 }
1495 }
1496 if (j->cardtype == QTI_LINEJACK && !j->flags.pstncheck && j->flags.pstn_present) {
1497 ixj_pstn_state(j);
1498 }
1499 if (j->ex.bytes) {
1500 wake_up_interruptible(&j->poll_q);
1501 }
1502 clear_bit(board, &j->busyflags);
1503 }
1504 ixj_add_timer(j);
1505}
1506
1507static int ixj_status_wait(IXJ *j)
1508{
1509 unsigned long jif;
1510
1511 jif = jiffies + ((60 * hertz) / 100);
1512 while (!IsStatusReady(j)) {
1513 ixj_perfmon(j->statuswait);
1514 if (time_after(jiffies, jif)) {
1515 ixj_perfmon(j->statuswaitfail);
1516 return -1;
1517 }
1518 }
1519 return 0;
1520}
1521
1522static int ixj_PCcontrol_wait(IXJ *j)
1523{
1524 unsigned long jif;
1525
1526 jif = jiffies + ((60 * hertz) / 100);
1527 while (!IsPCControlReady(j)) {
1528 ixj_perfmon(j->pcontrolwait);
1529 if (time_after(jiffies, jif)) {
1530 ixj_perfmon(j->pcontrolwaitfail);
1531 return -1;
1532 }
1533 }
1534 return 0;
1535}
1536
1537static int ixj_WriteDSPCommand(unsigned short cmd, IXJ *j)
1538{
1539 BYTES bytes;
1540 unsigned long jif;
1541
1542 atomic_inc(&j->DSPWrite);
1543 if(atomic_read(&j->DSPWrite) > 1) {
1544 printk("IXJ %d DSP write overlap attempting command 0x%4.4x\n", j->board, cmd);
1545 return -1;
1546 }
1547 bytes.high = (cmd & 0xFF00) >> 8;
1548 bytes.low = cmd & 0x00FF;
1549 jif = jiffies + ((60 * hertz) / 100);
1550 while (!IsControlReady(j)) {
1551 ixj_perfmon(j->iscontrolready);
1552 if (time_after(jiffies, jif)) {
1553 ixj_perfmon(j->iscontrolreadyfail);
1554 atomic_dec(&j->DSPWrite);
1555 if(atomic_read(&j->DSPWrite) > 0) {
1556 printk("IXJ %d DSP overlaped command 0x%4.4x during control ready failure.\n", j->board, cmd);
1557 while(atomic_read(&j->DSPWrite) > 0) {
1558 atomic_dec(&j->DSPWrite);
1559 }
1560 }
1561 return -1;
1562 }
1563 }
1564 outb(bytes.low, j->DSPbase + 6);
1565 outb(bytes.high, j->DSPbase + 7);
1566
1567 if (ixj_status_wait(j)) {
1568 j->ssr.low = 0xFF;
1569 j->ssr.high = 0xFF;
1570 atomic_dec(&j->DSPWrite);
1571 if(atomic_read(&j->DSPWrite) > 0) {
1572 printk("IXJ %d DSP overlaped command 0x%4.4x during status wait failure.\n", j->board, cmd);
1573 while(atomic_read(&j->DSPWrite) > 0) {
1574 atomic_dec(&j->DSPWrite);
1575 }
1576 }
1577 return -1;
1578 }
1579
1580 j->ssr.low = inb_p(j->DSPbase + 2);
1581 j->ssr.high = inb_p(j->DSPbase + 3);
1582 atomic_dec(&j->DSPWrite);
1583 if(atomic_read(&j->DSPWrite) > 0) {
1584 printk("IXJ %d DSP overlaped command 0x%4.4x\n", j->board, cmd);
1585 while(atomic_read(&j->DSPWrite) > 0) {
1586 atomic_dec(&j->DSPWrite);
1587 }
1588 }
1589 return 0;
1590}
1591
1592
1593
1594
1595
1596
1597static inline int ixj_gpio_read(IXJ *j)
1598{
1599 if (ixj_WriteDSPCommand(0x5143, j))
1600 return -1;
1601
1602 j->gpio.bytes.low = j->ssr.low;
1603 j->gpio.bytes.high = j->ssr.high;
1604
1605 return 0;
1606}
1607
1608static inline void LED_SetState(int state, IXJ *j)
1609{
1610 if (j->cardtype == QTI_LINEJACK) {
1611 j->pld_scrw.bits.led1 = state & 0x1 ? 1 : 0;
1612 j->pld_scrw.bits.led2 = state & 0x2 ? 1 : 0;
1613 j->pld_scrw.bits.led3 = state & 0x4 ? 1 : 0;
1614 j->pld_scrw.bits.led4 = state & 0x8 ? 1 : 0;
1615
1616 outb(j->pld_scrw.byte, j->XILINXbase);
1617 }
1618}
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634static int ixj_set_port(IXJ *j, int arg)
1635{
1636 if (j->cardtype == QTI_PHONEJACK_LITE) {
1637 if (arg != PORT_POTS)
1638 return 10;
1639 else
1640 return 0;
1641 }
1642 switch (arg) {
1643 case PORT_POTS:
1644 j->port = PORT_POTS;
1645 switch (j->cardtype) {
1646 case QTI_PHONECARD:
1647 if (j->flags.pcmciasct == 1)
1648 SLIC_SetState(PLD_SLIC_STATE_ACTIVE, j);
1649 else
1650 return 11;
1651 break;
1652 case QTI_PHONEJACK_PCI:
1653 j->pld_slicw.pcib.mic = 0;
1654 j->pld_slicw.pcib.spk = 0;
1655 outb(j->pld_slicw.byte, j->XILINXbase + 0x01);
1656 break;
1657 case QTI_LINEJACK:
1658 ixj_set_pots(j, 0);
1659 if (ixj_WriteDSPCommand(0xC528, j))
1660
1661 return 2;
1662 j->pld_scrw.bits.daafsyncen = 0;
1663
1664 outb(j->pld_scrw.byte, j->XILINXbase);
1665 j->pld_clock.byte = 0;
1666 outb(j->pld_clock.byte, j->XILINXbase + 0x04);
1667 j->pld_slicw.bits.rly1 = 1;
1668 j->pld_slicw.bits.spken = 0;
1669 outb(j->pld_slicw.byte, j->XILINXbase + 0x01);
1670 ixj_mixer(0x1200, j);
1671 ixj_mixer(0x1401, j);
1672 ixj_mixer(0x1300, j);
1673 ixj_mixer(0x1501, j);
1674 ixj_mixer(0x0E80, j);
1675 ixj_mixer(0x0F00, j);
1676 ixj_mixer(0x0080, j);
1677 ixj_mixer(0x0180, j);
1678 SLIC_SetState(PLD_SLIC_STATE_STANDBY, j);
1679
1680 break;
1681 case QTI_PHONEJACK:
1682 j->gpio.bytes.high = 0x0B;
1683 j->gpio.bits.gpio6 = 0;
1684 j->gpio.bits.gpio7 = 0;
1685 ixj_WriteDSPCommand(j->gpio.word, j);
1686 break;
1687 }
1688 break;
1689 case PORT_PSTN:
1690 if (j->cardtype == QTI_LINEJACK) {
1691 ixj_WriteDSPCommand(0xC534, j);
1692
1693 j->pld_slicw.bits.rly3 = 0;
1694 j->pld_slicw.bits.rly1 = 1;
1695 j->pld_slicw.bits.spken = 0;
1696 outb(j->pld_slicw.byte, j->XILINXbase + 0x01);
1697 j->port = PORT_PSTN;
1698 } else {
1699 return 4;
1700 }
1701 break;
1702 case PORT_SPEAKER:
1703 j->port = PORT_SPEAKER;
1704 switch (j->cardtype) {
1705 case QTI_PHONECARD:
1706 if (j->flags.pcmciasct) {
1707 SLIC_SetState(PLD_SLIC_STATE_OC, j);
1708 }
1709 break;
1710 case QTI_PHONEJACK_PCI:
1711 j->pld_slicw.pcib.mic = 1;
1712 j->pld_slicw.pcib.spk = 1;
1713 outb(j->pld_slicw.byte, j->XILINXbase + 0x01);
1714 break;
1715 case QTI_LINEJACK:
1716 ixj_set_pots(j, 0);
1717 if (ixj_WriteDSPCommand(0xC528, j))
1718
1719 return 2;
1720 j->pld_scrw.bits.daafsyncen = 0;
1721
1722 outb(j->pld_scrw.byte, j->XILINXbase);
1723 j->pld_clock.byte = 0;
1724 outb(j->pld_clock.byte, j->XILINXbase + 0x04);
1725 j->pld_slicw.bits.rly1 = 1;
1726 j->pld_slicw.bits.spken = 1;
1727 outb(j->pld_slicw.byte, j->XILINXbase + 0x01);
1728 ixj_mixer(0x1201, j);
1729 ixj_mixer(0x1400, j);
1730 ixj_mixer(0x1301, j);
1731 ixj_mixer(0x1500, j);
1732 ixj_mixer(0x0E06, j);
1733 ixj_mixer(0x0F80, j);
1734 ixj_mixer(0x0000, j);
1735 ixj_mixer(0x0100, j);
1736 break;
1737 case QTI_PHONEJACK:
1738 j->gpio.bytes.high = 0x0B;
1739 j->gpio.bits.gpio6 = 0;
1740 j->gpio.bits.gpio7 = 1;
1741 ixj_WriteDSPCommand(j->gpio.word, j);
1742 break;
1743 }
1744 break;
1745 case PORT_HANDSET:
1746 if (j->cardtype != QTI_PHONEJACK) {
1747 return 5;
1748 } else {
1749 j->gpio.bytes.high = 0x0B;
1750 j->gpio.bits.gpio6 = 1;
1751 j->gpio.bits.gpio7 = 0;
1752 ixj_WriteDSPCommand(j->gpio.word, j);
1753 j->port = PORT_HANDSET;
1754 }
1755 break;
1756 default:
1757 return 6;
1758 break;
1759 }
1760 return 0;
1761}
1762
1763static int ixj_set_pots(IXJ *j, int arg)
1764{
1765 if (j->cardtype == QTI_LINEJACK) {
1766 if (arg) {
1767 if (j->port == PORT_PSTN) {
1768 j->pld_slicw.bits.rly1 = 0;
1769 outb(j->pld_slicw.byte, j->XILINXbase + 0x01);
1770 j->flags.pots_pstn = 1;
1771 return 1;
1772 } else {
1773 j->flags.pots_pstn = 0;
1774 return 0;
1775 }
1776 } else {
1777 j->pld_slicw.bits.rly1 = 1;
1778 outb(j->pld_slicw.byte, j->XILINXbase + 0x01);
1779 j->flags.pots_pstn = 0;
1780 return 1;
1781 }
1782 } else {
1783 return 0;
1784 }
1785}
1786
1787static void ixj_ring_on(IXJ *j)
1788{
1789 if (j->dsp.low == 0x20)
1790 {
1791 if (ixjdebug & 0x0004)
1792 printk(KERN_INFO "IXJ Ring On /dev/phone%d\n", j->board);
1793
1794 j->gpio.bytes.high = 0x0B;
1795 j->gpio.bytes.low = 0x00;
1796 j->gpio.bits.gpio1 = 1;
1797 j->gpio.bits.gpio2 = 1;
1798 j->gpio.bits.gpio5 = 0;
1799 ixj_WriteDSPCommand(j->gpio.word, j);
1800 } else
1801 {
1802 if (ixjdebug & 0x0004)
1803 printk(KERN_INFO "IXJ Ring On /dev/phone%d\n", j->board);
1804
1805 SLIC_SetState(PLD_SLIC_STATE_RINGING, j);
1806 }
1807}
1808
1809static int ixj_siadc(IXJ *j, int val)
1810{
1811 if(j->cardtype == QTI_PHONECARD){
1812 if(j->flags.pcmciascp){
1813 if(val == -1)
1814 return j->siadc.bits.rxg;
1815
1816 if(val < 0 || val > 0x1F)
1817 return -1;
1818
1819 j->siadc.bits.hom = 0;
1820 j->siadc.bits.lom = 0;
1821 j->siadc.bits.rxg = val;
1822 j->psccr.bits.addr = 6;
1823 j->psccr.bits.rw = 0;
1824 j->psccr.bits.dev = 0;
1825 outb(j->siadc.byte, j->XILINXbase + 0x00);
1826 outb(j->psccr.byte, j->XILINXbase + 0x01);
1827 ixj_PCcontrol_wait(j);
1828 return j->siadc.bits.rxg;
1829 }
1830 }
1831 return -1;
1832}
1833
1834static int ixj_sidac(IXJ *j, int val)
1835{
1836 if(j->cardtype == QTI_PHONECARD){
1837 if(j->flags.pcmciascp){
1838 if(val == -1)
1839 return j->sidac.bits.txg;
1840
1841 if(val < 0 || val > 0x1F)
1842 return -1;
1843
1844 j->sidac.bits.srm = 1;
1845 j->sidac.bits.slm = 1;
1846 j->sidac.bits.txg = val;
1847 j->psccr.bits.addr = 7;
1848 j->psccr.bits.rw = 0;
1849 j->psccr.bits.dev = 0;
1850 outb(j->sidac.byte, j->XILINXbase + 0x00);
1851 outb(j->psccr.byte, j->XILINXbase + 0x01);
1852 ixj_PCcontrol_wait(j);
1853 return j->sidac.bits.txg;
1854 }
1855 }
1856 return -1;
1857}
1858
1859static int ixj_pcmcia_cable_check(IXJ *j)
1860{
1861 j->pccr1.byte = inb_p(j->XILINXbase + 0x03);
1862 if (!j->flags.pcmciastate) {
1863 j->pccr2.byte = inb_p(j->XILINXbase + 0x02);
1864 if (j->pccr1.bits.drf || j->pccr2.bits.rstc) {
1865 j->flags.pcmciastate = 4;
1866 return 0;
1867 }
1868 if (j->pccr1.bits.ed) {
1869 j->pccr1.bits.ed = 0;
1870 j->psccr.bits.dev = 3;
1871 j->psccr.bits.rw = 1;
1872 outw_p(j->psccr.byte << 8, j->XILINXbase + 0x00);
1873 ixj_PCcontrol_wait(j);
1874 j->pslic.byte = inw_p(j->XILINXbase + 0x00) & 0xFF;
1875 j->pslic.bits.led2 = j->pslic.bits.det ? 1 : 0;
1876 j->psccr.bits.dev = 3;
1877 j->psccr.bits.rw = 0;
1878 outw_p(j->psccr.byte << 8 | j->pslic.byte, j->XILINXbase + 0x00);
1879 ixj_PCcontrol_wait(j);
1880 return j->pslic.bits.led2 ? 1 : 0;
1881 } else if (j->flags.pcmciasct) {
1882 return j->r_hook;
1883 } else {
1884 return 1;
1885 }
1886 } else if (j->flags.pcmciastate == 4) {
1887 if (!j->pccr1.bits.drf) {
1888 j->flags.pcmciastate = 3;
1889 }
1890 return 0;
1891 } else if (j->flags.pcmciastate == 3) {
1892 j->pccr2.bits.pwr = 0;
1893 j->pccr2.bits.rstc = 1;
1894 outb(j->pccr2.byte, j->XILINXbase + 0x02);
1895 j->checkwait = jiffies + (hertz * 2);
1896 j->flags.incheck = 1;
1897 j->flags.pcmciastate = 2;
1898 return 0;
1899 } else if (j->flags.pcmciastate == 2) {
1900 if (j->flags.incheck) {
1901 if (time_before(jiffies, j->checkwait)) {
1902 return 0;
1903 } else {
1904 j->flags.incheck = 0;
1905 }
1906 }
1907 j->pccr2.bits.pwr = 0;
1908 j->pccr2.bits.rstc = 0;
1909 outb_p(j->pccr2.byte, j->XILINXbase + 0x02);
1910 j->flags.pcmciastate = 1;
1911 return 0;
1912 } else if (j->flags.pcmciastate == 1) {
1913 j->flags.pcmciastate = 0;
1914 if (!j->pccr1.bits.drf) {
1915 j->psccr.bits.dev = 3;
1916 j->psccr.bits.rw = 1;
1917 outb_p(j->psccr.byte, j->XILINXbase + 0x01);
1918 ixj_PCcontrol_wait(j);
1919 j->flags.pcmciascp = 1;
1920
1921 j->flags.pcmciasct = (inw_p(j->XILINXbase + 0x00) >> 8) & 0x03;
1922
1923 if (j->flags.pcmciasct == 3) {
1924 j->flags.pcmciastate = 4;
1925 return 0;
1926 } else if (j->flags.pcmciasct == 0) {
1927 j->pccr2.bits.pwr = 1;
1928 j->pccr2.bits.rstc = 0;
1929 outb_p(j->pccr2.byte, j->XILINXbase + 0x02);
1930 j->port = PORT_SPEAKER;
1931 } else {
1932 j->port = PORT_POTS;
1933 }
1934 j->sic1.bits.cpd = 0;
1935 j->sic1.bits.mpd = 0;
1936 j->sic1.bits.hpd = 0;
1937 j->sic1.bits.lpd = 0;
1938 j->sic1.bits.spd = 1;
1939 j->psccr.bits.addr = 1;
1940 j->psccr.bits.rw = 0;
1941 j->psccr.bits.dev = 0;
1942 outb(j->sic1.byte, j->XILINXbase + 0x00);
1943 outb(j->psccr.byte, j->XILINXbase + 0x01);
1944 ixj_PCcontrol_wait(j);
1945
1946 j->sic2.bits.al = 0;
1947 j->sic2.bits.dl2 = 0;
1948 j->sic2.bits.dl1 = 0;
1949 j->sic2.bits.pll = 0;
1950 j->sic2.bits.hpd = 0;
1951 j->psccr.bits.addr = 2;
1952 j->psccr.bits.rw = 0;
1953 j->psccr.bits.dev = 0;
1954 outb(j->sic2.byte, j->XILINXbase + 0x00);
1955 outb(j->psccr.byte, j->XILINXbase + 0x01);
1956 ixj_PCcontrol_wait(j);
1957
1958 j->psccr.bits.addr = 3;
1959 j->psccr.bits.rw = 0;
1960 j->psccr.bits.dev = 0;
1961 outb(0x00, j->XILINXbase + 0x00);
1962 outb(j->psccr.byte, j->XILINXbase + 0x01);
1963 ixj_PCcontrol_wait(j);
1964
1965 j->psccr.bits.addr = 4;
1966 j->psccr.bits.rw = 0;
1967 j->psccr.bits.dev = 0;
1968 outb(0x09, j->XILINXbase + 0x00);
1969 outb(j->psccr.byte, j->XILINXbase + 0x01);
1970 ixj_PCcontrol_wait(j);
1971
1972 j->sirxg.bits.lig = 1;
1973 j->sirxg.bits.lim = 1;
1974 j->sirxg.bits.mcg = 0;
1975 j->sirxg.bits.mcm = 0;
1976 j->sirxg.bits.him = 0;
1977 j->sirxg.bits.iir = 1;
1978 j->psccr.bits.addr = 5;
1979 j->psccr.bits.rw = 0;
1980 j->psccr.bits.dev = 0;
1981 outb(j->sirxg.byte, j->XILINXbase + 0x00);
1982 outb(j->psccr.byte, j->XILINXbase + 0x01);
1983 ixj_PCcontrol_wait(j);
1984
1985 ixj_siadc(j, 0x17);
1986 ixj_sidac(j, 0x1D);
1987
1988 j->siaatt.bits.sot = 0;
1989 j->psccr.bits.addr = 9;
1990 j->psccr.bits.rw = 0;
1991 j->psccr.bits.dev = 0;
1992 outb(j->siaatt.byte, j->XILINXbase + 0x00);
1993 outb(j->psccr.byte, j->XILINXbase + 0x01);
1994 ixj_PCcontrol_wait(j);
1995
1996 if (j->flags.pcmciasct == 1 && !j->readers && !j->writers) {
1997 j->psccr.byte = j->pslic.byte = 0;
1998 j->pslic.bits.powerdown = 1;
1999 j->psccr.bits.dev = 3;
2000 j->psccr.bits.rw = 0;
2001 outw_p(j->psccr.byte << 8 | j->pslic.byte, j->XILINXbase + 0x00);
2002 ixj_PCcontrol_wait(j);
2003 }
2004 }
2005 return 0;
2006 } else {
2007 j->flags.pcmciascp = 0;
2008 return 0;
2009 }
2010 return 0;
2011}
2012
2013static int ixj_hookstate(IXJ *j)
2014{
2015 unsigned long det;
2016 int fOffHook = 0;
2017
2018 switch (j->cardtype) {
2019 case QTI_PHONEJACK:
2020 ixj_gpio_read(j);
2021 fOffHook = j->gpio.bits.gpio3read ? 1 : 0;
2022 break;
2023 case QTI_LINEJACK:
2024 case QTI_PHONEJACK_LITE:
2025 case QTI_PHONEJACK_PCI:
2026 SLIC_GetState(j);
2027 if(j->cardtype == QTI_LINEJACK && j->flags.pots_pstn == 1 && (j->readers || j->writers)) {
2028 fOffHook = j->pld_slicr.bits.potspstn ? 1 : 0;
2029 if(fOffHook != j->p_hook) {
2030 if(!j->checkwait) {
2031 j->checkwait = jiffies;
2032 }
2033 if(time_before(jiffies, j->checkwait + 2)) {
2034 fOffHook ^= 1;
2035 } else {
2036 j->checkwait = 0;
2037 }
2038 j->p_hook = fOffHook;
2039 printk("IXJ : /dev/phone%d pots-pstn hookstate check %d at %ld\n", j->board, fOffHook, jiffies);
2040 }
2041 } else {
2042 if (j->pld_slicr.bits.state == PLD_SLIC_STATE_ACTIVE ||
2043 j->pld_slicr.bits.state == PLD_SLIC_STATE_STANDBY) {
2044 if (j->flags.ringing || j->flags.cringing) {
2045 if (!in_interrupt()) {
2046 det = jiffies + (hertz / 50);
2047 while (time_before(jiffies, det)) {
2048 set_current_state(TASK_INTERRUPTIBLE);
2049 schedule_timeout(1);
2050 }
2051 }
2052 SLIC_GetState(j);
2053 if (j->pld_slicr.bits.state == PLD_SLIC_STATE_RINGING) {
2054 ixj_ring_on(j);
2055 }
2056 }
2057 if (j->cardtype == QTI_PHONEJACK_PCI) {
2058 j->pld_scrr.byte = inb_p(j->XILINXbase);
2059 fOffHook = j->pld_scrr.pcib.det ? 1 : 0;
2060 } else
2061 fOffHook = j->pld_slicr.bits.det ? 1 : 0;
2062 }
2063 }
2064 break;
2065 case QTI_PHONECARD:
2066 fOffHook = ixj_pcmcia_cable_check(j);
2067 break;
2068 }
2069 if (j->r_hook != fOffHook) {
2070 j->r_hook = fOffHook;
2071 if (j->port == PORT_SPEAKER || j->port == PORT_HANDSET) {
2072 j->ex.bits.hookstate = 1;
2073 ixj_kill_fasync(j, SIG_HOOKSTATE, POLL_IN);
2074 } else if (!fOffHook) {
2075 j->flash_end = jiffies + ((60 * hertz) / 100);
2076 }
2077 }
2078 if (fOffHook) {
2079 if(time_before(jiffies, j->flash_end)) {
2080 j->ex.bits.flash = 1;
2081 j->flash_end = 0;
2082 ixj_kill_fasync(j, SIG_FLASH, POLL_IN);
2083 }
2084 } else {
2085 if(time_before(jiffies, j->flash_end)) {
2086 fOffHook = 1;
2087 }
2088 }
2089
2090 if (j->port == PORT_PSTN && j->daa_mode == SOP_PU_CONVERSATION)
2091 fOffHook |= 2;
2092
2093 if (j->port == PORT_SPEAKER) {
2094 if(j->cardtype == QTI_PHONECARD) {
2095 if(j->flags.pcmciascp && j->flags.pcmciasct) {
2096 fOffHook |= 2;
2097 }
2098 } else {
2099 fOffHook |= 2;
2100 }
2101 }
2102
2103 if (j->port == PORT_HANDSET)
2104 fOffHook |= 2;
2105
2106 return fOffHook;
2107}
2108
2109static void ixj_ring_off(IXJ *j)
2110{
2111 if (j->dsp.low == 0x20)
2112 {
2113 if (ixjdebug & 0x0004)
2114 printk(KERN_INFO "IXJ Ring Off\n");
2115 j->gpio.bytes.high = 0x0B;
2116 j->gpio.bytes.low = 0x00;
2117 j->gpio.bits.gpio1 = 0;
2118 j->gpio.bits.gpio2 = 1;
2119 j->gpio.bits.gpio5 = 0;
2120 ixj_WriteDSPCommand(j->gpio.word, j);
2121 } else
2122 {
2123 if (ixjdebug & 0x0004)
2124 printk(KERN_INFO "IXJ Ring Off\n");
2125
2126 if(!j->flags.cidplay)
2127 SLIC_SetState(PLD_SLIC_STATE_STANDBY, j);
2128
2129 SLIC_GetState(j);
2130 }
2131}
2132
2133static void ixj_ring_start(IXJ *j)
2134{
2135 j->flags.cringing = 1;
2136 if (ixjdebug & 0x0004)
2137 printk(KERN_INFO "IXJ Cadence Ringing Start /dev/phone%d\n", j->board);
2138 if (ixj_hookstate(j) & 1) {
2139 if (j->port == PORT_POTS)
2140 ixj_ring_off(j);
2141 j->flags.cringing = 0;
2142 if (ixjdebug & 0x0004)
2143 printk(KERN_INFO "IXJ Cadence Ringing Stopped /dev/phone%d off hook\n", j->board);
2144 } else if(j->cadence_f[5].enable && (!j->cadence_f[5].en_filter)) {
2145 j->ring_cadence_jif = jiffies;
2146 j->flags.cidsent = j->flags.cidring = 0;
2147 j->cadence_f[5].state = 0;
2148 if(j->cadence_f[5].on1)
2149 ixj_ring_on(j);
2150 } else {
2151 j->ring_cadence_jif = jiffies;
2152 j->ring_cadence_t = 15;
2153 if (j->ring_cadence & 1 << j->ring_cadence_t) {
2154 ixj_ring_on(j);
2155 } else {
2156 ixj_ring_off(j);
2157 }
2158 j->flags.cidsent = j->flags.cidring = j->flags.firstring = 0;
2159 }
2160}
2161
2162static int ixj_ring(IXJ *j)
2163{
2164 char cntr;
2165 unsigned long jif, det;
2166
2167 j->flags.ringing = 1;
2168 if (ixj_hookstate(j) & 1) {
2169 ixj_ring_off(j);
2170 j->flags.ringing = 0;
2171 return 1;
2172 }
2173 det = 0;
2174 for (cntr = 0; cntr < j->maxrings; cntr++) {
2175 jif = jiffies + (1 * hertz);
2176 ixj_ring_on(j);
2177 while (time_before(jiffies, jif)) {
2178 if (ixj_hookstate(j) & 1) {
2179 ixj_ring_off(j);
2180 j->flags.ringing = 0;
2181 return 1;
2182 }
2183 set_current_state(TASK_INTERRUPTIBLE);
2184 schedule_timeout(1);
2185 if (signal_pending(current))
2186 break;
2187 }
2188 jif = jiffies + (3 * hertz);
2189 ixj_ring_off(j);
2190 while (time_before(jiffies, jif)) {
2191 if (ixj_hookstate(j) & 1) {
2192 det = jiffies + (hertz / 100);
2193 while (time_before(jiffies, det)) {
2194 set_current_state(TASK_INTERRUPTIBLE);
2195 schedule_timeout(1);
2196 if (signal_pending(current))
2197 break;
2198 }
2199 if (ixj_hookstate(j) & 1) {
2200 j->flags.ringing = 0;
2201 return 1;
2202 }
2203 }
2204 set_current_state(TASK_INTERRUPTIBLE);
2205 schedule_timeout(1);
2206 if (signal_pending(current))
2207 break;
2208 }
2209 }
2210 ixj_ring_off(j);
2211 j->flags.ringing = 0;
2212 return 0;
2213}
2214
2215static int ixj_open(struct phone_device *p, struct file *file_p)
2216{
2217 IXJ *j = get_ixj(p->board);
2218 file_p->private_data = j;
2219
2220 if (!j->DSPbase)
2221 return -ENODEV;
2222
2223 if (file_p->f_mode & FMODE_READ) {
2224 if(!j->readers) {
2225 j->readers++;
2226 } else {
2227 return -EBUSY;
2228 }
2229 }
2230
2231 if (file_p->f_mode & FMODE_WRITE) {
2232 if(!j->writers) {
2233 j->writers++;
2234 } else {
2235 if (file_p->f_mode & FMODE_READ){
2236 j->readers--;
2237 }
2238 return -EBUSY;
2239 }
2240 }
2241
2242 if (j->cardtype == QTI_PHONECARD) {
2243 j->pslic.bits.powerdown = 0;
2244 j->psccr.bits.dev = 3;
2245 j->psccr.bits.rw = 0;
2246 outw_p(j->psccr.byte << 8 | j->pslic.byte, j->XILINXbase + 0x00);
2247 ixj_PCcontrol_wait(j);
2248 }
2249
2250 j->flags.cidplay = 0;
2251 j->flags.cidcw_ack = 0;
2252
2253 MOD_INC_USE_COUNT;
2254
2255 if (ixjdebug & 0x0002)
2256 printk(KERN_INFO "Opening board %d\n", p->board);
2257
2258 j->framesread = j->frameswritten = 0;
2259 return 0;
2260}
2261
2262int ixj_release(struct inode *inode, struct file *file_p)
2263{
2264 IXJ_TONE ti;
2265 int cnt;
2266 IXJ *j = file_p->private_data;
2267 int board = j->p.board;
2268
2269
2270
2271
2272
2273 while(test_and_set_bit(board, (void *)&j->busyflags) != 0) {
2274 set_current_state(TASK_INTERRUPTIBLE);
2275 schedule_timeout(1);
2276 }
2277 if (ixjdebug & 0x0002)
2278 printk(KERN_INFO "Closing board %d\n", NUM(inode->i_rdev));
2279
2280 if (j->cardtype == QTI_PHONECARD)
2281 ixj_set_port(j, PORT_SPEAKER);
2282 else
2283 ixj_set_port(j, PORT_POTS);
2284
2285 aec_stop(j);
2286 ixj_play_stop(j);
2287 ixj_record_stop(j);
2288 set_play_volume(j, 0x100);
2289 set_rec_volume(j, 0x100);
2290 ixj_ring_off(j);
2291
2292
2293 ti.tone_index = 10;
2294 ti.gain0 = 1;
2295 ti.freq0 = hz941;
2296 ti.gain1 = 0;
2297 ti.freq1 = hz1209;
2298 ixj_init_tone(j, &ti);
2299 ti.tone_index = 11;
2300 ti.gain0 = 1;
2301 ti.freq0 = hz941;
2302 ti.gain1 = 0;
2303 ti.freq1 = hz1336;
2304 ixj_init_tone(j, &ti);
2305 ti.tone_index = 12;
2306 ti.gain0 = 1;
2307 ti.freq0 = hz941;
2308 ti.gain1 = 0;
2309 ti.freq1 = hz1477;
2310 ixj_init_tone(j, &ti);
2311 ti.tone_index = 13;
2312 ti.gain0 = 1;
2313 ti.freq0 = hz800;
2314 ti.gain1 = 0;
2315 ti.freq1 = 0;
2316 ixj_init_tone(j, &ti);
2317 ti.tone_index = 14;
2318 ti.gain0 = 1;
2319 ti.freq0 = hz1000;
2320 ti.gain1 = 0;
2321 ti.freq1 = 0;
2322 ixj_init_tone(j, &ti);
2323 ti.tone_index = 15;
2324 ti.gain0 = 1;
2325 ti.freq0 = hz1250;
2326 ti.gain1 = 0;
2327 ti.freq1 = 0;
2328 ixj_init_tone(j, &ti);
2329 ti.tone_index = 16;
2330 ti.gain0 = 1;
2331 ti.freq0 = hz950;
2332 ti.gain1 = 0;
2333 ti.freq1 = 0;
2334 ixj_init_tone(j, &ti);
2335 ti.tone_index = 17;
2336 ti.gain0 = 1;
2337 ti.freq0 = hz1100;
2338 ti.gain1 = 0;
2339 ti.freq1 = 0;
2340 ixj_init_tone(j, &ti);
2341 ti.tone_index = 18;
2342 ti.gain0 = 1;
2343 ti.freq0 = hz1400;
2344 ti.gain1 = 0;
2345 ti.freq1 = 0;
2346 ixj_init_tone(j, &ti);
2347 ti.tone_index = 19;
2348 ti.gain0 = 1;
2349 ti.freq0 = hz1500;
2350 ti.gain1 = 0;
2351 ti.freq1 = 0;
2352 ixj_init_tone(j, &ti);
2353 ti.tone_index = 20;
2354 ti.gain0 = 1;
2355 ti.freq0 = hz1600;
2356 ti.gain1 = 0;
2357 ti.freq1 = 0;
2358 ixj_init_tone(j, &ti);
2359 ti.tone_index = 21;
2360 ti.gain0 = 1;
2361 ti.freq0 = hz1800;
2362 ti.gain1 = 0;
2363 ti.freq1 = 0;
2364 ixj_init_tone(j, &ti);
2365 ti.tone_index = 22;
2366 ti.gain0 = 1;
2367 ti.freq0 = hz2100;
2368 ti.gain1 = 0;
2369 ti.freq1 = 0;
2370 ixj_init_tone(j, &ti);
2371 ti.tone_index = 23;
2372 ti.gain0 = 1;
2373 ti.freq0 = hz1300;
2374 ti.gain1 = 0;
2375 ti.freq1 = 0;
2376 ixj_init_tone(j, &ti);
2377 ti.tone_index = 24;
2378 ti.gain0 = 1;
2379 ti.freq0 = hz2450;
2380 ti.gain1 = 0;
2381 ti.freq1 = 0;
2382 ixj_init_tone(j, &ti);
2383 ti.tone_index = 25;
2384 ti.gain0 = 1;
2385 ti.freq0 = hz350;
2386 ti.gain1 = 0;
2387 ti.freq1 = hz440;
2388 ixj_init_tone(j, &ti);
2389 ti.tone_index = 26;
2390 ti.gain0 = 1;
2391 ti.freq0 = hz440;
2392 ti.gain1 = 0;
2393 ti.freq1 = hz480;
2394 ixj_init_tone(j, &ti);
2395 ti.tone_index = 27;
2396 ti.gain0 = 1;
2397 ti.freq0 = hz480;
2398 ti.gain1 = 0;
2399 ti.freq1 = hz620;
2400 ixj_init_tone(j, &ti);
2401
2402 set_rec_depth(j, 2);
2403
2404 set_play_depth(j, 2);
2405
2406 j->ex.bits.dtmf_ready = 0;
2407 j->dtmf_state = 0;
2408 j->dtmf_wp = j->dtmf_rp = 0;
2409 j->rec_mode = j->play_mode = -1;
2410 j->flags.ringing = 0;
2411 j->maxrings = MAXRINGS;
2412 j->ring_cadence = USA_RING_CADENCE;
2413 if(j->cadence_f[5].enable) {
2414 j->cadence_f[5].enable = j->cadence_f[5].en_filter = j->cadence_f[5].state = 0;
2415 }
2416 j->drybuffer = 0;
2417 j->winktime = 320;
2418 j->flags.dtmf_oob = 0;
2419 for (cnt = 0; cnt < 4; cnt++)
2420 j->cadence_f[cnt].enable = 0;
2421
2422 idle(j);
2423
2424 if(j->cardtype == QTI_PHONECARD) {
2425 SLIC_SetState(PLD_SLIC_STATE_OC, j);
2426 }
2427
2428 if (file_p->f_mode & FMODE_READ)
2429 j->readers--;
2430 if (file_p->f_mode & FMODE_WRITE)
2431 j->writers--;
2432
2433 if (j->read_buffer && !j->readers) {
2434 kfree(j->read_buffer);
2435 j->read_buffer = NULL;
2436 j->read_buffer_size = 0;
2437 }
2438 if (j->write_buffer && !j->writers) {
2439 kfree(j->write_buffer);
2440 j->write_buffer = NULL;
2441 j->write_buffer_size = 0;
2442 }
2443 j->rec_codec = j->play_codec = 0;
2444 j->rec_frame_size = j->play_frame_size = 0;
2445 j->flags.cidsent = j->flags.cidring = 0;
2446 ixj_fasync(-1, file_p, 0);
2447
2448 if(j->cardtype == QTI_LINEJACK && !j->readers && !j->writers) {
2449 ixj_set_port(j, PORT_PSTN);
2450 daa_set_mode(j, SOP_PU_SLEEP);
2451 ixj_set_pots(j, 1);
2452 }
2453 ixj_WriteDSPCommand(0x0FE3, j);
2454
2455
2456 for (cnt = 0; cnt < 35; cnt++)
2457 j->ixj_signals[cnt] = SIGIO;
2458
2459
2460 j->ex_sig.bits.dtmf_ready = j->ex_sig.bits.hookstate = j->ex_sig.bits.flash = j->ex_sig.bits.pstn_ring =
2461 j->ex_sig.bits.caller_id = j->ex_sig.bits.pstn_wink = j->ex_sig.bits.f0 = j->ex_sig.bits.f1 = j->ex_sig.bits.f2 =
2462 j->ex_sig.bits.f3 = j->ex_sig.bits.fc0 = j->ex_sig.bits.fc1 = j->ex_sig.bits.fc2 = j->ex_sig.bits.fc3 = 1;
2463
2464 file_p->private_data = NULL;
2465 clear_bit(board, &j->busyflags);
2466 MOD_DEC_USE_COUNT;
2467 return 0;
2468}
2469
2470static int read_filters(IXJ *j)
2471{
2472 unsigned short fc, cnt, trg;
2473 int var;
2474
2475 trg = 0;
2476 if (ixj_WriteDSPCommand(0x5144, j)) {
2477 if(ixjdebug & 0x0001) {
2478 printk(KERN_INFO "Read Frame Counter failed!\n");
2479 }
2480 return -1;
2481 }
2482 fc = j->ssr.high << 8 | j->ssr.low;
2483 if (fc == j->frame_count)
2484 return 1;
2485
2486 j->frame_count = fc;
2487
2488 if (j->dtmf_proc)
2489 return 1;
2490
2491 var = 10;
2492
2493 for (cnt = 0; cnt < 4; cnt++) {
2494 if (ixj_WriteDSPCommand(0x5154 + cnt, j)) {
2495 if(ixjdebug & 0x0001) {
2496 printk(KERN_INFO "Select Filter %d failed!\n", cnt);
2497 }
2498 return -1;
2499 }
2500 if (ixj_WriteDSPCommand(0x515C, j)) {
2501 if(ixjdebug & 0x0001) {
2502 printk(KERN_INFO "Read Filter History %d failed!\n", cnt);
2503 }
2504 return -1;
2505 }
2506 j->filter_hist[cnt] = j->ssr.high << 8 | j->ssr.low;
2507
2508 if (j->cadence_f[cnt].enable) {
2509 if (j->filter_hist[cnt] & 3 && !(j->filter_hist[cnt] & 12)) {
2510 if (j->cadence_f[cnt].state == 0) {
2511 j->cadence_f[cnt].state = 1;
2512 j->cadence_f[cnt].on1min = jiffies + (long)((j->cadence_f[cnt].on1 * (hertz * (100 - var)) / 10000));
2513 j->cadence_f[cnt].on1dot = jiffies + (long)((j->cadence_f[cnt].on1 * (hertz * (100)) / 10000));
2514 j->cadence_f[cnt].on1max = jiffies + (long)((j->cadence_f[cnt].on1 * (hertz * (100 + var)) / 10000));
2515 } else if (j->cadence_f[cnt].state == 2 &&
2516 (time_after(jiffies, j->cadence_f[cnt].off1min) &&
2517 time_before(jiffies, j->cadence_f[cnt].off1max))) {
2518 if (j->cadence_f[cnt].on2) {
2519 j->cadence_f[cnt].state = 3;
2520 j->cadence_f[cnt].on2min = jiffies + (long)((j->cadence_f[cnt].on2 * (hertz * (100 - var)) / 10000));
2521 j->cadence_f[cnt].on2dot = jiffies + (long)((j->cadence_f[cnt].on2 * (hertz * (100)) / 10000));
2522 j->cadence_f[cnt].on2max = jiffies + (long)((j->cadence_f[cnt].on2 * (hertz * (100 + var)) / 10000));
2523 } else {
2524 j->cadence_f[cnt].state = 7;
2525 }
2526 } else if (j->cadence_f[cnt].state == 4 &&
2527 (time_after(jiffies, j->cadence_f[cnt].off2min) &&
2528 time_before(jiffies, j->cadence_f[cnt].off2max))) {
2529 if (j->cadence_f[cnt].on3) {
2530 j->cadence_f[cnt].state = 5;
2531 j->cadence_f[cnt].on3min = jiffies + (long)((j->cadence_f[cnt].on3 * (hertz * (100 - var)) / 10000));
2532 j->cadence_f[cnt].on3dot = jiffies + (long)((j->cadence_f[cnt].on3 * (hertz * (100)) / 10000));
2533 j->cadence_f[cnt].on3max = jiffies + (long)((j->cadence_f[cnt].on3 * (hertz * (100 + var)) / 10000));
2534 } else {
2535 j->cadence_f[cnt].state = 7;
2536 }
2537 } else {
2538 j->cadence_f[cnt].state = 0;
2539 }
2540 } else if (j->filter_hist[cnt] & 12 && !(j->filter_hist[cnt] & 3)) {
2541 if (j->cadence_f[cnt].state == 1) {
2542 if(!j->cadence_f[cnt].on1) {
2543 j->cadence_f[cnt].state = 7;
2544 } else if((time_after(jiffies, j->cadence_f[cnt].on1min) &&
2545 time_before(jiffies, j->cadence_f[cnt].on1max))) {
2546 if(j->cadence_f[cnt].off1) {
2547 j->cadence_f[cnt].state = 2;
2548 j->cadence_f[cnt].off1min = jiffies + (long)((j->cadence_f[cnt].off1 * (hertz * (100 - var)) / 10000));
2549 j->cadence_f[cnt].off1dot = jiffies + (long)((j->cadence_f[cnt].off1 * (hertz * (100)) / 10000));
2550 j->cadence_f[cnt].off1max = jiffies + (long)((j->cadence_f[cnt].off1 * (hertz * (100 + var)) / 10000));
2551 } else {
2552 j->cadence_f[cnt].state = 7;
2553 }
2554 } else {
2555 j->cadence_f[cnt].state = 0;
2556 }
2557 } else if (j->cadence_f[cnt].state == 3) {
2558 if((time_after(jiffies, j->cadence_f[cnt].on2min) &&
2559 time_before(jiffies, j->cadence_f[cnt].on2max))) {
2560 if(j->cadence_f[cnt].off2) {
2561 j->cadence_f[cnt].state = 4;
2562 j->cadence_f[cnt].off2min = jiffies + (long)((j->cadence_f[cnt].off2 * (hertz * (100 - var)) / 10000));
2563 j->cadence_f[cnt].off2dot = jiffies + (long)((j->cadence_f[cnt].off2 * (hertz * (100)) / 10000));
2564 j->cadence_f[cnt].off2max = jiffies + (long)((j->cadence_f[cnt].off2 * (hertz * (100 + var)) / 10000));
2565 } else {
2566 j->cadence_f[cnt].state = 7;
2567 }
2568 } else {
2569 j->cadence_f[cnt].state = 0;
2570 }
2571 } else if (j->cadence_f[cnt].state == 5) {
2572 if ((time_after(jiffies, j->cadence_f[cnt].on3min) &&
2573 time_before(jiffies, j->cadence_f[cnt].on3max))) {
2574 if(j->cadence_f[cnt].off3) {
2575 j->cadence_f[cnt].state = 6;
2576 j->cadence_f[cnt].off3min = jiffies + (long)((j->cadence_f[cnt].off3 * (hertz * (100 - var)) / 10000));
2577 j->cadence_f[cnt].off3dot = jiffies + (long)((j->cadence_f[cnt].off3 * (hertz * (100)) / 10000));
2578 j->cadence_f[cnt].off3max = jiffies + (long)((j->cadence_f[cnt].off3 * (hertz * (100 + var)) / 10000));
2579 } else {
2580 j->cadence_f[cnt].state = 7;
2581 }
2582 } else {
2583 j->cadence_f[cnt].state = 0;
2584 }
2585 } else {
2586 j->cadence_f[cnt].state = 0;
2587 }
2588 } else {
2589 switch(j->cadence_f[cnt].state) {
2590 case 1:
2591 if(time_after(jiffies, j->cadence_f[cnt].on1dot) &&
2592 !j->cadence_f[cnt].off1 &&
2593 !j->cadence_f[cnt].on2 && !j->cadence_f[cnt].off2 &&
2594 !j->cadence_f[cnt].on3 && !j->cadence_f[cnt].off3) {
2595 j->cadence_f[cnt].state = 7;
2596 }
2597 break;
2598 case 3:
2599 if(time_after(jiffies, j->cadence_f[cnt].on2dot) &&
2600 !j->cadence_f[cnt].off2 &&
2601 !j->cadence_f[cnt].on3 && !j->cadence_f[cnt].off3) {
2602 j->cadence_f[cnt].state = 7;
2603 }
2604 break;
2605 case 5:
2606 if(time_after(jiffies, j->cadence_f[cnt].on3dot) &&
2607 !j->cadence_f[cnt].off3) {
2608 j->cadence_f[cnt].state = 7;
2609 }
2610 break;
2611 }
2612 }
2613
2614 if (ixjdebug & 0x0040) {
2615 printk(KERN_INFO "IXJ Tone Cadence state = %d /dev/phone%d at %ld\n", j->cadence_f[cnt].state, j->board, jiffies);
2616 switch(j->cadence_f[cnt].state) {
2617 case 0:
2618 printk(KERN_INFO "IXJ /dev/phone%d No Tone detected\n", j->board);
2619 break;
2620 case 1:
2621 printk(KERN_INFO "IXJ /dev/phone%d Next Tone Cadence state at %u %ld - %ld - %ld\n", j->board,
2622 j->cadence_f[cnt].on1, j->cadence_f[cnt].on1min, j->cadence_f[cnt].on1dot, j->cadence_f[cnt].on1max);
2623 break;
2624 case 2:
2625 printk(KERN_INFO "IXJ /dev/phone%d Next Tone Cadence state at %ld - %ld\n", j->board, j->cadence_f[cnt].off1min,
2626 j->cadence_f[cnt].off1max);
2627 break;
2628 case 3:
2629 printk(KERN_INFO "IXJ /dev/phone%d Next Tone Cadence state at %ld - %ld\n", j->board, j->cadence_f[cnt].on2min,
2630 j->cadence_f[cnt].on2max);
2631 break;
2632 case 4:
2633 printk(KERN_INFO "IXJ /dev/phone%d Next Tone Cadence state at %ld - %ld\n", j->board, j->cadence_f[cnt].off2min,
2634 j->cadence_f[cnt].off2max);
2635 break;
2636 case 5:
2637 printk(KERN_INFO "IXJ /dev/phone%d Next Tone Cadence state at %ld - %ld\n", j->board, j->cadence_f[cnt].on3min,
2638 j->cadence_f[cnt].on3max);
2639 break;
2640 case 6:
2641 printk(KERN_INFO "IXJ /dev/phone%d Next Tone Cadence state at %ld - %ld\n", j->board, j->cadence_f[cnt].off3min,
2642 j->cadence_f[cnt].off3max);
2643 break;
2644 }
2645 }
2646 }
2647 if (j->cadence_f[cnt].state == 7) {
2648 j->cadence_f[cnt].state = 0;
2649 if (j->cadence_f[cnt].enable == 1)
2650 j->cadence_f[cnt].enable = 0;
2651 switch (cnt) {
2652 case 0:
2653 if(ixjdebug & 0x0020) {
2654 printk(KERN_INFO "Filter Cadence 0 triggered %ld\n", jiffies);
2655 }
2656 j->ex.bits.fc0 = 1;
2657 ixj_kill_fasync(j, SIG_FC0, POLL_IN);
2658 break;
2659 case 1:
2660 if(ixjdebug & 0x0020) {
2661 printk(KERN_INFO "Filter Cadence 1 triggered %ld\n", jiffies);
2662 }
2663 j->ex.bits.fc1 = 1;
2664 ixj_kill_fasync(j, SIG_FC1, POLL_IN);
2665 break;
2666 case 2:
2667 if(ixjdebug & 0x0020) {
2668 printk(KERN_INFO "Filter Cadence 2 triggered %ld\n", jiffies);
2669 }
2670 j->ex.bits.fc2 = 1;
2671 ixj_kill_fasync(j, SIG_FC2, POLL_IN);
2672 break;
2673 case 3:
2674 if(ixjdebug & 0x0020) {
2675 printk(KERN_INFO "Filter Cadence 3 triggered %ld\n", jiffies);
2676 }
2677 j->ex.bits.fc3 = 1;
2678 ixj_kill_fasync(j, SIG_FC3, POLL_IN);
2679 break;
2680 }
2681 }
2682 if (j->filter_en[cnt] && ((j->filter_hist[cnt] & 3 && !(j->filter_hist[cnt] & 12)) ||
2683 (j->filter_hist[cnt] & 12 && !(j->filter_hist[cnt] & 3)))) {
2684 if((j->filter_hist[cnt] & 3 && !(j->filter_hist[cnt] & 12))) {
2685 trg = 1;
2686 } else if((j->filter_hist[cnt] & 12 && !(j->filter_hist[cnt] & 3))) {
2687 trg = 0;
2688 }
2689 switch (cnt) {
2690 case 0:
2691 if(ixjdebug & 0x0020) {
2692 printk(KERN_INFO "Filter 0 triggered %d at %ld\n", trg, jiffies);
2693 }
2694 j->ex.bits.f0 = 1;
2695 ixj_kill_fasync(j, SIG_F0, POLL_IN);
2696 break;
2697 case 1:
2698 if(ixjdebug & 0x0020) {
2699 printk(KERN_INFO "Filter 1 triggered %d at %ld\n", trg, jiffies);
2700 }
2701 j->ex.bits.f1 = 1;
2702 ixj_kill_fasync(j, SIG_F1, POLL_IN);
2703 break;
2704 case 2:
2705 if(ixjdebug & 0x0020) {
2706 printk(KERN_INFO "Filter 2 triggered %d at %ld\n", trg, jiffies);
2707 }
2708 j->ex.bits.f2 = 1;
2709 ixj_kill_fasync(j, SIG_F2, POLL_IN);
2710 break;
2711 case 3:
2712 if(ixjdebug & 0x0020) {
2713 printk(KERN_INFO "Filter 3 triggered %d at %ld\n", trg, jiffies);
2714 }
2715 j->ex.bits.f3 = 1;
2716 ixj_kill_fasync(j, SIG_F3, POLL_IN);
2717 break;
2718 }
2719 }
2720 }
2721 return 0;
2722}
2723
2724static int LineMonitor(IXJ *j)
2725{
2726 if (j->dtmf_proc) {
2727 return -1;
2728 }
2729 j->dtmf_proc = 1;
2730
2731 if (ixj_WriteDSPCommand(0x7000, j))
2732 return -1;
2733
2734 j->dtmf.bytes.high = j->ssr.high;
2735 j->dtmf.bytes.low = j->ssr.low;
2736 if (!j->dtmf_state && j->dtmf.bits.dtmf_valid) {
2737 j->dtmf_state = 1;
2738 j->dtmf_current = j->dtmf.bits.digit;
2739 }
2740 if (j->dtmf_state && !j->dtmf.bits.dtmf_valid)
2741 {
2742 if(!j->cidcw_wait) {
2743 j->dtmfbuffer[j->dtmf_wp] = j->dtmf_current;
2744 j->dtmf_wp++;
2745 if (j->dtmf_wp == 79)
2746 j->dtmf_wp = 0;
2747 j->ex.bits.dtmf_ready = 1;
2748 if(j->ex_sig.bits.dtmf_ready) {
2749 ixj_kill_fasync(j, SIG_DTMF_READY, POLL_IN);
2750 }
2751 }
2752 else if(j->dtmf_current == 0x00 || j->dtmf_current == 0x0D) {
2753 if(ixjdebug & 0x0020) {
2754 printk("IXJ phone%d saw CIDCW Ack DTMF %d from display at %ld\n", j->board, j->dtmf_current, jiffies);
2755 }
2756 j->flags.cidcw_ack = 1;
2757 }
2758 j->dtmf_state = 0;
2759 }
2760 j->dtmf_proc = 0;
2761
2762 return 0;
2763}
2764
2765
2766
2767
2768
2769
2770
2771static void ulaw2alaw(unsigned char *buff, unsigned long len)
2772{
2773 static unsigned char table_ulaw2alaw[] =
2774 {
2775 0x2A, 0x2B, 0x28, 0x29, 0x2E, 0x2F, 0x2C, 0x2D,
2776 0x22, 0x23, 0x20, 0x21, 0x26, 0x27, 0x24, 0x25,
2777 0x3A, 0x3B, 0x38, 0x39, 0x3E, 0x3F, 0x3C, 0x3D,
2778 0x32, 0x33, 0x30, 0x31, 0x36, 0x37, 0x34, 0x35,
2779 0x0B, 0x08, 0x09, 0x0E, 0x0F, 0x0C, 0x0D, 0x02,
2780 0x03, 0x00, 0x01, 0x06, 0x07, 0x04, 0x05, 0x1A,
2781 0x1B, 0x18, 0x19, 0x1E, 0x1F, 0x1C, 0x1D, 0x12,
2782 0x13, 0x10, 0x11, 0x16, 0x17, 0x14, 0x15, 0x6B,
2783 0x68, 0x69, 0x6E, 0x6F, 0x6C, 0x6D, 0x62, 0x63,
2784 0x60, 0x61, 0x66, 0x67, 0x64, 0x65, 0x7B, 0x79,
2785 0x7E, 0x7F, 0x7C, 0x7D, 0x72, 0x73, 0x70, 0x71,
2786 0x76, 0x77, 0x74, 0x75, 0x4B, 0x49, 0x4F, 0x4D,
2787 0x42, 0x43, 0x40, 0x41, 0x46, 0x47, 0x44, 0x45,
2788 0x5A, 0x5B, 0x58, 0x59, 0x5E, 0x5F, 0x5C, 0x5D,
2789 0x52, 0x52, 0x53, 0x53, 0x50, 0x50, 0x51, 0x51,
2790 0x56, 0x56, 0x57, 0x57, 0x54, 0x54, 0x55, 0xD5,
2791 0xAA, 0xAB, 0xA8, 0xA9, 0xAE, 0xAF, 0xAC, 0xAD,
2792 0xA2, 0xA3, 0xA0, 0xA1, 0xA6, 0xA7, 0xA4, 0xA5,
2793 0xBA, 0xBB, 0xB8, 0xB9, 0xBE, 0xBF, 0xBC, 0xBD,
2794 0xB2, 0xB3, 0xB0, 0xB1, 0xB6, 0xB7, 0xB4, 0xB5,
2795 0x8B, 0x88, 0x89, 0x8E, 0x8F, 0x8C, 0x8D, 0x82,
2796 0x83, 0x80, 0x81, 0x86, 0x87, 0x84, 0x85, 0x9A,
2797 0x9B, 0x98, 0x99, 0x9E, 0x9F, 0x9C, 0x9D, 0x92,
2798 0x93, 0x90, 0x91, 0x96, 0x97, 0x94, 0x95, 0xEB,
2799 0xE8, 0xE9, 0xEE, 0xEF, 0xEC, 0xED, 0xE2, 0xE3,
2800 0xE0, 0xE1, 0xE6, 0xE7, 0xE4, 0xE5, 0xFB, 0xF9,
2801 0xFE, 0xFF, 0xFC, 0xFD, 0xF2, 0xF3, 0xF0, 0xF1,
2802 0xF6, 0xF7, 0xF4, 0xF5, 0xCB, 0xC9, 0xCF, 0xCD,
2803 0xC2, 0xC3, 0xC0, 0xC1, 0xC6, 0xC7, 0xC4, 0xC5,
2804 0xDA, 0xDB, 0xD8, 0xD9, 0xDE, 0xDF, 0xDC, 0xDD,
2805 0xD2, 0xD2, 0xD3, 0xD3, 0xD0, 0xD0, 0xD1, 0xD1,
2806 0xD6, 0xD6, 0xD7, 0xD7, 0xD4, 0xD4, 0xD5, 0xD5
2807 };
2808
2809 while (len--)
2810 {
2811 *buff = table_ulaw2alaw[*(unsigned char *)buff];
2812 buff++;
2813 }
2814}
2815
2816static void alaw2ulaw(unsigned char *buff, unsigned long len)
2817{
2818 static unsigned char table_alaw2ulaw[] =
2819 {
2820 0x29, 0x2A, 0x27, 0x28, 0x2D, 0x2E, 0x2B, 0x2C,
2821 0x21, 0x22, 0x1F, 0x20, 0x25, 0x26, 0x23, 0x24,
2822 0x39, 0x3A, 0x37, 0x38, 0x3D, 0x3E, 0x3B, 0x3C,
2823 0x31, 0x32, 0x2F, 0x30, 0x35, 0x36, 0x33, 0x34,
2824 0x0A, 0x0B, 0x08, 0x09, 0x0E, 0x0F, 0x0C, 0x0D,
2825 0x02, 0x03, 0x00, 0x01, 0x06, 0x07, 0x04, 0x05,
2826 0x1A, 0x1B, 0x18, 0x19, 0x1E, 0x1F, 0x1C, 0x1D,
2827 0x12, 0x13, 0x10, 0x11, 0x16, 0x17, 0x14, 0x15,
2828 0x62, 0x63, 0x60, 0x61, 0x66, 0x67, 0x64, 0x65,
2829 0x5D, 0x5D, 0x5C, 0x5C, 0x5F, 0x5F, 0x5E, 0x5E,
2830 0x74, 0x76, 0x70, 0x72, 0x7C, 0x7E, 0x78, 0x7A,
2831 0x6A, 0x6B, 0x68, 0x69, 0x6E, 0x6F, 0x6C, 0x6D,
2832 0x48, 0x49, 0x46, 0x47, 0x4C, 0x4D, 0x4A, 0x4B,
2833 0x40, 0x41, 0x3F, 0x3F, 0x44, 0x45, 0x42, 0x43,
2834 0x56, 0x57, 0x54, 0x55, 0x5A, 0x5B, 0x58, 0x59,
2835 0x4F, 0x4F, 0x4E, 0x4E, 0x52, 0x53, 0x50, 0x51,
2836 0xA9, 0xAA, 0xA7, 0xA8, 0xAD, 0xAE, 0xAB, 0xAC,
2837 0xA1, 0xA2, 0x9F, 0xA0, 0xA5, 0xA6, 0xA3, 0xA4,
2838 0xB9, 0xBA, 0xB7, 0xB8, 0xBD, 0xBE, 0xBB, 0xBC,
2839 0xB1, 0xB2, 0xAF, 0xB0, 0xB5, 0xB6, 0xB3, 0xB4,
2840 0x8A, 0x8B, 0x88, 0x89, 0x8E, 0x8F, 0x8C, 0x8D,
2841 0x82, 0x83, 0x80, 0x81, 0x86, 0x87, 0x84, 0x85,
2842 0x9A, 0x9B, 0x98, 0x99, 0x9E, 0x9F, 0x9C, 0x9D,
2843 0x92, 0x93, 0x90, 0x91, 0x96, 0x97, 0x94, 0x95,
2844 0xE2, 0xE3, 0xE0, 0xE1, 0xE6, 0xE7, 0xE4, 0xE5,
2845 0xDD, 0xDD, 0xDC, 0xDC, 0xDF, 0xDF, 0xDE, 0xDE,
2846 0xF4, 0xF6, 0xF0, 0xF2, 0xFC, 0xFE, 0xF8, 0xFA,
2847 0xEA, 0xEB, 0xE8, 0xE9, 0xEE, 0xEF, 0xEC, 0xED,
2848 0xC8, 0xC9, 0xC6, 0xC7, 0xCC, 0xCD, 0xCA, 0xCB,
2849 0xC0, 0xC1, 0xBF, 0xBF, 0xC4, 0xC5, 0xC2, 0xC3,
2850 0xD6, 0xD7, 0xD4, 0xD5, 0xDA, 0xDB, 0xD8, 0xD9,
2851 0xCF, 0xCF, 0xCE, 0xCE, 0xD2, 0xD3, 0xD0, 0xD1
2852 };
2853
2854 while (len--)
2855 {
2856 *buff = table_alaw2ulaw[*(unsigned char *)buff];
2857 buff++;
2858 }
2859}
2860
2861static ssize_t ixj_read(struct file * file_p, char *buf, size_t length, loff_t * ppos)
2862{
2863 unsigned long i = *ppos;
2864 IXJ * j = get_ixj(NUM(file_p->f_dentry->d_inode->i_rdev));
2865
2866 DECLARE_WAITQUEUE(wait, current);
2867
2868 if (j->flags.inread)
2869 return -EALREADY;
2870
2871 j->flags.inread = 1;
2872
2873 add_wait_queue(&j->read_q, &wait);
2874 set_current_state(TASK_INTERRUPTIBLE);
2875 mb();
2876
2877 while (!j->read_buffer_ready || (j->dtmf_state && j->flags.dtmf_oob)) {
2878 ++j->read_wait;
2879 if (file_p->f_flags & O_NONBLOCK) {
2880 set_current_state(TASK_RUNNING);
2881 remove_wait_queue(&j->read_q, &wait);
2882 j->flags.inread = 0;
2883 return -EAGAIN;
2884 }
2885 if (!ixj_hookstate(j)) {
2886 set_current_state(TASK_RUNNING);
2887 remove_wait_queue(&j->read_q, &wait);
2888 j->flags.inread = 0;
2889 return 0;
2890 }
2891 interruptible_sleep_on(&j->read_q);
2892 if (signal_pending(current)) {
2893 set_current_state(TASK_RUNNING);
2894 remove_wait_queue(&j->read_q, &wait);
2895 j->flags.inread = 0;
2896 return -EINTR;
2897 }
2898 }
2899
2900 remove_wait_queue(&j->read_q, &wait);
2901 set_current_state(TASK_RUNNING);
2902
2903 if(j->rec_codec == ALAW)
2904 ulaw2alaw(j->read_buffer, min(length, j->read_buffer_size));
2905 i = copy_to_user(buf, j->read_buffer, min(length, j->read_buffer_size));
2906 j->read_buffer_ready = 0;
2907 if (i) {
2908 j->flags.inread = 0;
2909 return -EFAULT;
2910 } else {
2911 j->flags.inread = 0;
2912 return min(length, j->read_buffer_size);
2913 }
2914}
2915
2916static ssize_t ixj_enhanced_read(struct file * file_p, char *buf, size_t length,
2917 loff_t * ppos)
2918{
2919 int pre_retval;
2920 ssize_t read_retval = 0;
2921 IXJ *j = get_ixj(NUM(file_p->f_dentry->d_inode->i_rdev));
2922
2923 pre_retval = ixj_PreRead(j, 0L);
2924 switch (pre_retval) {
2925 case NORMAL:
2926 read_retval = ixj_read(file_p, buf, length, ppos);
2927 ixj_PostRead(j, 0L);
2928 break;
2929 case NOPOST:
2930 read_retval = ixj_read(file_p, buf, length, ppos);
2931 break;
2932 case POSTONLY:
2933 ixj_PostRead(j, 0L);
2934 break;
2935 default:
2936 read_retval = pre_retval;
2937 }
2938 return read_retval;
2939}
2940
2941static ssize_t ixj_write(struct file *file_p, const char *buf, size_t count, loff_t * ppos)
2942{
2943 unsigned long i = *ppos;
2944 IXJ *j = file_p->private_data;
2945
2946 DECLARE_WAITQUEUE(wait, current);
2947
2948 if (j->flags.inwrite)
2949 return -EALREADY;
2950
2951 j->flags.inwrite = 1;
2952
2953 add_wait_queue(&j->write_q, &wait);
2954 set_current_state(TASK_INTERRUPTIBLE);
2955 mb();
2956
2957
2958 while (!j->write_buffers_empty) {
2959 ++j->write_wait;
2960 if (file_p->f_flags & O_NONBLOCK) {
2961 set_current_state(TASK_RUNNING);
2962 remove_wait_queue(&j->write_q, &wait);
2963 j->flags.inwrite = 0;
2964 return -EAGAIN;
2965 }
2966 if (!ixj_hookstate(j)) {
2967 set_current_state(TASK_RUNNING);
2968 remove_wait_queue(&j->write_q, &wait);
2969 j->flags.inwrite = 0;
2970 return 0;
2971 }
2972 interruptible_sleep_on(&j->write_q);
2973 if (signal_pending(current)) {
2974 set_current_state(TASK_RUNNING);
2975 remove_wait_queue(&j->write_q, &wait);
2976 j->flags.inwrite = 0;
2977 return -EINTR;
2978 }
2979 }
2980 set_current_state(TASK_RUNNING);
2981 remove_wait_queue(&j->write_q, &wait);
2982 if (j->write_buffer_wp + count >= j->write_buffer_end)
2983 j->write_buffer_wp = j->write_buffer;
2984 i = copy_from_user(j->write_buffer_wp, buf, min(count, j->write_buffer_size));
2985 if (i) {
2986 j->flags.inwrite = 0;
2987 return -EFAULT;
2988 }
2989 if(j->play_codec == ALAW)
2990 alaw2ulaw(j->write_buffer_wp, min(count, j->write_buffer_size));
2991 j->flags.inwrite = 0;
2992 return min(count, j->write_buffer_size);
2993}
2994
2995static ssize_t ixj_enhanced_write(struct file * file_p, const char *buf, size_t count, loff_t * ppos)
2996{
2997 int pre_retval;
2998 ssize_t write_retval = 0;
2999
3000 IXJ *j = get_ixj(NUM(file_p->f_dentry->d_inode->i_rdev));
3001
3002 pre_retval = ixj_PreWrite(j, 0L);
3003 switch (pre_retval) {
3004 case NORMAL:
3005 write_retval = ixj_write(file_p, buf, count, ppos);
3006 if (write_retval > 0) {
3007 ixj_PostWrite(j, 0L);
3008 j->write_buffer_wp += write_retval;
3009 j->write_buffers_empty--;
3010 }
3011 break;
3012 case NOPOST:
3013 write_retval = ixj_write(file_p, buf, count, ppos);
3014 if (write_retval > 0) {
3015 j->write_buffer_wp += write_retval;
3016 j->write_buffers_empty--;
3017 }
3018 break;
3019 case POSTONLY:
3020 ixj_PostWrite(j, 0L);
3021 break;
3022 default:
3023 write_retval = pre_retval;
3024 }
3025 return write_retval;
3026}
3027
3028static void ixj_read_frame(IXJ *j)
3029{
3030 int cnt, dly;
3031
3032 if (j->read_buffer) {
3033 for (cnt = 0; cnt < j->rec_frame_size * 2; cnt += 2) {
3034 if (!(cnt % 16) && !IsRxReady(j)) {
3035 dly = 0;
3036 while (!IsRxReady(j)) {
3037 if (dly++ > 5) {
3038 dly = 0;
3039 break;
3040 }
3041 udelay(10);
3042 }
3043 }
3044
3045 if (j->rec_codec == G729 && (cnt == 0 || cnt == 10 || cnt == 20)) {
3046 inb_p(j->DSPbase + 0x0E);
3047 inb_p(j->DSPbase + 0x0F);
3048 }
3049 *(j->read_buffer + cnt) = inb_p(j->DSPbase + 0x0E);
3050 *(j->read_buffer + cnt + 1) = inb_p(j->DSPbase + 0x0F);
3051 }
3052 ++j->framesread;
3053 if (j->intercom != -1) {
3054 if (IsTxReady(get_ixj(j->intercom))) {
3055 for (cnt = 0; cnt < j->rec_frame_size * 2; cnt += 2) {
3056 if (!(cnt % 16) && !IsTxReady(j)) {
3057 dly = 0;
3058 while (!IsTxReady(j)) {
3059 if (dly++ > 5) {
3060 dly = 0;
3061 break;
3062 }
3063 udelay(10);
3064 }
3065 }
3066 outb_p(*(j->read_buffer + cnt), get_ixj(j->intercom)->DSPbase + 0x0C);
3067 outb_p(*(j->read_buffer + cnt + 1), get_ixj(j->intercom)->DSPbase + 0x0D);
3068 }
3069 get_ixj(j->intercom)->frameswritten++;
3070 }
3071 } else {
3072 j->read_buffer_ready = 1;
3073 wake_up_interruptible(&j->read_q);
3074
3075 wake_up_interruptible(&j->poll_q);
3076
3077 if(j->ixj_signals[SIG_READ_READY])
3078 ixj_kill_fasync(j, SIG_READ_READY, POLL_OUT);
3079 }
3080 }
3081}
3082
3083static short fsk[][6][20] =
3084{
3085 {
3086 {
3087 0, 17846, 29934, 32364, 24351, 8481, -10126, -25465, -32587, -29196,
3088 -16384, 1715, 19260, 30591, 32051, 23170, 6813, -11743, -26509, -32722
3089 },
3090 {
3091 -28377, -14876, 3425, 20621, 31163, 31650, 21925, 5126, -13328, -27481,
3092 -32767, -27481, -13328, 5126, 21925, 31650, 31163, 20621, 3425, -14876
3093 },
3094 {
3095 -28377, -32722, -26509, -11743, 6813, 23170, 32051, 30591, 19260, 1715,
3096 -16384, -29196, -32587, -25465, -10126, 8481, 24351, 32364, 29934, 17846
3097 },
3098 {
3099 0, -17846, -29934, -32364, -24351, -8481, 10126, 25465, 32587, 29196,
3100 16384, -1715, -19260, -30591, -32051, -23170, -6813, 11743, 26509, 32722
3101 },
3102 {
3103 28377, 14876, -3425, -20621, -31163, -31650, -21925, -5126, 13328, 27481,
3104 32767, 27481, 13328, -5126, -21925, -31650, -31163, -20621, -3425, 14876
3105 },
3106 {
3107 28377, 32722, 26509, 11743, -6813, -23170, -32051, -30591, -19260, -1715,
3108 16384, 29196, 32587, 25465, 10126, -8481, -24351, -32364, -29934, -17846
3109 }
3110 },
3111 {
3112 {
3113 0, 10126, 19260, 26509, 31163, 32767, 31163, 26509, 19260, 10126,
3114 0, -10126, -19260, -26509, -31163, -32767, -31163, -26509, -19260, -10126
3115 },
3116 {
3117 -28377, -21925, -13328, -3425, 6813, 16384, 24351, 29934, 32587, 32051,
3118 28377, 21925, 13328, 3425, -6813, -16384, -24351, -29934, -32587, -32051
3119 },
3120 {
3121 -28377, -32051, -32587, -29934, -24351, -16384, -6813, 3425, 13328, 21925,
3122 28377, 32051, 32587, 29934, 24351, 16384, 6813, -3425, -13328, -21925
3123 },
3124 {
3125 0, -10126, -19260, -26509, -31163, -32767, -31163, -26509, -19260, -10126,
3126 0, 10126, 19260, 26509, 31163, 32767, 31163, 26509, 19260, 10126
3127 },
3128 {
3129 28377, 21925, 13328, 3425, -6813, -16383, -24351, -29934, -32587, -32051,
3130 -28377, -21925, -13328, -3425, 6813, 16383, 24351, 29934, 32587, 32051
3131 },
3132 {
3133 28377, 32051, 32587, 29934, 24351, 16384, 6813, -3425, -13328, -21925,
3134 -28377, -32051, -32587, -29934, -24351, -16384, -6813, 3425, 13328, 21925
3135 }
3136 }
3137};
3138
3139
3140static void ixj_write_cid_bit(IXJ *j, int bit)
3141{
3142 while (j->fskcnt < 20) {
3143 if(j->fskdcnt < (j->fsksize - 1))
3144 j->fskdata[j->fskdcnt++] = fsk[bit][j->fskz][j->fskcnt];
3145
3146 j->fskcnt += 3;
3147 }
3148 j->fskcnt %= 20;
3149
3150 if (!bit)
3151 j->fskz++;
3152 if (j->fskz >= 6)
3153 j->fskz = 0;
3154
3155}
3156
3157static void ixj_write_cid_byte(IXJ *j, char byte)
3158{
3159 IXJ_CBYTE cb;
3160
3161 cb.cbyte = byte;
3162 ixj_write_cid_bit(j, 0);
3163 ixj_write_cid_bit(j, cb.cbits.b0 ? 1 : 0);
3164 ixj_write_cid_bit(j, cb.cbits.b1 ? 1 : 0);
3165 ixj_write_cid_bit(j, cb.cbits.b2 ? 1 : 0);
3166 ixj_write_cid_bit(j, cb.cbits.b3 ? 1 : 0);
3167 ixj_write_cid_bit(j, cb.cbits.b4 ? 1 : 0);
3168 ixj_write_cid_bit(j, cb.cbits.b5 ? 1 : 0);
3169 ixj_write_cid_bit(j, cb.cbits.b6 ? 1 : 0);
3170 ixj_write_cid_bit(j, cb.cbits.b7 ? 1 : 0);
3171 ixj_write_cid_bit(j, 1);
3172}
3173
3174static void ixj_write_cid_seize(IXJ *j)
3175{
3176 int cnt;
3177
3178 for (cnt = 0; cnt < 150; cnt++) {
3179 ixj_write_cid_bit(j, 0);
3180 ixj_write_cid_bit(j, 1);
3181 }
3182 for (cnt = 0; cnt < 180; cnt++) {
3183 ixj_write_cid_bit(j, 1);
3184 }
3185}
3186
3187static void ixj_write_cidcw_seize(IXJ *j)
3188{
3189 int cnt;
3190
3191 for (cnt = 0; cnt < 80; cnt++) {
3192 ixj_write_cid_bit(j, 1);
3193 }
3194}
3195
3196static int ixj_write_cid_string(IXJ *j, char *s, int checksum)
3197{
3198 int cnt;
3199
3200 for (cnt = 0; cnt < strlen(s); cnt++) {
3201 ixj_write_cid_byte(j, s[cnt]);
3202 checksum = (checksum + s[cnt]);
3203 }
3204 return checksum;
3205}
3206
3207static void ixj_pad_fsk(IXJ *j, int pad)
3208{
3209 int cnt;
3210
3211 for (cnt = 0; cnt < pad; cnt++) {
3212 if(j->fskdcnt < (j->fsksize - 1))
3213 j->fskdata[j->fskdcnt++] = 0x0000;
3214 }
3215 for (cnt = 0; cnt < 720; cnt++) {
3216 if(j->fskdcnt < (j->fsksize - 1))
3217 j->fskdata[j->fskdcnt++] = 0x0000;
3218 }
3219}
3220
3221static void ixj_pre_cid(IXJ *j)
3222{
3223 j->cid_play_codec = j->play_codec;
3224 j->cid_play_frame_size = j->play_frame_size;
3225 j->cid_play_volume = get_play_volume(j);
3226 j->cid_play_flag = j->flags.playing;
3227
3228 j->cid_rec_codec = j->rec_codec;
3229 j->cid_rec_volume = get_rec_volume(j);
3230 j->cid_rec_flag = j->flags.recording;
3231
3232 j->cid_play_aec_level = j->aec_level;
3233
3234 switch(j->baseframe.low) {
3235 case 0xA0:
3236 j->cid_base_frame_size = 20;
3237 break;
3238 case 0x50:
3239 j->cid_base_frame_size = 10;
3240 break;
3241 case 0xF0:
3242 j->cid_base_frame_size = 30;
3243 break;
3244 }
3245
3246 ixj_play_stop(j);
3247 ixj_cpt_stop(j);
3248
3249 j->flags.cidplay = 1;
3250
3251 set_base_frame(j, 30);
3252 set_play_codec(j, LINEAR16);
3253 set_play_volume(j, 0x1B);
3254 ixj_play_start(j);
3255}
3256
3257static void ixj_post_cid(IXJ *j)
3258{
3259 ixj_play_stop(j);
3260
3261 if(j->cidsize > 5000) {
3262 SLIC_SetState(PLD_SLIC_STATE_STANDBY, j);
3263 }
3264 j->flags.cidplay = 0;
3265 if(ixjdebug & 0x0200) {
3266 printk("IXJ phone%d Finished Playing CallerID data %ld\n", j->board, jiffies);
3267 }
3268
3269 ixj_fsk_free(j);
3270
3271 j->fskdcnt = 0;
3272 set_base_frame(j, j->cid_base_frame_size);
3273 set_play_codec(j, j->cid_play_codec);
3274 ixj_aec_start(j, j->cid_play_aec_level);
3275 set_play_volume(j, j->cid_play_volume);
3276
3277 set_rec_codec(j, j->cid_rec_codec);
3278 set_rec_volume(j, j->cid_rec_volume);
3279
3280 if(j->cid_rec_flag)
3281 ixj_record_start(j);
3282
3283 if(j->cid_play_flag)
3284 ixj_play_start(j);
3285
3286 if(j->cid_play_flag) {
3287 wake_up_interruptible(&j->write_q);
3288 }
3289}
3290
3291static void ixj_write_cid(IXJ *j)
3292{
3293 char sdmf1[50];
3294 char sdmf2[50];
3295 char sdmf3[80];
3296 char mdmflen, len1, len2, len3;
3297 int pad;
3298
3299 int checksum = 0;
3300
3301 if (j->dsp.low == 0x20 || j->flags.cidplay)
3302 return;
3303
3304 j->fskz = j->fskphase = j->fskcnt = j->fskdcnt = 0;
3305 j->cidsize = j->cidcnt = 0;
3306
3307 ixj_fsk_alloc(j);
3308
3309 strcpy(sdmf1, j->cid_send.month);
3310 strcat(sdmf1, j->cid_send.day);
3311 strcat(sdmf1, j->cid_send.hour);
3312 strcat(sdmf1, j->cid_send.min);
3313 strcpy(sdmf2, j->cid_send.number);
3314 strcpy(sdmf3, j->cid_send.name);
3315
3316 len1 = strlen(sdmf1);
3317 len2 = strlen(sdmf2);
3318 len3 = strlen(sdmf3);
3319 mdmflen = len1 + len2 + len3 + 6;
3320
3321 while(1){
3322 ixj_write_cid_seize(j);
3323
3324 ixj_write_cid_byte(j, 0x80);
3325 checksum = 0x80;
3326 ixj_write_cid_byte(j, mdmflen);
3327 checksum = checksum + mdmflen;
3328
3329 ixj_write_cid_byte(j, 0x01);
3330 checksum = checksum + 0x01;
3331 ixj_write_cid_byte(j, len1);
3332 checksum = checksum + len1;
3333 checksum = ixj_write_cid_string(j, sdmf1, checksum);
3334 if(ixj_hookstate(j) & 1)
3335 break;
3336
3337 ixj_write_cid_byte(j, 0x02);
3338 checksum = checksum + 0x02;
3339 ixj_write_cid_byte(j, len2);
3340 checksum = checksum + len2;
3341 checksum = ixj_write_cid_string(j, sdmf2, checksum);
3342 if(ixj_hookstate(j) & 1)
3343 break;
3344
3345 ixj_write_cid_byte(j, 0x07);
3346 checksum = checksum + 0x07;
3347 ixj_write_cid_byte(j, len3);
3348 checksum = checksum + len3;
3349 checksum = ixj_write_cid_string(j, sdmf3, checksum);
3350 if(ixj_hookstate(j) & 1)
3351 break;
3352
3353 checksum %= 256;
3354 checksum ^= 0xFF;
3355 checksum += 1;
3356
3357 ixj_write_cid_byte(j, (char) checksum);
3358
3359 pad = j->fskdcnt % 240;
3360 if (pad) {
3361 pad = 240 - pad;
3362 }
3363 ixj_pad_fsk(j, pad);
3364 break;
3365 }
3366
3367 ixj_write_frame(j);
3368}
3369
3370static void ixj_write_cidcw(IXJ *j)
3371{
3372 IXJ_TONE ti;
3373
3374 char sdmf1[50];
3375 char sdmf2[50];
3376 char sdmf3[80];
3377 char mdmflen, len1, len2, len3;
3378 int pad;
3379
3380 int checksum = 0;
3381
3382 if (j->dsp.low == 0x20 || j->flags.cidplay)
3383 return;
3384
3385 j->fskz = j->fskphase = j->fskcnt = j->fskdcnt = 0;
3386 j->cidsize = j->cidcnt = 0;
3387
3388 ixj_fsk_alloc(j);
3389
3390 j->flags.cidcw_ack = 0;
3391
3392 ti.tone_index = 23;
3393 ti.gain0 = 1;
3394 ti.freq0 = hz440;
3395 ti.gain1 = 0;
3396 ti.freq1 = 0;
3397 ixj_init_tone(j, &ti);
3398
3399 ixj_set_tone_on(1500, j);
3400 ixj_set_tone_off(32, j);
3401 if(ixjdebug & 0x0200) {
3402 printk("IXJ cidcw phone%d first tone start at %ld\n", j->board, jiffies);
3403 }
3404 ixj_play_tone(j, 23);
3405
3406 clear_bit(j->board, &j->busyflags);
3407 while(j->tone_state) {
3408 set_current_state(TASK_INTERRUPTIBLE);
3409 schedule_timeout(1);
3410 }
3411 while(test_and_set_bit(j->board, (void *)&j->busyflags) != 0) {
3412 set_current_state(TASK_INTERRUPTIBLE);
3413 schedule_timeout(1);
3414 }
3415 if(ixjdebug & 0x0200) {
3416 printk("IXJ cidcw phone%d first tone end at %ld\n", j->board, jiffies);
3417 }
3418
3419 ti.tone_index = 24;
3420 ti.gain0 = 1;
3421 ti.freq0 = hz2130;
3422 ti.gain1 = 0;
3423 ti.freq1 = hz2750;
3424 ixj_init_tone(j, &ti);
3425
3426 ixj_set_tone_off(10, j);
3427 ixj_set_tone_on(600, j);
3428 if(ixjdebug & 0x0200) {
3429 printk("IXJ cidcw phone%d second tone start at %ld\n", j->board, jiffies);
3430 }
3431 ixj_play_tone(j, 24);
3432
3433 clear_bit(j->board, &j->busyflags);
3434 while(j->tone_state) {
3435 set_current_state(TASK_INTERRUPTIBLE);
3436 schedule_timeout(1);
3437 }
3438 while(test_and_set_bit(j->board, (void *)&j->busyflags) != 0) {
3439 set_current_state(TASK_INTERRUPTIBLE);
3440 schedule_timeout(1);
3441 }
3442 if(ixjdebug & 0x0200) {
3443 printk("IXJ cidcw phone%d sent second tone at %ld\n", j->board, jiffies);
3444 }
3445
3446 j->cidcw_wait = jiffies + ((50 * hertz) / 100);
3447
3448 clear_bit(j->board, &j->busyflags);
3449 while(!j->flags.cidcw_ack && time_before(jiffies, j->cidcw_wait)) {
3450 set_current_state(TASK_INTERRUPTIBLE);
3451 schedule_timeout(1);
3452 }
3453 while(test_and_set_bit(j->board, (void *)&j->busyflags) != 0) {
3454 set_current_state(TASK_INTERRUPTIBLE);
3455 schedule_timeout(1);
3456 }
3457 j->cidcw_wait = 0;
3458 if(!j->flags.cidcw_ack) {
3459 if(ixjdebug & 0x0200) {
3460 printk("IXJ cidcw phone%d did not receive ACK from display %ld\n", j->board, jiffies);
3461 }
3462 ixj_post_cid(j);
3463 if(j->cid_play_flag) {
3464 wake_up_interruptible(&j->write_q);
3465 }
3466 return;
3467 } else {
3468 ixj_pre_cid(j);
3469 }
3470 j->flags.cidcw_ack = 0;
3471 strcpy(sdmf1, j->cid_send.month);
3472 strcat(sdmf1, j->cid_send.day);
3473 strcat(sdmf1, j->cid_send.hour);
3474 strcat(sdmf1, j->cid_send.min);
3475 strcpy(sdmf2, j->cid_send.number);
3476 strcpy(sdmf3, j->cid_send.name);
3477
3478 len1 = strlen(sdmf1);
3479 len2 = strlen(sdmf2);
3480 len3 = strlen(sdmf3);
3481 mdmflen = len1 + len2 + len3 + 6;
3482
3483 ixj_write_cidcw_seize(j);
3484
3485 ixj_write_cid_byte(j, 0x80);
3486 checksum = 0x80;
3487 ixj_write_cid_byte(j, mdmflen);
3488 checksum = checksum + mdmflen;
3489
3490 ixj_write_cid_byte(j, 0x01);
3491 checksum = checksum + 0x01;
3492 ixj_write_cid_byte(j, len1);
3493 checksum = checksum + len1;
3494 checksum = ixj_write_cid_string(j, sdmf1, checksum);
3495
3496 ixj_write_cid_byte(j, 0x02);
3497 checksum = checksum + 0x02;
3498 ixj_write_cid_byte(j, len2);
3499 checksum = checksum + len2;
3500 checksum = ixj_write_cid_string(j, sdmf2, checksum);
3501
3502 ixj_write_cid_byte(j, 0x07);
3503 checksum = checksum + 0x07;
3504 ixj_write_cid_byte(j, len3);
3505 checksum = checksum + len3;
3506 checksum = ixj_write_cid_string(j, sdmf3, checksum);
3507
3508 checksum %= 256;
3509 checksum ^= 0xFF;
3510 checksum += 1;
3511
3512 ixj_write_cid_byte(j, (char) checksum);
3513
3514 pad = j->fskdcnt % 240;
3515 if (pad) {
3516 pad = 240 - pad;
3517 }
3518 ixj_pad_fsk(j, pad);
3519 if(ixjdebug & 0x0200) {
3520 printk("IXJ cidcw phone%d sent FSK data at %ld\n", j->board, jiffies);
3521 }
3522}
3523
3524static void ixj_write_vmwi(IXJ *j, int msg)
3525{
3526 char mdmflen;
3527 int pad;
3528
3529 int checksum = 0;
3530
3531 if (j->dsp.low == 0x20 || j->flags.cidplay)
3532 return;
3533
3534 j->fskz = j->fskphase = j->fskcnt = j->fskdcnt = 0;
3535 j->cidsize = j->cidcnt = 0;
3536
3537 ixj_fsk_alloc(j);
3538
3539 mdmflen = 3;
3540
3541 if (j->port == PORT_POTS)
3542 SLIC_SetState(PLD_SLIC_STATE_OHT, j);
3543
3544 ixj_write_cid_seize(j);
3545
3546 ixj_write_cid_byte(j, 0x82);
3547 checksum = 0x82;
3548 ixj_write_cid_byte(j, mdmflen);
3549 checksum = checksum + mdmflen;
3550
3551 ixj_write_cid_byte(j, 0x0B);
3552 checksum = checksum + 0x0B;
3553 ixj_write_cid_byte(j, 1);
3554 checksum = checksum + 1;
3555
3556 if(msg) {
3557 ixj_write_cid_byte(j, 0xFF);
3558 checksum = checksum + 0xFF;
3559 }
3560 else {
3561 ixj_write_cid_byte(j, 0x00);
3562 checksum = checksum + 0x00;
3563 }
3564
3565 checksum %= 256;
3566 checksum ^= 0xFF;
3567 checksum += 1;
3568
3569 ixj_write_cid_byte(j, (char) checksum);
3570
3571 pad = j->fskdcnt % 240;
3572 if (pad) {
3573 pad = 240 - pad;
3574 }
3575 ixj_pad_fsk(j, pad);
3576}
3577
3578static void ixj_write_frame(IXJ *j)
3579{
3580 int cnt, frame_count, dly;
3581 IXJ_WORD dat;
3582 BYTES blankword;
3583
3584 frame_count = 0;
3585 if(j->flags.cidplay) {
3586 for(cnt = 0; cnt < 480; cnt++) {
3587 if (!(cnt % 16) && !IsTxReady(j)) {
3588 dly = 0;
3589 while (!IsTxReady(j)) {
3590 if (dly++ > 5) {
3591 dly = 0;
3592 break;
3593 }
3594 udelay(10);
3595 }
3596 }
3597 dat.word = j->fskdata[j->cidcnt++];
3598 outb_p(dat.bytes.low, j->DSPbase + 0x0C);
3599 outb_p(dat.bytes.high, j->DSPbase + 0x0D);
3600 cnt++;
3601 }
3602 if(j->cidcnt >= j->fskdcnt) {
3603 ixj_post_cid(j);
3604 }
3605
3606
3607
3608 if (j->write_buffer_rp > j->write_buffer_wp) {
3609 j->write_buffer_rp += j->cid_play_frame_size * 2;
3610 if (j->write_buffer_rp >= j->write_buffer_end) {
3611 j->write_buffer_rp = j->write_buffer;
3612 }
3613 j->write_buffers_empty++;
3614 wake_up_interruptible(&j->write_q);
3615
3616 wake_up_interruptible(&j->poll_q);
3617 }
3618 } else if (j->write_buffer && j->write_buffers_empty < 1) {
3619 if (j->write_buffer_wp > j->write_buffer_rp) {
3620 frame_count =
3621 (j->write_buffer_wp - j->write_buffer_rp) / (j->play_frame_size * 2);
3622 }
3623 if (j->write_buffer_rp > j->write_buffer_wp) {
3624 frame_count =
3625 (j->write_buffer_wp - j->write_buffer) / (j->play_frame_size * 2) +
3626 (j->write_buffer_end - j->write_buffer_rp) / (j->play_frame_size * 2);
3627 }
3628 if (frame_count >= 1) {
3629 if (j->ver.low == 0x12 && j->play_mode && j->flags.play_first_frame) {
3630 switch (j->play_mode) {
3631 case PLAYBACK_MODE_ULAW:
3632 case PLAYBACK_MODE_ALAW:
3633 blankword.low = blankword.high = 0xFF;
3634 break;
3635 case PLAYBACK_MODE_8LINEAR:
3636 case PLAYBACK_MODE_16LINEAR:
3637 blankword.low = blankword.high = 0x00;
3638 break;
3639 case PLAYBACK_MODE_8LINEAR_WSS:
3640 blankword.low = blankword.high = 0x80;
3641 break;
3642 }
3643 for (cnt = 0; cnt < 16; cnt++) {
3644 if (!(cnt % 16) && !IsTxReady(j)) {
3645 dly = 0;
3646 while (!IsTxReady(j)) {
3647 if (dly++ > 5) {
3648 dly = 0;
3649 break;
3650 }
3651 udelay(10);
3652 }
3653 }
3654 outb_p((blankword.low), j->DSPbase + 0x0C);
3655 outb_p((blankword.high), j->DSPbase + 0x0D);
3656 }
3657 j->flags.play_first_frame = 0;
3658 } else if (j->play_codec == G723_63 && j->flags.play_first_frame) {
3659 for (cnt = 0; cnt < 24; cnt++) {
3660 if(cnt == 12) {
3661 blankword.low = 0x02;
3662 blankword.high = 0x00;
3663 }
3664 else {
3665 blankword.low = blankword.high = 0x00;
3666 }
3667 if (!(cnt % 16) && !IsTxReady(j)) {
3668 dly = 0;
3669 while (!IsTxReady(j)) {
3670 if (dly++ > 5) {
3671 dly = 0;
3672 break;
3673 }
3674 udelay(10);
3675 }
3676 }
3677 outb_p((blankword.low), j->DSPbase + 0x0C);
3678 outb_p((blankword.high), j->DSPbase + 0x0D);
3679 }
3680 j->flags.play_first_frame = 0;
3681 }
3682 for (cnt = 0; cnt < j->play_frame_size * 2; cnt += 2) {
3683 if (!(cnt % 16) && !IsTxReady(j)) {
3684 dly = 0;
3685 while (!IsTxReady(j)) {
3686 if (dly++ > 5) {
3687 dly = 0;
3688 break;
3689 }
3690 udelay(10);
3691 }
3692 }
3693
3694 if (j->play_codec == G729 && (cnt == 0 || cnt == 10 || cnt == 20)) {
3695 if(j->write_buffer_rp + cnt == 0 && j->write_buffer_rp + cnt + 1 == 0 && j->write_buffer_rp + cnt + 2 == 0 &&
3696 j->write_buffer_rp + cnt + 3 == 0 && j->write_buffer_rp + cnt + 4 == 0 && j->write_buffer_rp + cnt + 5 == 0 &&
3697 j->write_buffer_rp + cnt + 6 == 0 && j->write_buffer_rp + cnt + 7 == 0 && j->write_buffer_rp + cnt + 8 == 0 &&
3698 j->write_buffer_rp + cnt + 9 == 0) {
3699
3700 outb_p(0x00, j->DSPbase + 0x0C);
3701 outb_p(0x00, j->DSPbase + 0x0D);
3702 } else {
3703
3704 outb_p(0x01, j->DSPbase + 0x0C);
3705 outb_p(0x00, j->DSPbase + 0x0D);
3706 }
3707 }
3708 outb_p(*(j->write_buffer_rp + cnt), j->DSPbase + 0x0C);
3709 outb_p(*(j->write_buffer_rp + cnt + 1), j->DSPbase + 0x0D);
3710 *(j->write_buffer_rp + cnt) = 0;
3711 *(j->write_buffer_rp + cnt + 1) = 0;
3712 }
3713 j->write_buffer_rp += j->play_frame_size * 2;
3714 if (j->write_buffer_rp >= j->write_buffer_end) {
3715 j->write_buffer_rp = j->write_buffer;
3716 }
3717 j->write_buffers_empty++;
3718 wake_up_interruptible(&j->write_q);
3719
3720 wake_up_interruptible(&j->poll_q);
3721
3722 ++j->frameswritten;
3723 }
3724 } else {
3725 j->drybuffer++;
3726 }
3727 if(j->ixj_signals[SIG_WRITE_READY]) {
3728 ixj_kill_fasync(j, SIG_WRITE_READY, POLL_OUT);
3729 }
3730}
3731
3732static int idle(IXJ *j)
3733{
3734 if (ixj_WriteDSPCommand(0x0000, j))
3735
3736 return 0;
3737
3738 if (j->ssr.high || j->ssr.low) {
3739 return 0;
3740 } else {
3741 j->play_mode = -1;
3742 j->flags.playing = 0;
3743 j->rec_mode = -1;
3744 j->flags.recording = 0;
3745 return 1;
3746 }
3747}
3748
3749static int set_base_frame(IXJ *j, int size)
3750{
3751 unsigned short cmd;
3752 int cnt;
3753
3754 idle(j);
3755 j->cid_play_aec_level = j->aec_level;
3756 aec_stop(j);
3757 for (cnt = 0; cnt < 10; cnt++) {
3758 if (idle(j))
3759 break;
3760 }
3761 if (j->ssr.high || j->ssr.low)
3762 return -1;
3763 if (j->dsp.low != 0x20) {
3764 switch (size) {
3765 case 30:
3766 cmd = 0x07F0;
3767
3768 break;
3769 case 20:
3770 cmd = 0x07A0;
3771
3772 break;
3773 case 10:
3774 cmd = 0x0750;
3775
3776 break;
3777 default:
3778 return -1;
3779 }
3780 } else {
3781 if (size == 30)
3782 return size;
3783 else
3784 return -1;
3785 }
3786 if (ixj_WriteDSPCommand(cmd, j)) {
3787 j->baseframe.high = j->baseframe.low = 0xFF;
3788 return -1;
3789 } else {
3790 j->baseframe.high = j->ssr.high;
3791 j->baseframe.low = j->ssr.low;
3792
3793 if(j->baseframe.high == 0x00 && j->baseframe.low == 0x00) {
3794 return -1;
3795 }
3796 }
3797 ixj_aec_start(j, j->cid_play_aec_level);
3798 return size;
3799}
3800
3801static int set_rec_codec(IXJ *j, int rate)
3802{
3803 int retval = 0;
3804
3805 j->rec_codec = rate;
3806
3807 switch (rate) {
3808 case G723_63:
3809 if (j->ver.low != 0x12 || ixj_convert_loaded) {
3810 j->rec_frame_size = 12;
3811 j->rec_mode = 0;
3812 } else {
3813 retval = 1;
3814 }
3815 break;
3816 case G723_53:
3817 if (j->ver.low != 0x12 || ixj_convert_loaded) {
3818 j->rec_frame_size = 10;
3819 j->rec_mode = 0;
3820 } else {
3821 retval = 1;
3822 }
3823 break;
3824 case TS85:
3825 if (j->dsp.low == 0x20 || j->flags.ts85_loaded) {
3826 j->rec_frame_size = 16;
3827 j->rec_mode = 0;
3828 } else {
3829 retval = 1;
3830 }
3831 break;
3832 case TS48:
3833 if (j->ver.low != 0x12 || ixj_convert_loaded) {
3834 j->rec_frame_size = 9;
3835 j->rec_mode = 0;
3836 } else {
3837 retval = 1;
3838 }
3839 break;
3840 case TS41:
3841 if (j->ver.low != 0x12 || ixj_convert_loaded) {
3842 j->rec_frame_size = 8;
3843 j->rec_mode = 0;
3844 } else {
3845 retval = 1;
3846 }
3847 break;
3848 case G728:
3849 if (j->dsp.low != 0x20) {
3850 j->rec_frame_size = 48;
3851 j->rec_mode = 0;
3852 } else {
3853 retval = 1;
3854 }
3855 break;
3856 case G729:
3857 if (j->dsp.low != 0x20) {
3858 if (!j->flags.g729_loaded) {
3859 retval = 1;
3860 break;
3861 }
3862 switch (j->baseframe.low) {
3863 case 0xA0:
3864 j->rec_frame_size = 10;
3865 break;
3866 case 0x50:
3867 j->rec_frame_size = 5;
3868 break;
3869 default:
3870 j->rec_frame_size = 15;
3871 break;
3872 }
3873 j->rec_mode = 0;
3874 } else {
3875 retval = 1;
3876 }
3877 break;
3878 case G729B:
3879 if (j->dsp.low != 0x20) {
3880 if (!j->flags.g729_loaded) {
3881 retval = 1;
3882 break;
3883 }
3884 switch (j->baseframe.low) {
3885 case 0xA0:
3886 j->rec_frame_size = 12;
3887 break;
3888 case 0x50:
3889 j->rec_frame_size = 6;
3890 break;
3891 default:
3892 j->rec_frame_size = 18;
3893 break;
3894 }
3895 j->rec_mode = 0;
3896 } else {
3897 retval = 1;
3898 }
3899 break;
3900 case ULAW:
3901 switch (j->baseframe.low) {
3902 case 0xA0:
3903 j->rec_frame_size = 80;
3904 break;
3905 case 0x50:
3906 j->rec_frame_size = 40;
3907 break;
3908 default:
3909 j->rec_frame_size = 120;
3910 break;
3911 }
3912 j->rec_mode = 4;
3913 break;
3914 case ALAW:
3915 switch (j->baseframe.low) {
3916 case 0xA0:
3917 j->rec_frame_size = 80;
3918 break;
3919 case 0x50:
3920 j->rec_frame_size = 40;
3921 break;
3922 default:
3923 j->rec_frame_size = 120;
3924 break;
3925 }
3926 j->rec_mode = 4;
3927 break;
3928 case LINEAR16:
3929 switch (j->baseframe.low) {
3930 case 0xA0:
3931 j->rec_frame_size = 160;
3932 break;
3933 case 0x50:
3934 j->rec_frame_size = 80;
3935 break;
3936 default:
3937 j->rec_frame_size = 240;
3938 break;
3939 }
3940 j->rec_mode = 5;
3941 break;
3942 case LINEAR8:
3943 switch (j->baseframe.low) {
3944 case 0xA0:
3945 j->rec_frame_size = 80;
3946 break;
3947 case 0x50:
3948 j->rec_frame_size = 40;
3949 break;
3950 default:
3951 j->rec_frame_size = 120;
3952 break;
3953 }
3954 j->rec_mode = 6;
3955 break;
3956 case WSS:
3957 switch (j->baseframe.low) {
3958 case 0xA0:
3959 j->rec_frame_size = 80;
3960 break;
3961 case 0x50:
3962 j->rec_frame_size = 40;
3963 break;
3964 default:
3965 j->rec_frame_size = 120;
3966 break;
3967 }
3968 j->rec_mode = 7;
3969 break;
3970 default:
3971 j->rec_frame_size = 0;
3972 j->rec_mode = -1;
3973 if (j->read_buffer) {
3974 kfree(j->read_buffer);
3975 j->read_buffer = NULL;
3976 j->read_buffer_size = 0;
3977 }
3978 retval = 1;
3979 break;
3980 }
3981 return retval;
3982}
3983
3984static int ixj_record_start(IXJ *j)
3985{
3986 unsigned short cmd = 0x0000;
3987
3988 if (j->read_buffer) {
3989 ixj_record_stop(j);
3990 }
3991 j->flags.recording = 1;
3992 ixj_WriteDSPCommand(0x0FE0, j);
3993
3994 if(ixjdebug & 0x0002)
3995 printk("IXJ %d Starting Record Codec %d at %ld\n", j->board, j->rec_codec, jiffies);
3996
3997 if (!j->rec_mode) {
3998 switch (j->rec_codec) {
3999 case G723_63:
4000 cmd = 0x5131;
4001 break;
4002 case G723_53:
4003 cmd = 0x5132;
4004 break;
4005 case TS85:
4006 cmd = 0x5130;
4007
4008 break;
4009 case TS48:
4010 cmd = 0x5133;
4011
4012 break;
4013 case TS41:
4014 cmd = 0x5134;
4015
4016 break;
4017 case G728:
4018 cmd = 0x5135;
4019 break;
4020 case G729:
4021 case G729B:
4022 cmd = 0x5136;
4023 break;
4024 default:
4025 return 1;
4026 }
4027 if (ixj_WriteDSPCommand(cmd, j))
4028 return -1;
4029 }
4030 if (!j->read_buffer) {
4031 if (!j->read_buffer)
4032 j->read_buffer = kmalloc(j->rec_frame_size * 2, GFP_ATOMIC);
4033 if (!j->read_buffer) {
4034 printk("Read buffer allocation for ixj board %d failed!\n", j->board);
4035 return -ENOMEM;
4036 }
4037 }
4038 j->read_buffer_size = j->rec_frame_size * 2;
4039
4040 if (ixj_WriteDSPCommand(0x5102, j))
4041
4042 return -1;
4043
4044 switch (j->rec_mode) {
4045 case 0:
4046 cmd = 0x1C03;
4047
4048 break;
4049 case 4:
4050 if (j->ver.low == 0x12) {
4051 cmd = 0x1E03;
4052
4053 } else {
4054 cmd = 0x1E01;
4055
4056 }
4057 break;
4058 case 5:
4059 if (j->ver.low == 0x12) {
4060 cmd = 0x1E83;
4061
4062 } else {
4063 cmd = 0x1E81;
4064
4065 }
4066 break;
4067 case 6:
4068 if (j->ver.low == 0x12) {
4069 cmd = 0x1F03;
4070
4071 } else {
4072 cmd = 0x1F01;
4073
4074 }
4075 break;
4076 case 7:
4077 if (j->ver.low == 0x12) {
4078 cmd = 0x1F83;
4079 } else {
4080 cmd = 0x1F81;
4081 }
4082 break;
4083 }
4084 if (ixj_WriteDSPCommand(cmd, j))
4085 return -1;
4086
4087 if (j->flags.playing) {
4088 ixj_aec_start(j, j->aec_level);
4089 }
4090 return 0;
4091}
4092
4093static void ixj_record_stop(IXJ *j)
4094{
4095 if(ixjdebug & 0x0002)
4096 printk("IXJ %d Stopping Record Codec %d at %ld\n", j->board, j->rec_codec, jiffies);
4097
4098 if (j->read_buffer) {
4099 kfree(j->read_buffer);
4100 j->read_buffer = NULL;
4101 j->read_buffer_size = 0;
4102 }
4103 if (j->rec_mode > -1) {
4104 ixj_WriteDSPCommand(0x5120, j);
4105 j->rec_mode = -1;
4106 }
4107 j->flags.recording = 0;
4108}
4109static void ixj_vad(IXJ *j, int arg)
4110{
4111 if (arg)
4112 ixj_WriteDSPCommand(0x513F, j);
4113 else
4114 ixj_WriteDSPCommand(0x513E, j);
4115}
4116
4117static void set_rec_depth(IXJ *j, int depth)
4118{
4119 if (depth > 60)
4120 depth = 60;
4121 if (depth < 0)
4122 depth = 0;
4123 ixj_WriteDSPCommand(0x5180 + depth, j);
4124}
4125
4126static void set_dtmf_prescale(IXJ *j, int volume)
4127{
4128 ixj_WriteDSPCommand(0xCF07, j);
4129 ixj_WriteDSPCommand(volume, j);
4130}
4131
4132static int get_dtmf_prescale(IXJ *j)
4133{
4134 ixj_WriteDSPCommand(0xCF05, j);
4135 return j->ssr.high << 8 | j->ssr.low;
4136}
4137
4138static void set_rec_volume(IXJ *j, int volume)
4139{
4140 if(j->aec_level == AEC_AGC) {
4141 if (ixjdebug & 0x0002)
4142 printk(KERN_INFO "IXJ: /dev/phone%d Setting AGC Threshold to 0x%4.4x\n", j->board, volume);
4143 ixj_WriteDSPCommand(0xCF96, j);
4144 ixj_WriteDSPCommand(volume, j);
4145 } else {
4146 if (ixjdebug & 0x0002)
4147 printk(KERN_INFO "IXJ: /dev/phone %d Setting Record Volume to 0x%4.4x\n", j->board, volume);
4148 ixj_WriteDSPCommand(0xCF03, j);
4149 ixj_WriteDSPCommand(volume, j);
4150 }
4151}
4152
4153static int set_rec_volume_linear(IXJ *j, int volume)
4154{
4155 int newvolume, dsprecmax;
4156
4157 if (ixjdebug & 0x0002)
4158 printk(KERN_INFO "IXJ: /dev/phone %d Setting Linear Record Volume to 0x%4.4x\n", j->board, volume);
4159 if(volume > 100 || volume < 0) {
4160 return -1;
4161 }
4162
4163
4164 switch (j->cardtype) {
4165 case QTI_PHONEJACK:
4166 dsprecmax = 0x440;
4167 break;
4168 case QTI_LINEJACK:
4169 dsprecmax = 0x180;
4170 ixj_mixer(0x0203, j);
4171 ixj_mixer(0x0303, j);
4172 ixj_mixer(0x0C00, j);
4173 break;
4174 case QTI_PHONEJACK_LITE:
4175 dsprecmax = 0x4C0;
4176 break;
4177 case QTI_PHONEJACK_PCI:
4178 dsprecmax = 0x100;
4179 break;
4180 case QTI_PHONECARD:
4181 dsprecmax = 0x400;
4182 break;
4183 default:
4184 return -1;
4185 }
4186 newvolume = (dsprecmax * volume) / 100;
4187 set_rec_volume(j, newvolume);
4188 return 0;
4189}
4190
4191static int get_rec_volume(IXJ *j)
4192{
4193 if(j->aec_level == AEC_AGC) {
4194 if (ixjdebug & 0x0002)
4195 printk(KERN_INFO "Getting AGC Threshold\n");
4196 ixj_WriteDSPCommand(0xCF86, j);
4197 if (ixjdebug & 0x0002)
4198 printk(KERN_INFO "AGC Threshold is 0x%2.2x%2.2x\n", j->ssr.high, j->ssr.low);
4199 return j->ssr.high << 8 | j->ssr.low;
4200 } else {
4201 if (ixjdebug & 0x0002)
4202 printk(KERN_INFO "Getting Record Volume\n");
4203 ixj_WriteDSPCommand(0xCF01, j);
4204 return j->ssr.high << 8 | j->ssr.low;
4205 }
4206}
4207
4208static int get_rec_volume_linear(IXJ *j)
4209{
4210 int volume, newvolume, dsprecmax;
4211
4212 switch (j->cardtype) {
4213 case QTI_PHONEJACK:
4214 dsprecmax = 0x440;
4215 break;
4216 case QTI_LINEJACK:
4217 dsprecmax = 0x180;
4218 break;
4219 case QTI_PHONEJACK_LITE:
4220 dsprecmax = 0x4C0;
4221 break;
4222 case QTI_PHONEJACK_PCI:
4223 dsprecmax = 0x100;
4224 break;
4225 case QTI_PHONECARD:
4226 dsprecmax = 0x400;
4227 break;
4228 default:
4229 return -1;
4230 }
4231 volume = get_rec_volume(j);
4232 newvolume = (volume * 100) / dsprecmax;
4233 if(newvolume > 100)
4234 newvolume = 100;
4235 return newvolume;
4236}
4237
4238static int get_rec_level(IXJ *j)
4239{
4240 int retval;
4241
4242 ixj_WriteDSPCommand(0xCF88, j);
4243
4244 retval = j->ssr.high << 8 | j->ssr.low;
4245 retval = (retval * 256) / 240;
4246 return retval;
4247}
4248
4249static void ixj_aec_start(IXJ *j, int level)
4250{
4251 j->aec_level = level;
4252 if (ixjdebug & 0x0002)
4253 printk(KERN_INFO "AGC set = 0x%2.2x\n", j->aec_level);
4254 if (!level) {
4255 aec_stop(j);
4256 } else {
4257 if (j->rec_codec == G729 || j->play_codec == G729 || j->rec_codec == G729B || j->play_codec == G729B) {
4258 ixj_WriteDSPCommand(0xE022, j);
4259
4260 ixj_WriteDSPCommand(0x0300, j);
4261 }
4262 ixj_WriteDSPCommand(0xB001, j);
4263
4264 ixj_WriteDSPCommand(0xE013, j);
4265
4266 switch (level) {
4267 case AEC_LOW:
4268 ixj_WriteDSPCommand(0x0000, j);
4269
4270 ixj_WriteDSPCommand(0xE011, j);
4271 ixj_WriteDSPCommand(0xFFFF, j);
4272
4273 ixj_WriteDSPCommand(0xCF97, j);
4274 ixj_WriteDSPCommand(0x0000, j);
4275
4276 break;
4277
4278 case AEC_MED:
4279 ixj_WriteDSPCommand(0x0600, j);
4280
4281 ixj_WriteDSPCommand(0xE011, j);
4282 ixj_WriteDSPCommand(0x0080, j);
4283
4284 ixj_WriteDSPCommand(0xCF97, j);
4285 ixj_WriteDSPCommand(0x0000, j);
4286
4287 break;
4288
4289 case AEC_HIGH:
4290 ixj_WriteDSPCommand(0x0C00, j);
4291
4292 ixj_WriteDSPCommand(0xE011, j);
4293 ixj_WriteDSPCommand(0x0080, j);
4294
4295 ixj_WriteDSPCommand(0xCF97, j);
4296 ixj_WriteDSPCommand(0x0000, j);
4297
4298 break;
4299
4300 case AEC_AGC:
4301
4302 ixj_WriteDSPCommand(0x0002, j);
4303
4304 ixj_WriteDSPCommand(0xE011, j);
4305 ixj_WriteDSPCommand(0x0100, j);
4306
4307 ixj_WriteDSPCommand(0xE012, j);
4308
4309 if(j->cardtype == QTI_LINEJACK || j->cardtype == QTI_PHONECARD)
4310 ixj_WriteDSPCommand(0x0224, j);
4311 else
4312 ixj_WriteDSPCommand(0x1224, j);
4313
4314 ixj_WriteDSPCommand(0xE014, j);
4315 ixj_WriteDSPCommand(0x0003, j);
4316
4317 ixj_WriteDSPCommand(0xE338, j);
4318
4319
4320 ixj_WriteDSPCommand(0xCF90, j);
4321 ixj_WriteDSPCommand(0x0020, j);
4322
4323 ixj_WriteDSPCommand(0xCF91, j);
4324 ixj_WriteDSPCommand(0x1000, j);
4325
4326 ixj_WriteDSPCommand(0xCF92, j);
4327 ixj_WriteDSPCommand(0x0800, j);
4328
4329 ixj_WriteDSPCommand(0xCF93, j);
4330 ixj_WriteDSPCommand(0x1F40, j);
4331
4332 ixj_WriteDSPCommand(0xCF94, j);
4333 ixj_WriteDSPCommand(0x0005, j);
4334
4335 ixj_WriteDSPCommand(0xCF95, j);
4336 ixj_WriteDSPCommand(0x000D, j);
4337
4338 ixj_WriteDSPCommand(0xCF96, j);
4339 ixj_WriteDSPCommand(0x1200, j);
4340
4341 ixj_WriteDSPCommand(0xCF97, j);
4342 ixj_WriteDSPCommand(0x0001, j);
4343
4344 break;
4345
4346 case AEC_AUTO:
4347 ixj_WriteDSPCommand(0x0002, j);
4348
4349 ixj_WriteDSPCommand(0xE011, j);
4350 ixj_WriteDSPCommand(0x0100, j);
4351
4352 ixj_WriteDSPCommand(0xE012, j);
4353
4354 if(j->cardtype == QTI_LINEJACK || j->cardtype == QTI_PHONECARD)
4355 ixj_WriteDSPCommand(0x0224, j);
4356 else
4357 ixj_WriteDSPCommand(0x1224, j);
4358
4359 ixj_WriteDSPCommand(0xE014, j);
4360 ixj_WriteDSPCommand(0x0003, j);
4361
4362 ixj_WriteDSPCommand(0xE338, j);
4363
4364 break;
4365 }
4366 }
4367}
4368
4369static void aec_stop(IXJ *j)
4370{
4371 j->aec_level = AEC_OFF;
4372 if (j->rec_codec == G729 || j->play_codec == G729 || j->rec_codec == G729B || j->play_codec == G729B) {
4373 ixj_WriteDSPCommand(0xE022, j);
4374
4375 ixj_WriteDSPCommand(0x0700, j);
4376 }
4377 if (j->play_mode != -1 && j->rec_mode != -1)
4378 {
4379 ixj_WriteDSPCommand(0xB002, j);
4380 }
4381}
4382
4383static int set_play_codec(IXJ *j, int rate)
4384{
4385 int retval = 0;
4386
4387 j->play_codec = rate;
4388
4389 switch (rate) {
4390 case G723_63:
4391 if (j->ver.low != 0x12 || ixj_convert_loaded) {
4392 j->play_frame_size = 12;
4393 j->play_mode = 0;
4394 } else {
4395 retval = 1;
4396 }
4397 break;
4398 case G723_53:
4399 if (j->ver.low != 0x12 || ixj_convert_loaded) {
4400 j->play_frame_size = 10;
4401 j->play_mode = 0;
4402 } else {
4403 retval = 1;
4404 }
4405 break;
4406 case TS85:
4407 if (j->dsp.low == 0x20 || j->flags.ts85_loaded) {
4408 j->play_frame_size = 16;
4409 j->play_mode = 0;
4410 } else {
4411 retval = 1;
4412 }
4413 break;
4414 case TS48:
4415 if (j->ver.low != 0x12 || ixj_convert_loaded) {
4416 j->play_frame_size = 9;
4417 j->play_mode = 0;
4418 } else {
4419 retval = 1;
4420 }
4421 break;
4422 case TS41:
4423 if (j->ver.low != 0x12 || ixj_convert_loaded) {
4424 j->play_frame_size = 8;
4425 j->play_mode = 0;
4426 } else {
4427 retval = 1;
4428 }
4429 break;
4430 case G728:
4431 if (j->dsp.low != 0x20) {
4432 j->play_frame_size = 48;
4433 j->play_mode = 0;
4434 } else {
4435 retval = 1;
4436 }
4437 break;
4438 case G729:
4439 if (j->dsp.low != 0x20) {
4440 if (!j->flags.g729_loaded) {
4441 retval = 1;
4442 break;
4443 }
4444 switch (j->baseframe.low) {
4445 case 0xA0:
4446 j->play_frame_size = 10;
4447 break;
4448 case 0x50:
4449 j->play_frame_size = 5;
4450 break;
4451 default:
4452 j->play_frame_size = 15;
4453 break;
4454 }
4455 j->play_mode = 0;
4456 } else {
4457 retval = 1;
4458 }
4459 break;
4460 case G729B:
4461 if (j->dsp.low != 0x20) {
4462 if (!j->flags.g729_loaded) {
4463 retval = 1;
4464 break;
4465 }
4466 switch (j->baseframe.low) {
4467 case 0xA0:
4468 j->play_frame_size = 12;
4469 break;
4470 case 0x50:
4471 j->play_frame_size = 6;
4472 break;
4473 default:
4474 j->play_frame_size = 18;
4475 break;
4476 }
4477 j->play_mode = 0;
4478 } else {
4479 retval = 1;
4480 }
4481 break;
4482 case ULAW:
4483 switch (j->baseframe.low) {
4484 case 0xA0:
4485 j->play_frame_size = 80;
4486 break;
4487 case 0x50:
4488 j->play_frame_size = 40;
4489 break;
4490 default:
4491 j->play_frame_size = 120;
4492 break;
4493 }
4494 j->play_mode = 2;
4495 break;
4496 case ALAW:
4497 switch (j->baseframe.low) {
4498 case 0xA0:
4499 j->play_frame_size = 80;
4500 break;
4501 case 0x50:
4502 j->play_frame_size = 40;
4503 break;
4504 default:
4505 j->play_frame_size = 120;
4506 break;
4507 }
4508 j->play_mode = 2;
4509 break;
4510 case LINEAR16:
4511 switch (j->baseframe.low) {
4512 case 0xA0:
4513 j->play_frame_size = 160;
4514 break;
4515 case 0x50:
4516 j->play_frame_size = 80;
4517 break;
4518 default:
4519 j->play_frame_size = 240;
4520 break;
4521 }
4522 j->play_mode = 6;
4523 break;
4524 case LINEAR8:
4525 switch (j->baseframe.low) {
4526 case 0xA0:
4527 j->play_frame_size = 80;
4528 break;
4529 case 0x50:
4530 j->play_frame_size = 40;
4531 break;
4532 default:
4533 j->play_frame_size = 120;
4534 break;
4535 }
4536 j->play_mode = 4;
4537 break;
4538 case WSS:
4539 switch (j->baseframe.low) {
4540 case 0xA0:
4541 j->play_frame_size = 80;
4542 break;
4543 case 0x50:
4544 j->play_frame_size = 40;
4545 break;
4546 default:
4547 j->play_frame_size = 120;
4548 break;
4549 }
4550 j->play_mode = 5;
4551 break;
4552 default:
4553 j->play_frame_size = 0;
4554 j->play_mode = -1;
4555 if (j->write_buffer) {
4556 kfree(j->write_buffer);
4557 j->write_buffer = NULL;
4558 j->write_buffer_size = 0;
4559 }
4560 retval = 1;
4561 break;
4562 }
4563 return retval;
4564}
4565
4566static int ixj_play_start(IXJ *j)
4567{
4568 unsigned short cmd = 0x0000;
4569
4570 if (j->write_buffer) {
4571 ixj_play_stop(j);
4572 }
4573
4574 if(ixjdebug & 0x0002)
4575 printk("IXJ %d Starting Play Codec %d at %ld\n", j->board, j->play_codec, jiffies);
4576
4577 j->flags.playing = 1;
4578 ixj_WriteDSPCommand(0x0FE0, j);
4579
4580 j->flags.play_first_frame = 1;
4581 j->drybuffer = 0;
4582
4583 if (!j->play_mode) {
4584 switch (j->play_codec) {
4585 case G723_63:
4586 cmd = 0x5231;
4587 break;
4588 case G723_53:
4589 cmd = 0x5232;
4590 break;
4591 case TS85:
4592 cmd = 0x5230;
4593
4594 break;
4595 case TS48:
4596 cmd = 0x5233;
4597
4598 break;
4599 case TS41:
4600 cmd = 0x5234;
4601
4602 break;
4603 case G728:
4604 cmd = 0x5235;
4605 break;
4606 case G729:
4607 case G729B:
4608 cmd = 0x5236;
4609 break;
4610 default:
4611 return 1;
4612 }
4613 if (ixj_WriteDSPCommand(cmd, j))
4614 return -1;
4615 }
4616 j->write_buffer = kmalloc(j->play_frame_size * 2, GFP_ATOMIC);
4617 if (!j->write_buffer) {
4618 printk("Write buffer allocation for ixj board %d failed!\n", j->board);
4619 return -ENOMEM;
4620 }
4621
4622 j->write_buffers_empty = 1;
4623 j->write_buffer_size = j->play_frame_size * 2;
4624 j->write_buffer_end = j->write_buffer + j->play_frame_size * 2;
4625 j->write_buffer_rp = j->write_buffer_wp = j->write_buffer;
4626
4627 if (ixj_WriteDSPCommand(0x5202, j))
4628
4629 return -1;
4630
4631 switch (j->play_mode) {
4632 case 0:
4633 cmd = 0x2C03;
4634 break;
4635 case 2:
4636 if (j->ver.low == 0x12) {
4637 cmd = 0x2C23;
4638 } else {
4639 cmd = 0x2C21;
4640 }
4641 break;
4642 case 4:
4643 if (j->ver.low == 0x12) {
4644 cmd = 0x2C43;
4645 } else {
4646 cmd = 0x2C41;
4647 }
4648 break;
4649 case 5:
4650 if (j->ver.low == 0x12) {
4651 cmd = 0x2C53;
4652 } else {
4653 cmd = 0x2C51;
4654 }
4655 break;
4656 case 6:
4657 if (j->ver.low == 0x12) {
4658 cmd = 0x2C63;
4659 } else {
4660 cmd = 0x2C61;
4661 }
4662 break;
4663 }
4664 if (ixj_WriteDSPCommand(cmd, j))
4665 return -1;
4666
4667 if (ixj_WriteDSPCommand(0x2000, j))
4668 return -1;
4669
4670 if (ixj_WriteDSPCommand(0x2000 + j->play_frame_size, j))
4671 return -1;
4672
4673 if (j->flags.recording) {
4674 ixj_aec_start(j, j->aec_level);
4675 }
4676
4677 return 0;
4678}
4679
4680static void ixj_play_stop(IXJ *j)
4681{
4682 if(ixjdebug & 0x0002)
4683 printk("IXJ %d Stopping Play Codec %d at %ld\n", j->board, j->play_codec, jiffies);
4684
4685 if (j->write_buffer) {
4686 kfree(j->write_buffer);
4687 j->write_buffer = NULL;
4688 j->write_buffer_size = 0;
4689 }
4690 if (j->play_mode > -1) {
4691 ixj_WriteDSPCommand(0x5221, j);
4692
4693 j->play_mode = -1;
4694 }
4695 j->flags.playing = 0;
4696}
4697
4698static inline int get_play_level(IXJ *j)
4699{
4700 int retval;
4701
4702 ixj_WriteDSPCommand(0xCF8F, j);
4703 return j->ssr.high << 8 | j->ssr.low;
4704 retval = j->ssr.high << 8 | j->ssr.low;
4705 retval = (retval * 256) / 240;
4706 return retval;
4707}
4708
4709static unsigned int ixj_poll(struct file *file_p, poll_table * wait)
4710{
4711 unsigned int mask = 0;
4712
4713 IXJ *j = get_ixj(NUM(file_p->f_dentry->d_inode->i_rdev));
4714
4715 poll_wait(file_p, &(j->poll_q), wait);
4716 if (j->read_buffer_ready > 0)
4717 mask |= POLLIN | POLLRDNORM;
4718 if (j->write_buffers_empty > 0)
4719 mask |= POLLOUT | POLLWRNORM;
4720 if (j->ex.bytes)
4721 mask |= POLLPRI;
4722 return mask;
4723}
4724
4725static int ixj_play_tone(IXJ *j, char tone)
4726{
4727 if (!j->tone_state) {
4728 if(ixjdebug & 0x0002) {
4729 printk("IXJ %d starting tone %d at %ld\n", j->board, tone, jiffies);
4730 }
4731 if (j->dsp.low == 0x20) {
4732 idle(j);
4733 }
4734 j->tone_start_jif = jiffies;
4735
4736 j->tone_state = 1;
4737 }
4738
4739 j->tone_index = tone;
4740 if (ixj_WriteDSPCommand(0x6000 + j->tone_index, j))
4741 return -1;
4742
4743 return 0;
4744}
4745
4746static int ixj_set_tone_on(unsigned short arg, IXJ *j)
4747{
4748 j->tone_on_time = arg;
4749
4750 if (ixj_WriteDSPCommand(0x6E04, j))
4751
4752 return -1;
4753
4754 if (ixj_WriteDSPCommand(arg, j))
4755 return -1;
4756
4757 return 0;
4758}
4759
4760static int SCI_WaitHighSCI(IXJ *j)
4761{
4762 int cnt;
4763
4764 j->pld_scrr.byte = inb_p(j->XILINXbase);
4765 if (!j->pld_scrr.bits.sci) {
4766 for (cnt = 0; cnt < 10; cnt++) {
4767 udelay(32);
4768 j->pld_scrr.byte = inb_p(j->XILINXbase);
4769
4770 if ((j->pld_scrr.bits.sci))
4771 return 1;
4772 }
4773 if (ixjdebug & 0x0001)
4774 printk(KERN_INFO "SCI Wait High failed %x\n", j->pld_scrr.byte);
4775 return 0;
4776 } else
4777 return 1;
4778}
4779
4780static int SCI_WaitLowSCI(IXJ *j)
4781{
4782 int cnt;
4783
4784 j->pld_scrr.byte = inb_p(j->XILINXbase);
4785 if (j->pld_scrr.bits.sci) {
4786 for (cnt = 0; cnt < 10; cnt++) {
4787 udelay(32);
4788 j->pld_scrr.byte = inb_p(j->XILINXbase);
4789
4790 if (!(j->pld_scrr.bits.sci))
4791 return 1;
4792 }
4793 if (ixjdebug & 0x0001)
4794 printk(KERN_INFO "SCI Wait Low failed %x\n", j->pld_scrr.byte);
4795 return 0;
4796 } else
4797 return 1;
4798}
4799
4800static int SCI_Control(IXJ *j, int control)
4801{
4802 switch (control) {
4803 case SCI_End:
4804 j->pld_scrw.bits.c0 = 0;
4805
4806 j->pld_scrw.bits.c1 = 0;
4807
4808 break;
4809 case SCI_Enable_DAA:
4810 j->pld_scrw.bits.c0 = 1;
4811
4812 j->pld_scrw.bits.c1 = 0;
4813
4814 break;
4815 case SCI_Enable_Mixer:
4816 j->pld_scrw.bits.c0 = 0;
4817
4818 j->pld_scrw.bits.c1 = 1;
4819
4820 break;
4821 case SCI_Enable_EEPROM:
4822 j->pld_scrw.bits.c0 = 1;
4823
4824 j->pld_scrw.bits.c1 = 1;
4825
4826 break;
4827 default:
4828 return 0;
4829 break;
4830 }
4831 outb_p(j->pld_scrw.byte, j->XILINXbase);
4832
4833 switch (control) {
4834 case SCI_End:
4835 return 1;
4836 break;
4837 case SCI_Enable_DAA:
4838 case SCI_Enable_Mixer:
4839 case SCI_Enable_EEPROM:
4840 if (!SCI_WaitHighSCI(j))
4841 return 0;
4842 break;
4843 default:
4844 return 0;
4845 break;
4846 }
4847 return 1;
4848}
4849
4850static int SCI_Prepare(IXJ *j)
4851{
4852 if (!SCI_Control(j, SCI_End))
4853 return 0;
4854
4855 if (!SCI_WaitLowSCI(j))
4856 return 0;
4857
4858 return 1;
4859}
4860
4861static int ixj_get_mixer(long val, IXJ *j)
4862{
4863 int reg = (val & 0x1F00) >> 8;
4864 return j->mix.vol[reg];
4865}
4866
4867static int ixj_mixer(long val, IXJ *j)
4868{
4869 BYTES bytes;
4870
4871 bytes.high = (val & 0x1F00) >> 8;
4872 bytes.low = val & 0x00FF;
4873
4874
4875 j->mix.vol[bytes.high] = bytes.low;
4876
4877 outb_p(bytes.high & 0x1F, j->XILINXbase + 0x03);
4878
4879 outb_p(bytes.low, j->XILINXbase + 0x02);
4880
4881 SCI_Control(j, SCI_Enable_Mixer);
4882
4883 SCI_Control(j, SCI_End);
4884
4885 return 0;
4886}
4887
4888static int daa_load(BYTES * p_bytes, IXJ *j)
4889{
4890 outb_p(p_bytes->high, j->XILINXbase + 0x03);
4891 outb_p(p_bytes->low, j->XILINXbase + 0x02);
4892 if (!SCI_Control(j, SCI_Enable_DAA))
4893 return 0;
4894 else
4895 return 1;
4896}
4897
4898static int ixj_daa_cr4(IXJ *j, char reg)
4899{
4900 BYTES bytes;
4901
4902 switch (j->daa_mode) {
4903 case SOP_PU_SLEEP:
4904 bytes.high = 0x14;
4905 break;
4906 case SOP_PU_RINGING:
4907 bytes.high = 0x54;
4908 break;
4909 case SOP_PU_CONVERSATION:
4910 bytes.high = 0x94;
4911 break;
4912 case SOP_PU_PULSEDIALING:
4913 bytes.high = 0xD4;
4914 break;
4915 }
4916
4917 j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.reg = reg;
4918
4919 switch (j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.bitreg.AGX) {
4920 case 0:
4921 j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.bitreg.AGR_Z = 0;
4922 break;
4923 case 1:
4924 j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.bitreg.AGR_Z = 2;
4925 break;
4926 case 2:
4927 j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.bitreg.AGR_Z = 1;
4928 break;
4929 case 3:
4930 j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.bitreg.AGR_Z = 3;
4931 break;
4932 }
4933
4934 bytes.low = j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.reg;
4935
4936 if (!daa_load(&bytes, j))
4937 return 0;
4938
4939 if (!SCI_Prepare(j))
4940 return 0;
4941
4942 return 1;
4943}
4944
4945static char daa_int_read(IXJ *j)
4946{
4947 BYTES bytes;
4948
4949 if (!SCI_Prepare(j))
4950 return 0;
4951
4952 bytes.high = 0x38;
4953 bytes.low = 0x00;
4954 outb_p(bytes.high, j->XILINXbase + 0x03);
4955 outb_p(bytes.low, j->XILINXbase + 0x02);
4956
4957 if (!SCI_Control(j, SCI_Enable_DAA))
4958 return 0;
4959
4960 bytes.high = inb_p(j->XILINXbase + 0x03);
4961 bytes.low = inb_p(j->XILINXbase + 0x02);
4962 if (bytes.low != ALISDAA_ID_BYTE) {
4963 if (ixjdebug & 0x0001)
4964 printk("Cannot read DAA ID Byte high = %d low = %d\n", bytes.high, bytes.low);
4965 return 0;
4966 }
4967 if (!SCI_Control(j, SCI_Enable_DAA))
4968 return 0;
4969 if (!SCI_Control(j, SCI_End))
4970 return 0;
4971
4972 bytes.high = inb_p(j->XILINXbase + 0x03);
4973 bytes.low = inb_p(j->XILINXbase + 0x02);
4974
4975 j->m_DAAShadowRegs.XOP_REGS.XOP.xr0.reg = bytes.high;
4976
4977 return 1;
4978}
4979
4980static char daa_CR_read(IXJ *j, int cr)
4981{
4982 IXJ_WORD wdata;
4983 BYTES bytes;
4984
4985 if (!SCI_Prepare(j))
4986 return 0;
4987
4988 switch (j->daa_mode) {
4989 case SOP_PU_SLEEP:
4990 bytes.high = 0x30 + cr;
4991 break;
4992 case SOP_PU_RINGING:
4993 bytes.high = 0x70 + cr;
4994 break;
