LXR linux-old/include/asm-ppc64/user

   1#ifndef _USER_EXPORTS_H
   2#define _USER_EXPORTS_H
   3
   4/* 
   5 * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
   6 *   Copyright (C) 2002 Dave Engebretsen & Mike Corrigan
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License
  10 * as published by the Free Software Foundation; either version
  11 * 2 of the License, or (at your option) any later version.
  12 */
  13
  14typedef unsigned char u8;
  15typedef unsigned short u16;
  16typedef unsigned int u32;
  17#ifdef __powerpc64__
  18typedef unsigned long u64;
  19#else
  20typedef unsigned long long u64;
  21#endif
  22
  23struct user_exports {
  24        /*==================================================================
  25         * Cache line 1: 0x0000 - 0x007F
  26         * Kernel only data - undefined for user space
  27         *==================================================================
  28         */
  29        u64 undefined[16]; 
  30
  31        /*==================================================================
  32         * Cache line 2: 0x0080 - 0x00FF
  33         * Kernel / User data
  34         *==================================================================
  35         */
  36        u8  eye_catcher[6];      /* Eyecatcher: PPC64         0x00 */
  37        u16 version;             /* Version number            0x06 */
  38        u16 platform;            /* Platform type             0x08 */
  39        u16 processor;           /* Processor type            0x0A */
  40        u32 processorCount;      /* # of physical processors  0x0C */
  41        u64 physicalMemorySize;  /* Size of real memory(B)    0x10 */
  42
  43        u16 dCacheL1Size;        /* L1 d-cache size           0x18 */
  44        u16 dCacheL1LineSize;    /* L1 d-cache line size      0x1A */
  45        u16 dCacheL1LogLineSize; /* L1 d-cache line size Log2 0x1C */
  46        u16 dCacheL1LinesPerPage;/* L1 d-cache lines / page   0x1E */
  47        u16 dCacheL1Assoc;       /* L1 d-cache associativity  0x20 */
  48
  49        u16 iCacheL1Size;        /* L1 i-cache size           0x22 */
  50        u16 iCacheL1LineSize;    /* L1 i-cache line size      0x24 */
  51        u16 iCacheL1LogLineSize; /* L1 i-cache line size Log2 0x26 */
  52        u16 iCacheL1LinesPerPage;/* L1 i-cache lines / page   0x28 */
  53        u16 iCacheL1Assoc;       /* L1 i-cache associativity  0x2A */
  54
  55        u16 cacheL2Size;         /* L2 cache size             0x2C */
  56        u16 cacheL2Assoc;        /* L2 cache associativity    0x2E */
  57
  58        u64 tb_orig_stamp;       /* Timebase at boot          0x30 */
  59        u64 tb_ticks_per_sec;    /* Timebase tics / sec       0x38 */
  60        u64 tb_to_xs;            /* Inverse of TB to 2^20     0x40 */
  61        u64 stamp_xsec;          /*                           0x48 */
  62        volatile u64 tb_update_count; /* Timebase atomicity   0x50 */
  63        u32 tz_minuteswest;      /* Minutes west of Greenwich 0x58 */
  64        u32 tz_dsttime;          /* Type of dst correction    0x5C */
  65
  66        u64 resv1[4];            /* Reserverd          0x60 - 0x7F */
  67};
  68
  69/* Platform types */
  70#define PLATFORM_PSERIES      0x0100
  71#define PLATFORM_PSERIES_LPAR 0x0101
  72#define PLATFORM_ISERIES_LPAR 0x0201
  73
  74/* Processor types */
  75#define PV_NORTHSTAR    0x0033
  76#define PV_PULSAR       0x0034
  77#define PV_POWER4       0x0035
  78#define PV_ICESTAR      0x0036
  79#define PV_SSTAR        0x0037
  80#define PV_POWER4p      0x0038
  81#define PV_POWER4ul     0x0039
  82#define PV_630          0x0040
  83#define PV_630p         0x0041
  84
  85#endif /* USER_EXPORTS_H */
  86