LXR linux-old/arch/ppc/mm/4xx

   1/*
   2 * This file contains the routines for initializing the MMU
   3 * on the 4xx series of chips.
   4 *  -- paulus
   5 *
   6 *  Derived from arch/ppc/mm/init.c:
   7 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   8 *
   9 *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
  10 *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
  11 *    Copyright (C) 1996 Paul Mackerras
  12 *  Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
  13 *
  14 *  Derived from "arch/i386/mm/init.c"
  15 *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
  16 *
  17 *  This program is free software; you can redistribute it and/or
  18 *  modify it under the terms of the GNU General Public License
  19 *  as published by the Free Software Foundation; either version
  20 *  2 of the License, or (at your option) any later version.
  21 *
  22 */
  23
  24#include <linux/config.h>
  25#include <linux/signal.h>
  26#include <linux/sched.h>
  27#include <linux/kernel.h>
  28#include <linux/errno.h>
  29#include <linux/string.h>
  30#include <linux/types.h>
  31#include <linux/ptrace.h>
  32#include <linux/mman.h>
  33#include <linux/mm.h>
  34#include <linux/swap.h>
  35#include <linux/stddef.h>
  36#include <linux/vmalloc.h>
  37#include <linux/init.h>
  38#include <linux/delay.h>
  39#include <linux/bootmem.h>
  40#include <linux/highmem.h>
  41
  42#include <asm/pgalloc.h>
  43#include <asm/prom.h>
  44#include <asm/io.h>
  45#include <asm/mmu_context.h>
  46#include <asm/pgtable.h>
  47#include <asm/mmu.h>
  48#include <asm/uaccess.h>
  49#include <asm/smp.h>
  50#include <asm/bootx.h>
  51#include <asm/machdep.h>
  52#include <asm/setup.h>
  53
  54/*
  55 * MMU_init_hw does the chip-specific initialization of the MMU hardware.
  56 */
  57void __init MMU_init_hw(void)
  58{
  59        /*
  60         * The Zone Protection Register (ZPR) defines how protection will
  61         * be applied to every page which is a member of a given zone. At
  62         * present, we utilize only two of the 4xx's zones.
  63         * The zone index bits (of ZSEL) in the PTE are used for software
  64         * indicators, except the LSB.  For user access, zone 1 is used,
  65         * for kernel access, zone 0 is used.  We set all but zone 1
  66         * to zero, allowing only kernel access as indicated in the PTE.
  67         * For zone 1, we set a 01 binary (a value of 10 will not work)
  68         * to allow user access as indicated in the PTE.  This also allows
  69         * kernel access as indicated in the PTE.
  70         */
  71
  72        mtspr(SPRN_ZPR, 0x10000000);
  73
  74        flush_instruction_cache();
  75
  76        /*
  77         * Set up the real-mode cache parameters for the exception vector
  78         * handlers (which are run in real-mode).
  79         */
  80
  81        mtspr(SPRN_DCWR, 0x00000000);   /* All caching is write-back */
  82
  83        /*
  84         * Cache instruction and data space where the exception
  85         * vectors and the kernel live in real-mode.
  86         */
  87        /*
  88         * Once the following code is enhanced to not assume that it should
  89         * just enable caching on the first 512MB, we need to make sure that
  90         * we either are given the cache in a known state or handle correctly
  91         * the cache being enabled previously.  Currently this will clear
  92         * without flushing. -- Tom
  93         */
  94
  95        mtspr(SPRN_DCCR, 0xF0000000);   /* 512 MB of data space at 0x0. */
  96        mtspr(SPRN_ICCR, 0xF0000000);   /* 512 MB of instr. space at 0x0. */
  97}
  98