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32static char const rcsid[] =
33"$Id: idt77252.c,v 1.3 2001/11/17 00:30:19 ecd Exp $";
34
35
36#include <linux/module.h>
37#include <linux/config.h>
38#include <linux/pci.h>
39#include <linux/skbuff.h>
40#include <linux/kernel.h>
41#include <linux/vmalloc.h>
42#include <linux/netdevice.h>
43#include <linux/atmdev.h>
44#include <linux/atm.h>
45#include <linux/delay.h>
46#include <linux/init.h>
47#include <linux/bitops.h>
48#include <linux/wait.h>
49#include <asm/semaphore.h>
50#include <asm/io.h>
51#include <asm/uaccess.h>
52#include <asm/atomic.h>
53#include <asm/byteorder.h>
54
55#ifdef CONFIG_ATM_IDT77252_USE_SUNI
56#include "suni.h"
57#endif
58
59
60#include "idt77252.h"
61#include "idt77252_tables.h"
62
63static unsigned int vpibits = 1;
64
65
66#define CONFIG_ATM_IDT77252_SEND_IDLE 1
67
68
69
70
71
72#define DEBUG_MODULE 1
73#undef HAVE_EEPROM
74
75#ifdef CONFIG_ATM_IDT77252_DEBUG
76static unsigned long debug = DBG_GENERAL;
77#endif
78
79
80#define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY)
81
82
83
84
85
86static struct scq_info *alloc_scq(struct idt77252_dev *, int);
87static void free_scq(struct idt77252_dev *, struct scq_info *);
88static int queue_skb(struct idt77252_dev *, struct vc_map *,
89 struct sk_buff *, int oam);
90static void drain_scq(struct idt77252_dev *, struct vc_map *);
91static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *);
92static void fill_scd(struct idt77252_dev *, struct scq_info *, int);
93
94
95
96
97static int push_rx_skb(struct idt77252_dev *,
98 struct sk_buff *, int queue);
99static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *);
100static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *);
101static void recycle_rx_pool_skb(struct idt77252_dev *,
102 struct rx_pool *);
103static void add_rx_skb(struct idt77252_dev *, int queue,
104 unsigned int size, unsigned int count);
105
106
107
108
109static int init_rsq(struct idt77252_dev *);
110static void deinit_rsq(struct idt77252_dev *);
111static void idt77252_rx(struct idt77252_dev *);
112
113
114
115
116static int init_tsq(struct idt77252_dev *);
117static void deinit_tsq(struct idt77252_dev *);
118static void idt77252_tx(struct idt77252_dev *);
119
120
121
122
123
124static void idt77252_dev_close(struct atm_dev *dev);
125static int idt77252_open(struct atm_vcc *vcc, short vpi, int vci);
126static void idt77252_close(struct atm_vcc *vcc);
127static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb);
128static int idt77252_send_oam(struct atm_vcc *vcc, void *cell,
129 int flags);
130static void idt77252_phy_put(struct atm_dev *dev, unsigned char value,
131 unsigned long addr);
132static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr);
133static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos,
134 int flags);
135static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos,
136 char *page);
137static void idt77252_interrupt(int irq, void *dev_id,
138 struct pt_regs *regs);
139static void idt77252_softint(void *dev_id);
140
141
142static struct atmdev_ops idt77252_ops =
143{
144 dev_close: idt77252_dev_close,
145 open: idt77252_open,
146 close: idt77252_close,
147 send: idt77252_send,
148 send_oam: idt77252_send_oam,
149 phy_put: idt77252_phy_put,
150 phy_get: idt77252_phy_get,
151 change_qos: idt77252_change_qos,
152 proc_read: idt77252_proc_read
153};
154
155static struct idt77252_dev *idt77252_chain = NULL;
156static unsigned int idt77252_sram_write_errors = 0;
157
158
159
160
161
162
163
164static void
165waitfor_idle(struct idt77252_dev *card)
166{
167 u32 stat;
168
169 stat = readl(SAR_REG_STAT);
170 while (stat & SAR_STAT_CMDBZ)
171 stat = readl(SAR_REG_STAT);
172}
173
174static u32
175read_sram(struct idt77252_dev *card, unsigned long addr)
176{
177 unsigned long flags;
178 u32 value;
179
180 spin_lock_irqsave(&card->cmd_lock, flags);
181 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD);
182 waitfor_idle(card);
183 value = readl(SAR_REG_DR0);
184 spin_unlock_irqrestore(&card->cmd_lock, flags);
185 return value;
186}
187
188static void
189write_sram(struct idt77252_dev *card, unsigned long addr, u32 value)
190{
191 unsigned long flags;
192
193 if ((idt77252_sram_write_errors == 0) &&
194 (((addr > card->tst[0] + card->tst_size - 2) &&
195 (addr < card->tst[0] + card->tst_size)) ||
196 ((addr > card->tst[1] + card->tst_size - 2) &&
197 (addr < card->tst[1] + card->tst_size)))) {
198 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n",
199 card->name, addr, value);
200 }
201
202 spin_lock_irqsave(&card->cmd_lock, flags);
203 writel(value, SAR_REG_DR0);
204 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
205 waitfor_idle(card);
206 spin_unlock_irqrestore(&card->cmd_lock, flags);
207}
208
209static u8
210read_utility(void *dev, unsigned long ubus_addr)
211{
212 struct idt77252_dev *card = dev;
213 unsigned long flags;
214 u8 value;
215
216 if (!card) {
217 printk("Error: No such device.\n");
218 return -1;
219 }
220
221 spin_lock_irqsave(&card->cmd_lock, flags);
222 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD);
223 waitfor_idle(card);
224 value = readl(SAR_REG_DR0);
225 spin_unlock_irqrestore(&card->cmd_lock, flags);
226 return value;
227}
228
229static void
230write_utility(void *dev, unsigned long ubus_addr, u8 value)
231{
232 struct idt77252_dev *card = dev;
233 unsigned long flags;
234
235 if (!card) {
236 printk("Error: No such device.\n");
237 return;
238 }
239
240 spin_lock_irqsave(&card->cmd_lock, flags);
241 writel((u32) value, SAR_REG_DR0);
242 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD);
243 waitfor_idle(card);
244 spin_unlock_irqrestore(&card->cmd_lock, flags);
245}
246
247#ifdef HAVE_EEPROM
248static u32 rdsrtab[] =
249{
250 SAR_GP_EECS | SAR_GP_EESCLK,
251 0,
252 SAR_GP_EESCLK,
253 0,
254 SAR_GP_EESCLK,
255 0,
256 SAR_GP_EESCLK,
257 0,
258 SAR_GP_EESCLK,
259 0,
260 SAR_GP_EESCLK,
261 SAR_GP_EEDO,
262 SAR_GP_EESCLK | SAR_GP_EEDO,
263 0,
264 SAR_GP_EESCLK,
265 SAR_GP_EEDO,
266 SAR_GP_EESCLK | SAR_GP_EEDO
267};
268
269static u32 wrentab[] =
270{
271 SAR_GP_EECS | SAR_GP_EESCLK,
272 0,
273 SAR_GP_EESCLK,
274 0,
275 SAR_GP_EESCLK,
276 0,
277 SAR_GP_EESCLK,
278 0,
279 SAR_GP_EESCLK,
280 SAR_GP_EEDO,
281 SAR_GP_EESCLK | SAR_GP_EEDO,
282 SAR_GP_EEDO,
283 SAR_GP_EESCLK | SAR_GP_EEDO,
284 0,
285 SAR_GP_EESCLK,
286 0,
287 SAR_GP_EESCLK
288};
289
290static u32 rdtab[] =
291{
292 SAR_GP_EECS | SAR_GP_EESCLK,
293 0,
294 SAR_GP_EESCLK,
295 0,
296 SAR_GP_EESCLK,
297 0,
298 SAR_GP_EESCLK,
299 0,
300 SAR_GP_EESCLK,
301 0,
302 SAR_GP_EESCLK,
303 0,
304 SAR_GP_EESCLK,
305 SAR_GP_EEDO,
306 SAR_GP_EESCLK | SAR_GP_EEDO,
307 SAR_GP_EEDO,
308 SAR_GP_EESCLK | SAR_GP_EEDO
309};
310
311static u32 wrtab[] =
312{
313 SAR_GP_EECS | SAR_GP_EESCLK,
314 0,
315 SAR_GP_EESCLK,
316 0,
317 SAR_GP_EESCLK,
318 0,
319 SAR_GP_EESCLK,
320 0,
321 SAR_GP_EESCLK,
322 0,
323 SAR_GP_EESCLK,
324 0,
325 SAR_GP_EESCLK,
326 SAR_GP_EEDO,
327 SAR_GP_EESCLK | SAR_GP_EEDO,
328 0,
329 SAR_GP_EESCLK
330};
331
332static u32 clktab[] =
333{
334 0,
335 SAR_GP_EESCLK,
336 0,
337 SAR_GP_EESCLK,
338 0,
339 SAR_GP_EESCLK,
340 0,
341 SAR_GP_EESCLK,
342 0,
343 SAR_GP_EESCLK,
344 0,
345 SAR_GP_EESCLK,
346 0,
347 SAR_GP_EESCLK,
348 0,
349 SAR_GP_EESCLK,
350 0
351};
352
353static u32
354idt77252_read_gp(struct idt77252_dev *card)
355{
356 u32 gp;
357
358 gp = readl(SAR_REG_GP);
359#if 0
360 printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0");
361#endif
362 return gp;
363}
364
365static void
366idt77252_write_gp(struct idt77252_dev *card, u32 value)
367{
368 unsigned long flags;
369
370#if 0
371 printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS",
372 value & SAR_GP_EESCLK ? "HIGH" : "LOW ",
373 value & SAR_GP_EEDO ? "1" : "0");
374#endif
375
376 spin_lock_irqsave(&card->cmd_lock, flags);
377 waitfor_idle(card);
378 writel(value, SAR_REG_GP);
379 spin_unlock_irqrestore(&card->cmd_lock, flags);
380}
381
382static u8
383idt77252_eeprom_read_status(struct idt77252_dev *card)
384{
385 u8 byte;
386 u32 gp;
387 int i, j;
388
389 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
390
391 for (i = 0; i < sizeof(rdsrtab)/sizeof(rdsrtab[0]); i++) {
392 idt77252_write_gp(card, gp | rdsrtab[i]);
393 udelay(5);
394 }
395 idt77252_write_gp(card, gp | SAR_GP_EECS);
396 udelay(5);
397
398 byte = 0;
399 for (i = 0, j = 0; i < 8; i++) {
400 byte <<= 1;
401
402 idt77252_write_gp(card, gp | clktab[j++]);
403 udelay(5);
404
405 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
406
407 idt77252_write_gp(card, gp | clktab[j++]);
408 udelay(5);
409 }
410 idt77252_write_gp(card, gp | SAR_GP_EECS);
411 udelay(5);
412
413 return byte;
414}
415
416static u8
417idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset)
418{
419 u8 byte;
420 u32 gp;
421 int i, j;
422
423 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
424
425 for (i = 0; i < sizeof(rdtab)/sizeof(rdtab[0]); i++) {
426 idt77252_write_gp(card, gp | rdtab[i]);
427 udelay(5);
428 }
429 idt77252_write_gp(card, gp | SAR_GP_EECS);
430 udelay(5);
431
432 for (i = 0, j = 0; i < 8; i++) {
433 idt77252_write_gp(card, gp | clktab[j++] |
434 (offset & 1 ? SAR_GP_EEDO : 0));
435 udelay(5);
436
437 idt77252_write_gp(card, gp | clktab[j++] |
438 (offset & 1 ? SAR_GP_EEDO : 0));
439 udelay(5);
440
441 offset >>= 1;
442 }
443 idt77252_write_gp(card, gp | SAR_GP_EECS);
444 udelay(5);
445
446 byte = 0;
447 for (i = 0, j = 0; i < 8; i++) {
448 byte <<= 1;
449
450 idt77252_write_gp(card, gp | clktab[j++]);
451 udelay(5);
452
453 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
454
455 idt77252_write_gp(card, gp | clktab[j++]);
456 udelay(5);
457 }
458 idt77252_write_gp(card, gp | SAR_GP_EECS);
459 udelay(5);
460
461 return byte;
462}
463
464static void
465idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data)
466{
467 u32 gp;
468 int i, j;
469
470 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
471
472 for (i = 0; i < sizeof(wrentab)/sizeof(wrentab[0]); i++) {
473 idt77252_write_gp(card, gp | wrentab[i]);
474 udelay(5);
475 }
476 idt77252_write_gp(card, gp | SAR_GP_EECS);
477 udelay(5);
478
479 for (i = 0; i < sizeof(wrtab)/sizeof(wrtab[0]); i++) {
480 idt77252_write_gp(card, gp | wrtab[i]);
481 udelay(5);
482 }
483 idt77252_write_gp(card, gp | SAR_GP_EECS);
484 udelay(5);
485
486 for (i = 0, j = 0; i < 8; i++) {
487 idt77252_write_gp(card, gp | clktab[j++] |
488 (offset & 1 ? SAR_GP_EEDO : 0));
489 udelay(5);
490
491 idt77252_write_gp(card, gp | clktab[j++] |
492 (offset & 1 ? SAR_GP_EEDO : 0));
493 udelay(5);
494
495 offset >>= 1;
496 }
497 idt77252_write_gp(card, gp | SAR_GP_EECS);
498 udelay(5);
499
500 for (i = 0, j = 0; i < 8; i++) {
501 idt77252_write_gp(card, gp | clktab[j++] |
502 (data & 1 ? SAR_GP_EEDO : 0));
503 udelay(5);
504
505 idt77252_write_gp(card, gp | clktab[j++] |
506 (data & 1 ? SAR_GP_EEDO : 0));
507 udelay(5);
508
509 data >>= 1;
510 }
511 idt77252_write_gp(card, gp | SAR_GP_EECS);
512 udelay(5);
513}
514
515static void
516idt77252_eeprom_init(struct idt77252_dev *card)
517{
518 u32 gp;
519
520 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
521
522 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
523 udelay(5);
524 idt77252_write_gp(card, gp | SAR_GP_EECS);
525 udelay(5);
526 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
527 udelay(5);
528 idt77252_write_gp(card, gp | SAR_GP_EECS);
529 udelay(5);
530}
531#endif
532
533
534#ifdef CONFIG_ATM_IDT77252_DEBUG
535static void
536dump_tct(struct idt77252_dev *card, int index)
537{
538 unsigned long tct;
539 int i;
540
541 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE);
542
543 printk("%s: TCT %x:", card->name, index);
544 for (i = 0; i < 8; i++) {
545 printk(" %08x", read_sram(card, tct + i));
546 }
547 printk("\n");
548}
549
550static void
551idt77252_tx_dump(struct idt77252_dev *card)
552{
553 struct atm_vcc *vcc;
554 struct vc_map *vc;
555 int i;
556
557 printk("%s\n", __FUNCTION__);
558 for (i = 0; i < card->tct_size; i++) {
559 vc = card->vcs[i];
560 if (!vc)
561 continue;
562
563 vcc = NULL;
564 if (vc->rx_vcc)
565 vcc = vc->rx_vcc;
566 else if (vc->tx_vcc)
567 vcc = vc->tx_vcc;
568
569 if (!vcc)
570 continue;
571
572 printk("%s: Connection %d:\n", card->name, vc->index);
573 dump_tct(card, vc->index);
574 }
575}
576#endif
577
578
579
580
581
582
583
584
585static int
586sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue)
587{
588 struct sb_pool *pool = &card->sbpool[queue];
589 int index;
590
591 index = pool->index;
592 while (pool->skb[index]) {
593 index = (index + 1) & FBQ_MASK;
594 if (index == pool->index)
595 return -ENOBUFS;
596 }
597
598 pool->skb[index] = skb;
599 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index);
600
601 pool->index = (index + 1) & FBQ_MASK;
602 return 0;
603}
604
605static void
606sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb)
607{
608 unsigned int queue, index;
609 u32 handle;
610
611 handle = IDT77252_PRV_POOL(skb);
612
613 queue = POOL_QUEUE(handle);
614 if (queue > 3)
615 return;
616
617 index = POOL_INDEX(handle);
618 if (index > FBQ_SIZE - 1)
619 return;
620
621 card->sbpool[queue].skb[index] = NULL;
622}
623
624static struct sk_buff *
625sb_pool_skb(struct idt77252_dev *card, u32 handle)
626{
627 unsigned int queue, index;
628
629 queue = POOL_QUEUE(handle);
630 if (queue > 3)
631 return NULL;
632
633 index = POOL_INDEX(handle);
634 if (index > FBQ_SIZE - 1)
635 return NULL;
636
637 return card->sbpool[queue].skb[index];
638}
639
640static struct scq_info *
641alloc_scq(struct idt77252_dev *card, int class)
642{
643 struct scq_info *scq;
644
645 scq = (struct scq_info *) kmalloc(sizeof(struct scq_info), GFP_KERNEL);
646 if (!scq)
647 return NULL;
648 memset(scq, 0, sizeof(struct scq_info));
649
650 scq->base = pci_alloc_consistent(card->pcidev, SCQ_SIZE,
651 &scq->paddr);
652 if (scq->base == NULL) {
653 kfree(scq);
654 return NULL;
655 }
656 memset(scq->base, 0, SCQ_SIZE);
657
658 scq->next = scq->base;
659 scq->last = scq->base + (SCQ_ENTRIES - 1);
660 atomic_set(&scq->used, 0);
661
662 spin_lock_init(&scq->lock);
663 spin_lock_init(&scq->skblock);
664
665 skb_queue_head_init(&scq->transmit);
666 skb_queue_head_init(&scq->pending);
667
668 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08x\n",
669 scq->base, scq->next, scq->last, scq->paddr);
670
671 return scq;
672}
673
674static void
675free_scq(struct idt77252_dev *card, struct scq_info *scq)
676{
677 struct sk_buff *skb;
678 struct atm_vcc *vcc;
679
680 pci_free_consistent(card->pcidev, SCQ_SIZE,
681 scq->base, scq->paddr);
682
683 while ((skb = skb_dequeue(&scq->transmit))) {
684 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
685 skb->len, PCI_DMA_TODEVICE);
686
687 vcc = ATM_SKB(skb)->vcc;
688 if (vcc->pop)
689 vcc->pop(vcc, skb);
690 else
691 dev_kfree_skb(skb);
692 }
693
694 while ((skb = skb_dequeue(&scq->pending))) {
695 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
696 skb->len, PCI_DMA_TODEVICE);
697
698 vcc = ATM_SKB(skb)->vcc;
699 if (vcc->pop)
700 vcc->pop(vcc, skb);
701 else
702 dev_kfree_skb(skb);
703 }
704
705 kfree(scq);
706}
707
708
709static int
710push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb)
711{
712 struct scq_info *scq = vc->scq;
713 unsigned long flags;
714 struct scqe *tbd;
715 int entries;
716
717 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next);
718
719 atomic_inc(&scq->used);
720 entries = atomic_read(&scq->used);
721 if (entries > (SCQ_ENTRIES - 1)) {
722 atomic_dec(&scq->used);
723 goto out;
724 }
725
726 skb_queue_tail(&scq->transmit, skb);
727
728 spin_lock_irqsave(&vc->lock, flags);
729 if (vc->estimator) {
730 struct atm_vcc *vcc = vc->tx_vcc;
731
732 vc->estimator->cells += (skb->len + 47) / 48;
733 if (atomic_read(&vcc->sk->wmem_alloc) > (vcc->sk->sndbuf >> 1)) {
734 u32 cps = vc->estimator->maxcps;
735
736 vc->estimator->cps = cps;
737 vc->estimator->avcps = cps << 5;
738 if (vc->lacr < vc->init_er) {
739 vc->lacr = vc->init_er;
740 writel(TCMDQ_LACR | (vc->lacr << 16) |
741 vc->index, SAR_REG_TCMDQ);
742 }
743 }
744 }
745 spin_unlock_irqrestore(&vc->lock, flags);
746
747 tbd = &IDT77252_PRV_TBD(skb);
748
749 spin_lock_irqsave(&scq->lock, flags);
750 scq->next->word_1 = cpu_to_le32(tbd->word_1 |
751 SAR_TBD_TSIF | SAR_TBD_GTSI);
752 scq->next->word_2 = cpu_to_le32(tbd->word_2);
753 scq->next->word_3 = cpu_to_le32(tbd->word_3);
754 scq->next->word_4 = cpu_to_le32(tbd->word_4);
755
756 if (scq->next == scq->last)
757 scq->next = scq->base;
758 else
759 scq->next++;
760
761 write_sram(card, scq->scd,
762 scq->paddr +
763 (u32)((unsigned long)scq->next - (unsigned long)scq->base));
764 spin_unlock_irqrestore(&scq->lock, flags);
765
766 scq->trans_start = jiffies;
767
768 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) {
769 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index,
770 SAR_REG_TCMDQ);
771 }
772
773 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used));
774
775 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n",
776 card->name, atomic_read(&scq->used),
777 read_sram(card, scq->scd + 1), scq->next);
778
779 return 0;
780
781out:
782 if (jiffies - scq->trans_start > HZ) {
783 printk("%s: Error pushing TBD for %d.%d\n",
784 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci);
785#ifdef CONFIG_ATM_IDT77252_DEBUG
786 idt77252_tx_dump(card);
787#endif
788 scq->trans_start = jiffies;
789 }
790
791 return -ENOBUFS;
792}
793
794
795static void
796drain_scq(struct idt77252_dev *card, struct vc_map *vc)
797{
798 struct scq_info *scq = vc->scq;
799 struct sk_buff *skb;
800 struct atm_vcc *vcc;
801
802 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n",
803 card->name, atomic_read(&scq->used), scq->next);
804
805 skb = skb_dequeue(&scq->transmit);
806 if (skb) {
807 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb);
808
809 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
810 skb->len, PCI_DMA_TODEVICE);
811
812 vcc = ATM_SKB(skb)->vcc;
813
814 if (vcc->pop)
815 vcc->pop(vcc, skb);
816 else
817 dev_kfree_skb(skb);
818
819 atomic_inc(&vcc->stats->tx);
820 }
821
822 atomic_dec(&scq->used);
823
824 spin_lock(&scq->skblock);
825 while ((skb = skb_dequeue(&scq->pending))) {
826 if (push_on_scq(card, vc, skb)) {
827 skb_queue_head(&vc->scq->pending, skb);
828 break;
829 }
830 }
831 spin_unlock(&scq->skblock);
832}
833
834static int
835queue_skb(struct idt77252_dev *card, struct vc_map *vc,
836 struct sk_buff *skb, int oam)
837{
838 struct atm_vcc *vcc;
839 struct scqe *tbd;
840 unsigned long flags;
841 int error;
842 int aal;
843
844 if (skb->len == 0) {
845 printk("%s: invalid skb->len (%d)\n", card->name, skb->len);
846 return -EINVAL;
847 }
848
849 TXPRINTK("%s: Sending %d bytes of data.\n",
850 card->name, skb->len);
851
852 tbd = &IDT77252_PRV_TBD(skb);
853 vcc = ATM_SKB(skb)->vcc;
854
855 IDT77252_PRV_PADDR(skb) = pci_map_single(card->pcidev, skb->data,
856 skb->len, PCI_DMA_TODEVICE);
857
858 error = -EINVAL;
859
860 if (oam) {
861 if (skb->len != 52)
862 goto errout;
863
864 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU;
865 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
866 tbd->word_3 = 0x00000000;
867 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
868 (skb->data[2] << 8) | (skb->data[3] << 0);
869
870 if (test_bit(VCF_RSV, &vc->flags))
871 vc = card->vcs[0];
872
873 goto done;
874 }
875
876 if (test_bit(VCF_RSV, &vc->flags)) {
877 printk("%s: Trying to transmit on reserved VC\n", card->name);
878 goto errout;
879 }
880
881 aal = vcc->qos.aal;
882
883 switch (aal) {
884 case ATM_AAL0:
885 case ATM_AAL34:
886 if (skb->len > 52)
887 goto errout;
888
889 if (aal == ATM_AAL0)
890 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 |
891 ATM_CELL_PAYLOAD;
892 else
893 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 |
894 ATM_CELL_PAYLOAD;
895
896 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
897 tbd->word_3 = 0x00000000;
898 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
899 (skb->data[2] << 8) | (skb->data[3] << 0);
900 break;
901
902 case ATM_AAL5:
903 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len;
904 tbd->word_2 = IDT77252_PRV_PADDR(skb);
905 tbd->word_3 = skb->len;
906 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) |
907 (vcc->vci << SAR_TBD_VCI_SHIFT);
908 break;
909
910 case ATM_AAL1:
911 case ATM_AAL2:
912 default:
913 printk("%s: Traffic type not supported.\n", card->name);
914 error = -EPROTONOSUPPORT;
915 goto errout;
916 }
917
918done:
919 spin_lock_irqsave(&vc->scq->skblock, flags);
920 skb_queue_tail(&vc->scq->pending, skb);
921
922 while ((skb = skb_dequeue(&vc->scq->pending))) {
923 if (push_on_scq(card, vc, skb)) {
924 skb_queue_head(&vc->scq->pending, skb);
925 break;
926 }
927 }
928 spin_unlock_irqrestore(&vc->scq->skblock, flags);
929
930 return 0;
931
932errout:
933 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
934 skb->len, PCI_DMA_TODEVICE);
935 return error;
936}
937
938static unsigned long
939get_free_scd(struct idt77252_dev *card, struct vc_map *vc)
940{
941 int i;
942
943 for (i = 0; i < card->scd_size; i++) {
944 if (!card->scd2vc[i]) {
945 card->scd2vc[i] = vc;
946 vc->scd_index = i;
947 return card->scd_base + i * SAR_SRAM_SCD_SIZE;
948 }
949 }
950 return 0;
951}
952
953static void
954fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
955{
956 write_sram(card, scq->scd, scq->paddr);
957 write_sram(card, scq->scd + 1, 0x00000000);
958 write_sram(card, scq->scd + 2, 0xffffffff);
959 write_sram(card, scq->scd + 3, 0x00000000);
960}
961
962static void
963clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
964{
965 return;
966}
967
968
969
970
971
972
973
974static int
975init_rsq(struct idt77252_dev *card)
976{
977 struct rsq_entry *rsqe;
978
979 card->rsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
980 &card->rsq.paddr);
981 if (card->rsq.base == NULL) {
982 printk("%s: can't allocate RSQ.\n", card->name);
983 return -1;
984 }
985 memset(card->rsq.base, 0, RSQSIZE);
986
987 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1;
988 card->rsq.next = card->rsq.last;
989 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++)
990 rsqe->word_4 = 0;
991
992 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base,
993 SAR_REG_RSQH);
994 writel(card->rsq.paddr, SAR_REG_RSQB);
995
996 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name,
997 (unsigned long) card->rsq.base,
998 readl(SAR_REG_RSQB));
999 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n",
1000 card->name,
1001 readl(SAR_REG_RSQH),
1002 readl(SAR_REG_RSQB),
1003 readl(SAR_REG_RSQT));
1004
1005 return 0;
1006}
1007
1008static void
1009deinit_rsq(struct idt77252_dev *card)
1010{
1011 pci_free_consistent(card->pcidev, RSQSIZE,
1012 card->rsq.base, card->rsq.paddr);
1013}
1014
1015static void
1016dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)
1017{
1018 struct atm_vcc *vcc;
1019 struct sk_buff *skb;
1020 struct rx_pool *rpp;
1021 struct vc_map *vc;
1022 u32 header, vpi, vci;
1023 u32 stat;
1024 int i;
1025
1026 stat = le32_to_cpu(rsqe->word_4);
1027
1028 if (stat & SAR_RSQE_IDLE) {
1029 RXPRINTK("%s: message about inactive connection.\n",
1030 card->name);
1031 return;
1032 }
1033
1034 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2));
1035 if (skb == NULL) {
1036 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n",
1037 card->name, __FUNCTION__,
1038 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2),
1039 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4));
1040 return;
1041 }
1042
1043 header = le32_to_cpu(rsqe->word_1);
1044 vpi = (header >> 16) & 0x00ff;
1045 vci = (header >> 0) & 0xffff;
1046
1047 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n",
1048 card->name, vpi, vci, skb, skb->data);
1049
1050 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) {
1051 printk("%s: SDU received for out-of-range vc %u.%u\n",
1052 card->name, vpi, vci);
1053 recycle_rx_skb(card, skb);
1054 return;
1055 }
1056
1057 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1058 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1059 printk("%s: SDU received on non RX vc %u.%u\n",
1060 card->name, vpi, vci);
1061 recycle_rx_skb(card, skb);
1062 return;
1063 }
1064
1065 vcc = vc->rx_vcc;
1066
1067 pci_dma_sync_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1068 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1069
1070 if ((vcc->qos.aal == ATM_AAL0) ||
1071 (vcc->qos.aal == ATM_AAL34)) {
1072 struct sk_buff *sb;
1073 unsigned char *cell;
1074 u32 aal0;
1075
1076 cell = skb->data;
1077 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) {
1078 if ((sb = dev_alloc_skb(64)) == NULL) {
1079 printk("%s: Can't allocate buffers for aal0.\n",
1080 card->name);
1081 atomic_add(i, &vcc->stats->rx_drop);
1082 break;
1083 }
1084 if (!atm_charge(vcc, sb->truesize)) {
1085 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n",
1086 card->name);
1087 atomic_add(i - 1, &vcc->stats->rx_drop);
1088 dev_kfree_skb(sb);
1089 break;
1090 }
1091 aal0 = (vpi << ATM_HDR_VPI_SHIFT) |
1092 (vci << ATM_HDR_VCI_SHIFT);
1093 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0;
1094 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0;
1095
1096 *((u32 *) sb->data) = aal0;
1097 skb_put(sb, sizeof(u32));
1098 memcpy(skb_put(sb, ATM_CELL_PAYLOAD),
1099 cell, ATM_CELL_PAYLOAD);
1100
1101 ATM_SKB(sb)->vcc = vcc;
1102 sb->stamp = xtime;
1103 vcc->push(vcc, sb);
1104 atomic_inc(&vcc->stats->rx);
1105
1106 cell += ATM_CELL_PAYLOAD;
1107 }
1108
1109 recycle_rx_skb(card, skb);
1110 return;
1111 }
1112 if (vcc->qos.aal != ATM_AAL5) {
1113 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n",
1114 card->name, vcc->qos.aal);
1115 recycle_rx_skb(card, skb);
1116 return;
1117 }
1118 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD;
1119
1120 rpp = &vc->rcv.rx_pool;
1121
1122 rpp->len += skb->len;
1123 if (!rpp->count++)
1124 rpp->first = skb;
1125 *rpp->last = skb;
1126 rpp->last = &skb->next;
1127
1128 if (stat & SAR_RSQE_EPDU) {
1129 unsigned char *l1l2;
1130 unsigned int len;
1131
1132 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6);
1133
1134 len = (l1l2[0] << 8) | l1l2[1];
1135 len = len ? len : 0x10000;
1136
1137 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len);
1138
1139 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) {
1140 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. "
1141 "(CDC: %08x)\n",
1142 card->name, len, rpp->len, readl(SAR_REG_CDC));
1143 recycle_rx_pool_skb(card, rpp);
1144 atomic_inc(&vcc->stats->rx_err);
1145 return;
1146 }
1147 if (stat & SAR_RSQE_CRC) {
1148 RXPRINTK("%s: AAL5 CRC error.\n", card->name);
1149 recycle_rx_pool_skb(card, rpp);
1150 atomic_inc(&vcc->stats->rx_err);
1151 return;
1152 }
1153 if (rpp->count > 1) {
1154 struct sk_buff *sb;
1155
1156 skb = dev_alloc_skb(rpp->len);
1157 if (!skb) {
1158 RXPRINTK("%s: Can't alloc RX skb.\n",
1159 card->name);
1160 recycle_rx_pool_skb(card, rpp);
1161 atomic_inc(&vcc->stats->rx_err);
1162 return;
1163 }
1164 if (!atm_charge(vcc, skb->truesize)) {
1165 recycle_rx_pool_skb(card, rpp);
1166 dev_kfree_skb(skb);
1167 return;
1168 }
1169 sb = rpp->first;
1170 for (i = 0; i < rpp->count; i++) {
1171 memcpy(skb_put(skb, sb->len),
1172 sb->data, sb->len);
1173 sb = sb->next;
1174 }
1175
1176 recycle_rx_pool_skb(card, rpp);
1177
1178 skb_trim(skb, len);
1179 ATM_SKB(skb)->vcc = vcc;
1180 skb->stamp = xtime;
1181
1182 vcc->push(vcc, skb);
1183 atomic_inc(&vcc->stats->rx);
1184
1185 return;
1186 }
1187
1188 skb->next = NULL;
1189 flush_rx_pool(card, rpp);
1190
1191 if (!atm_charge(vcc, skb->truesize)) {
1192 recycle_rx_skb(card, skb);
1193 return;
1194 }
1195
1196 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1197 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1198 sb_pool_remove(card, skb);
1199
1200 skb_trim(skb, len);
1201 ATM_SKB(skb)->vcc = vcc;
1202 skb->stamp = xtime;
1203
1204 vcc->push(vcc, skb);
1205 atomic_inc(&vcc->stats->rx);
1206
1207 if (skb->truesize > SAR_FB_SIZE_3)
1208 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1);
1209 else if (skb->truesize > SAR_FB_SIZE_2)
1210 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1);
1211 else if (skb->truesize > SAR_FB_SIZE_1)
1212 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1);
1213 else
1214 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1);
1215 return;
1216 }
1217}
1218
1219static void
1220idt77252_rx(struct idt77252_dev *card)
1221{
1222 struct rsq_entry *rsqe;
1223
1224 if (card->rsq.next == card->rsq.last)
1225 rsqe = card->rsq.base;
1226 else
1227 rsqe = card->rsq.next + 1;
1228
1229 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) {
1230 RXPRINTK("%s: no entry in RSQ.\n", card->name);
1231 return;
1232 }
1233
1234 do {
1235 dequeue_rx(card, rsqe);
1236 rsqe->word_4 = 0;
1237 card->rsq.next = rsqe;
1238 if (card->rsq.next == card->rsq.last)
1239 rsqe = card->rsq.base;
1240 else
1241 rsqe = card->rsq.next + 1;
1242 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID);
1243
1244 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base,
1245 SAR_REG_RSQH);
1246}
1247
1248static void
1249idt77252_rx_raw(struct idt77252_dev *card)
1250{
1251 struct sk_buff *queue;
1252 u32 head, tail;
1253 struct atm_vcc *vcc;
1254 struct vc_map *vc;
1255 struct sk_buff *sb;
1256
1257 if (card->raw_cell_head == NULL) {
1258 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1));
1259 card->raw_cell_head = sb_pool_skb(card, handle);
1260 }
1261
1262 queue = card->raw_cell_head;
1263 if (!queue)
1264 return;
1265
1266 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16);
1267 tail = readl(SAR_REG_RAWCT);
1268
1269 pci_dma_sync_single(card->pcidev, IDT77252_PRV_PADDR(queue),
1270 queue->end - queue->head - 16, PCI_DMA_FROMDEVICE);
1271
1272 while (head != tail) {
1273 unsigned int vpi, vci, pti;
1274 u32 header;
1275
1276 header = le32_to_cpu(*(u32 *) &queue->data[0]);
1277
1278 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT;
1279 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT;
1280 pti = (header & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT;
1281
1282#ifdef CONFIG_ATM_IDT77252_DEBUG
1283 if (debug & DBG_RAW_CELL) {
1284 int i;
1285
1286 printk("%s: raw cell %x.%02x.%04x.%x.%x\n",
1287 card->name, (header >> 28) & 0x000f,
1288 (header >> 20) & 0x00ff,
1289 (header >> 4) & 0xffff,
1290 (header >> 1) & 0x0007,
1291 (header >> 0) & 0x0001);
1292 for (i = 16; i < 64; i++)
1293 printk(" %02x", queue->data[i]);
1294 printk("\n");
1295 }
1296#endif
1297
1298 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) {
1299 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n",
1300 card->name, vpi, vci);
1301 goto drop;
1302 }
1303
1304 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1305 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1306 RPRINTK("%s: SDU received on non RX vc %u.%u\n",
1307 card->name, vpi, vci);
1308 goto drop;
1309 }
1310
1311 vcc = vc->rx_vcc;
1312
1313 if (vcc->qos.aal != ATM_AAL0) {
1314 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n",
1315 card->name, vpi, vci);
1316 atomic_inc(&vcc->stats->rx_drop);
1317 goto drop;
1318 }
1319
1320 if ((sb = dev_alloc_skb(64)) == NULL) {
1321 printk("%s: Can't allocate buffers for AAL0.\n",
1322 card->name);
1323 atomic_inc(&vcc->stats->rx_err);
1324 goto drop;
1325 }
1326
1327 if ((vcc->sk != NULL) && !atm_charge(vcc, sb->truesize)) {
1328 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n",
1329 card->name);
1330 dev_kfree_skb(sb);
1331 goto drop;
1332 }
1333
1334 *((u32 *) sb->data) = header;
1335 skb_put(sb, sizeof(u32));
1336 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]),
1337 ATM_CELL_PAYLOAD);
1338
1339 ATM_SKB(sb)->vcc = vcc;
1340 sb->stamp = xtime;
1341 vcc->push(vcc, sb);
1342 atomic_inc(&vcc->stats->rx);
1343
1344drop:
1345 skb_pull(queue, 64);
1346
1347 head = IDT77252_PRV_PADDR(queue)
1348 + (queue->data - queue->head - 16);
1349
1350 if (queue->len < 128) {
1351 struct sk_buff *next;
1352 u32 handle;
1353
1354 head = le32_to_cpu(*(u32 *) &queue->data[0]);
1355 handle = le32_to_cpu(*(u32 *) &queue->data[4]);
1356
1357 next = sb_pool_skb(card, handle);
1358 recycle_rx_skb(card, queue);
1359
1360 if (next) {
1361 card->raw_cell_head = next;
1362 queue = card->raw_cell_head;
1363 pci_dma_sync_single(card->pcidev,
1364 IDT77252_PRV_PADDR(queue),
1365 queue->end - queue->data,
1366 PCI_DMA_FROMDEVICE);
1367 } else {
1368 card->raw_cell_head = NULL;
1369 printk("%s: raw cell queue overrun\n",
1370 card->name);
1371 break;
1372 }
1373 }
1374 }
1375}
1376
1377
1378
1379
1380
1381
1382
1383
1384static int
1385init_tsq(struct idt77252_dev *card)
1386{
1387 struct tsq_entry *tsqe;
1388
1389 card->tsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
1390 &card->tsq.paddr);
1391 if (card->tsq.base == NULL) {
1392 printk("%s: can't allocate TSQ.\n", card->name);
1393 return -1;
1394 }
1395 memset(card->tsq.base, 0, TSQSIZE);
1396
1397 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1;
1398 card->tsq.next = card->tsq.last;
1399 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++)
1400 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1401
1402 writel(card->tsq.paddr, SAR_REG_TSQB);
1403 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base,
1404 SAR_REG_TSQH);
1405
1406 return 0;
1407}
1408
1409static void
1410deinit_tsq(struct idt77252_dev *card)
1411{
1412 pci_free_consistent(card->pcidev, TSQSIZE,
1413 card->tsq.base, card->tsq.paddr);
1414}
1415
1416static void
1417idt77252_tx(struct idt77252_dev *card)
1418{
1419 struct tsq_entry *tsqe;
1420 unsigned int vpi, vci;
1421 struct vc_map *vc;
1422 u32 conn, stat;
1423
1424 if (card->tsq.next == card->tsq.last)
1425 tsqe = card->tsq.base;
1426 else
1427 tsqe = card->tsq.next + 1;
1428
1429 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe,
1430 card->tsq.base, card->tsq.next, card->tsq.last);
1431 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n",
1432 readl(SAR_REG_TSQB),
1433 readl(SAR_REG_TSQT),
1434 readl(SAR_REG_TSQH));
1435
1436 stat = le32_to_cpu(tsqe->word_2);
1437
1438 if (stat & SAR_TSQE_INVALID)
1439 return;
1440
1441 do {
1442 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe,
1443 le32_to_cpu(tsqe->word_1),
1444 le32_to_cpu(tsqe->word_2));
1445
1446 switch (stat & SAR_TSQE_TYPE) {
1447 case SAR_TSQE_TYPE_TIMER:
1448 TXPRINTK("%s: Timer RollOver detected.\n", card->name);
1449 break;
1450
1451 case SAR_TSQE_TYPE_IDLE:
1452
1453 conn = le32_to_cpu(tsqe->word_1);
1454
1455 if (SAR_TSQE_TAG(stat) == 0x10) {
1456#ifdef NOTDEF
1457 printk("%s: Connection %d halted.\n",
1458 card->name,
1459 le32_to_cpu(tsqe->word_1) & 0x1fff);
1460#endif
1461 break;
1462 }
1463
1464 vc = card->vcs[conn & 0x1fff];
1465 if (!vc) {
1466 printk("%s: could not find VC from conn %d\n",
1467 card->name, conn & 0x1fff);
1468 break;
1469 }
1470
1471 printk("%s: Connection %d IDLE.\n",
1472 card->name, vc->index);
1473
1474 set_bit(VCF_IDLE, &vc->flags);
1475 break;
1476
1477 case SAR_TSQE_TYPE_TSR:
1478
1479 conn = le32_to_cpu(tsqe->word_1);
1480
1481 vc = card->vcs[conn & 0x1fff];
1482 if (!vc) {
1483 printk("%s: no VC at index %d\n",
1484 card->name,
1485 le32_to_cpu(tsqe->word_1) & 0x1fff);
1486 break;
1487 }
1488
1489 drain_scq(card, vc);
1490 break;
1491
1492 case SAR_TSQE_TYPE_TBD_COMP:
1493
1494 conn = le32_to_cpu(tsqe->word_1);
1495
1496 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff;
1497 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff;
1498
1499 if (vpi >= (1 << card->vpibits) ||
1500 vci >= (1 << card->vcibits)) {
1501 printk("%s: TBD complete: "
1502 "out of range VPI.VCI %u.%u\n",
1503 card->name, vpi, vci);
1504 break;
1505 }
1506
1507 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1508 if (!vc) {
1509 printk("%s: TBD complete: "
1510 "no VC at VPI.VCI %u.%u\n",
1511 card->name, vpi, vci);
1512 break;
1513 }
1514
1515 drain_scq(card, vc);
1516 break;
1517 }
1518
1519 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1520
1521 card->tsq.next = tsqe;
1522 if (card->tsq.next == card->tsq.last)
1523 tsqe = card->tsq.base;
1524 else
1525 tsqe = card->tsq.next + 1;
1526
1527 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe,
1528 card->tsq.base, card->tsq.next, card->tsq.last);
1529
1530 stat = le32_to_cpu(tsqe->word_2);
1531
1532 } while (!(stat & SAR_TSQE_INVALID));
1533
1534 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base,
1535 SAR_REG_TSQH);
1536
1537 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n",
1538 card->index, readl(SAR_REG_TSQH),
1539 readl(SAR_REG_TSQT), card->tsq.next);
1540}
1541
1542
1543static void
1544tst_timer(unsigned long data)
1545{
1546 struct idt77252_dev *card = (struct idt77252_dev *)data;
1547 unsigned long base, idle, jump;
1548 unsigned long flags;
1549 u32 pc;
1550 int e;
1551
1552 spin_lock_irqsave(&card->tst_lock, flags);
1553
1554 base = card->tst[card->tst_index];
1555 idle = card->tst[card->tst_index ^ 1];
1556
1557 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) {
1558 jump = base + card->tst_size - 2;
1559
1560 pc = readl(SAR_REG_NOW) >> 2;
1561 if ((pc ^ idle) & ~(card->tst_size - 1)) {
1562 mod_timer(&card->tst_timer, jiffies + 1);
1563 goto out;
1564 }
1565
1566 clear_bit(TST_SWITCH_WAIT, &card->tst_state);
1567
1568 card->tst_index ^= 1;
1569 write_sram(card, jump, TSTE_OPC_JMP | (base << 2));
1570
1571 base = card->tst[card->tst_index];
1572 idle = card->tst[card->tst_index ^ 1];
1573
1574 for (e = 0; e < card->tst_size - 2; e++) {
1575 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) {
1576 write_sram(card, idle + e,
1577 card->soft_tst[e].tste & TSTE_MASK);
1578 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE);
1579 }
1580 }
1581 }
1582
1583 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) {
1584
1585 for (e = 0; e < card->tst_size - 2; e++) {
1586 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) {
1587 write_sram(card, idle + e,
1588 card->soft_tst[e].tste & TSTE_MASK);
1589 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE);
1590 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1591 }
1592 }
1593
1594 jump = base + card->tst_size - 2;
1595
1596 write_sram(card, jump, TSTE_OPC_NULL);
1597 set_bit(TST_SWITCH_WAIT, &card->tst_state);
1598
1599 mod_timer(&card->tst_timer, jiffies + 1);
1600 }
1601
1602out:
1603 spin_unlock_irqrestore(&card->tst_lock, flags);
1604}
1605
1606static int
1607__fill_tst(struct idt77252_dev *card, struct vc_map *vc,
1608 int n, unsigned int opc)
1609{
1610 unsigned long cl, avail;
1611 unsigned long idle;
1612 int e, r;
1613 u32 data;
1614
1615 avail = card->tst_size - 2;
1616 for (e = 0; e < avail; e++) {
1617 if (card->soft_tst[e].vc == NULL)
1618 break;
1619 }
1620 if (e >= avail) {
1621 printk("%s: No free TST entries found\n", card->name);
1622 return -1;
1623 }
1624
1625 NPRINTK("%s: conn %d: first TST entry at %d.\n",
1626 card->name, vc ? vc->index : -1, e);
1627
1628 r = n;
1629 cl = avail;
1630 data = opc & TSTE_OPC_MASK;
1631 if (vc && (opc != TSTE_OPC_NULL))
1632 data = opc | vc->index;
1633
1634 idle = card->tst[card->tst_index ^ 1];
1635
1636
1637
1638
1639 while (r > 0) {
1640 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) {
1641 if (vc)
1642 card->soft_tst[e].vc = vc;
1643 else
1644 card->soft_tst[e].vc = (void *)-1;
1645
1646 card->soft_tst[e].tste = data;
1647 if (timer_pending(&card->tst_timer))
1648 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1649 else {
1650 write_sram(card, idle + e, data);
1651 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1652 }
1653
1654 cl -= card->tst_size;
1655 r--;
1656 }
1657
1658 if (++e == avail)
1659 e = 0;
1660 cl += n;
1661 }
1662
1663 return 0;
1664}
1665
1666static int
1667fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)
1668{
1669 unsigned long flags;
1670 int res;
1671
1672 spin_lock_irqsave(&card->tst_lock, flags);
1673
1674 res = __fill_tst(card, vc, n, opc);
1675
1676 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1677 if (!timer_pending(&card->tst_timer))
1678 mod_timer(&card->tst_timer, jiffies + 1);
1679
1680 spin_unlock_irqrestore(&card->tst_lock, flags);
1681 return res;
1682}
1683
1684static int
1685__clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1686{
1687 unsigned long idle;
1688 int e;
1689
1690 idle = card->tst[card->tst_index ^ 1];
1691
1692 for (e = 0; e < card->tst_size - 2; e++) {
1693 if (card->soft_tst[e].vc == vc) {
1694 card->soft_tst[e].vc = NULL;
1695
1696 card->soft_tst[e].tste = TSTE_OPC_VAR;
1697 if (timer_pending(&card->tst_timer))
1698 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1699 else {
1700 write_sram(card, idle + e, TSTE_OPC_VAR);
1701 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1702 }
1703 }
1704 }
1705
1706 return 0;
1707}
1708
1709static int
1710clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1711{
1712 unsigned long flags;
1713 int res;
1714
1715 spin_lock_irqsave(&card->tst_lock, flags);
1716
1717 res = __clear_tst(card, vc);
1718
1719 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1720 if (!timer_pending(&card->tst_timer))
1721 mod_timer(&card->tst_timer, jiffies + 1);
1722
1723 spin_unlock_irqrestore(&card->tst_lock, flags);
1724 return res;
1725}
1726
1727static int
1728change_tst(struct idt77252_dev *card, struct vc_map *vc,
1729 int n, unsigned int opc)
1730{
1731 unsigned long flags;
1732 int res;
1733
1734 spin_lock_irqsave(&card->tst_lock, flags);
1735
1736 __clear_tst(card, vc);
1737 res = __fill_tst(card, vc, n, opc);
1738
1739 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1740 if (!timer_pending(&card->tst_timer))
1741 mod_timer(&card->tst_timer, jiffies + 1);
1742
1743 spin_unlock_irqrestore(&card->tst_lock, flags);
1744 return res;
1745}
1746
1747
1748static int
1749set_tct(struct idt77252_dev *card, struct vc_map *vc)
1750{
1751 unsigned long tct;
1752
1753 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE);
1754
1755 switch (vc->class) {
1756 case SCHED_CBR:
1757 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1758 card->name, tct, vc->scq->scd);
1759
1760 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd);
1761 write_sram(card, tct + 1, 0);
1762 write_sram(card, tct + 2, 0);
1763 write_sram(card, tct + 3, 0);
1764 write_sram(card, tct + 4, 0);
1765 write_sram(card, tct + 5, 0);
1766 write_sram(card, tct + 6, 0);
1767 write_sram(card, tct + 7, 0);
1768 break;
1769
1770 case SCHED_UBR:
1771 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1772 card->name, tct, vc->scq->scd);
1773
1774 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd);
1775 write_sram(card, tct + 1, 0);
1776 write_sram(card, tct + 2, TCT_TSIF);
1777 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE);
1778 write_sram(card, tct + 4, 0);
1779 write_sram(card, tct + 5, vc->init_er);
1780 write_sram(card, tct + 6, 0);
1781 write_sram(card, tct + 7, TCT_FLAG_UBR);
1782 break;
1783
1784 case SCHED_VBR:
1785 case SCHED_ABR:
1786 default:
1787 return -ENOSYS;
1788 }
1789
1790 return 0;
1791}
1792
1793
1794
1795
1796
1797
1798
1799static __inline__ int
1800idt77252_fbq_level(struct idt77252_dev *card, int queue)
1801{
1802 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f;
1803}
1804
1805static __inline__ int
1806idt77252_fbq_full(struct idt77252_dev *card, int queue)
1807{
1808 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f;
1809}
1810
1811static int
1812push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue)
1813{
1814 unsigned long flags;
1815 u32 handle;
1816 u32 addr;
1817
1818 skb->data = skb->tail = skb->head;
1819 skb->len = 0;
1820
1821 skb_reserve(skb, 16);
1822
1823 switch (queue) {
1824 case 0:
1825 skb_put(skb, SAR_FB_SIZE_0);
1826 break;
1827 case 1:
1828 skb_put(skb, SAR_FB_SIZE_1);
1829 break;
1830 case 2:
1831 skb_put(skb, SAR_FB_SIZE_2);
1832 break;
1833 case 3:
1834 skb_put(skb, SAR_FB_SIZE_3);
1835 break;
1836 default:
1837 dev_kfree_skb(skb);
1838 return -1;
1839 }
1840
1841 if (idt77252_fbq_full(card, queue))
1842 return -1;
1843
1844 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32));
1845
1846 handle = IDT77252_PRV_POOL(skb);
1847 addr = IDT77252_PRV_PADDR(skb);
1848
1849 spin_lock_irqsave(&card->cmd_lock, flags);
1850 writel(handle, card->fbq[queue]);
1851 writel(addr, card->fbq[queue]);
1852 spin_unlock_irqrestore(&card->cmd_lock, flags);
1853
1854 return 0;
1855}
1856
1857static void
1858add_rx_skb(struct idt77252_dev *card, int queue,
1859 unsigned int size, unsigned int count)
1860{
1861 struct sk_buff *skb;
1862 dma_addr_t paddr;
1863 u32 handle;
1864
1865 while (count--) {
1866 skb = dev_alloc_skb(size);
1867 if (!skb)
1868 return;
1869
1870 if (sb_pool_add(card, skb, queue)) {
1871 printk("%s: SB POOL full\n", __FUNCTION__);
1872 goto outfree;
1873 }
1874
1875 paddr = pci_map_single(card->pcidev, skb->data,
1876 skb->end - skb->data,
1877 PCI_DMA_FROMDEVICE);
1878 IDT77252_PRV_PADDR(skb) = paddr;
1879
1880 if (push_rx_skb(card, skb, queue)) {
1881 printk("%s: FB QUEUE full\n", __FUNCTION__);
1882 goto outunmap;
1883 }
1884 }
1885
1886 return;
1887
1888outunmap:
1889 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1890 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1891
1892 handle = IDT77252_PRV_POOL(skb);
1893 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL;
1894
1895outfree:
1896 dev_kfree_skb(skb);
1897}
1898
1899
1900static void
1901recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb)
1902{
1903 u32 handle = IDT77252_PRV_POOL(skb);
1904 int err;
1905
1906 err = push_rx_skb(card, skb, POOL_QUEUE(handle));
1907 if (err) {
1908 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1909 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1910 sb_pool_remove(card, skb);
1911 dev_kfree_skb(skb);
1912 }
1913}
1914
1915static void
1916flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp)
1917{
1918 rpp->len = 0;
1919 rpp->count = 0;
1920 rpp->first = NULL;
1921 rpp->last = &rpp->first;
1922}
1923
1924static void
1925recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp)
1926{
1927 struct sk_buff *skb, *next;
1928 int i;
1929
1930 skb = rpp->first;
1931 for (i = 0; i < rpp->count; i++) {
1932 next = skb->next;
1933 skb->next = NULL;
1934 recycle_rx_skb(card, skb);
1935 skb = next;
1936 }
1937 flush_rx_pool(card, rpp);
1938}
1939
1940
1941
1942
1943
1944
1945
1946static void
1947idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr)
1948{
1949 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value);
1950}
1951
1952static unsigned char
1953idt77252_phy_get(struct atm_dev *dev, unsigned long addr)
1954{
1955 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff));
1956}
1957
1958static int
1959idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam)
1960{
1961 struct atm_dev *dev = vcc->dev;
1962 struct idt77252_dev *card = dev->dev_data;
1963 struct vc_map *vc = vcc->dev_data;
1964 int err;
1965
1966 if (vc == NULL) {
1967 printk("%s: NULL connection in send().\n", card->name);
1968 atomic_inc(&vcc->stats->tx_err);
1969 dev_kfree_skb(skb);
1970 return -EINVAL;
1971 }
1972 if (!test_bit(VCF_TX, &vc->flags)) {
1973 printk("%s: Trying to transmit on a non-tx VC.\n", card->name);
1974 atomic_inc(&vcc->stats->tx_err);
1975 dev_kfree_skb(skb);
1976 return -EINVAL;
1977 }
1978
1979 switch (vcc->qos.aal) {
1980 case ATM_AAL0:
1981 case ATM_AAL1:
1982 case ATM_AAL5:
1983 break;
1984 default:
1985 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
1986 atomic_inc(&vcc->stats->tx_err);
1987 dev_kfree_skb(skb);
1988 return -EINVAL;
1989 }
1990
1991 if (skb_shinfo(skb)->nr_frags != 0) {
1992 printk("%s: No scatter-gather yet.\n", card->name);
1993 atomic_inc(&vcc->stats->tx_err);
1994 dev_kfree_skb(skb);
1995 return -EINVAL;
1996 }
1997 ATM_SKB(skb)->vcc = vcc;
1998
1999 err = queue_skb(card, vc, skb, oam);
2000 if (err) {
2001 atomic_inc(&vcc->stats->tx_err);
2002 dev_kfree_skb(skb);
2003 return err;
2004 }
2005
2006 return 0;
2007}
2008
2009int
2010idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb)
2011{
2012 return idt77252_send_skb(vcc, skb, 0);
2013}
2014
2015static int
2016idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags)
2017{
2018 struct atm_dev *dev = vcc->dev;
2019 struct idt77252_dev *card = dev->dev_data;
2020 struct sk_buff *skb;
2021
2022 skb = dev_alloc_skb(64);
2023 if (!skb) {
2024 printk("%s: Out of memory in send_oam().\n", card->name);
2025 atomic_inc(&vcc->stats->tx_err);
2026 return -ENOMEM;
2027 }
2028 atomic_add(skb->truesize, &vcc->sk->wmem_alloc);
2029
2030 memcpy(skb_put(skb, 52), cell, 52);
2031
2032 return idt77252_send_skb(vcc, skb, 1);
2033}
2034
2035static __inline__ unsigned int
2036idt77252_fls(unsigned int x)
2037{
2038 int r = 1;
2039
2040 if (x == 0)
2041 return 0;
2042 if (x & 0xffff0000) {
2043 x >>= 16;
2044 r += 16;
2045 }
2046 if (x & 0xff00) {
2047 x >>= 8;
2048 r += 8;
2049 }
2050 if (x & 0xf0) {
2051 x >>= 4;
2052 r += 4;
2053 }
2054 if (x & 0xc) {
2055 x >>= 2;
2056 r += 2;
2057 }
2058 if (x & 0x2)
2059 r += 1;
2060 return r;
2061}
2062
2063static u16
2064idt77252_int_to_atmfp(unsigned int rate)
2065{
2066 u16 m, e;
2067
2068 if (rate == 0)
2069 return 0;
2070 e = idt77252_fls(rate) - 1;
2071 if (e < 9)
2072 m = (rate - (1 << e)) << (9 - e);
2073 else if (e == 9)
2074 m = (rate - (1 << e));
2075 else
2076 m = (rate - (1 << e)) >> (e - 9);
2077 return 0x4000 | (e << 9) | m;
2078}
2079
2080static u8
2081idt77252_rate_logindex(struct idt77252_dev *card, int pcr)
2082{
2083 u16 afp;
2084
2085 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr);
2086 if (pcr < 0)
2087 return rate_to_log[(afp >> 5) & 0x1ff];
2088 return rate_to_log[((afp >> 5) + 1) & 0x1ff];
2089}
2090
2091static void
2092idt77252_est_timer(unsigned long data)
2093{
2094 struct vc_map *vc = (struct vc_map *)data;
2095 struct idt77252_dev *card = vc->card;
2096 struct rate_estimator *est;
2097 unsigned long flags;
2098 u32 rate, cps;
2099 u64 ncells;
2100 u8 lacr;
2101
2102 spin_lock_irqsave(&vc->lock, flags);
2103 est = vc->estimator;
2104 if (!est)
2105 goto out;
2106
2107 ncells = est->cells;
2108
2109 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval);
2110 est->last_cells = ncells;
2111 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log;
2112 est->cps = (est->avcps + 0x1f) >> 5;
2113
2114 cps = est->cps;
2115 if (cps < (est->maxcps >> 4))
2116 cps = est->maxcps >> 4;
2117
2118 lacr = idt77252_rate_logindex(card, cps);
2119 if (lacr > vc->max_er)
2120 lacr = vc->max_er;
2121
2122 if (lacr != vc->lacr) {
2123 vc->lacr = lacr;
2124 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ);
2125 }
2126
2127 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2128 add_timer(&est->timer);
2129
2130out:
2131 spin_unlock_irqrestore(&vc->lock, flags);
2132}
2133
2134static struct rate_estimator *
2135idt77252_init_est(struct vc_map *vc, int pcr)
2136{
2137 struct rate_estimator *est;
2138
2139 est = kmalloc(sizeof(struct rate_estimator), GFP_KERNEL);
2140 if (!est)
2141 return NULL;
2142 memset(est, 0, sizeof(*est));
2143
2144 est->maxcps = pcr < 0 ? -pcr : pcr;
2145 est->cps = est->maxcps;
2146 est->avcps = est->cps << 5;
2147
2148 est->interval = 2;
2149 est->ewma_log = 2;
2150 est->timer.data = (unsigned long)vc;
2151 est->timer.function = idt77252_est_timer;
2152 init_timer(&est->timer);
2153
2154 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2155 add_timer(&est->timer);
2156
2157 return est;
2158}
2159
2160static int
2161idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc,
2162 struct atm_vcc *vcc, struct atm_qos *qos)
2163{
2164 int tst_free, tst_used, tst_entries;
2165 unsigned long tmpl, modl;
2166 int tcr, tcra;
2167
2168 if ((qos->txtp.max_pcr == 0) &&
2169 (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) {
2170 printk("%s: trying to open a CBR VC with cell rate = 0\n",
2171 card->name);
2172 return -EINVAL;
2173 }
2174
2175 tst_used = 0;
2176 tst_free = card->tst_free;
2177 if (test_bit(VCF_TX, &vc->flags))
2178 tst_used = vc->ntste;
2179 tst_free += tst_used;
2180
2181 tcr = atm_pcr_goal(&qos->txtp);
2182 tcra = tcr >= 0 ? tcr : -tcr;
2183
2184 TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra);
2185
2186 tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2);
2187 modl = tmpl % (unsigned long)card->utopia_pcr;
2188
2189 tst_entries = (int) (tmpl / card->utopia_pcr);
2190 if (tcr > 0) {
2191 if (modl > 0)
2192 tst_entries++;
2193 } else if (tcr == 0) {
2194 tst_entries = tst_free - SAR_TST_RESERVED;
2195 if (tst_entries <= 0) {
2196 printk("%s: no CBR bandwidth free.\n", card->name);
2197 return -ENOSR;
2198 }
2199 }
2200
2201 if (tst_entries == 0) {
2202 printk("%s: selected CBR bandwidth < granularity.\n",
2203 card->name);
2204 return -EINVAL;
2205 }
2206
2207 if (tst_entries > (tst_free - SAR_TST_RESERVED)) {
2208 printk("%s: not enough CBR bandwidth free.\n", card->name);
2209 return -ENOSR;
2210 }
2211
2212 vc->ntste = tst_entries;
2213
2214 card->tst_free = tst_free - tst_entries;
2215 if (test_bit(VCF_TX, &vc->flags)) {
2216 if (tst_used == tst_entries)
2217 return 0;
2218
2219 OPRINTK("%s: modify %d -> %d entries in TST.\n",
2220 card->name, tst_used, tst_entries);
2221 change_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2222 return 0;
2223 }
2224
2225 OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries);
2226 fill_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2227 return 0;
2228}
2229
2230static int
2231idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc,
2232 struct atm_vcc *vcc, struct atm_qos *qos)
2233{
2234 unsigned long flags;
2235 int tcr;
2236
2237 spin_lock_irqsave(&vc->lock, flags);
2238 if (vc->estimator) {
2239 del_timer(&vc->estimator->timer);
2240 kfree(vc->estimator);
2241 vc->estimator = NULL;
2242 }
2243 spin_unlock_irqrestore(&vc->lock, flags);
2244
2245 tcr = atm_pcr_goal(&qos->txtp);
2246 if (tcr == 0)
2247 tcr = card->link_pcr;
2248
2249 vc->estimator = idt77252_init_est(vc, tcr);
2250
2251 vc->class = SCHED_UBR;
2252 vc->init_er = idt77252_rate_logindex(card, tcr);
2253 vc->lacr = vc->init_er;
2254 if (tcr < 0)
2255 vc->max_er = vc->init_er;
2256 else
2257 vc->max_er = 0xff;
2258
2259 return 0;
2260}
2261
2262static int
2263idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc,
2264 struct atm_vcc *vcc, struct atm_qos *qos)
2265{
2266 int error;
2267
2268 if (test_bit(VCF_TX, &vc->flags))
2269 return -EBUSY;
2270
2271 switch (qos->txtp.traffic_class) {
2272 case ATM_CBR:
2273 vc->class = SCHED_CBR;
2274 break;
2275
2276 case ATM_UBR:
2277 vc->class = SCHED_UBR;
2278 break;
2279
2280 case ATM_VBR:
2281 case ATM_ABR:
2282 default:
2283 return -EPROTONOSUPPORT;
2284 }
2285
2286 vc->scq = alloc_scq(card, vc->class);
2287 if (!vc->scq) {
2288 printk("%s: can't get SCQ.\n", card->name);
2289 return -ENOMEM;
2290 }
2291
2292 vc->scq->scd = get_free_scd(card, vc);
2293 if (vc->scq->scd == 0) {
2294 printk("%s: no SCD available.\n", card->name);
2295 free_scq(card, vc->scq);
2296 return -ENOMEM;
2297 }
2298
2299 fill_scd(card, vc->scq, vc->class);
2300
2301 if (set_tct(card, vc)) {
2302 printk("%s: class %d not supported.\n",
2303 card->name, qos->txtp.traffic_class);
2304
2305 card->scd2vc[vc->scd_index] = NULL;
2306 free_scq(card, vc->scq);
2307 return -EPROTONOSUPPORT;
2308 }
2309
2310 switch (vc->class) {
2311 case SCHED_CBR:
2312 error = idt77252_init_cbr(card, vc, vcc, qos);
2313 if (error) {
2314 card->scd2vc[vc->scd_index] = NULL;
2315 free_scq(card, vc->scq);
2316 return error;
2317 }
2318
2319 clear_bit(VCF_IDLE, &vc->flags);
2320 writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ);
2321 break;
2322
2323 case SCHED_UBR:
2324 error = idt77252_init_ubr(card, vc, vcc, qos);
2325 if (error) {
2326 card->scd2vc[vc->scd_index] = NULL;
2327 free_scq(card, vc->scq);
2328 return error;
2329 }
2330
2331 set_bit(VCF_IDLE, &vc->flags);
2332 break;
2333 }
2334
2335 vc->tx_vcc = vcc;
2336 set_bit(VCF_TX, &vc->flags);
2337 return 0;
2338}
2339
2340static int
2341idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc,
2342 struct atm_vcc *vcc, struct atm_qos *qos)
2343{
2344 unsigned long flags;
2345 unsigned long addr;
2346 u32 rcte = 0;
2347
2348 if (test_bit(VCF_RX, &vc->flags))
2349 return -EBUSY;
2350
2351 vc->rx_vcc = vcc;
2352 set_bit(VCF_RX, &vc->flags);
2353
2354 if ((vcc->vci == 3) || (vcc->vci == 4))
2355 return 0;
2356
2357 flush_rx_pool(card, &vc->rcv.rx_pool);
2358
2359 rcte |= SAR_RCTE_CONNECTOPEN;
2360 rcte |= SAR_RCTE_RAWCELLINTEN;
2361
2362 switch (qos->aal) {
2363 case ATM_AAL0:
2364 rcte |= SAR_RCTE_RCQ;
2365 break;
2366 case ATM_AAL1:
2367 rcte |= SAR_RCTE_OAM;
2368 break;
2369 case ATM_AAL34:
2370 rcte |= SAR_RCTE_AAL34;
2371 break;
2372 case ATM_AAL5:
2373 rcte |= SAR_RCTE_AAL5;
2374 break;
2375 default:
2376 rcte |= SAR_RCTE_RCQ;
2377 break;
2378 }
2379
2380 if (qos->aal != ATM_AAL5)
2381 rcte |= SAR_RCTE_FBP_1;
2382 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2)
2383 rcte |= SAR_RCTE_FBP_3;
2384 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1)
2385 rcte |= SAR_RCTE_FBP_2;
2386 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0)
2387 rcte |= SAR_RCTE_FBP_1;
2388 else
2389 rcte |= SAR_RCTE_FBP_01;
2390
2391 addr = card->rct_base + (vc->index << 2);
2392
2393 OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr);
2394 write_sram(card, addr, rcte);
2395
2396 spin_lock_irqsave(&card->cmd_lock, flags);
2397 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD);
2398 waitfor_idle(card);
2399 spin_unlock_irqrestore(&card->cmd_lock, flags);
2400
2401 return 0;
2402}
2403
2404static int
2405idt77252_find_vcc(struct atm_vcc *vcc, short *vpi, int *vci)
2406{
2407 unsigned long flags;
2408 struct atm_vcc *walk;
2409
2410 spin_lock_irqsave(&vcc->dev->lock, flags);
2411 if (*vpi == ATM_VPI_ANY) {
2412 *vpi = 0;
2413 walk = vcc->dev->vccs;
2414 while (walk) {
2415 if ((walk->vci == *vci) && (walk->vpi == *vpi)) {
2416 (*vpi)++;
2417 walk = vcc->dev->vccs;
2418 continue;
2419 }
2420 walk = walk->next;
2421 }
2422 }
2423
2424 if (*vci == ATM_VCI_ANY) {
2425 *vci = ATM_NOT_RSV_VCI;
2426 walk = vcc->dev->vccs;
2427 while (walk) {
2428 if ((walk->vci == *vci) && (walk->vpi == *vpi)) {
2429 (*vci)++;
2430 walk = vcc->dev->vccs;
2431 continue;
2432 }
2433 walk = walk->next;
2434 }
2435 }
2436
2437 spin_unlock_irqrestore(&vcc->dev->lock, flags);
2438 return 0;
2439}
2440
2441static int
2442idt77252_open(struct atm_vcc *vcc, short vpi, int vci)
2443{
2444 struct atm_dev *dev = vcc->dev;
2445 struct idt77252_dev *card = dev->dev_data;
2446 struct vc_map *vc;
2447 unsigned int index;
2448 unsigned int inuse;
2449 int error;
2450
2451 idt77252_find_vcc(vcc, &vpi, &vci);
2452
2453 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC)
2454 return 0;
2455
2456 if (vpi >= (1 << card->vpibits)) {
2457 printk("%s: unsupported VPI: %d\n", card->name, vpi);
2458 return -EINVAL;
2459 }
2460
2461 if (vci >= (1 << card->vcibits)) {
2462 printk("%s: unsupported VCI: %d\n", card->name, vci);
2463 return -EINVAL;
2464 }
2465
2466 vcc->vpi = vpi;
2467 vcc->vci = vci;
2468 set_bit(ATM_VF_ADDR, &vcc->flags);
2469
2470 down(&card->mutex);
2471
2472 OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci);
2473
2474 switch (vcc->qos.aal) {
2475 case ATM_AAL0:
2476 case ATM_AAL1:
2477 case ATM_AAL5:
2478 break;
2479 default:
2480 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
2481 up(&card->mutex);
2482 return -EPROTONOSUPPORT;
2483 }
2484
2485 index = VPCI2VC(card, vpi, vci);
2486 if (!card->vcs[index]) {
2487 card->vcs[index] = kmalloc(sizeof(struct vc_map), GFP_KERNEL);
2488 if (!card->vcs[index]) {
2489 printk("%s: can't alloc vc in open()\n", card->name);
2490 up(&card->mutex);
2491 return -ENOMEM;
2492 }
2493 memset(card->vcs[index], 0, sizeof(struct vc_map));
2494
2495 card->vcs[index]->card = card;
2496 card->vcs[index]->index = index;
2497
2498 spin_lock_init(&card->vcs[index]->lock);
2499 }
2500 vc = card->vcs[index];
2501
2502 vcc->dev_data = vc;
2503
2504 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n",
2505 card->name, vc->index, vcc->vpi, vcc->vci,
2506 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--",
2507 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--",
2508 vcc->qos.rxtp.max_sdu);
2509
2510 inuse = 0;
2511 if (vcc->qos.txtp.traffic_class != ATM_NONE &&
2512 test_bit(VCF_TX, &vc->flags))
2513 inuse = 1;
2514 if (vcc->qos.rxtp.traffic_class != ATM_NONE &&
2515 test_bit(VCF_RX, &vc->flags))
2516 inuse += 2;
2517
2518 if (inuse) {
2519 printk("%s: %s vci already in use.\n", card->name,
2520 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
2521 up(&card->mutex);
2522 return -EADDRINUSE;
2523 }
2524
2525 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2526 error = idt77252_init_tx(card, vc, vcc, &vcc->qos);
2527 if (error) {
2528 up(&card->mutex);
2529 return error;
2530 }
2531 }
2532
2533 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2534 error = idt77252_init_rx(card, vc, vcc, &vcc->qos);
2535 if (error) {
2536 up(&card->mutex);
2537 return error;
2538 }
2539 }
2540
2541 set_bit(ATM_VF_READY, &vcc->flags);
2542 MOD_INC_USE_COUNT;
2543
2544 up(&card->mutex);
2545 return 0;
2546}
2547
2548static void
2549idt77252_close(struct atm_vcc *vcc)
2550{
2551 struct atm_dev *dev = vcc->dev;
2552 struct idt77252_dev *card = dev->dev_data;
2553 struct vc_map *vc = vcc->dev_data;
2554 unsigned long flags;
2555 unsigned long addr;
2556 int timeout;
2557
2558 down(&card->mutex);
2559
2560 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n",
2561 card->name, vc->index, vcc->vpi, vcc->vci);
2562
2563 clear_bit(ATM_VF_READY, &vcc->flags);
2564
2565 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2566
2567 spin_lock_irqsave(&vc->lock, flags);
2568 clear_bit(VCF_RX, &vc->flags);
2569 vc->rx_vcc = NULL;
2570 spin_unlock_irqrestore(&vc->lock, flags);
2571
2572 if ((vcc->vci == 3) || (vcc->vci == 4))
2573 goto done;
2574
2575 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2576
2577 spin_lock_irqsave(&card->cmd_lock, flags);
2578 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD);
2579 waitfor_idle(card);
2580 spin_unlock_irqrestore(&card->cmd_lock, flags);
2581
2582 if (vc->rcv.rx_pool.count) {
2583 DPRINTK("%s: closing a VC with pending rx buffers.\n",
2584 card->name);
2585
2586 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2587 }
2588 }
2589
2590done:
2591 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2592
2593 spin_lock_irqsave(&vc->lock, flags);
2594 clear_bit(VCF_TX, &vc->flags);
2595 clear_bit(VCF_IDLE, &vc->flags);
2596 clear_bit(VCF_RSV, &vc->flags);
2597 vc->tx_vcc = NULL;
2598
2599 if (vc->estimator) {
2600 del_timer(&vc->estimator->timer);
2601 kfree(vc->estimator);
2602 vc->estimator = NULL;
2603 }
2604 spin_unlock_irqrestore(&vc->lock, flags);
2605
2606 timeout = 5 * HZ;
2607 while (atomic_read(&vc->scq->used) > 0) {
2608 timeout = schedule_timeout(timeout);
2609 if (!timeout)
2610 break;
2611 }
2612 if (!timeout)
2613 printk("%s: SCQ drain timeout: %u used\n",
2614 card->name, atomic_read(&vc->scq->used));
2615
2616 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ);
2617 clear_scd(card, vc->scq, vc->class);
2618
2619 if (vc->class == SCHED_CBR) {
2620 clear_tst(card, vc);
2621 card->tst_free += vc->ntste;
2622 vc->ntste = 0;
2623 }
2624
2625 card->scd2vc[vc->scd_index] = NULL;
2626 free_scq(card, vc->scq);
2627 }
2628
2629 MOD_DEC_USE_COUNT;
2630 up(&card->mutex);
2631}
2632
2633static int
2634idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
2635{
2636 struct atm_dev *dev = vcc->dev;
2637 struct idt77252_dev *card = dev->dev_data;
2638 struct vc_map *vc = vcc->dev_data;
2639 int error = 0;
2640
2641 down(&card->mutex);
2642
2643 if (qos->txtp.traffic_class != ATM_NONE) {
2644 if (!test_bit(VCF_TX, &vc->flags)) {
2645 error = idt77252_init_tx(card, vc, vcc, qos);
2646 if (error)
2647 goto out;
2648 } else {
2649 switch (qos->txtp.traffic_class) {
2650 case ATM_CBR:
2651 error = idt77252_init_cbr(card, vc, vcc, qos);
2652 if (error)
2653 goto out;
2654 break;
2655
2656 case ATM_UBR:
2657 error = idt77252_init_ubr(card, vc, vcc, qos);
2658 if (error)
2659 goto out;
2660
2661 if (!test_bit(VCF_IDLE, &vc->flags)) {
2662 writel(TCMDQ_LACR | (vc->lacr << 16) |
2663 vc->index, SAR_REG_TCMDQ);
2664 }
2665 break;
2666
2667 case ATM_VBR:
2668 case ATM_ABR:
2669 error = -EOPNOTSUPP;
2670 goto out;
2671 }
2672 }
2673 }
2674
2675 if ((qos->rxtp.traffic_class != ATM_NONE) &&
2676 !test_bit(VCF_RX, &vc->flags)) {
2677 error = idt77252_init_rx(card, vc, vcc, qos);
2678 if (error)
2679 goto out;
2680 }
2681
2682 memcpy(&vcc->qos, qos, sizeof(struct atm_qos));
2683
2684 set_bit(ATM_VF_HASQOS, &vcc->flags);
2685
2686out:
2687 up(&card->mutex);
2688 return error;
2689}
2690
2691static int
2692idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2693{
2694 struct idt77252_dev *card = dev->dev_data;
2695 int i, left;
2696
2697 left = (int) *pos;
2698 if (!left--)
2699 return sprintf(page, "IDT77252 Interrupts:\n");
2700 if (!left--)
2701 return sprintf(page, "TSIF: %lu\n", card->irqstat[15]);
2702 if (!left--)
2703 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]);
2704 if (!left--)
2705 return sprintf(page, "TSQF: %lu\n", card->irqstat[12]);
2706 if (!left--)
2707 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]);
2708 if (!left--)
2709 return sprintf(page, "PHYI: %lu\n", card->irqstat[10]);
2710 if (!left--)
2711 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]);
2712 if (!left--)
2713 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]);
2714 if (!left--)
2715 return sprintf(page, "RSQF: %lu\n", card->irqstat[6]);
2716 if (!left--)
2717 return sprintf(page, "EPDU: %lu\n", card->irqstat[5]);
2718 if (!left--)
2719 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]);
2720 if (!left--)
2721 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]);
2722 if (!left--)
2723 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]);
2724 if (!left--)
2725 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]);
2726 if (!left--)
2727 return sprintf(page, "IDT77252 Transmit Connection Table:\n");
2728
2729 for (i = 0; i < card->tct_size; i++) {
2730 unsigned long tct;
2731 struct atm_vcc *vcc;
2732 struct vc_map *vc;
2733 char *p;
2734
2735 vc = card->vcs[i];
2736 if (!vc)
2737 continue;
2738
2739 vcc = NULL;
2740 if (vc->tx_vcc)
2741 vcc = vc->tx_vcc;
2742 if (!vcc)
2743 continue;
2744 if (left--)
2745 continue;
2746
2747 p = page;
2748 p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci);
2749 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE);
2750
2751 for (i = 0; i < 8; i++)
2752 p += sprintf(p, " %08x", read_sram(card, tct + i));
2753 p += sprintf(p, "\n");
2754 return p - page;
2755 }
2756 return 0;
2757}
2758
2759
2760
2761
2762
2763
2764
2765static void
2766idt77252_collect_stat(struct idt77252_dev *card)
2767{
2768 u32 cdc, vpec, icc;
2769
2770 cdc = readl(SAR_REG_CDC);
2771 vpec = readl(SAR_REG_VPEC);
2772 icc = readl(SAR_REG_ICC);
2773
2774#ifdef NOTDEF
2775 printk("%s:", card->name);
2776
2777 if (cdc & 0x7f0000) {
2778 char *s = "";
2779
2780 printk(" [");
2781 if (cdc & (1 << 22)) {
2782 printk("%sRM ID", s);
2783 s = " | ";
2784 }
2785 if (cdc & (1 << 21)) {
2786 printk("%sCON TAB", s);
2787 s = " | ";
2788 }
2789 if (cdc & (1 << 20)) {
2790 printk("%sNO FB", s);
2791 s = " | ";
2792 }
2793 if (cdc & (1 << 19)) {
2794 printk("%sOAM CRC", s);
2795 s = " | ";
2796 }
2797 if (cdc & (1 << 18)) {
2798 printk("%sRM CRC", s);
2799 s = " | ";
2800 }
2801 if (cdc & (1 << 17)) {
2802 printk("%sRM FIFO", s);
2803 s = " | ";
2804 }
2805 if (cdc & (1 << 16)) {
2806 printk("%sRX FIFO", s);
2807 s = " | ";
2808 }
2809 printk("]");
2810 }
2811
2812 printk(" CDC %04x, VPEC %04x, ICC: %04x\n",
2813 cdc & 0xffff, vpec & 0xffff, icc & 0xffff);
2814#endif
2815}
2816
2817static void
2818idt77252_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
2819{
2820 struct idt77252_dev *card = dev_id;
2821 u32 stat;
2822
2823 stat = readl(SAR_REG_STAT) & 0xffff;
2824 if (!stat)
2825 return;
2826
2827 if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) {
2828 printk("%s: Re-entering irq_handler()\n", card->name);
2829 goto out;
2830 }
2831
2832 writel(stat, SAR_REG_STAT);
2833
2834 if (stat & SAR_STAT_TSIF) {
2835 INTPRINTK("%s: TSIF\n", card->name);
2836 card->irqstat[15]++;
2837 idt77252_tx(card);
2838 }
2839 if (stat & SAR_STAT_TXICP) {
2840 INTPRINTK("%s: TXICP\n", card->name);
2841 card->irqstat[14]++;
2842#ifdef CONFIG_ATM_IDT77252_DEBUG
2843 idt77252_tx_dump(card);
2844#endif
2845 }
2846 if (stat & SAR_STAT_TSQF) {
2847 INTPRINTK("%s: TSQF\n", card->name);
2848 card->irqstat[12]++;
2849 idt77252_tx(card);
2850 }
2851 if (stat & SAR_STAT_TMROF) {
2852 INTPRINTK("%s: TMROF\n", card->name);
2853 card->irqstat[11]++;
2854 idt77252_collect_stat(card);
2855 }
2856
2857 if (stat & SAR_STAT_EPDU) {
2858 INTPRINTK("%s: EPDU\n", card->name);
2859 card->irqstat[5]++;
2860 idt77252_rx(card);
2861 }
2862 if (stat & SAR_STAT_RSQAF) {
2863 INTPRINTK("%s: RSQAF\n", card->name);
2864 card->irqstat[1]++;
2865 idt77252_rx(card);
2866 }
2867 if (stat & SAR_STAT_RSQF) {
2868 INTPRINTK("%s: RSQF\n", card->name);
2869 card->irqstat[6]++;
2870 idt77252_rx(card);
2871 }
2872 if (stat & SAR_STAT_RAWCF) {
2873 INTPRINTK("%s: RAWCF\n", card->name);
2874 card->irqstat[4]++;
2875 idt77252_rx_raw(card);
2876 }
2877
2878 if (stat & SAR_STAT_PHYI) {
2879 INTPRINTK("%s: PHYI", card->name);
2880 card->irqstat[10]++;
2881 if (card->atmdev->phy && card->atmdev->phy->interrupt)
2882 card->atmdev->phy->interrupt(card->atmdev);
2883 }
2884
2885 if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A |
2886 SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) {
2887
2888 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG);
2889
2890 INTPRINTK("%s: FBQA: %04x\n", card->name, stat);
2891
2892 if (stat & SAR_STAT_FBQ0A)
2893 card->irqstat[2]++;
2894 if (stat & SAR_STAT_FBQ1A)
2895 card->irqstat[3]++;
2896 if (stat & SAR_STAT_FBQ2A)
2897 card->irqstat[7]++;
2898 if (stat & SAR_STAT_FBQ3A)
2899 card->irqstat[8]++;
2900
2901 queue_task(&card->tqueue, &tq_immediate);
2902 mark_bh(IMMEDIATE_BH);
2903 }
2904
2905out:
2906 clear_bit(IDT77252_BIT_INTERRUPT, &card->flags);
2907}
2908
2909static void
2910idt77252_softint(void *dev_id)
2911{
2912 struct idt77252_dev *card = dev_id;
2913 u32 stat;
2914 int done;
2915
2916 for (done = 1; ; done = 1) {
2917 stat = readl(SAR_REG_STAT) >> 16;
2918
2919 if ((stat & 0x0f) < SAR_FBQ0_HIGH) {
2920 add_rx_skb(card, 0, SAR_FB_SIZE_0, 32);
2921 done = 0;
2922 }
2923
2924 stat >>= 4;
2925 if ((stat & 0x0f) < SAR_FBQ1_HIGH) {
2926 add_rx_skb(card, 1, SAR_FB_SIZE_1, 32);
2927 done = 0;
2928 }
2929
2930 stat >>= 4;
2931 if ((stat & 0x0f) < SAR_FBQ2_HIGH) {
2932 add_rx_skb(card, 2, SAR_FB_SIZE_2, 32);
2933 done = 0;
2934 }
2935
2936 stat >>= 4;
2937 if ((stat & 0x0f) < SAR_FBQ3_HIGH) {
2938 add_rx_skb(card, 3, SAR_FB_SIZE_3, 32);
2939 done = 0;
2940 }
2941
2942 if (done)
2943 break;
2944 }
2945
2946 writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG);
2947}
2948
2949
2950static int
2951open_card_oam(struct idt77252_dev *card)
2952{
2953 unsigned long flags;
2954 unsigned long addr;
2955 struct vc_map *vc;
2956 int vpi, vci;
2957 int index;
2958 u32 rcte;
2959
2960 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2961 for (vci = 3; vci < 5; vci++) {
2962 index = VPCI2VC(card, vpi, vci);
2963
2964 vc = kmalloc(sizeof(struct vc_map), GFP_KERNEL);
2965 if (!vc) {
2966 printk("%s: can't alloc vc\n", card->name);
2967 return -ENOMEM;
2968 }
2969 memset(vc, 0, sizeof(struct vc_map));
2970
2971 vc->index = index;
2972 card->vcs[index] = vc;
2973
2974 flush_rx_pool(card, &vc->rcv.rx_pool);
2975
2976 rcte = SAR_RCTE_CONNECTOPEN |
2977 SAR_RCTE_RAWCELLINTEN |
2978 SAR_RCTE_RCQ |
2979 SAR_RCTE_FBP_1;
2980
2981 addr = card->rct_base + (vc->index << 2);
2982 write_sram(card, addr, rcte);
2983
2984 spin_lock_irqsave(&card->cmd_lock, flags);
2985 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2),
2986 SAR_REG_CMD);
2987 waitfor_idle(card);
2988 spin_unlock_irqrestore(&card->cmd_lock, flags);
2989 }
2990 }
2991
2992 return 0;
2993}
2994
2995static void
2996close_card_oam(struct idt77252_dev *card)
2997{
2998 unsigned long flags;
2999 unsigned long addr;
3000 struct vc_map *vc;
3001 int vpi, vci;
3002 int index;
3003
3004 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
3005 for (vci = 3; vci < 5; vci++) {
3006 index = VPCI2VC(card, vpi, vci);
3007 vc = card->vcs[index];
3008
3009 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
3010
3011 spin_lock_irqsave(&card->cmd_lock, flags);
3012 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2),
3013 SAR_REG_CMD);
3014 waitfor_idle(card);
3015 spin_unlock_irqrestore(&card->cmd_lock, flags);
3016
3017 if (vc->rcv.rx_pool.count) {
3018 DPRINTK("%s: closing a VC "
3019 "with pending rx buffers.\n",
3020 card->name);
3021
3022 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
3023 }
3024 }
3025 }
3026}
3027
3028static int
3029open_card_ubr0(struct idt77252_dev *card)
3030{
3031 struct vc_map *vc;
3032
3033 vc = kmalloc(sizeof(struct vc_map), GFP_KERNEL);
3034 if (!vc) {
3035 printk("%s: can't alloc vc\n", card->name);
3036 return -ENOMEM;
3037 }
3038 memset(vc, 0, sizeof(struct vc_map));
3039 card->vcs[0] = vc;
3040 vc->class = SCHED_UBR0;
3041
3042 vc->scq = alloc_scq(card, vc->class);
3043 if (!vc->scq) {
3044 printk("%s: can't get SCQ.\n", card->name);
3045 return -ENOMEM;
3046 }
3047
3048 card->scd2vc[0] = vc;
3049 vc->scd_index = 0;
3050 vc->scq->scd = card->scd_base;
3051
3052 fill_scd(card, vc->scq, vc->class);
3053
3054 write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base);
3055 write_sram(card, card->tct_base + 1, 0);
3056 write_sram(card, card->tct_base + 2, 0);
3057 write_sram(card, card->tct_base + 3, 0);
3058 write_sram(card, card->tct_base + 4, 0);
3059 write_sram(card, card->tct_base + 5, 0);
3060 write_sram(card, card->tct_base + 6, 0);
3061 write_sram(card, card->tct_base + 7, TCT_FLAG_UBR);
3062
3063 clear_bit(VCF_IDLE, &vc->flags);
3064 writel(TCMDQ_START | 0, SAR_REG_TCMDQ);
3065 return 0;
3066}
3067
3068static int
3069idt77252_dev_open(struct idt77252_dev *card)
3070{
3071 u32 conf;
3072
3073 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3074 printk("%s: SAR not yet initialized.\n", card->name);
3075 return -1;
3076 }
3077
3078 conf = SAR_CFG_RXPTH|
3079 SAR_RX_DELAY |
3080 SAR_CFG_RAWIE |
3081 SAR_CFG_RQFIE |
3082 SAR_CFG_TMOIE |
3083 SAR_CFG_FBIE |
3084 SAR_CFG_TXEN |
3085 SAR_CFG_TXINT |
3086 SAR_CFG_TXUIE |
3087 SAR_CFG_TXSFI |
3088 SAR_CFG_PHYIE
3089 ;
3090
3091#ifdef CONFIG_ATM_IDT77252_RCV_ALL
3092
3093 conf |= SAR_CFG_VPECA;
3094#endif
3095
3096 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3097
3098 if (open_card_oam(card)) {
3099 printk("%s: Error initializing OAM.\n", card->name);
3100 return -1;
3101 }
3102
3103 if (open_card_ubr0(card)) {
3104 printk("%s: Error initializing UBR0.\n", card->name);
3105 return -1;
3106 }
3107
3108 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name);
3109 return 0;
3110}
3111
3112void
3113idt77252_dev_close(struct atm_dev *dev)
3114{
3115 struct idt77252_dev *card = dev->dev_data;
3116 u32 conf;
3117
3118 close_card_oam(card);
3119
3120 conf = SAR_CFG_RXPTH |
3121 SAR_RX_DELAY |
3122 SAR_CFG_RAWIE |
3123 SAR_CFG_RQFIE |
3124 SAR_CFG_TMOIE |
3125 SAR_CFG_FBIE |
3126 SAR_CFG_TXEN |
3127 SAR_CFG_TXINT |
3128 SAR_CFG_TXUIE |
3129 SAR_CFG_TXSFI
3130 ;
3131
3132 writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG);
3133
3134 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name);
3135}
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145static void
3146deinit_card(struct idt77252_dev *card)
3147{
3148 struct sk_buff *skb;
3149 int i, j;
3150
3151 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3152 printk("%s: SAR not yet initialized.\n", card->name);
3153 return;
3154 }
3155 DIPRINTK("idt77252: deinitialize card %u\n", card->index);
3156
3157 writel(0, SAR_REG_CFG);
3158
3159 if (card->atmdev)
3160 atm_dev_deregister(card->atmdev);
3161
3162 for (i = 0; i < 4; i++) {
3163 for (j = 0; j < FBQ_SIZE; j++) {
3164 skb = card->sbpool[i].skb[j];
3165 if (skb) {
3166 pci_unmap_single(card->pcidev,
3167 IDT77252_PRV_PADDR(skb),
3168 skb->end - skb->data,
3169 PCI_DMA_FROMDEVICE);
3170 card->sbpool[i].skb[j] = NULL;
3171 dev_kfree_skb(skb);
3172 }
3173 }
3174 }
3175
3176 if (card->soft_tst)
3177 vfree(card->soft_tst);
3178
3179 if (card->scd2vc)
3180 vfree(card->scd2vc);
3181
3182 if (card->vcs)
3183 vfree(card->vcs);
3184
3185 if (card->raw_cell_hnd) {
3186 pci_free_consistent(card->pcidev, 2 * sizeof(u32),
3187 card->raw_cell_hnd, card->raw_cell_paddr);
3188 }
3189
3190 if (card->rsq.base) {
3191 DIPRINTK("%s: Release RSQ ...\n", card->name);
3192 deinit_rsq(card);
3193 }
3194
3195 if (card->tsq.base) {
3196 DIPRINTK("%s: Release TSQ ...\n", card->name);
3197 deinit_tsq(card);
3198 }
3199
3200 DIPRINTK("idt77252: Release IRQ.\n");
3201 free_irq(card->pcidev->irq, card);
3202
3203 for (i = 0; i < 4; i++) {
3204 if (card->fbq[i])
3205 iounmap((void *) card->fbq[i]);
3206 }
3207
3208 if (card->membase)
3209 iounmap((void *) card->membase);
3210
3211 clear_bit(IDT77252_BIT_INIT, &card->flags);
3212 DIPRINTK("%s: Card deinitialized.\n", card->name);
3213}
3214
3215
3216static int __devinit
3217init_sram(struct idt77252_dev *card)
3218{
3219 int i;
3220
3221 for (i = 0; i < card->sramsize; i += 4)
3222 write_sram(card, (i >> 2), 0);
3223
3224
3225 if (card->sramsize == (512 * 1024)) {
3226 card->tct_base = SAR_SRAM_TCT_128_BASE;
3227 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1)
3228 / SAR_SRAM_TCT_SIZE;
3229 card->rct_base = SAR_SRAM_RCT_128_BASE;
3230 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1)
3231 / SAR_SRAM_RCT_SIZE;
3232 card->rt_base = SAR_SRAM_RT_128_BASE;
3233 card->scd_base = SAR_SRAM_SCD_128_BASE;
3234 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1)
3235 / SAR_SRAM_SCD_SIZE;
3236 card->tst[0] = SAR_SRAM_TST1_128_BASE;
3237 card->tst[1] = SAR_SRAM_TST2_128_BASE;
3238 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1;
3239 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE;
3240 card->abrst_size = SAR_ABRSTD_SIZE_8K;
3241 card->fifo_base = SAR_SRAM_FIFO_128_BASE;
3242 card->fifo_size = SAR_RXFD_SIZE_32K;
3243 } else {
3244 card->tct_base = SAR_SRAM_TCT_32_BASE;
3245 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1)
3246 / SAR_SRAM_TCT_SIZE;
3247 card->rct_base = SAR_SRAM_RCT_32_BASE;
3248 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1)
3249 / SAR_SRAM_RCT_SIZE;
3250 card->rt_base = SAR_SRAM_RT_32_BASE;
3251 card->scd_base = SAR_SRAM_SCD_32_BASE;
3252 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1)
3253 / SAR_SRAM_SCD_SIZE;
3254 card->tst[0] = SAR_SRAM_TST1_32_BASE;
3255 card->tst[1] = SAR_SRAM_TST2_32_BASE;
3256 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1);
3257 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE;
3258 card->abrst_size = SAR_ABRSTD_SIZE_1K;
3259 card->fifo_base = SAR_SRAM_FIFO_32_BASE;
3260 card->fifo_size = SAR_RXFD_SIZE_4K;
3261 }
3262
3263
3264 for (i = 0; i < card->tct_size; i++) {
3265 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0);
3266 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0);
3267 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0);
3268 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0);
3269 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0);
3270 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0);
3271 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0);
3272 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0);
3273 }
3274
3275
3276 for (i = 0; i < card->rct_size; i++) {
3277 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE,
3278 (u32) SAR_RCTE_RAWCELLINTEN);
3279 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1,
3280 (u32) 0);
3281 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2,
3282 (u32) 0);
3283 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3,
3284 (u32) 0xffffffff);
3285 }
3286
3287 writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 |
3288 (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0);
3289 writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 |
3290 (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1);
3291 writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 |
3292 (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2);
3293 writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 |
3294 (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3);
3295
3296
3297 for (i = 0; i < 256; i++) {
3298 write_sram(card, card->rt_base + i, log_to_rate[i]);
3299 }
3300
3301 for (i = 0; i < 128; i++) {
3302 unsigned int tmp;
3303
3304 tmp = rate_to_log[(i << 2) + 0] << 0;
3305 tmp |= rate_to_log[(i << 2) + 1] << 8;
3306 tmp |= rate_to_log[(i << 2) + 2] << 16;
3307 tmp |= rate_to_log[(i << 2) + 3] << 24;
3308 write_sram(card, card->rt_base + 256 + i, tmp);
3309 }
3310
3311#if 0
3312 for (i = 0; i < 128; i++) {
3313 unsigned int tmp;
3314
3315 tmp = RDF[0][(i << 1) + 0] << 16;
3316 tmp |= RDF[0][(i << 1) + 1] << 0;
3317 write_sram(card, card->rt_base + 512 + i, tmp);
3318 }
3319
3320 for (i = 0; i < 128; i++) {
3321 unsigned int tmp;
3322
3323 tmp = AIR[0][(i << 1) + 0] << 16;
3324 tmp |= AIR[0][(i << 1) + 1] << 0;
3325 write_sram(card, card->rt_base + 640 + i, tmp);
3326 }
3327#endif
3328
3329 IPRINTK("%s: initialize rate table ...\n", card->name);
3330 writel(card->rt_base << 2, SAR_REG_RTBL);
3331
3332
3333 IPRINTK("%s: initialize TST ...\n", card->name);
3334 card->tst_free = card->tst_size - 2;
3335
3336 for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++)
3337 write_sram(card, i, TSTE_OPC_VAR);
3338 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3339 idt77252_sram_write_errors = 1;
3340 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3341 idt77252_sram_write_errors = 0;
3342 for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++)
3343 write_sram(card, i, TSTE_OPC_VAR);
3344 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3345 idt77252_sram_write_errors = 1;
3346 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3347 idt77252_sram_write_errors = 0;
3348
3349 card->tst_index = 0;
3350 writel(card->tst[0] << 2, SAR_REG_TSTB);
3351
3352
3353 IPRINTK("%s: initialize ABRSTD ...\n", card->name);
3354 writel(card->abrst_size | (card->abrst_base << 2),
3355 SAR_REG_ABRSTD);
3356
3357 IPRINTK("%s: initialize receive fifo ...\n", card->name);
3358 writel(card->fifo_size | (card->fifo_base << 2),
3359 SAR_REG_RXFD);
3360
3361 IPRINTK("%s: SRAM initialization complete.\n", card->name);
3362 return 0;
3363}
3364
3365static int __devinit
3366init_card(struct atm_dev *dev)
3367{
3368 struct idt77252_dev *card = dev->dev_data;
3369 struct pci_dev *pcidev = card->pcidev;
3370 unsigned long tmpl, modl;
3371 unsigned int linkrate, rsvdcr;
3372 unsigned int tst_entries;
3373 struct net_device *tmp;
3374 char tname[10];
3375
3376 u32 size;
3377 u_char pci_byte;
3378 u32 conf;
3379 int i, k;
3380
3381 if (test_bit(IDT77252_BIT_INIT, &card->flags)) {
3382 printk("Error: SAR already initialized.\n");
3383 return -1;
3384 }
3385
3386
3387
3388
3389
3390
3391 IPRINTK("%s: Checking PCI retries.\n", card->name);
3392 if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) {
3393 printk("%s: can't read PCI retry timeout.\n", card->name);
3394 deinit_card(card);
3395 return -1;
3396 }
3397 if (pci_byte != 0) {
3398 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n",
3399 card->name, pci_byte);
3400 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) {
3401 printk("%s: can't set PCI retry timeout.\n",
3402 card->name);
3403 deinit_card(card);
3404 return -1;
3405 }
3406 }
3407 IPRINTK("%s: Checking PCI TRDY.\n", card->name);
3408 if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) {
3409 printk("%s: can't read PCI TRDY timeout.\n", card->name);
3410 deinit_card(card);
3411 return -1;
3412 }
3413 if (pci_byte != 0) {
3414 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n",
3415 card->name, pci_byte);
3416 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) {
3417 printk("%s: can't set PCI TRDY timeout.\n", card->name);
3418 deinit_card(card);
3419 return -1;
3420 }
3421 }
3422
3423 if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) {
3424 printk("%s: resetting timer overflow.\n", card->name);
3425 writel(SAR_STAT_TMROF, SAR_REG_STAT);
3426 }
3427 IPRINTK("%s: Request IRQ ... ", card->name);
3428 if (request_irq(pcidev->irq, idt77252_interrupt, SA_INTERRUPT|SA_SHIRQ,
3429 card->name, card) != 0) {
3430 printk("%s: can't allocate IRQ.\n", card->name);
3431 deinit_card(card);
3432 return -1;
3433 }
3434 IPRINTK("got %d.\n", pcidev->irq);
3435
3436
3437
3438
3439
3440 IPRINTK("%s: Initializing SRAM\n", card->name);
3441
3442
3443 conf = SAR_CFG_TX_FIFO_SIZE_9 |
3444 SAR_CFG_RXSTQ_SIZE_8k |
3445 SAR_CFG_IDLE_CLP |
3446#ifndef CONFIG_ATM_IDT77252_SEND_IDLE
3447 SAR_CFG_NO_IDLE |
3448#endif
3449 0;
3450
3451 if (card->sramsize == (512 * 1024))
3452 conf |= SAR_CFG_CNTBL_1k;
3453 else
3454 conf |= SAR_CFG_CNTBL_512;
3455
3456 switch (vpibits) {
3457 case 0:
3458 conf |= SAR_CFG_VPVCS_0;
3459 break;
3460 default:
3461 case 1:
3462 conf |= SAR_CFG_VPVCS_1;
3463 break;
3464 case 2:
3465 conf |= SAR_CFG_VPVCS_2;
3466 break;
3467 case 8:
3468 conf |= SAR_CFG_VPVCS_8;
3469 break;
3470 }
3471
3472 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3473
3474 if (init_sram(card) < 0)
3475 return -1;
3476
3477
3478
3479
3480
3481 if (0 != init_tsq(card)) {
3482 deinit_card(card);
3483 return -1;
3484 }
3485
3486 if (0 != init_rsq(card)) {
3487 deinit_card(card);
3488 return -1;
3489 }
3490
3491 card->vpibits = vpibits;
3492 if (card->sramsize == (512 * 1024)) {
3493 card->vcibits = 10 - card->vpibits;
3494 } else {
3495 card->vcibits = 9 - card->vpibits;
3496 }
3497
3498 card->vcimask = 0;
3499 for (k = 0, i = 1; k < card->vcibits; k++) {
3500 card->vcimask |= i;
3501 i <<= 1;
3502 }
3503
3504 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name);
3505 writel(0, SAR_REG_VPM);
3506
3507
3508 writel(0, SAR_REG_GP);
3509
3510
3511 card->raw_cell_hnd = pci_alloc_consistent(card->pcidev, 2 * sizeof(u32),
3512 &card->raw_cell_paddr);
3513 if (!card->raw_cell_hnd) {
3514 printk("%s: memory allocation failure.\n", card->name);
3515 deinit_card(card);
3516 return -1;
3517 }
3518 memset(card->raw_cell_hnd, 0, 2 * sizeof(u32));
3519 writel(card->raw_cell_paddr, SAR_REG_RAWHND);
3520 IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name,
3521 card->raw_cell_hnd);
3522
3523 size = sizeof(struct vc_map *) * card->tct_size;
3524 IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size);
3525 if (NULL == (card->vcs = vmalloc(size))) {
3526 printk("%s: memory allocation failure.\n", card->name);
3527 deinit_card(card);
3528 return -1;
3529 }
3530 memset(card->vcs, 0, size);
3531
3532 size = sizeof(struct vc_map *) * card->scd_size;
3533 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n",
3534 card->name, size);
3535 if (NULL == (card->scd2vc = vmalloc(size))) {
3536 printk("%s: memory allocation failure.\n", card->name);
3537 deinit_card(card);
3538 return -1;
3539 }
3540 memset(card->scd2vc, 0, size);
3541
3542 size = sizeof(struct tst_info) * (card->tst_size - 2);
3543 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n",
3544 card->name, size);
3545 if (NULL == (card->soft_tst = vmalloc(size))) {
3546 printk("%s: memory allocation failure.\n", card->name);
3547 deinit_card(card);
3548 return -1;
3549 }
3550 for (i = 0; i < card->tst_size - 2; i++) {
3551 card->soft_tst[i].tste = TSTE_OPC_VAR;
3552 card->soft_tst[i].vc = NULL;
3553 }
3554
3555 if (dev->phy == NULL) {
3556 printk("%s: No LT device defined.\n", card->name);
3557 deinit_card(card);
3558 return -1;
3559 }
3560 if (dev->phy->ioctl == NULL) {
3561 printk("%s: LT had no IOCTL funtion defined.\n", card->name);
3562 deinit_card(card);
3563 return -1;
3564 }
3565
3566#ifdef CONFIG_ATM_IDT77252_USE_SUNI
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576 linkrate = 149760000;
3577#endif
3578
3579 card->link_pcr = (linkrate / 8 / 53);
3580 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n",
3581 card->name, linkrate, card->link_pcr);
3582
3583#ifdef CONFIG_ATM_IDT77252_SEND_IDLE
3584 card->utopia_pcr = card->link_pcr;
3585#else
3586 card->utopia_pcr = (160000000 / 8 / 54);
3587#endif
3588
3589 rsvdcr = 0;
3590 if (card->utopia_pcr > card->link_pcr)
3591 rsvdcr = card->utopia_pcr - card->link_pcr;
3592
3593 tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2);
3594 modl = tmpl % (unsigned long)card->utopia_pcr;
3595 tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr);
3596 if (modl)
3597 tst_entries++;
3598 card->tst_free -= tst_entries;
3599 fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL);
3600
3601#ifdef HAVE_EEPROM
3602 idt77252_eeprom_init(card);
3603 printk("%s: EEPROM: %02x:", card->name,
3604 idt77252_eeprom_read_status(card));
3605
3606 for (i = 0; i < 0x80; i++) {
3607 printk(" %02x",
3608 idt77252_eeprom_read_byte(card, i)
3609 );
3610 }
3611 printk("\n");
3612#endif
3613
3614
3615
3616
3617 sprintf(tname, "eth%d", card->index);
3618 tmp = dev_get_by_name(tname);
3619 if (tmp) {
3620 memcpy(card->atmdev->esi, tmp->dev_addr, 6);
3621
3622 printk("%s: ESI %02x:%02x:%02x:%02x:%02x:%02x\n",
3623 card->name, card->atmdev->esi[0], card->atmdev->esi[1],
3624 card->atmdev->esi[2], card->atmdev->esi[3],
3625 card->atmdev->esi[4], card->atmdev->esi[5]);
3626 }
3627
3628
3629
3630
3631
3632 writel(0xffff, SAR_REG_MDFCT);
3633
3634 set_bit(IDT77252_BIT_INIT, &card->flags);
3635
3636 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name);
3637 return 0;
3638}
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648static int __devinit
3649idt77252_preset(struct idt77252_dev *card)
3650{
3651 u16 pci_command;
3652
3653
3654
3655
3656
3657 XPRINTK("%s: Enable PCI master and memory access for SAR.\n",
3658 card->name);
3659 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) {
3660 printk("%s: can't read PCI_COMMAND.\n", card->name);
3661 deinit_card(card);
3662 return -1;
3663 }
3664 if (!(pci_command & PCI_COMMAND_IO)) {
3665 printk("%s: PCI_COMMAND: %04x (???)\n",
3666 card->name, pci_command);
3667 deinit_card(card);
3668 return (-1);
3669 }
3670 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
3671 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) {
3672 printk("%s: can't write PCI_COMMAND.\n", card->name);
3673 deinit_card(card);
3674 return -1;
3675 }
3676
3677
3678
3679
3680
3681 writel(SAR_CFG_SWRST, SAR_REG_CFG);
3682 mdelay(1);
3683 writel(0, SAR_REG_CFG);
3684
3685 IPRINTK("%s: Software resetted.\n", card->name);
3686 return 0;
3687}
3688
3689
3690static unsigned long __devinit
3691probe_sram(struct idt77252_dev *card)
3692{
3693 u32 data, addr;
3694
3695 writel(0, SAR_REG_DR0);
3696 writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD);
3697
3698 for (addr = 0x4000; addr < 0x80000; addr += 0x4000) {
3699 writel(0xdeadbeef, SAR_REG_DR0);
3700 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
3701
3702 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD);
3703 data = readl(SAR_REG_DR0);
3704
3705 if (data != 0)
3706 break;
3707 }
3708
3709 return addr * sizeof(u32);
3710}
3711
3712static int __devinit
3713idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id)
3714{
3715 static struct idt77252_dev **last = &idt77252_chain;
3716 static int index = 0;
3717
3718 unsigned long membase, srambase;
3719 struct idt77252_dev *card;
3720 struct atm_dev *dev;
3721 ushort revision = 0;
3722 int i;
3723
3724
3725 if (pci_read_config_word(pcidev, PCI_REVISION_ID, &revision)) {
3726 printk("idt77252-%d: can't read PCI_REVISION_ID\n", index);
3727 return -ENODEV;
3728 }
3729
3730 card = kmalloc(sizeof(struct idt77252_dev), GFP_KERNEL);
3731 if (!card) {
3732 printk("idt77252-%d: can't allocate private data\n", index);
3733 return -ENOMEM;
3734 }
3735 memset(card, 0, sizeof(struct idt77252_dev));
3736
3737 card->revision = revision;
3738 card->index = index;
3739 card->pcidev = pcidev;
3740 sprintf(card->name, "idt77252-%d", card->index);
3741
3742 card->tqueue.routine = idt77252_softint;
3743 card->tqueue.data = (void *)card;
3744
3745 membase = pci_resource_start(pcidev, 1);
3746 srambase = pci_resource_start(pcidev, 2);
3747
3748 init_MUTEX(&card->mutex);
3749 spin_lock_init(&card->cmd_lock);
3750 spin_lock_init(&card->tst_lock);
3751
3752 card->tst_timer.data = (unsigned long)card;
3753 card->tst_timer.function = tst_timer;
3754 init_timer(&card->tst_timer);
3755
3756
3757 card->membase = (unsigned long) ioremap(membase, 1024);
3758 if (!card->membase) {
3759 printk("%s: can't ioremap() membase\n", card->name);
3760 kfree(card);
3761 return -EIO;
3762 }
3763
3764 if (idt77252_preset(card)) {
3765 printk("%s: preset failed\n", card->name);
3766 iounmap((void *) card->membase);
3767 kfree(card);
3768 return -EIO;
3769 }
3770
3771 dev = atm_dev_register("idt77252", &idt77252_ops, -1, 0);
3772 if (!dev) {
3773 printk("%s: can't register atm device\n", card->name);
3774 iounmap((void *) card->membase);
3775 kfree(card);
3776 return -EIO;
3777 }
3778 dev->dev_data = card;
3779 card->atmdev = dev;
3780
3781#ifdef CONFIG_ATM_IDT77252_USE_SUNI
3782 suni_init(dev);
3783 if (!dev->phy) {
3784 printk("%s: can't init SUNI\n", card->name);
3785 deinit_card(card);
3786 kfree(card);
3787 return -EIO;
3788 }
3789#endif
3790
3791 card->sramsize = probe_sram(card);
3792
3793 for (i = 0; i < 4; i++) {
3794 card->fbq[i] = (unsigned long)
3795 ioremap(srambase | 0x200000 | (i << 18), 4);
3796 if (!card->fbq[i]) {
3797 printk("%s: can't ioremap() FBQ%d\n", card->name, i);
3798 deinit_card(card);
3799 kfree(card);
3800 return -EIO;
3801 }
3802 }
3803
3804 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n",
3805 card->name, ((revision > 1) && (revision < 25)) ?
3806 'A' + revision - 1 : '?', membase, srambase,
3807 card->sramsize / 1024);
3808
3809 if (init_card(dev)) {
3810 printk("%s: init_card failed\n", card->name);
3811 deinit_card(card);
3812 kfree(card);
3813 return -EIO;
3814 }
3815
3816 dev->ci_range.vpi_bits = card->vpibits;
3817 dev->ci_range.vci_bits = card->vcibits;
3818 dev->link_rate = card->link_pcr;
3819
3820 if (dev->phy->start)
3821 dev->phy->start(dev);
3822
3823 if (idt77252_dev_open(card)) {
3824 printk("%s: dev_open failed\n", card->name);
3825
3826 if (dev->phy->stop)
3827 dev->phy->stop(dev);
3828 deinit_card(card);
3829 kfree(card);
3830 return -EIO;
3831 }
3832
3833 *last = card;
3834 last = &card->next;
3835 index++;
3836
3837 return 0;
3838}
3839
3840static struct pci_device_id idt77252_pci_tbl[] __devinitdata =
3841{
3842 { PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_IDT_IDT77252,
3843 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
3844 { 0, }
3845};
3846
3847static struct pci_driver idt77252_driver = {
3848 name: "idt77252",
3849 id_table: idt77252_pci_tbl,
3850 probe: idt77252_init_one,
3851};
3852
3853static int __init idt77252_init(void)
3854{
3855 struct sk_buff *skb;
3856
3857 printk("%s: at %p\n", __FUNCTION__, idt77252_init);
3858
3859 if (sizeof(skb->cb) < sizeof(struct atm_skb_data) +
3860 sizeof(struct idt77252_skb_prv)) {
3861 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n",
3862 __FUNCTION__, (unsigned long) sizeof(skb->cb),
3863 (unsigned long) sizeof(struct atm_skb_data) +
3864 sizeof(struct idt77252_skb_prv));
3865 return -EIO;
3866 }
3867
3868 if (pci_register_driver(&idt77252_driver) > 0)
3869 return 0;
3870
3871 pci_unregister_driver(&idt77252_driver);
3872 return -ENODEV;
3873}
3874
3875static void __exit idt77252_exit(void)
3876{
3877 struct idt77252_dev *card;
3878 struct atm_dev *dev;
3879
3880 pci_unregister_driver(&idt77252_driver);
3881
3882 while (idt77252_chain) {
3883 card = idt77252_chain;
3884 dev = card->atmdev;
3885 idt77252_chain = card->next;
3886
3887 if (dev->phy->stop)
3888 dev->phy->stop(dev);
3889 deinit_card(card);
3890 kfree(card);
3891 }
3892
3893 DIPRINTK("idt77252: finished cleanup-module().\n");
3894}
3895
3896module_init(idt77252_init);
3897module_exit(idt77252_exit);
3898
3899EXPORT_NO_SYMBOLS;
3900MODULE_LICENSE("GPL");
3901
3902MODULE_PARM(vpibits, "i");
3903MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)");
3904#ifdef CONFIG_ATM_IDT77252_DEBUG
3905MODULE_PARM(debug, "i");
3906MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h");
3907#endif
3908
3909MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>");
3910MODULE_DESCRIPTION("IDT77252 ABR SAR Driver");
3911
