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7#include <linux/config.h>
8#include <linux/types.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/pci.h>
12#include <linux/init.h>
13#include <linux/ioport.h>
14
15#include <asm/segment.h>
16#include <asm/io.h>
17#include <asm/smp.h>
18#include <asm/smpboot.h>
19
20#include "pci-i386.h"
21
22unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2;
23
24int pcibios_last_bus = -1;
25struct pci_bus *pci_root_bus = NULL;
26struct pci_ops *pci_root_ops = NULL;
27
28int (*pci_config_read)(int seg, int bus, int dev, int fn, int reg, int len, u32 *value) = NULL;
29int (*pci_config_write)(int seg, int bus, int dev, int fn, int reg, int len, u32 value) = NULL;
30
31#ifdef CONFIG_MULTIQUAD
32#define BUS2QUAD(global) (mp_bus_id_to_node[global])
33#define BUS2LOCAL(global) (mp_bus_id_to_local[global])
34#define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])
35#else
36#define BUS2QUAD(global) (0)
37#define BUS2LOCAL(global) (global)
38#define QUADLOCAL2BUS(quad,local) (local)
39#endif
40
41
42
43
44
45static spinlock_t pci_config_lock = SPIN_LOCK_UNLOCKED;
46
47
48
49
50
51
52#ifdef CONFIG_PCI_DIRECT
53
54#ifdef CONFIG_MULTIQUAD
55#define PCI_CONF1_ADDRESS(bus, dev, fn, reg) \
56 (0x80000000 | (BUS2LOCAL(bus) << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
57
58static int pci_conf1_mq_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value)
59{
60 unsigned long flags;
61
62 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
63 return -EINVAL;
64
65 spin_lock_irqsave(&pci_config_lock, flags);
66
67 outl_quad(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8, BUS2QUAD(bus));
68
69 switch (len) {
70 case 1:
71 *value = inb_quad(0xCFC + (reg & 3), BUS2QUAD(bus));
72 break;
73 case 2:
74 *value = inw_quad(0xCFC + (reg & 2), BUS2QUAD(bus));
75 break;
76 case 4:
77 *value = inl_quad(0xCFC, BUS2QUAD(bus));
78 break;
79 }
80
81 spin_unlock_irqrestore(&pci_config_lock, flags);
82
83 return 0;
84}
85
86static int pci_conf1_mq_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value)
87{
88 unsigned long flags;
89
90 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
91 return -EINVAL;
92
93 spin_lock_irqsave(&pci_config_lock, flags);
94
95 outl_quad(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8, BUS2QUAD(bus));
96
97 switch (len) {
98 case 1:
99 outb_quad((u8)value, 0xCFC + (reg & 3), BUS2QUAD(bus));
100 break;
101 case 2:
102 outw_quad((u16)value, 0xCFC + (reg & 2), BUS2QUAD(bus));
103 break;
104 case 4:
105 outl_quad((u32)value, 0xCFC, BUS2QUAD(bus));
106 break;
107 }
108
109 spin_unlock_irqrestore(&pci_config_lock, flags);
110
111 return 0;
112}
113
114static int pci_conf1_read_mq_config_byte(struct pci_dev *dev, int where, u8 *value)
115{
116 int result;
117 u32 data;
118
119 result = pci_conf1_mq_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
120 PCI_FUNC(dev->devfn), where, 1, &data);
121
122 *value = (u8)data;
123
124 return result;
125}
126
127static int pci_conf1_read_mq_config_word(struct pci_dev *dev, int where, u16 *value)
128{
129 int result;
130 u32 data;
131
132 result = pci_conf1_mq_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
133 PCI_FUNC(dev->devfn), where, 2, &data);
134
135 *value = (u16)data;
136
137 return result;
138}
139
140static int pci_conf1_read_mq_config_dword(struct pci_dev *dev, int where, u32 *value)
141{
142 if (!value)
143 return -EINVAL;
144
145 return pci_conf1_mq_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
146 PCI_FUNC(dev->devfn), where, 4, value);
147}
148
149static int pci_conf1_write_mq_config_byte(struct pci_dev *dev, int where, u8 value)
150{
151 return pci_conf1_mq_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
152 PCI_FUNC(dev->devfn), where, 1, value);
153}
154
155static int pci_conf1_write_mq_config_word(struct pci_dev *dev, int where, u16 value)
156{
157 return pci_conf1_mq_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
158 PCI_FUNC(dev->devfn), where, 2, value);
159}
160
161static int pci_conf1_write_mq_config_dword(struct pci_dev *dev, int where, u32 value)
162{
163 return pci_conf1_mq_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
164 PCI_FUNC(dev->devfn), where, 4, value);
165}
166
167static struct pci_ops pci_direct_mq_conf1 = {
168 pci_conf1_read_mq_config_byte,
169 pci_conf1_read_mq_config_word,
170 pci_conf1_read_mq_config_dword,
171 pci_conf1_write_mq_config_byte,
172 pci_conf1_write_mq_config_word,
173 pci_conf1_write_mq_config_dword
174};
175
176#endif
177#define PCI_CONF1_ADDRESS(bus, dev, fn, reg) \
178 (0x80000000 | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
179
180static int pci_conf1_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value)
181{
182 unsigned long flags;
183
184 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
185 return -EINVAL;
186
187 spin_lock_irqsave(&pci_config_lock, flags);
188
189 outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8);
190
191 switch (len) {
192 case 1:
193 *value = inb(0xCFC + (reg & 3));
194 break;
195 case 2:
196 *value = inw(0xCFC + (reg & 2));
197 break;
198 case 4:
199 *value = inl(0xCFC);
200 break;
201 }
202
203 spin_unlock_irqrestore(&pci_config_lock, flags);
204
205 return 0;
206}
207
208static int pci_conf1_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value)
209{
210 unsigned long flags;
211
212 if ((bus > 255 || dev > 31 || fn > 7 || reg > 255))
213 return -EINVAL;
214
215 spin_lock_irqsave(&pci_config_lock, flags);
216
217 outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8);
218
219 switch (len) {
220 case 1:
221 outb((u8)value, 0xCFC + (reg & 3));
222 break;
223 case 2:
224 outw((u16)value, 0xCFC + (reg & 2));
225 break;
226 case 4:
227 outl((u32)value, 0xCFC);
228 break;
229 }
230
231 spin_unlock_irqrestore(&pci_config_lock, flags);
232
233 return 0;
234}
235
236#undef PCI_CONF1_ADDRESS
237
238static int pci_conf1_read_config_byte(struct pci_dev *dev, int where, u8 *value)
239{
240 int result;
241 u32 data;
242
243 result = pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
244 PCI_FUNC(dev->devfn), where, 1, &data);
245
246 *value = (u8)data;
247
248 return result;
249}
250
251static int pci_conf1_read_config_word(struct pci_dev *dev, int where, u16 *value)
252{
253 int result;
254 u32 data;
255
256 result = pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
257 PCI_FUNC(dev->devfn), where, 2, &data);
258
259 *value = (u16)data;
260
261 return result;
262}
263
264static int pci_conf1_read_config_dword(struct pci_dev *dev, int where, u32 *value)
265{
266 return pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
267 PCI_FUNC(dev->devfn), where, 4, value);
268}
269
270static int pci_conf1_write_config_byte(struct pci_dev *dev, int where, u8 value)
271{
272 return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
273 PCI_FUNC(dev->devfn), where, 1, value);
274}
275
276static int pci_conf1_write_config_word(struct pci_dev *dev, int where, u16 value)
277{
278 return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
279 PCI_FUNC(dev->devfn), where, 2, value);
280}
281
282static int pci_conf1_write_config_dword(struct pci_dev *dev, int where, u32 value)
283{
284 return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
285 PCI_FUNC(dev->devfn), where, 4, value);
286}
287
288static struct pci_ops pci_direct_conf1 = {
289 pci_conf1_read_config_byte,
290 pci_conf1_read_config_word,
291 pci_conf1_read_config_dword,
292 pci_conf1_write_config_byte,
293 pci_conf1_write_config_word,
294 pci_conf1_write_config_dword
295};
296
297
298
299
300
301
302#define PCI_CONF2_ADDRESS(dev, reg) (u16)(0xC000 | (dev << 8) | reg)
303
304static int pci_conf2_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value)
305{
306 unsigned long flags;
307
308 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
309 return -EINVAL;
310
311 if (dev & 0x10)
312 return PCIBIOS_DEVICE_NOT_FOUND;
313
314 spin_lock_irqsave(&pci_config_lock, flags);
315
316 outb((u8)(0xF0 | (fn << 1)), 0xCF8);
317 outb((u8)bus, 0xCFA);
318
319 switch (len) {
320 case 1:
321 *value = inb(PCI_CONF2_ADDRESS(dev, reg));
322 break;
323 case 2:
324 *value = inw(PCI_CONF2_ADDRESS(dev, reg));
325 break;
326 case 4:
327 *value = inl(PCI_CONF2_ADDRESS(dev, reg));
328 break;
329 }
330
331 outb (0, 0xCF8);
332
333 spin_unlock_irqrestore(&pci_config_lock, flags);
334
335 return 0;
336}
337
338static int pci_conf2_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value)
339{
340 unsigned long flags;
341
342 if ((bus > 255 || dev > 31 || fn > 7 || reg > 255))
343 return -EINVAL;
344
345 if (dev & 0x10)
346 return PCIBIOS_DEVICE_NOT_FOUND;
347
348 spin_lock_irqsave(&pci_config_lock, flags);
349
350 outb((u8)(0xF0 | (fn << 1)), 0xCF8);
351 outb((u8)bus, 0xCFA);
352
353 switch (len) {
354 case 1:
355 outb ((u8)value, PCI_CONF2_ADDRESS(dev, reg));
356 break;
357 case 2:
358 outw ((u16)value, PCI_CONF2_ADDRESS(dev, reg));
359 break;
360 case 4:
361 outl ((u32)value, PCI_CONF2_ADDRESS(dev, reg));
362 break;
363 }
364
365 outb (0, 0xCF8);
366
367 spin_unlock_irqrestore(&pci_config_lock, flags);
368
369 return 0;
370}
371
372#undef PCI_CONF2_ADDRESS
373
374static int pci_conf2_read_config_byte(struct pci_dev *dev, int where, u8 *value)
375{
376 int result;
377 u32 data;
378 result = pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
379 PCI_FUNC(dev->devfn), where, 1, &data);
380 *value = (u8)data;
381 return result;
382}
383
384static int pci_conf2_read_config_word(struct pci_dev *dev, int where, u16 *value)
385{
386 int result;
387 u32 data;
388 result = pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
389 PCI_FUNC(dev->devfn), where, 2, &data);
390 *value = (u16)data;
391 return result;
392}
393
394static int pci_conf2_read_config_dword(struct pci_dev *dev, int where, u32 *value)
395{
396 return pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
397 PCI_FUNC(dev->devfn), where, 4, value);
398}
399
400static int pci_conf2_write_config_byte(struct pci_dev *dev, int where, u8 value)
401{
402 return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
403 PCI_FUNC(dev->devfn), where, 1, value);
404}
405
406static int pci_conf2_write_config_word(struct pci_dev *dev, int where, u16 value)
407{
408 return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
409 PCI_FUNC(dev->devfn), where, 2, value);
410}
411
412static int pci_conf2_write_config_dword(struct pci_dev *dev, int where, u32 value)
413{
414 return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
415 PCI_FUNC(dev->devfn), where, 4, value);
416}
417
418static struct pci_ops pci_direct_conf2 = {
419 pci_conf2_read_config_byte,
420 pci_conf2_read_config_word,
421 pci_conf2_read_config_dword,
422 pci_conf2_write_config_byte,
423 pci_conf2_write_config_word,
424 pci_conf2_write_config_dword
425};
426
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435
436
437
438static int __devinit pci_sanity_check(struct pci_ops *o)
439{
440 u16 x;
441 struct pci_bus bus;
442 struct pci_dev dev;
443
444 if (pci_probe & PCI_NO_CHECKS)
445 return 1;
446 bus.number = 0;
447 dev.bus = &bus;
448 for(dev.devfn=0; dev.devfn < 0x100; dev.devfn++)
449 if ((!o->read_word(&dev, PCI_CLASS_DEVICE, &x) &&
450 (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)) ||
451 (!o->read_word(&dev, PCI_VENDOR_ID, &x) &&
452 (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)))
453 return 1;
454 DBG("PCI: Sanity check failed\n");
455 return 0;
456}
457
458static struct pci_ops * __devinit pci_check_direct(void)
459{
460 unsigned int tmp;
461 unsigned long flags;
462
463 __save_flags(flags); __cli();
464
465
466
467
468 if (pci_probe & PCI_PROBE_CONF1) {
469 outb (0x01, 0xCFB);
470 tmp = inl (0xCF8);
471 outl (0x80000000, 0xCF8);
472 if (inl (0xCF8) == 0x80000000 &&
473 pci_sanity_check(&pci_direct_conf1)) {
474 outl (tmp, 0xCF8);
475 __restore_flags(flags);
476 printk(KERN_INFO "PCI: Using configuration type 1\n");
477 request_region(0xCF8, 8, "PCI conf1");
478
479#ifdef CONFIG_MULTIQUAD
480
481 if(clustered_apic_mode == CLUSTERED_APIC_NUMAQ)
482 return &pci_direct_mq_conf1;
483#endif
484 return &pci_direct_conf1;
485 }
486 outl (tmp, 0xCF8);
487 }
488
489
490
491
492 if (pci_probe & PCI_PROBE_CONF2) {
493 outb (0x00, 0xCFB);
494 outb (0x00, 0xCF8);
495 outb (0x00, 0xCFA);
496 if (inb (0xCF8) == 0x00 && inb (0xCFA) == 0x00 &&
497 pci_sanity_check(&pci_direct_conf2)) {
498 __restore_flags(flags);
499 printk(KERN_INFO "PCI: Using configuration type 2\n");
500 request_region(0xCF8, 4, "PCI conf2");
501 return &pci_direct_conf2;
502 }
503 }
504
505 __restore_flags(flags);
506 return NULL;
507}
508
509#endif
510
511
512
513
514
515#ifdef CONFIG_PCI_BIOS
516
517#define PCIBIOS_PCI_FUNCTION_ID 0xb1XX
518#define PCIBIOS_PCI_BIOS_PRESENT 0xb101
519#define PCIBIOS_FIND_PCI_DEVICE 0xb102
520#define PCIBIOS_FIND_PCI_CLASS_CODE 0xb103
521#define PCIBIOS_GENERATE_SPECIAL_CYCLE 0xb106
522#define PCIBIOS_READ_CONFIG_BYTE 0xb108
523#define PCIBIOS_READ_CONFIG_WORD 0xb109
524#define PCIBIOS_READ_CONFIG_DWORD 0xb10a
525#define PCIBIOS_WRITE_CONFIG_BYTE 0xb10b
526#define PCIBIOS_WRITE_CONFIG_WORD 0xb10c
527#define PCIBIOS_WRITE_CONFIG_DWORD 0xb10d
528#define PCIBIOS_GET_ROUTING_OPTIONS 0xb10e
529#define PCIBIOS_SET_PCI_HW_INT 0xb10f
530
531
532#define BIOS32_SIGNATURE (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24))
533
534
535#define PCI_SIGNATURE (('P' << 0) + ('C' << 8) + ('I' << 16) + (' ' << 24))
536
537
538#define PCI_SERVICE (('$' << 0) + ('P' << 8) + ('C' << 16) + ('I' << 24))
539
540
541#define PCIBIOS_HW_TYPE1 0x01
542#define PCIBIOS_HW_TYPE2 0x02
543#define PCIBIOS_HW_TYPE1_SPEC 0x10
544#define PCIBIOS_HW_TYPE2_SPEC 0x20
545
546
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548
549
550
551
552
553
554
555
556union bios32 {
557 struct {
558 unsigned long signature;
559 unsigned long entry;
560 unsigned char revision;
561 unsigned char length;
562 unsigned char checksum;
563 unsigned char reserved[5];
564 } fields;
565 char chars[16];
566};
567
568
569
570
571
572
573
574
575static struct {
576 unsigned long address;
577 unsigned short segment;
578} bios32_indirect = { 0, __KERNEL_CS };
579
580
581
582
583
584static unsigned long bios32_service(unsigned long service)
585{
586 unsigned char return_code;
587 unsigned long address;
588 unsigned long length;
589 unsigned long entry;
590 unsigned long flags;
591
592 __save_flags(flags); __cli();
593 __asm__("lcall (%%edi); cld"
594 : "=a" (return_code),
595 "=b" (address),
596 "=c" (length),
597 "=d" (entry)
598 : "0" (service),
599 "1" (0),
600 "D" (&bios32_indirect));
601 __restore_flags(flags);
602
603 switch (return_code) {
604 case 0:
605 return address + entry;
606 case 0x80:
607 printk(KERN_WARNING "bios32_service(0x%lx): not present\n", service);
608 return 0;
609 default:
610 printk(KERN_WARNING "bios32_service(0x%lx): returned 0x%x -- BIOS bug!\n",
611 service, return_code);
612 return 0;
613 }
614}
615
616static struct {
617 unsigned long address;
618 unsigned short segment;
619} pci_indirect = { 0, __KERNEL_CS };
620
621static int pci_bios_present;
622
623static int __devinit check_pcibios(void)
624{
625 u32 signature, eax, ebx, ecx;
626 u8 status, major_ver, minor_ver, hw_mech;
627 unsigned long flags, pcibios_entry;
628
629 if ((pcibios_entry = bios32_service(PCI_SERVICE))) {
630 pci_indirect.address = pcibios_entry + PAGE_OFFSET;
631
632 __save_flags(flags); __cli();
633 __asm__(
634 "lcall (%%edi); cld\n\t"
635 "jc 1f\n\t"
636 "xor %%ah, %%ah\n"
637 "1:"
638 : "=d" (signature),
639 "=a" (eax),
640 "=b" (ebx),
641 "=c" (ecx)
642 : "1" (PCIBIOS_PCI_BIOS_PRESENT),
643 "D" (&pci_indirect)
644 : "memory");
645 __restore_flags(flags);
646
647 status = (eax >> 8) & 0xff;
648 hw_mech = eax & 0xff;
649 major_ver = (ebx >> 8) & 0xff;
650 minor_ver = ebx & 0xff;
651 if (pcibios_last_bus < 0)
652 pcibios_last_bus = ecx & 0xff;
653 DBG("PCI: BIOS probe returned s=%02x hw=%02x ver=%02x.%02x l=%02x\n",
654 status, hw_mech, major_ver, minor_ver, pcibios_last_bus);
655 if (status || signature != PCI_SIGNATURE) {
656 printk (KERN_ERR "PCI: BIOS BUG #%x[%08x] found\n",
657 status, signature);
658 return 0;
659 }
660 printk(KERN_INFO "PCI: PCI BIOS revision %x.%02x entry at 0x%lx, last bus=%d\n",
661 major_ver, minor_ver, pcibios_entry, pcibios_last_bus);
662#ifdef CONFIG_PCI_DIRECT
663 if (!(hw_mech & PCIBIOS_HW_TYPE1))
664 pci_probe &= ~PCI_PROBE_CONF1;
665 if (!(hw_mech & PCIBIOS_HW_TYPE2))
666 pci_probe &= ~PCI_PROBE_CONF2;
667#endif
668 return 1;
669 }
670 return 0;
671}
672
673static int __devinit pci_bios_find_device (unsigned short vendor, unsigned short device_id,
674 unsigned short index, unsigned char *bus, unsigned char *device_fn)
675{
676 unsigned short bx;
677 unsigned short ret;
678
679 __asm__("lcall (%%edi); cld\n\t"
680 "jc 1f\n\t"
681 "xor %%ah, %%ah\n"
682 "1:"
683 : "=b" (bx),
684 "=a" (ret)
685 : "1" (PCIBIOS_FIND_PCI_DEVICE),
686 "c" (device_id),
687 "d" (vendor),
688 "S" ((int) index),
689 "D" (&pci_indirect));
690 *bus = (bx >> 8) & 0xff;
691 *device_fn = bx & 0xff;
692 return (int) (ret & 0xff00) >> 8;
693}
694
695static int pci_bios_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value)
696{
697 unsigned long result = 0;
698 unsigned long flags;
699 unsigned long bx = ((bus << 8) | (dev << 3) | fn);
700
701 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
702 return -EINVAL;
703
704 spin_lock_irqsave(&pci_config_lock, flags);
705
706 switch (len) {
707 case 1:
708 __asm__("lcall (%%esi); cld\n\t"
709 "jc 1f\n\t"
710 "xor %%ah, %%ah\n"
711 "1:"
712 : "=c" (*value),
713 "=a" (result)
714 : "1" (PCIBIOS_READ_CONFIG_BYTE),
715 "b" (bx),
716 "D" ((long)reg),
717 "S" (&pci_indirect));
718 break;
719 case 2:
720 __asm__("lcall (%%esi); cld\n\t"
721 "jc 1f\n\t"
722 "xor %%ah, %%ah\n"
723 "1:"
724 : "=c" (*value),
725 "=a" (result)
726 : "1" (PCIBIOS_READ_CONFIG_WORD),
727 "b" (bx),
728 "D" ((long)reg),
729 "S" (&pci_indirect));
730 break;
731 case 4:
732 __asm__("lcall (%%esi); cld\n\t"
733 "jc 1f\n\t"
734 "xor %%ah, %%ah\n"
735 "1:"
736 : "=c" (*value),
737 "=a" (result)
738 : "1" (PCIBIOS_READ_CONFIG_DWORD),
739 "b" (bx),
740 "D" ((long)reg),
741 "S" (&pci_indirect));
742 break;
743 }
744
745 spin_unlock_irqrestore(&pci_config_lock, flags);
746
747 return (int)((result & 0xff00) >> 8);
748}
749
750static int pci_bios_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value)
751{
752 unsigned long result = 0;
753 unsigned long flags;
754 unsigned long bx = ((bus << 8) | (dev << 3) | fn);
755
756 if ((bus > 255 || dev > 31 || fn > 7 || reg > 255))
757 return -EINVAL;
758
759 spin_lock_irqsave(&pci_config_lock, flags);
760
761 switch (len) {
762 case 1:
763 __asm__("lcall (%%esi); cld\n\t"
764 "jc 1f\n\t"
765 "xor %%ah, %%ah\n"
766 "1:"
767 : "=a" (result)
768 : "0" (PCIBIOS_WRITE_CONFIG_BYTE),
769 "c" (value),
770 "b" (bx),
771 "D" ((long)reg),
772 "S" (&pci_indirect));
773 break;
774 case 2:
775 __asm__("lcall (%%esi); cld\n\t"
776 "jc 1f\n\t"
777 "xor %%ah, %%ah\n"
778 "1:"
779 : "=a" (result)
780 : "0" (PCIBIOS_WRITE_CONFIG_WORD),
781 "c" (value),
782 "b" (bx),
783 "D" ((long)reg),
784 "S" (&pci_indirect));
785 break;
786 case 4:
787 __asm__("lcall (%%esi); cld\n\t"
788 "jc 1f\n\t"
789 "xor %%ah, %%ah\n"
790 "1:"
791 : "=a" (result)
792 : "0" (PCIBIOS_WRITE_CONFIG_DWORD),
793 "c" (value),
794 "b" (bx),
795 "D" ((long)reg),
796 "S" (&pci_indirect));
797 break;
798 }
799
800 spin_unlock_irqrestore(&pci_config_lock, flags);
801
802 return (int)((result & 0xff00) >> 8);
803}
804
805static int pci_bios_read_config_byte(struct pci_dev *dev, int where, u8 *value)
806{
807 int result;
808 u32 data;
809
810 if (!value)
811 BUG();
812
813 result = pci_bios_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
814 PCI_FUNC(dev->devfn), where, 1, &data);
815
816 *value = (u8)data;
817
818 return result;
819}
820
821static int pci_bios_read_config_word(struct pci_dev *dev, int where, u16 *value)
822{
823 int result;
824 u32 data;
825
826 if (!value)
827 BUG();
828
829 result = pci_bios_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
830 PCI_FUNC(dev->devfn), where, 2, &data);
831
832 *value = (u16)data;
833
834 return result;
835}
836
837static int pci_bios_read_config_dword(struct pci_dev *dev, int where, u32 *value)
838{
839 if (!value)
840 BUG();
841
842 return pci_bios_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
843 PCI_FUNC(dev->devfn), where, 4, value);
844}
845
846static int pci_bios_write_config_byte(struct pci_dev *dev, int where, u8 value)
847{
848 return pci_bios_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
849 PCI_FUNC(dev->devfn), where, 1, value);
850}
851
852static int pci_bios_write_config_word(struct pci_dev *dev, int where, u16 value)
853{
854 return pci_bios_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
855 PCI_FUNC(dev->devfn), where, 2, value);
856}
857
858static int pci_bios_write_config_dword(struct pci_dev *dev, int where, u32 value)
859{
860 return pci_bios_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
861 PCI_FUNC(dev->devfn), where, 4, value);
862}
863
864
865
866
867
868
869static struct pci_ops pci_bios_access = {
870 pci_bios_read_config_byte,
871 pci_bios_read_config_word,
872 pci_bios_read_config_dword,
873 pci_bios_write_config_byte,
874 pci_bios_write_config_word,
875 pci_bios_write_config_dword
876};
877
878
879
880
881
882static struct pci_ops * __devinit pci_find_bios(void)
883{
884 union bios32 *check;
885 unsigned char sum;
886 int i, length;
887
888
889
890
891
892
893
894 for (check = (union bios32 *) __va(0xe0000);
895 check <= (union bios32 *) __va(0xffff0);
896 ++check) {
897 if (check->fields.signature != BIOS32_SIGNATURE)
898 continue;
899 length = check->fields.length * 16;
900 if (!length)
901 continue;
902 sum = 0;
903 for (i = 0; i < length ; ++i)
904 sum += check->chars[i];
905 if (sum != 0)
906 continue;
907 if (check->fields.revision != 0) {
908 printk("PCI: unsupported BIOS32 revision %d at 0x%p\n",
909 check->fields.revision, check);
910 continue;
911 }
912 DBG("PCI: BIOS32 Service Directory structure at 0x%p\n", check);
913 if (check->fields.entry >= 0x100000) {
914 printk("PCI: BIOS32 entry (0x%p) in high memory, cannot use.\n", check);
915 return NULL;
916 } else {
917 unsigned long bios32_entry = check->fields.entry;
918 DBG("PCI: BIOS32 Service Directory entry at 0x%lx\n", bios32_entry);
919 bios32_indirect.address = bios32_entry + PAGE_OFFSET;
920 if (check_pcibios())
921 return &pci_bios_access;
922 }
923 break;
924 }
925
926 return NULL;
927}
928
929
930
931
932
933
934
935
936static void __devinit pcibios_sort(void)
937{
938 LIST_HEAD(sorted_devices);
939 struct list_head *ln;
940 struct pci_dev *dev, *d;
941 int idx, found;
942 unsigned char bus, devfn;
943
944 DBG("PCI: Sorting device list...\n");
945 while (!list_empty(&pci_devices)) {
946 ln = pci_devices.next;
947 dev = pci_dev_g(ln);
948 idx = found = 0;
949 while (pci_bios_find_device(dev->vendor, dev->device, idx, &bus, &devfn) == PCIBIOS_SUCCESSFUL) {
950 idx++;
951 for (ln=pci_devices.next; ln != &pci_devices; ln=ln->next) {
952 d = pci_dev_g(ln);
953 if (d->bus->number == bus && d->devfn == devfn) {
954 list_del(&d->global_list);
955 list_add_tail(&d->global_list, &sorted_devices);
956 if (d == dev)
957 found = 1;
958 break;
959 }
960 }
961 if (ln == &pci_devices) {
962 printk(KERN_WARNING "PCI: BIOS reporting unknown device %02x:%02x\n", bus, devfn);
963
964
965
966
967 break;
968 }
969 }
970 if (!found) {
971 printk(KERN_WARNING "PCI: Device %02x:%02x not found by BIOS\n",
972 dev->bus->number, dev->devfn);
973 list_del(&dev->global_list);
974 list_add_tail(&dev->global_list, &sorted_devices);
975 }
976 }
977 list_splice(&sorted_devices, &pci_devices);
978}
979
980
981
982
983
984struct irq_routing_options {
985 u16 size;
986 struct irq_info *table;
987 u16 segment;
988} __attribute__((packed));
989
990struct irq_routing_table * __devinit pcibios_get_irq_routing_table(void)
991{
992 struct irq_routing_options opt;
993 struct irq_routing_table *rt = NULL;
994 int ret, map;
995 unsigned long page;
996
997 if (!pci_bios_present)
998 return NULL;
999 page = __get_free_page(GFP_KERNEL);
1000 if (!page)
1001 return NULL;
1002 opt.table = (struct irq_info *) page;
1003 opt.size = PAGE_SIZE;
1004 opt.segment = __KERNEL_DS;
1005
1006 DBG("PCI: Fetching IRQ routing table... ");
1007 __asm__("push %%es\n\t"
1008 "push %%ds\n\t"
1009 "pop %%es\n\t"
1010 "lcall (%%esi); cld\n\t"
1011 "pop %%es\n\t"
1012 "jc 1f\n\t"
1013 "xor %%ah, %%ah\n"
1014 "1:"
1015 : "=a" (ret),
1016 "=b" (map)
1017 : "0" (PCIBIOS_GET_ROUTING_OPTIONS),
1018 "1" (0),
1019 "D" ((long) &opt),
1020 "S" (&pci_indirect));
1021 DBG("OK ret=%d, size=%d, map=%x\n", ret, opt.size, map);
1022 if (ret & 0xff00)
1023 printk(KERN_ERR "PCI: Error %02x when fetching IRQ routing table.\n", (ret >> 8) & 0xff);
1024 else if (opt.size) {
1025 rt = kmalloc(sizeof(struct irq_routing_table) + opt.size, GFP_KERNEL);
1026 if (rt) {
1027 memset(rt, 0, sizeof(struct irq_routing_table));
1028 rt->size = opt.size + sizeof(struct irq_routing_table);
1029 rt->exclusive_irqs = map;
1030 memcpy(rt->slots, (void *) page, opt.size);
1031 printk(KERN_INFO "PCI: Using BIOS Interrupt Routing Table\n");
1032 }
1033 }
1034 free_page(page);
1035 return rt;
1036}
1037
1038
1039int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq)
1040{
1041 int ret;
1042
1043 __asm__("lcall (%%esi); cld\n\t"
1044 "jc 1f\n\t"
1045 "xor %%ah, %%ah\n"
1046 "1:"
1047 : "=a" (ret)
1048 : "0" (PCIBIOS_SET_PCI_HW_INT),
1049 "b" ((dev->bus->number << 8) | dev->devfn),
1050 "c" ((irq << 8) | (pin + 10)),
1051 "S" (&pci_indirect));
1052 return !(ret & 0xff00);
1053}
1054
1055#endif
1056
1057
1058
1059
1060
1061
1062
1063
1064static void __devinit pcibios_fixup_ghosts(struct pci_bus *b)
1065{
1066 struct list_head *ln, *mn;
1067 struct pci_dev *d, *e;
1068 int mirror = PCI_DEVFN(16,0);
1069 int seen_host_bridge = 0;
1070 int i;
1071
1072 DBG("PCI: Scanning for ghost devices on bus %d\n", b->number);
1073 for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
1074 d = pci_dev_b(ln);
1075 if ((d->class >> 8) == PCI_CLASS_BRIDGE_HOST)
1076 seen_host_bridge++;
1077 for (mn=ln->next; mn != &b->devices; mn=mn->next) {
1078 e = pci_dev_b(mn);
1079 if (e->devfn != d->devfn + mirror ||
1080 e->vendor != d->vendor ||
1081 e->device != d->device ||
1082 e->class != d->class)
1083 continue;
1084 for(i=0; i<PCI_NUM_RESOURCES; i++)
1085 if (e->resource[i].start != d->resource[i].start ||
1086 e->resource[i].end != d->resource[i].end ||
1087 e->resource[i].flags != d->resource[i].flags)
1088 continue;
1089 break;
1090 }
1091 if (mn == &b->devices)
1092 return;
1093 }
1094 if (!seen_host_bridge)
1095 return;
1096 printk(KERN_WARNING "PCI: Ignoring ghost devices on bus %02x\n", b->number);
1097
1098 ln = &b->devices;
1099 while (ln->next != &b->devices) {
1100 d = pci_dev_b(ln->next);
1101 if (d->devfn >= mirror) {
1102 list_del(&d->global_list);
1103 list_del(&d->bus_list);
1104 kfree(d);
1105 } else
1106 ln = ln->next;
1107 }
1108}
1109
1110
1111
1112
1113
1114static void __devinit pcibios_fixup_peer_bridges(void)
1115{
1116 int n;
1117 struct pci_bus bus;
1118 struct pci_dev dev;
1119 u16 l;
1120
1121 if (pcibios_last_bus <= 0 || pcibios_last_bus >= 0xff)
1122 return;
1123 DBG("PCI: Peer bridge fixup\n");
1124 for (n=0; n <= pcibios_last_bus; n++) {
1125 if (pci_bus_exists(&pci_root_buses, n))
1126 continue;
1127 bus.number = n;
1128 bus.ops = pci_root_ops;
1129 dev.bus = &bus;
1130 for(dev.devfn=0; dev.devfn<256; dev.devfn += 8)
1131 if (!pci_read_config_word(&dev, PCI_VENDOR_ID, &l) &&
1132 l != 0x0000 && l != 0xffff) {
1133 DBG("Found device at %02x:%02x [%04x]\n", n, dev.devfn, l);
1134 printk(KERN_INFO "PCI: Discovered peer bus %02x\n", n);
1135 pci_scan_bus(n, pci_root_ops, NULL);
1136 break;
1137 }
1138 }
1139}
1140
1141
1142
1143
1144
1145static void __devinit pci_fixup_i450nx(struct pci_dev *d)
1146{
1147
1148
1149
1150 int pxb, reg;
1151 u8 busno, suba, subb;
1152#ifdef CONFIG_MULTIQUAD
1153 int quad = BUS2QUAD(d->bus->number);
1154#endif
1155 printk("PCI: Searching for i450NX host bridges on %s\n", d->slot_name);
1156 reg = 0xd0;
1157 for(pxb=0; pxb<2; pxb++) {
1158 pci_read_config_byte(d, reg++, &busno);
1159 pci_read_config_byte(d, reg++, &suba);
1160 pci_read_config_byte(d, reg++, &subb);
1161 DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
1162 if (busno)
1163 pci_scan_bus(QUADLOCAL2BUS(quad,busno), pci_root_ops, NULL);
1164 if (suba < subb)
1165 pci_scan_bus(QUADLOCAL2BUS(quad,suba+1), pci_root_ops, NULL);
1166 }
1167 pcibios_last_bus = -1;
1168}
1169
1170static void __devinit pci_fixup_i450gx(struct pci_dev *d)
1171{
1172
1173
1174
1175
1176 u8 busno;
1177 pci_read_config_byte(d, 0x4a, &busno);
1178 printk(KERN_INFO "PCI: i440KX/GX host bridge %s: secondary bus %02x\n", d->slot_name, busno);
1179 pci_scan_bus(busno, pci_root_ops, NULL);
1180 pcibios_last_bus = -1;
1181}
1182
1183static void __devinit pci_fixup_umc_ide(struct pci_dev *d)
1184{
1185
1186
1187
1188
1189 int i;
1190
1191 printk(KERN_WARNING "PCI: Fixing base address flags for device %s\n", d->slot_name);
1192 for(i=0; i<4; i++)
1193 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
1194}
1195
1196static void __devinit pci_fixup_ncr53c810(struct pci_dev *d)
1197{
1198
1199
1200
1201
1202 if (!d->class) {
1203 printk("PCI: fixing NCR 53C810 class code for %s\n", d->slot_name);
1204 d->class = PCI_CLASS_STORAGE_SCSI << 8;
1205 }
1206}
1207
1208static void __devinit pci_fixup_ide_bases(struct pci_dev *d)
1209{
1210 int i;
1211
1212
1213
1214
1215 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
1216 return;
1217 DBG("PCI: IDE base address fixup for %s\n", d->slot_name);
1218 for(i=0; i<4; i++) {
1219 struct resource *r = &d->resource[i];
1220 if ((r->start & ~0x80) == 0x374) {
1221 r->start |= 2;
1222 r->end = r->start;
1223 }
1224 }
1225}
1226
1227static void __devinit pci_fixup_ide_trash(struct pci_dev *d)
1228{
1229 int i;
1230
1231
1232
1233
1234
1235 DBG("PCI: IDE base address trash cleared for %s\n", d->slot_name);
1236 for(i=0; i<4; i++)
1237 d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
1238}
1239
1240static void __devinit pci_fixup_latency(struct pci_dev *d)
1241{
1242
1243
1244
1245
1246 DBG("PCI: Setting max latency to 32\n");
1247 pcibios_max_latency = 32;
1248}
1249
1250static void __devinit pci_fixup_piix4_acpi(struct pci_dev *d)
1251{
1252
1253
1254
1255 d->irq = 9;
1256}
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275#define VIA_8363_KL133_REVISION_ID 0x81
1276#define VIA_8363_KM133_REVISION_ID 0x84
1277
1278static void __init pci_fixup_via_northbridge_bug(struct pci_dev *d)
1279{
1280 u8 v;
1281 u8 revision;
1282 int where = 0x55;
1283 int mask = 0x1f;
1284
1285 pci_read_config_byte(d, PCI_REVISION_ID, &revision);
1286
1287 if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
1288
1289
1290
1291 pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
1292
1293 where = 0x95;
1294
1295 } else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
1296 (revision == VIA_8363_KL133_REVISION_ID ||
1297 revision == VIA_8363_KM133_REVISION_ID)) {
1298 mask = 0x3f;
1299
1300 }
1301
1302 pci_read_config_byte(d, where, &v);
1303 if (v & ~mask) {
1304 printk("Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
1305 d->device, revision, where, v, mask, v & mask);
1306 v &= mask;
1307 pci_write_config_byte(d, where, v);
1308 }
1309}
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320static void __init pci_fixup_transparent_bridge(struct pci_dev *dev)
1321{
1322 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
1323 (dev->device & 0xff00) == 0x2400)
1324 dev->transparent = 1;
1325}
1326
1327struct pci_fixup pcibios_fixups[] = {
1328 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx },
1329 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx },
1330 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide },
1331 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash },
1332 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases },
1333 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency },
1334 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency },
1335 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi },
1336 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug },
1337 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug },
1338 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug },
1339 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug },
1340 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810 },
1341 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge },
1342 { 0 }
1343};
1344
1345
1346
1347
1348
1349
1350void __devinit pcibios_fixup_bus(struct pci_bus *b)
1351{
1352 pcibios_fixup_ghosts(b);
1353 pci_read_bridge_bases(b);
1354}
1355
1356
1357void __devinit pcibios_config_init(void)
1358{
1359
1360
1361
1362
1363
1364#ifdef CONFIG_PCI_DIRECT
1365 struct pci_ops *tmp = NULL;
1366#endif
1367
1368
1369#ifdef CONFIG_PCI_BIOS
1370 if ((pci_probe & PCI_PROBE_BIOS)
1371 && ((pci_root_ops = pci_find_bios()))) {
1372 pci_probe |= PCI_BIOS_SORT;
1373 pci_bios_present = 1;
1374 pci_config_read = pci_bios_read;
1375 pci_config_write = pci_bios_write;
1376 }
1377#endif
1378
1379#ifdef CONFIG_PCI_DIRECT
1380 if ((pci_probe & (PCI_PROBE_CONF1 | PCI_PROBE_CONF2))
1381 && (tmp = pci_check_direct())) {
1382 pci_root_ops = tmp;
1383 if (pci_root_ops == &pci_direct_conf1) {
1384 pci_config_read = pci_conf1_read;
1385 pci_config_write = pci_conf1_write;
1386 }
1387 else {
1388 pci_config_read = pci_conf2_read;
1389 pci_config_write = pci_conf2_write;
1390 }
1391 }
1392#endif
1393
1394 return;
1395}
1396
1397void __init pcibios_init(void)
1398{
1399 int quad;
1400
1401 if (!pci_root_ops)
1402 pcibios_config_init();
1403 if (!pci_root_ops) {
1404 printk(KERN_WARNING "PCI: System does not support PCI\n");
1405 return;
1406 }
1407
1408 printk(KERN_INFO "PCI: Probing PCI hardware\n");
1409 pci_root_bus = pci_scan_bus(0, pci_root_ops, NULL);
1410 if (clustered_apic_mode && (numnodes > 1)) {
1411 for (quad = 1; quad < numnodes; ++quad) {
1412 printk("Scanning PCI bus %d for quad %d\n",
1413 QUADLOCAL2BUS(quad,0), quad);
1414 pci_scan_bus(QUADLOCAL2BUS(quad,0),
1415 pci_root_ops, NULL);
1416 }
1417 }
1418
1419 pcibios_irq_init();
1420 pcibios_fixup_peer_bridges();
1421 pcibios_fixup_irqs();
1422 pcibios_resource_survey();
1423
1424#ifdef CONFIG_PCI_BIOS
1425 if ((pci_probe & PCI_BIOS_SORT) && !(pci_probe & PCI_NO_SORT))
1426 pcibios_sort();
1427#endif
1428}
1429
1430char * __devinit pcibios_setup(char *str)
1431{
1432 if (!strcmp(str, "off")) {
1433 pci_probe = 0;
1434 return NULL;
1435 }
1436#ifdef CONFIG_PCI_BIOS
1437 else if (!strcmp(str, "bios")) {
1438 pci_probe = PCI_PROBE_BIOS;
1439 return NULL;
1440 } else if (!strcmp(str, "nobios")) {
1441 pci_probe &= ~PCI_PROBE_BIOS;
1442 return NULL;
1443 } else if (!strcmp(str, "nosort")) {
1444 pci_probe |= PCI_NO_SORT;
1445 return NULL;
1446 } else if (!strcmp(str, "biosirq")) {
1447 pci_probe |= PCI_BIOS_IRQ_SCAN;
1448 return NULL;
1449 }
1450#endif
1451#ifdef CONFIG_PCI_DIRECT
1452 else if (!strcmp(str, "conf1")) {
1453 pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
1454 return NULL;
1455 }
1456 else if (!strcmp(str, "conf2")) {
1457 pci_probe = PCI_PROBE_CONF2 | PCI_NO_CHECKS;
1458 return NULL;
1459 }
1460#endif
1461 else if (!strcmp(str, "rom")) {
1462 pci_probe |= PCI_ASSIGN_ROMS;
1463 return NULL;
1464 } else if (!strcmp(str, "assign-busses")) {
1465 pci_probe |= PCI_ASSIGN_ALL_BUSSES;
1466 return NULL;
1467 } else if (!strncmp(str, "irqmask=", 8)) {
1468 pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
1469 return NULL;
1470 } else if (!strncmp(str, "lastbus=", 8)) {
1471 pcibios_last_bus = simple_strtol(str+8, NULL, 0);
1472 return NULL;
1473 }
1474 return str;
1475}
1476
1477unsigned int pcibios_assign_all_busses(void)
1478{
1479 return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
1480}
1481
1482int pcibios_enable_device(struct pci_dev *dev, int mask)
1483{
1484 int err;
1485
1486 if ((err = pcibios_enable_resources(dev, mask)) < 0)
1487 return err;
1488 pcibios_enable_irq(dev);
1489 return 0;
1490}
1491
