LXR linux-old/include/asm-ppc/system.h

   1/*
   2 * BK Id: SCCS/s.system.h 1.14 08/20/01 14:34:41 paulus
   3 */
   4/*
   5 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
   6 */
   7#ifndef __PPC_SYSTEM_H
   8#define __PPC_SYSTEM_H
   9
  10#include <linux/config.h>
  11#include <linux/kdev_t.h>
  12
  13#include <asm/processor.h>
  14#include <asm/atomic.h>
  15#include <asm/hw_irq.h>
  16
  17/*
  18 * Memory barrier.
  19 * The sync instruction guarantees that all memory accesses initiated
  20 * by this processor have been performed (with respect to all other
  21 * mechanisms that access memory).  The eieio instruction is a barrier
  22 * providing an ordering (separately) for (a) cacheable stores and (b)
  23 * loads and stores to non-cacheable memory (e.g. I/O devices).
  24 *
  25 * mb() prevents loads and stores being reordered across this point.
  26 * rmb() prevents loads being reordered across this point.
  27 * wmb() prevents stores being reordered across this point.
  28 *
  29 * We can use the eieio instruction for wmb, but since it doesn't
  30 * give any ordering guarantees about loads, we have to use the
  31 * stronger but slower sync instruction for mb and rmb.
  32 */
  33#define mb()  __asm__ __volatile__ ("sync" : : : "memory")
  34#define rmb()  __asm__ __volatile__ ("sync" : : : "memory")
  35#define wmb()  __asm__ __volatile__ ("eieio" : : : "memory")
  36
  37#define set_mb(var, value)      do { var = value; mb(); } while (0)
  38#define set_wmb(var, value)     do { var = value; wmb(); } while (0)
  39
  40#ifdef CONFIG_SMP
  41#define smp_mb()        mb()
  42#define smp_rmb()       rmb()
  43#define smp_wmb()       wmb()
  44#else
  45#define smp_mb()        __asm__ __volatile__("": : :"memory")
  46#define smp_rmb()       __asm__ __volatile__("": : :"memory")
  47#define smp_wmb()       __asm__ __volatile__("": : :"memory")
  48#endif /* CONFIG_SMP */
  49
  50#ifdef __KERNEL__
  51extern void xmon_irq(int, void *, struct pt_regs *);
  52extern void xmon(struct pt_regs *excp);
  53extern void print_backtrace(unsigned long *);
  54extern void show_regs(struct pt_regs * regs);
  55extern void flush_instruction_cache(void);
  56extern void hard_reset_now(void);
  57extern void poweroff_now(void);
  58#ifdef CONFIG_6xx
  59extern long _get_L2CR(void);
  60extern void _set_L2CR(unsigned long);
  61#else
  62#define _get_L2CR()     0
  63#define _set_L2CR(val)  do { } while(0)
  64#endif
  65extern void via_cuda_init(void);
  66extern void pmac_nvram_init(void);
  67extern void read_rtc_time(void);
  68extern void pmac_find_display(void);
  69extern void giveup_fpu(struct task_struct *);
  70extern void enable_kernel_fp(void);
  71extern void giveup_altivec(struct task_struct *);
  72extern void load_up_altivec(struct task_struct *);
  73extern void cvt_fd(float *from, double *to, unsigned long *fpscr);
  74extern void cvt_df(double *from, float *to, unsigned long *fpscr);
  75extern int call_rtas(const char *, int, int, unsigned long *, ...);
  76extern int abs(int);
  77extern void cacheable_memzero(void *p, unsigned int nb);
  78
  79struct device_node;
  80extern void note_scsi_host(struct device_node *, void *);
  81
  82struct task_struct;
  83#define prepare_to_switch()     do { } while(0)
  84#define switch_to(prev,next,last) _switch_to((prev),(next),&(last))
  85extern void _switch_to(struct task_struct *, struct task_struct *,
  86                       struct task_struct **);
  87
  88struct thread_struct;
  89extern struct task_struct *_switch(struct thread_struct *prev,
  90                                   struct thread_struct *next);
  91
  92extern unsigned int rtas_data;
  93
  94struct pt_regs;
  95extern void dump_regs(struct pt_regs *);
  96
  97#ifndef CONFIG_SMP
  98
  99#define cli()   __cli()
 100#define sti()   __sti()
 101#define save_flags(flags)       __save_flags(flags)
 102#define restore_flags(flags)    __restore_flags(flags)
 103#define save_and_cli(flags)     __save_and_cli(flags)
 104
 105#else /* CONFIG_SMP */
 106
 107extern void __global_cli(void);
 108extern void __global_sti(void);
 109extern unsigned long __global_save_flags(void);
 110extern void __global_restore_flags(unsigned long);
 111#define cli() __global_cli()
 112#define sti() __global_sti()
 113#define save_flags(x) ((x)=__global_save_flags())
 114#define restore_flags(x) __global_restore_flags(x)
 115
 116#endif /* !CONFIG_SMP */
 117
 118#define local_irq_disable()             __cli()
 119#define local_irq_enable()              __sti()
 120#define local_irq_save(flags)           __save_and_cli(flags)
 121#define local_irq_restore(flags)        __restore_flags(flags)
 122
 123#endif /* __KERNEL__ */
 124
 125#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 126
 127static __inline__ unsigned long
 128xchg_u32(volatile void *p, unsigned long val)
 129{
 130        unsigned long prev;
 131
 132        __asm__ __volatile__ ("\n\
 1331:      lwarx   %0,0,%2 \n\
 134        stwcx.  %3,0,%2 \n\
 135        bne-    1b"
 136        : "=&r" (prev), "=m" (*(volatile unsigned long *)p)
 137        : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p)
 138        : "cc", "memory");
 139
 140        return prev;
 141}
 142
 143/*
 144 * This function doesn't exist, so you'll get a linker error
 145 * if something tries to do an invalid xchg().
 146 */
 147extern void __xchg_called_with_bad_pointer(void);
 148
 149#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 150#define tas(ptr) (xchg((ptr),1))
 151
 152static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
 153{
 154        switch (size) {
 155        case 4:
 156                return (unsigned long )xchg_u32(ptr, x);
 157#if 0   /* xchg_u64 doesn't exist on 32-bit PPC */
 158        case 8:
 159                return (unsigned long )xchg_u64(ptr, x);
 160#endif /* 0 */
 161        }
 162        __xchg_called_with_bad_pointer();
 163        return x;
 164
 165
 166}
 167
 168extern inline void * xchg_ptr(void * m, void * val)
 169{
 170        return (void *) xchg_u32(m, (unsigned long) val);
 171}
 172
 173
 174#define __HAVE_ARCH_CMPXCHG     1
 175
 176static __inline__ unsigned long
 177__cmpxchg_u32(volatile int *p, int old, int new)
 178{
 179        int prev;
 180
 181        __asm__ __volatile__ ("\n\
 1821:      lwarx   %0,0,%2 \n\
 183        cmpw    0,%0,%3 \n\
 184        bne     2f \n\
 185        stwcx.  %4,0,%2 \n\
 186        bne-    1b\n"
 187#ifdef CONFIG_SMP
 188"       sync\n"
 189#endif /* CONFIG_SMP */
 190"2:"
 191        : "=&r" (prev), "=m" (*p)
 192        : "r" (p), "r" (old), "r" (new), "m" (*p)
 193        : "cc", "memory");
 194
 195        return prev;
 196}
 197
 198/* This function doesn't exist, so you'll get a linker error
 199   if something tries to do an invalid cmpxchg().  */
 200extern void __cmpxchg_called_with_bad_pointer(void);
 201
 202static __inline__ unsigned long
 203__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 204{
 205        switch (size) {
 206        case 4:
 207                return __cmpxchg_u32(ptr, old, new);
 208#if 0   /* we don't have __cmpxchg_u64 on 32-bit PPC */
 209        case 8:
 210                return __cmpxchg_u64(ptr, old, new);
 211#endif /* 0 */
 212        }
 213        __cmpxchg_called_with_bad_pointer();
 214        return old;
 215}
 216
 217#define cmpxchg(ptr,o,n)                                                 \
 218  ({                                                                     \
 219     __typeof__(*(ptr)) _o_ = (o);                                       \
 220     __typeof__(*(ptr)) _n_ = (n);                                       \
 221     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
 222                                    (unsigned long)_n_, sizeof(*(ptr))); \
 223  })
 224
 225#endif /* __PPC_SYSTEM_H */
 226