LXR linux-old/include/asm-ppc/processor.h

   1/*
   2 * BK Id: SCCS/s.processor.h 1.33 12/01/01 20:09:11 benh
   3 */
   4#ifdef __KERNEL__
   5#ifndef __ASM_PPC_PROCESSOR_H
   6#define __ASM_PPC_PROCESSOR_H
   7
   8/*
   9 * Default implementation of macro that returns current
  10 * instruction pointer ("program counter").
  11 */
  12#define current_text_addr() ({ __label__ _l; _l: &&_l;})
  13
  14#include <linux/config.h>
  15
  16#include <asm/ptrace.h>
  17#include <asm/types.h>
  18#include <asm/mpc8xx.h>
  19
  20/* Machine State Register (MSR) Fields */
  21
  22#ifdef CONFIG_PPC64BRIDGE
  23#define MSR_SF          (1<<63)
  24#define MSR_ISF         (1<<61)
  25#endif /* CONFIG_PPC64BRIDGE */
  26#define MSR_VEC         (1<<25)         /* Enable AltiVec */
  27#define MSR_POW         (1<<18)         /* Enable Power Management */
  28#define MSR_WE          (1<<18)         /* Wait State Enable */
  29#define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
  30#define MSR_CE          (1<<17)         /* Critical Interrupt Enable */
  31#define MSR_ILE         (1<<16)         /* Interrupt Little Endian */
  32#define MSR_EE          (1<<15)         /* External Interrupt Enable */
  33#define MSR_PR          (1<<14)         /* Problem State / Privilege Level */
  34#define MSR_FP          (1<<13)         /* Floating Point enable */
  35#define MSR_ME          (1<<12)         /* Machine Check Enable */
  36#define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
  37#define MSR_SE          (1<<10)         /* Single Step */
  38#define MSR_DWE         (1<<10)         /* Debug Wait Enable (4xx) */
  39#define MSR_BE          (1<<9)          /* Branch Trace */
  40#define MSR_DE          (1<<9)          /* Debug Exception Enable */
  41#define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
  42#define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
  43#define MSR_IR          (1<<5)          /* Instruction Relocate */
  44#define MSR_DR          (1<<4)          /* Data Relocate */
  45#define MSR_PE          (1<<3)          /* Protection Enable */
  46#define MSR_PX          (1<<2)          /* Protection Exclusive Mode */
  47#define MSR_RI          (1<<1)          /* Recoverable Exception */
  48#define MSR_LE          (1<<0)          /* Little Endian */
  49
  50#ifdef CONFIG_APUS_FAST_EXCEPT
  51#define MSR_            MSR_ME|MSR_IP|MSR_RI
  52#else
  53#define MSR_            MSR_ME|MSR_RI
  54#endif
  55#define MSR_KERNEL      MSR_|MSR_IR|MSR_DR
  56#define MSR_USER        MSR_KERNEL|MSR_PR|MSR_EE
  57
  58/* Floating Point Status and Control Register (FPSCR) Fields */
  59
  60#define FPSCR_FX        0x80000000      /* FPU exception summary */
  61#define FPSCR_FEX       0x40000000      /* FPU enabled exception summary */
  62#define FPSCR_VX        0x20000000      /* Invalid operation summary */
  63#define FPSCR_OX        0x10000000      /* Overflow exception summary */
  64#define FPSCR_UX        0x08000000      /* Underflow exception summary */
  65#define FPSCR_ZX        0x04000000      /* Zero-devide exception summary */
  66#define FPSCR_XX        0x02000000      /* Inexact exception summary */
  67#define FPSCR_VXSNAN    0x01000000      /* Invalid op for SNaN */
  68#define FPSCR_VXISI     0x00800000      /* Invalid op for Inv - Inv */
  69#define FPSCR_VXIDI     0x00400000      /* Invalid op for Inv / Inv */
  70#define FPSCR_VXZDZ     0x00200000      /* Invalid op for Zero / Zero */
  71#define FPSCR_VXIMZ     0x00100000      /* Invalid op for Inv * Zero */
  72#define FPSCR_VXVC      0x00080000      /* Invalid op for Compare */
  73#define FPSCR_FR        0x00040000      /* Fraction rounded */
  74#define FPSCR_FI        0x00020000      /* Fraction inexact */
  75#define FPSCR_FPRF      0x0001f000      /* FPU Result Flags */
  76#define FPSCR_FPCC      0x0000f000      /* FPU Condition Codes */
  77#define FPSCR_VXSOFT    0x00000400      /* Invalid op for software request */
  78#define FPSCR_VXSQRT    0x00000200      /* Invalid op for square root */
  79#define FPSCR_VXCVI     0x00000100      /* Invalid op for integer convert */
  80#define FPSCR_VE        0x00000080      /* Invalid op exception enable */
  81#define FPSCR_OE        0x00000040      /* IEEE overflow exception enable */
  82#define FPSCR_UE        0x00000020      /* IEEE underflow exception enable */
  83#define FPSCR_ZE        0x00000010      /* IEEE zero divide exception enable */
  84#define FPSCR_XE        0x00000008      /* FP inexact exception enable */
  85#define FPSCR_NI        0x00000004      /* FPU non IEEE-Mode */
  86#define FPSCR_RN        0x00000003      /* FPU rounding control */
  87
  88/* Special Purpose Registers (SPRNs)*/
  89
  90#define SPRN_CCR0       0x3B3   /* Core Configuration Register (4xx) */
  91#define SPRN_CDBCR      0x3D7   /* Cache Debug Control Register */
  92#define SPRN_CTR        0x009   /* Count Register */
  93#define SPRN_DABR       0x3F5   /* Data Address Breakpoint Register */
  94#define SPRN_DAC1       0x3F6   /* Data Address Compare 1 */
  95#define SPRN_DAC2       0x3F7   /* Data Address Compare 2 */
  96#define SPRN_DAR        0x013   /* Data Address Register */
  97#define SPRN_DBAT0L     0x219   /* Data BAT 0 Lower Register */
  98#define SPRN_DBAT0U     0x218   /* Data BAT 0 Upper Register */
  99#define SPRN_DBAT1L     0x21B   /* Data BAT 1 Lower Register */
 100#define SPRN_DBAT1U     0x21A   /* Data BAT 1 Upper Register */
 101#define SPRN_DBAT2L     0x21D   /* Data BAT 2 Lower Register */
 102#define SPRN_DBAT2U     0x21C   /* Data BAT 2 Upper Register */
 103#define SPRN_DBAT3L     0x21F   /* Data BAT 3 Lower Register */
 104#define SPRN_DBAT3U     0x21E   /* Data BAT 3 Upper Register */
 105#define SPRN_DBCR       0x3F2   /* Debug Control Regsiter */
 106#define   DBCR_EDM      0x80000000
 107#define   DBCR_IDM      0x40000000
 108#define   DBCR_RST(x)   (((x) & 0x3) << 28)
 109#define     DBCR_RST_NONE               0
 110#define     DBCR_RST_CORE               1
 111#define     DBCR_RST_CHIP               2
 112#define     DBCR_RST_SYSTEM             3
 113#define   DBCR_IC       0x08000000      /* Instruction Completion Debug Evnt */
 114#define   DBCR_BT       0x04000000      /* Branch Taken Debug Event */
 115#define   DBCR_EDE      0x02000000      /* Exception Debug Event */
 116#define   DBCR_TDE      0x01000000      /* TRAP Debug Event */
 117#define   DBCR_FER      0x00F80000      /* First Events Remaining Mask */
 118#define   DBCR_FT       0x00040000      /* Freeze Timers on Debug Event */
 119#define   DBCR_IA1      0x00020000      /* Instr. Addr. Compare 1 Enable */
 120#define   DBCR_IA2      0x00010000      /* Instr. Addr. Compare 2 Enable */
 121#define   DBCR_D1R      0x00008000      /* Data Addr. Compare 1 Read Enable */
 122#define   DBCR_D1W      0x00004000      /* Data Addr. Compare 1 Write Enable */
 123#define   DBCR_D1S(x)   (((x) & 0x3) << 12)     /* Data Adrr. Compare 1 Size */
 124#define     DAC_BYTE    0
 125#define     DAC_HALF    1
 126#define     DAC_WORD    2
 127#define     DAC_QUAD    3
 128#define   DBCR_D2R      0x00000800      /* Data Addr. Compare 2 Read Enable */
 129#define   DBCR_D2W      0x00000400      /* Data Addr. Compare 2 Write Enable */
 130#define   DBCR_D2S(x)   (((x) & 0x3) << 8)      /* Data Addr. Compare 2 Size */
 131#define   DBCR_SBT      0x00000040      /* Second Branch Taken Debug Event */
 132#define   DBCR_SED      0x00000020      /* Second Exception Debug Event */
 133#define   DBCR_STD      0x00000010      /* Second Trap Debug Event */
 134#define   DBCR_SIA      0x00000008      /* Second IAC Enable */
 135#define   DBCR_SDA      0x00000004      /* Second DAC Enable */
 136#define   DBCR_JOI      0x00000002      /* JTAG Serial Outbound Int. Enable */
 137#define   DBCR_JII      0x00000001      /* JTAG Serial Inbound Int. Enable */
 138#define SPRN_DBCR0      0x3F2   /* Debug Control Register 0 */
 139#define SPRN_DBCR1      0x3BD   /* Debug Control Register 1 */
 140#define SPRN_DBSR       0x3F0   /* Debug Status Register */
 141#define   DBSR_IC           0x80000000  /* Instruction Completion             */
 142#define   DBSR_TIE          0x10000000  /* Trap Instruction debug Event       */
 143#define SPRN_DCCR       0x3FA   /* Data Cache Cacheability Register */
 144#define   DCCR_NOCACHE          0       /* Noncacheable */
 145#define   DCCR_CACHE            1       /* Cacheable */
 146#define SPRN_DCMP       0x3D1   /* Data TLB Compare Register */
 147#define SPRN_DCWR       0x3BA   /* Data Cache Write-thru Register */
 148#define   DCWR_COPY             0       /* Copy-back */
 149#define   DCWR_WRITE            1       /* Write-through */
 150#define SPRN_DEAR       0x3D5   /* Data Error Address Register */
 151#define SPRN_DEC        0x016   /* Decrement Register */
 152#define SPRN_DER        0x095   /* Debug Enable Regsiter */
 153#define   DER_RSTE      0x40000000      /* Reset Interrupt */
 154#define   DER_CHSTPE    0x20000000      /* Check Stop */
 155#define   DER_MCIE      0x10000000      /* Machine Check Interrupt */
 156#define   DER_EXTIE     0x02000000      /* External Interrupt */
 157#define   DER_ALIE      0x01000000      /* Alignment Interrupt */
 158#define   DER_PRIE      0x00800000      /* Program Interrupt */
 159#define   DER_FPUVIE    0x00400000      /* FP Unavailable Interrupt */
 160#define   DER_DECIE     0x00200000      /* Decrementer Interrupt */
 161#define   DER_SYSIE     0x00040000      /* System Call Interrupt */
 162#define   DER_TRE       0x00020000      /* Trace Interrupt */
 163#define   DER_SEIE      0x00004000      /* FP SW Emulation Interrupt */
 164#define   DER_ITLBMSE   0x00002000      /* Imp. Spec. Instruction TLB Miss */
 165#define   DER_ITLBERE   0x00001000      /* Imp. Spec. Instruction TLB Error */
 166#define   DER_DTLBMSE   0x00000800      /* Imp. Spec. Data TLB Miss */
 167#define   DER_DTLBERE   0x00000400      /* Imp. Spec. Data TLB Error */
 168#define   DER_LBRKE     0x00000008      /* Load/Store Breakpoint Interrupt */
 169#define   DER_IBRKE     0x00000004      /* Instruction Breakpoint Interrupt */
 170#define   DER_EBRKE     0x00000002      /* External Breakpoint Interrupt */
 171#define   DER_DPIE      0x00000001      /* Dev. Port Nonmaskable Request */
 172#define SPRN_DMISS      0x3D0   /* Data TLB Miss Register */
 173#define SPRN_DSISR      0x012   /* Data Storage Interrupt Status Register */
 174#define SPRN_EAR        0x11A   /* External Address Register */
 175#define SPRN_ESR        0x3D4   /* Exception Syndrome Register */
 176#define   ESR_IMCP      0x80000000      /* Instr. Machine Check - Protection */
 177#define   ESR_IMCN      0x40000000      /* Instr. Machine Check - Non-config */
 178#define   ESR_IMCB      0x20000000      /* Instr. Machine Check - Bus error */
 179#define   ESR_IMCT      0x10000000      /* Instr. Machine Check - Timeout */
 180#define   ESR_PIL       0x08000000      /* Program Exception - Illegal */
 181#define   ESR_PPR       0x04000000      /* Program Exception - Priveleged */
 182#define   ESR_PTR       0x02000000      /* Program Exception - Trap */
 183#define   ESR_DST       0x00800000      /* Storage Exception - Data miss */
 184#define   ESR_DIZ       0x00400000      /* Storage Exception - Zone fault */
 185#define SPRN_EVPR       0x3D6   /* Exception Vector Prefix Register */
 186#define SPRN_HASH1      0x3D2   /* Primary Hash Address Register */
 187#define SPRN_HASH2      0x3D3   /* Secondary Hash Address Resgister */
 188#define SPRN_HID0       0x3F0   /* Hardware Implementation Register 0 */
 189#define   HID0_EMCP     (1<<31)         /* Enable Machine Check pin */
 190#define   HID0_EBA      (1<<29)         /* Enable Bus Address Parity */
 191#define   HID0_EBD      (1<<28)         /* Enable Bus Data Parity */
 192#define   HID0_SBCLK    (1<<27)
 193#define   HID0_EICE     (1<<26)
 194#define   HID0_ECLK     (1<<25)
 195#define   HID0_PAR      (1<<24)
 196#define   HID0_DOZE     (1<<23)
 197#define   HID0_NAP      (1<<22)
 198#define   HID0_SLEEP    (1<<21)
 199#define   HID0_DPM      (1<<20)
 200#define   HID0_ICE      (1<<15)         /* Instruction Cache Enable */
 201#define   HID0_DCE      (1<<14)         /* Data Cache Enable */
 202#define   HID0_ILOCK    (1<<13)         /* Instruction Cache Lock */
 203#define   HID0_DLOCK    (1<<12)         /* Data Cache Lock */
 204#define   HID0_ICFI     (1<<11)         /* Instr. Cache Flash Invalidate */
 205#define   HID0_DCI      (1<<10)         /* Data Cache Invalidate */
 206#define   HID0_SPD      (1<<9)          /* Speculative disable */
 207#define   HID0_SGE      (1<<7)          /* Store Gathering Enable */
 208#define   HID0_SIED     (1<<7)          /* Serial Instr. Execution [Disable] */
 209#define   HID0_DFCA     (1<<6)          /* Data Cache Flush Assist */
 210#define   HID0_BTIC     (1<<5)          /* Branch Target Instruction Cache Enable */
 211#define   HID0_ABE      (1<<3)          /* Address Broadcast Enable */
 212#define   HID0_FOLD     (1<<3)          /* Branch Folding enable - 7450 */
 213#define   HID0_BHTE     (1<<2)          /* Branch History Table Enable */
 214#define   HID0_BTCD     (1<<1)          /* Branch target cache disable */
 215#define   HID0_NOPDST   (1<<1)          /* No-op dst, dstt, etc. instr. */
 216#define   HID0_NOPTI    (1<<0)          /* No-op dcbt and dcbst instr. */
 217#define SPRN_HID1       0x3F1   /* Hardware Implementation Register 1 */
 218#define SPRN_IABR       0x3F2   /* Instruction Address Breakpoint Register */
 219#define SPRN_IAC1       0x3F4   /* Instruction Address Compare 1 */
 220#define SPRN_IAC2       0x3F5   /* Instruction Address Compare 2 */
 221#define SPRN_IBAT0L     0x211   /* Instruction BAT 0 Lower Register */
 222#define SPRN_IBAT0U     0x210   /* Instruction BAT 0 Upper Register */
 223#define SPRN_IBAT1L     0x213   /* Instruction BAT 1 Lower Register */
 224#define SPRN_IBAT1U     0x212   /* Instruction BAT 1 Upper Register */
 225#define SPRN_IBAT2L     0x215   /* Instruction BAT 2 Lower Register */
 226#define SPRN_IBAT2U     0x214   /* Instruction BAT 2 Upper Register */
 227#define SPRN_IBAT3L     0x217   /* Instruction BAT 3 Lower Register */
 228#define SPRN_IBAT3U     0x216   /* Instruction BAT 3 Upper Register */
 229#define SPRN_ICCR       0x3FB   /* Instruction Cache Cacheability Register */
 230#define   ICCR_NOCACHE          0       /* Noncacheable */
 231#define   ICCR_CACHE            1       /* Cacheable */
 232#define SPRN_ICDBDR     0x3D3   /* Instruction Cache Debug Data Register */
 233#define SPRN_ICMP       0x3D5   /* Instruction TLB Compare Register */
 234#define SPRN_ICTC       0x3FB   /* Instruction Cache Throttling Control Reg */
 235#define SPRN_IMISS      0x3D4   /* Instruction TLB Miss Register */
 236#define SPRN_IMMR       0x27E   /* Internal Memory Map Register */
 237#define SPRN_L2CR       0x3F9   /* Level 2 Cache Control Regsiter */
 238#define L2CR_L2E                0x80000000      /* L2 enable */
 239#define L2CR_L2PE               0x40000000      /* L2 parity enable */
 240#define L2CR_L2SIZ_MASK         0x30000000      /* L2 size mask */
 241#define L2CR_L2SIZ_256KB        0x10000000      /* L2 size 256KB */
 242#define L2CR_L2SIZ_512KB        0x20000000      /* L2 size 512KB */
 243#define L2CR_L2SIZ_1MB          0x30000000      /* L2 size 1MB */
 244#define L2CR_L2CLK_MASK         0x0e000000      /* L2 clock mask */
 245#define L2CR_L2CLK_DISABLED     0x00000000      /* L2 clock disabled */
 246#define L2CR_L2CLK_DIV1         0x02000000      /* L2 clock / 1 */
 247#define L2CR_L2CLK_DIV1_5       0x04000000      /* L2 clock / 1.5 */
 248#define L2CR_L2CLK_DIV2         0x08000000      /* L2 clock / 2 */
 249#define L2CR_L2CLK_DIV2_5       0x0a000000      /* L2 clock / 2.5 */
 250#define L2CR_L2CLK_DIV3         0x0c000000      /* L2 clock / 3 */
 251#define L2CR_L2RAM_MASK         0x01800000      /* L2 RAM type mask */
 252#define L2CR_L2RAM_FLOW         0x00000000      /* L2 RAM flow through */
 253#define L2CR_L2RAM_PIPE         0x01000000      /* L2 RAM pipelined */
 254#define L2CR_L2RAM_PIPE_LW      0x01800000      /* L2 RAM pipelined latewr */
 255#define L2CR_L2DO               0x00400000      /* L2 data only */
 256#define L2CR_L2I                0x00200000      /* L2 global invalidate */
 257#define L2CR_L2CTL              0x00100000      /* L2 RAM control */
 258#define L2CR_L2WT               0x00080000      /* L2 write-through */
 259#define L2CR_L2TS               0x00040000      /* L2 test support */
 260#define L2CR_L2OH_MASK          0x00030000      /* L2 output hold mask */
 261#define L2CR_L2OH_0_5           0x00000000      /* L2 output hold 0.5 ns */
 262#define L2CR_L2OH_1_0           0x00010000      /* L2 output hold 1.0 ns */
 263#define L2CR_L2SL               0x00008000      /* L2 DLL slow */
 264#define L2CR_L2DF               0x00004000      /* L2 differential clock */
 265#define L2CR_L2BYP              0x00002000      /* L2 DLL bypass */
 266#define L2CR_L2IP               0x00000001      /* L2 GI in progress */
 267#define SPRN_L2CR2      0x3f8
 268#define SPRN_L3CR       0x3FA   /* Level 3 Cache Control Regsiter (7450) */
 269#define L3CR_L3E                0x80000000      /* L3 enable */
 270#define SPRN_MSSCR0     0x3f6   /* Memory Subsystem Control Register 0 */
 271#define SPRN_MSSSR0     0x3f7   /* Memory Subsystem Status Register 1 */
 272#define SPRN_ICTRL      0x3f3   /* Instruction Cache & Interrupt control reg */
 273#define SPRN_LDSTCR     0x3f8   /* Load/Store control register */
 274#define SPRN_LDSTDB     0x3f4   /* */
 275#define SPRN_LR         0x008   /* Link Register */
 276#define SPRN_MMCR0      0x3B8   /* Monitor Mode Control Register 0 */
 277#define SPRN_MMCR1      0x3BC   /* Monitor Mode Control Register 1 */
 278#define SPRN_PBL1       0x3FC   /* Protection Bound Lower 1 */
 279#define SPRN_PBL2       0x3FE   /* Protection Bound Lower 2 */
 280#define SPRN_PBU1       0x3FD   /* Protection Bound Upper 1 */
 281#define SPRN_PBU2       0x3FF   /* Protection Bound Upper 2 */
 282#define SPRN_PID        0x3B1   /* Process ID */
 283#define SPRN_PIR        0x3FF   /* Processor Identification Register */
 284#define SPRN_PIT        0x3DB   /* Programmable Interval Timer */
 285#define SPRN_PMC1       0x3B9   /* Performance Counter Register 1 */
 286#define SPRN_PMC2       0x3BA   /* Performance Counter Register 2 */
 287#define SPRN_PMC3       0x3BD   /* Performance Counter Register 3 */
 288#define SPRN_PMC4       0x3BE   /* Performance Counter Register 4 */
 289#define SPRN_PVR        0x11F   /* Processor Version Register */
 290#define SPRN_RPA        0x3D6   /* Required Physical Address Register */
 291#define SPRN_SDA        0x3BF   /* Sampled Data Address Register */
 292#define SPRN_SDR1       0x019   /* MMU Hash Base Register */
 293#define SPRN_SGR        0x3B9   /* Storage Guarded Register */
 294#define   SGR_NORMAL            0
 295#define   SGR_GUARDED           1
 296#define SPRN_SIA        0x3BB   /* Sampled Instruction Address Register */
 297#define SPRN_SPRG0      0x110   /* Special Purpose Register General 0 */
 298#define SPRN_SPRG1      0x111   /* Special Purpose Register General 1 */
 299#define SPRN_SPRG2      0x112   /* Special Purpose Register General 2 */
 300#define SPRN_SPRG3      0x113   /* Special Purpose Register General 3 */
 301#define SPRN_SPRG4      0x114   /* Special Purpose Register General 4 (4xx) */
 302#define SPRN_SPRG5      0x115   /* Special Purpose Register General 5 (4xx) */
 303#define SPRN_SPRG6      0x116   /* Special Purpose Register General 6 (4xx) */
 304#define SPRN_SPRG7      0x117   /* Special Purpose Register General 7 (4xx) */
 305#define SPRN_SRR0       0x01A   /* Save/Restore Register 0 */
 306#define SPRN_SRR1       0x01B   /* Save/Restore Register 1 */
 307#define SPRN_SRR2       0x3DE   /* Save/Restore Register 2 */
 308#define SPRN_SRR3       0x3DF   /* Save/Restore Register 3 */
 309#define SPRN_TBRL       0x10C   /* Time Base Read Lower Register (user, R/O) */
 310#define SPRN_TBRU       0x10D   /* Time Base Read Upper Register (user, R/O) */
 311#define SPRN_TBWL       0x11C   /* Time Base Lower Register (supervisor, R/W) */
 312#define SPRN_TBWU       0x11D   /* Time Base Upper Register (supervisor, R/W) */
 313#define SPRN_TCR        0x3DA   /* Timer Control Register */
 314#define   TCR_WP(x)             (((x)&0x3)<<30) /* WDT Period */
 315#define     WP_2_17             0               /* 2^17 clocks */
 316#define     WP_2_21             1               /* 2^21 clocks */
 317#define     WP_2_25             2               /* 2^25 clocks */
 318#define     WP_2_29             3               /* 2^29 clocks */
 319#define   TCR_WRC(x)            (((x)&0x3)<<28) /* WDT Reset Control */
 320#define     WRC_NONE            0               /* No reset will occur */
 321#define     WRC_CORE            1               /* Core reset will occur */
 322#define     WRC_CHIP            2               /* Chip reset will occur */
 323#define     WRC_SYSTEM          3               /* System reset will occur */
 324#define   TCR_WIE               0x08000000      /* WDT Interrupt Enable */
 325#define   TCR_PIE               0x04000000      /* PIT Interrupt Enable */
 326#define   TCR_FP(x)             (((x)&0x3)<<24) /* FIT Period */
 327#define     FP_2_9              0               /* 2^9 clocks */
 328#define     FP_2_13             1               /* 2^13 clocks */
 329#define     FP_2_17             2               /* 2^17 clocks */
 330#define     FP_2_21             3               /* 2^21 clocks */
 331#define   TCR_FIE               0x00800000      /* FIT Interrupt Enable */
 332#define   TCR_ARE               0x00400000      /* Auto Reload Enable */
 333#define SPRN_THRM1      0x3FC   /* Thermal Management Register 1 */
 334/* these bits were defined in inverted endian sense originally, ugh, confusing */
 335#define   THRM1_TIN             (1 << 31)
 336#define   THRM1_TIV             (1 << 30)
 337#define   THRM1_THRES(x)        ((x&0x7f)<<23)
 338#define   THRM3_SITV(x)         ((x&0x3fff)<<1)
 339#define   THRM1_TID             (1<<2)
 340#define   THRM1_TIE             (1<<1)
 341#define   THRM1_V               (1<<0)
 342#define SPRN_THRM2      0x3FD   /* Thermal Management Register 2 */
 343#define SPRN_THRM3      0x3FE   /* Thermal Management Register 3 */
 344#define   THRM3_E               (1<<0)
 345#define SPRN_TSR        0x3D8   /* Timer Status Register */
 346#define   TSR_ENW               0x80000000      /* Enable Next Watchdog */
 347#define   TSR_WIS               0x40000000      /* WDT Interrupt Status */
 348#define   TSR_WRS(x)            (((x)&0x3)<<28) /* WDT Reset Status */
 349#define     WRS_NONE            0               /* No WDT reset occurred */
 350#define     WRS_CORE            1               /* WDT forced core reset */
 351#define     WRS_CHIP            2               /* WDT forced chip reset */
 352#define     WRS_SYSTEM          3               /* WDT forced system reset */
 353#define   TSR_PIS               0x08000000      /* PIT Interrupt Status */
 354#define   TSR_FIS               0x04000000      /* FIT Interrupt Status */
 355#define SPRN_UMMCR0     0x3A8   /* User Monitor Mode Control Register 0 */
 356#define SPRN_UMMCR1     0x3AC   /* User Monitor Mode Control Register 0 */
 357#define SPRN_UPMC1      0x3A9   /* User Performance Counter Register 1 */
 358#define SPRN_UPMC2      0x3AA   /* User Performance Counter Register 2 */
 359#define SPRN_UPMC3      0x3AD   /* User Performance Counter Register 3 */
 360#define SPRN_UPMC4      0x3AE   /* User Performance Counter Register 4 */
 361#define SPRN_USIA       0x3AB   /* User Sampled Instruction Address Register */
 362#define SPRN_VRSAVE     0x100   /* Vector Register Save Register */
 363#define SPRN_XER        0x001   /* Fixed Point Exception Register */
 364#define SPRN_ZPR        0x3B0   /* Zone Protection Register */
 365
 366/* Short-hand versions for a number of the above SPRNs */
 367
 368#define CTR     SPRN_CTR        /* Counter Register */
 369#define DAR     SPRN_DAR        /* Data Address Register */
 370#define DABR    SPRN_DABR       /* Data Address Breakpoint Register */
 371#define DBAT0L  SPRN_DBAT0L     /* Data BAT 0 Lower Register */
 372#define DBAT0U  SPRN_DBAT0U     /* Data BAT 0 Upper Register */
 373#define DBAT1L  SPRN_DBAT1L     /* Data BAT 1 Lower Register */
 374#define DBAT1U  SPRN_DBAT1U     /* Data BAT 1 Upper Register */
 375#define DBAT2L  SPRN_DBAT2L     /* Data BAT 2 Lower Register */
 376#define DBAT2U  SPRN_DBAT2U     /* Data BAT 2 Upper Register */
 377#define DBAT3L  SPRN_DBAT3L     /* Data BAT 3 Lower Register */
 378#define DBAT3U  SPRN_DBAT3U     /* Data BAT 3 Upper Register */
 379#define DCMP    SPRN_DCMP       /* Data TLB Compare Register */
 380#define DEC     SPRN_DEC        /* Decrement Register */
 381#define DMISS   SPRN_DMISS      /* Data TLB Miss Register */
 382#define DSISR   SPRN_DSISR      /* Data Storage Interrupt Status Register */
 383#define EAR     SPRN_EAR        /* External Address Register */
 384#define HASH1   SPRN_HASH1      /* Primary Hash Address Register */
 385#define HASH2   SPRN_HASH2      /* Secondary Hash Address Register */
 386#define HID0    SPRN_HID0       /* Hardware Implementation Register 0 */
 387#define HID1    SPRN_HID1       /* Hardware Implementation Register 1 */
 388#define IABR    SPRN_IABR       /* Instruction Address Breakpoint Register */
 389#define IBAT0L  SPRN_IBAT0L     /* Instruction BAT 0 Lower Register */
 390#define IBAT0U  SPRN_IBAT0U     /* Instruction BAT 0 Upper Register */
 391#define IBAT1L  SPRN_IBAT1L     /* Instruction BAT 1 Lower Register */
 392#define IBAT1U  SPRN_IBAT1U     /* Instruction BAT 1 Upper Register */
 393#define IBAT2L  SPRN_IBAT2L     /* Instruction BAT 2 Lower Register */
 394#define IBAT2U  SPRN_IBAT2U     /* Instruction BAT 2 Upper Register */
 395#define IBAT3L  SPRN_IBAT3L     /* Instruction BAT 3 Lower Register */
 396#define IBAT3U  SPRN_IBAT3U     /* Instruction BAT 3 Upper Register */
 397#define ICMP    SPRN_ICMP       /* Instruction TLB Compare Register */
 398#define IMISS   SPRN_IMISS      /* Instruction TLB Miss Register */
 399#define IMMR    SPRN_IMMR       /* PPC 860/821 Internal Memory Map Register */
 400#define L2CR    SPRN_L2CR       /* PPC 750 L2 control register */
 401#define LR      SPRN_LR
 402#define PVR     SPRN_PVR        /* Processor Version */
 403#define RPA     SPRN_RPA        /* Required Physical Address Register */
 404#define SDR1    SPRN_SDR1       /* MMU hash base register */
 405#define SPR0    SPRN_SPRG0      /* Supervisor Private Registers */
 406#define SPR1    SPRN_SPRG1
 407#define SPR2    SPRN_SPRG2
 408#define SPR3    SPRN_SPRG3
 409#define SPR4    SPRN_SPRG4      /* Supervisor Private Registers (4xx) */
 410#define SPR5    SPRN_SPRG5
 411#define SPR6    SPRN_SPRG6
 412#define SPR7    SPRN_SPRG7
 413#define SPRG0   SPRN_SPRG0
 414#define SPRG1   SPRN_SPRG1
 415#define SPRG2   SPRN_SPRG2
 416#define SPRG3   SPRN_SPRG3
 417#define SPRG4   SPRN_SPRG4
 418#define SPRG5   SPRN_SPRG5
 419#define SPRG6   SPRN_SPRG6
 420#define SPRG7   SPRN_SPRG7
 421#define SRR0    SPRN_SRR0       /* Save and Restore Register 0 */
 422#define SRR1    SPRN_SRR1       /* Save and Restore Register 1 */
 423#define TBRL    SPRN_TBRL       /* Time Base Read Lower Register */
 424#define TBRU    SPRN_TBRU       /* Time Base Read Upper Register */
 425#define TBWL    SPRN_TBWL       /* Time Base Write Lower Register */
 426#define TBWU    SPRN_TBWU       /* Time Base Write Upper Register */
 427#define ICTC    1019
 428#define THRM1   SPRN_THRM1      /* Thermal Management Register 1 */
 429#define THRM2   SPRN_THRM2      /* Thermal Management Register 2 */
 430#define THRM3   SPRN_THRM3      /* Thermal Management Register 3 */
 431#define XER     SPRN_XER
 432
 433/* Processor Version Register */
 434
 435/* Processor Version Register (PVR) field extraction */
 436
 437#define PVR_VER(pvr)  (((pvr) >>  16) & 0xFFFF) /* Version field */
 438#define PVR_REV(pvr)  (((pvr) >>   0) & 0xFFFF) /* Revison field */
 439
 440/*
 441 * IBM has further subdivided the standard PowerPC 16-bit version and
 442 * revision subfields of the PVR for the PowerPC 403s into the following:
 443 */
 444
 445#define PVR_FAM(pvr)    (((pvr) >> 20) & 0xFFF) /* Family field */
 446#define PVR_MEM(pvr)    (((pvr) >> 16) & 0xF)   /* Member field */
 447#define PVR_CORE(pvr)   (((pvr) >> 12) & 0xF)   /* Core field */
 448#define PVR_CFG(pvr)    (((pvr) >>  8) & 0xF)   /* Configuration field */
 449#define PVR_MAJ(pvr)    (((pvr) >>  4) & 0xF)   /* Major revision field */
 450#define PVR_MIN(pvr)    (((pvr) >>  0) & 0xF)   /* Minor revision field */
 451
 452/* Processor Version Numbers */
 453
 454#define PVR_403GA       0x00200000
 455#define PVR_403GB       0x00200100
 456#define PVR_403GC       0x00200200
 457#define PVR_403GCX      0x00201400
 458#define PVR_405GP       0x40110000
 459#define PVR_STB03XXX    0x40310000 
 460#define PVR_601         0x00010000
 461#define PVR_602         0x00050000
 462#define PVR_603         0x00030000
 463#define PVR_603e        0x00060000
 464#define PVR_603ev       0x00070000
 465#define PVR_603r        0x00071000
 466#define PVR_604         0x00040000
 467#define PVR_604e        0x00090000
 468#define PVR_604r        0x000A0000
 469#define PVR_620         0x00140000
 470#define PVR_740         0x00080000
 471#define PVR_750         PVR_740
 472#define PVR_740P        0x10080000
 473#define PVR_750P        PVR_740P
 474#define PVR_7400        0x000C0000
 475#define PVR_7410        0x800C0000
 476/*
 477 * For the 8xx processors, all of them report the same PVR family for
 478 * the PowerPC core. The various versions of these processors must be
 479 * differentiated by the version number in the Communication Processor
 480 * Module (CPM).
 481 */
 482#define PVR_821         0x00500000
 483#define PVR_823         PVR_821
 484#define PVR_850         PVR_821
 485#define PVR_860         PVR_821
 486#define PVR_8240        0x00810100
 487#define PVR_8260        PVR_8240
 488
 489/* We only need to define a new _MACH_xxx for machines which are part of
 490 * a configuration which supports more than one type of different machine.
 491 * This is currently limited to CONFIG_ALL_PPC and CHRP/PReP/PMac. -- Tom
 492 */
 493#define _MACH_prep      0x00000001
 494#define _MACH_Pmac      0x00000002      /* pmac or pmac clone (non-chrp) */
 495#define _MACH_chrp      0x00000004      /* chrp machine */
 496
 497/* see residual.h for these */
 498#define _PREP_Motorola 0x01  /* motorola prep */
 499#define _PREP_Firm     0x02  /* firmworks prep */
 500#define _PREP_IBM      0x00  /* ibm prep */
 501#define _PREP_Bull     0x03  /* bull prep */
 502
 503/* these are arbitrary */
 504#define _CHRP_Motorola 0x04  /* motorola chrp, the cobra */
 505#define _CHRP_IBM      0x05  /* IBM chrp, the longtrail and longtrail 2 */
 506
 507#define _GLOBAL(n)\
 508        .globl n;\
 509n:
 510
 511/* Macros for setting and retrieving special purpose registers */
 512
 513#define stringify(s)    tostring(s)
 514#define tostring(s)     #s
 515
 516#define mfdcr(rn)       ({unsigned int rval; \
 517                        asm volatile("mfdcr %0," stringify(rn) \
 518                                     : "=r" (rval)); rval;})
 519#define mtdcr(rn, v)    asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
 520
 521#define mfmsr()         ({unsigned int rval; \
 522                        asm volatile("mfmsr %0" : "=r" (rval)); rval;})
 523#define mtmsr(v)        asm volatile("mtmsr %0" : : "r" (v))
 524
 525#define mfspr(rn)       ({unsigned int rval; \
 526                        asm volatile("mfspr %0," stringify(rn) \
 527                                     : "=r" (rval)); rval;})
 528#define mtspr(rn, v)    asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
 529
 530/* Segment Registers */
 531
 532#define SR0     0
 533#define SR1     1
 534#define SR2     2
 535#define SR3     3
 536#define SR4     4
 537#define SR5     5
 538#define SR6     6
 539#define SR7     7
 540#define SR8     8
 541#define SR9     9
 542#define SR10    10
 543#define SR11    11
 544#define SR12    12
 545#define SR13    13
 546#define SR14    14
 547#define SR15    15
 548
 549#ifndef __ASSEMBLY__
 550#if defined(CONFIG_ALL_PPC)
 551extern int _machine;
 552
 553/* what kind of prep workstation we are */
 554extern int _prep_type;
 555
 556/*
 557 * This is used to identify the board type from a given PReP board
 558 * vendor. Board revision is also made available.
 559 */
 560extern unsigned char ucSystemType;
 561extern unsigned char ucBoardRev;
 562extern unsigned char ucBoardRevMaj, ucBoardRevMin;
 563#else
 564#define _machine 0
 565#endif /* CONFIG_ALL_PPC */
 566
 567struct task_struct;
 568void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
 569void release_thread(struct task_struct *);
 570
 571/*
 572 * Create a new kernel thread.
 573 */
 574extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 575
 576/*
 577 * Bus types
 578 */
 579#define EISA_bus 0
 580#define EISA_bus__is_a_macro /* for versions in ksyms.c */
 581#define MCA_bus 0
 582#define MCA_bus__is_a_macro /* for versions in ksyms.c */
 583
 584/* Lazy FPU handling on uni-processor */
 585extern struct task_struct *last_task_used_math;
 586extern struct task_struct *last_task_used_altivec;
 587
 588/*
 589 * this is the minimum allowable io space due to the location
 590 * of the io areas on prep (first one at 0x80000000) but
 591 * as soon as I get around to remapping the io areas with the BATs
 592 * to match the mac we can raise this. -- Cort
 593 */
 594#define TASK_SIZE       (0x80000000UL)
 595
 596/* This decides where the kernel will search for a free chunk of vm
 597 * space during mmap's.
 598 */
 599#define TASK_UNMAPPED_BASE      (TASK_SIZE / 8 * 3)
 600
 601typedef struct {
 602        unsigned long seg;
 603} mm_segment_t;
 604
 605struct thread_struct {
 606        unsigned long   ksp;            /* Kernel stack pointer */
 607        unsigned long   wchan;          /* Event task is sleeping on */
 608        struct pt_regs  *regs;          /* Pointer to saved register state */
 609        mm_segment_t    fs;             /* for get_fs() validation */
 610        void            *pgdir;         /* root of page-table tree */
 611        signed long     last_syscall;
 612        double          fpr[32];        /* Complete floating point set */
 613        unsigned long   fpscr_pad;      /* fpr ... fpscr must be contiguous */
 614        unsigned long   fpscr;          /* Floating point status */
 615#ifdef CONFIG_ALTIVEC
 616        vector128       vr[32];         /* Complete AltiVec set */
 617        vector128       vscr;           /* AltiVec status */
 618        unsigned long   vrsave;
 619#endif /* CONFIG_ALTIVEC */
 620};
 621
 622#define INIT_SP         (sizeof(init_stack) + (unsigned long) &init_stack)
 623
 624#define INIT_THREAD  { \
 625        INIT_SP, /* ksp */ \
 626        0, /* wchan */ \
 627        0, /* regs */ \
 628        KERNEL_DS, /*fs*/ \
 629        swapper_pg_dir, /* pgdir */ \
 630        0, /* last_syscall */ \
 631        {0}, 0, 0 \
 632}
 633
 634/*
 635 * Return saved PC of a blocked thread. For now, this is the "user" PC
 636 */
 637static inline unsigned long thread_saved_pc(struct thread_struct *t)
 638{
 639        return (t->regs) ? t->regs->nip : 0;
 640}
 641
 642#define copy_segments(tsk, mm)          do { } while (0)
 643#define release_segments(mm)            do { } while (0)
 644
 645unsigned long get_wchan(struct task_struct *p);
 646
 647#define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
 648#define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
 649
 650/*
 651 * NOTE! The task struct and the stack go together
 652 */
 653#define THREAD_SIZE (2*PAGE_SIZE)
 654#define alloc_task_struct() \
 655        ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
 656#define free_task_struct(p)     free_pages((unsigned long)(p),1)
 657#define get_task_struct(tsk)      atomic_inc(&virt_to_page(tsk)->count)
 658
 659/* in process.c - for early bootup debug -- Cort */
 660int ll_printk(const char *, ...);
 661void ll_puts(const char *);
 662
 663#define init_task       (init_task_union.task)
 664#define init_stack      (init_task_union.stack)
 665
 666/* In misc.c */
 667void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 668
 669#define cpu_relax()     do { } while (0)
 670
 671/*
 672 * Prefetch macros.
 673 */
 674#define ARCH_HAS_PREFETCH
 675#define ARCH_HAS_PREFETCHW
 676#define ARCH_HAS_SPINLOCK_PREFETCH
 677
 678extern inline void prefetch(const void *x)
 679{
 680         __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
 681}
 682
 683extern inline void prefetchw(const void *x)
 684{
 685         __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
 686}
 687
 688#define spin_lock_prefetch(x)   prefetchw(x)
 689
 690#endif /* !__ASSEMBLY__ */
 691
 692#define have_of (_machine == _MACH_chrp || _machine == _MACH_Pmac)
 693
 694#endif /* __ASM_PPC_PROCESSOR_H */
 695#endif /* __KERNEL__ */
 696