LXR linux-old/include/asm-ia64/processor.h

   1#ifndef _ASM_IA64_PROCESSOR_H
   2#define _ASM_IA64_PROCESSOR_H
   3
   4/*
   5 * Copyright (C) 1998-2001 Hewlett-Packard Co
   6 * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com>
   7 * Copyright (C) 1998-2001 Stephane Eranian <eranian@hpl.hp.com>
   8 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
   9 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
  10 *
  11 * 11/24/98     S.Eranian       added ia64_set_iva()
  12 * 12/03/99     D. Mosberger    implement thread_saved_pc() via kernel unwind API
  13 * 06/16/00     A. Mallick      added csd/ssd/tssd for ia32 support
  14 */
  15
  16#include <linux/config.h>
  17
  18#include <asm/ptrace.h>
  19#include <asm/kregs.h>
  20#include <asm/system.h>
  21#include <asm/types.h>
  22
  23#define IA64_NUM_DBG_REGS       8
  24/*
  25 * Limits for PMC and PMD are set to less than maximum architected values
  26 * but should be sufficient for a while
  27 */
  28#define IA64_NUM_PMC_REGS       32
  29#define IA64_NUM_PMD_REGS       32
  30#define IA64_NUM_PMD_COUNTERS   4
  31
  32#define DEFAULT_MAP_BASE        0x2000000000000000
  33#define DEFAULT_TASK_SIZE       0xa000000000000000
  34
  35/*
  36 * TASK_SIZE really is a mis-named.  It really is the maximum user
  37 * space address (plus one).  On IA-64, there are five regions of 2TB
  38 * each (assuming 8KB page size), for a total of 8TB of user virtual
  39 * address space.
  40 */
  41#define TASK_SIZE               (current->thread.task_size)
  42
  43/*
  44 * This decides where the kernel will search for a free chunk of vm
  45 * space during mmap's.
  46 */
  47#define TASK_UNMAPPED_BASE      (current->thread.map_base)
  48
  49/*
  50 * Bus types
  51 */
  52#define EISA_bus 0
  53#define EISA_bus__is_a_macro /* for versions in ksyms.c */
  54#define MCA_bus 0
  55#define MCA_bus__is_a_macro /* for versions in ksyms.c */
  56
  57/* Processor status register bits: */
  58#define IA64_PSR_BE_BIT         1
  59#define IA64_PSR_UP_BIT         2
  60#define IA64_PSR_AC_BIT         3
  61#define IA64_PSR_MFL_BIT        4
  62#define IA64_PSR_MFH_BIT        5
  63#define IA64_PSR_IC_BIT         13
  64#define IA64_PSR_I_BIT          14
  65#define IA64_PSR_PK_BIT         15
  66#define IA64_PSR_DT_BIT         17
  67#define IA64_PSR_DFL_BIT        18
  68#define IA64_PSR_DFH_BIT        19
  69#define IA64_PSR_SP_BIT         20
  70#define IA64_PSR_PP_BIT         21
  71#define IA64_PSR_DI_BIT         22
  72#define IA64_PSR_SI_BIT         23
  73#define IA64_PSR_DB_BIT         24
  74#define IA64_PSR_LP_BIT         25
  75#define IA64_PSR_TB_BIT         26
  76#define IA64_PSR_RT_BIT         27
  77/* The following are not affected by save_flags()/restore_flags(): */
  78#define IA64_PSR_CPL0_BIT       32
  79#define IA64_PSR_CPL1_BIT       33
  80#define IA64_PSR_IS_BIT         34
  81#define IA64_PSR_MC_BIT         35
  82#define IA64_PSR_IT_BIT         36
  83#define IA64_PSR_ID_BIT         37
  84#define IA64_PSR_DA_BIT         38
  85#define IA64_PSR_DD_BIT         39
  86#define IA64_PSR_SS_BIT         40
  87#define IA64_PSR_RI_BIT         41
  88#define IA64_PSR_ED_BIT         43
  89#define IA64_PSR_BN_BIT         44
  90
  91#define IA64_PSR_BE     (__IA64_UL(1) << IA64_PSR_BE_BIT)
  92#define IA64_PSR_UP     (__IA64_UL(1) << IA64_PSR_UP_BIT)
  93#define IA64_PSR_AC     (__IA64_UL(1) << IA64_PSR_AC_BIT)
  94#define IA64_PSR_MFL    (__IA64_UL(1) << IA64_PSR_MFL_BIT)
  95#define IA64_PSR_MFH    (__IA64_UL(1) << IA64_PSR_MFH_BIT)
  96#define IA64_PSR_IC     (__IA64_UL(1) << IA64_PSR_IC_BIT)
  97#define IA64_PSR_I      (__IA64_UL(1) << IA64_PSR_I_BIT)
  98#define IA64_PSR_PK     (__IA64_UL(1) << IA64_PSR_PK_BIT)
  99#define IA64_PSR_DT     (__IA64_UL(1) << IA64_PSR_DT_BIT)
 100#define IA64_PSR_DFL    (__IA64_UL(1) << IA64_PSR_DFL_BIT)
 101#define IA64_PSR_DFH    (__IA64_UL(1) << IA64_PSR_DFH_BIT)
 102#define IA64_PSR_SP     (__IA64_UL(1) << IA64_PSR_SP_BIT)
 103#define IA64_PSR_PP     (__IA64_UL(1) << IA64_PSR_PP_BIT)
 104#define IA64_PSR_DI     (__IA64_UL(1) << IA64_PSR_DI_BIT)
 105#define IA64_PSR_SI     (__IA64_UL(1) << IA64_PSR_SI_BIT)
 106#define IA64_PSR_DB     (__IA64_UL(1) << IA64_PSR_DB_BIT)
 107#define IA64_PSR_LP     (__IA64_UL(1) << IA64_PSR_LP_BIT)
 108#define IA64_PSR_TB     (__IA64_UL(1) << IA64_PSR_TB_BIT)
 109#define IA64_PSR_RT     (__IA64_UL(1) << IA64_PSR_RT_BIT)
 110/* The following are not affected by save_flags()/restore_flags(): */
 111#define IA64_PSR_IS     (__IA64_UL(1) << IA64_PSR_IS_BIT)
 112#define IA64_PSR_MC     (__IA64_UL(1) << IA64_PSR_MC_BIT)
 113#define IA64_PSR_IT     (__IA64_UL(1) << IA64_PSR_IT_BIT)
 114#define IA64_PSR_ID     (__IA64_UL(1) << IA64_PSR_ID_BIT)
 115#define IA64_PSR_DA     (__IA64_UL(1) << IA64_PSR_DA_BIT)
 116#define IA64_PSR_DD     (__IA64_UL(1) << IA64_PSR_DD_BIT)
 117#define IA64_PSR_SS     (__IA64_UL(1) << IA64_PSR_SS_BIT)
 118#define IA64_PSR_RI     (__IA64_UL(3) << IA64_PSR_RI_BIT)
 119#define IA64_PSR_ED     (__IA64_UL(1) << IA64_PSR_ED_BIT)
 120#define IA64_PSR_BN     (__IA64_UL(1) << IA64_PSR_BN_BIT)
 121
 122/* User mask bits: */
 123#define IA64_PSR_UM     (IA64_PSR_BE | IA64_PSR_UP | IA64_PSR_AC | IA64_PSR_MFL | IA64_PSR_MFH)
 124
 125/* Default Control Register */
 126#define IA64_DCR_PP_BIT          0      /* privileged performance monitor default */
 127#define IA64_DCR_BE_BIT          1      /* big-endian default */
 128#define IA64_DCR_LC_BIT          2      /* ia32 lock-check enable */
 129#define IA64_DCR_DM_BIT          8      /* defer TLB miss faults */
 130#define IA64_DCR_DP_BIT          9      /* defer page-not-present faults */
 131#define IA64_DCR_DK_BIT         10      /* defer key miss faults */
 132#define IA64_DCR_DX_BIT         11      /* defer key permission faults */
 133#define IA64_DCR_DR_BIT         12      /* defer access right faults */
 134#define IA64_DCR_DA_BIT         13      /* defer access bit faults */
 135#define IA64_DCR_DD_BIT         14      /* defer debug faults */
 136
 137#define IA64_DCR_PP     (__IA64_UL(1) << IA64_DCR_PP_BIT)
 138#define IA64_DCR_BE     (__IA64_UL(1) << IA64_DCR_BE_BIT)
 139#define IA64_DCR_LC     (__IA64_UL(1) << IA64_DCR_LC_BIT)
 140#define IA64_DCR_DM     (__IA64_UL(1) << IA64_DCR_DM_BIT)
 141#define IA64_DCR_DP     (__IA64_UL(1) << IA64_DCR_DP_BIT)
 142#define IA64_DCR_DK     (__IA64_UL(1) << IA64_DCR_DK_BIT)
 143#define IA64_DCR_DX     (__IA64_UL(1) << IA64_DCR_DX_BIT)
 144#define IA64_DCR_DR     (__IA64_UL(1) << IA64_DCR_DR_BIT)
 145#define IA64_DCR_DA     (__IA64_UL(1) << IA64_DCR_DA_BIT)
 146#define IA64_DCR_DD     (__IA64_UL(1) << IA64_DCR_DD_BIT)
 147
 148/* Interrupt Status Register */
 149#define IA64_ISR_X_BIT          32      /* execute access */
 150#define IA64_ISR_W_BIT          33      /* write access */
 151#define IA64_ISR_R_BIT          34      /* read access */
 152#define IA64_ISR_NA_BIT         35      /* non-access */
 153#define IA64_ISR_SP_BIT         36      /* speculative load exception */
 154#define IA64_ISR_RS_BIT         37      /* mandatory register-stack exception */
 155#define IA64_ISR_IR_BIT         38      /* invalid register frame exception */
 156
 157#define IA64_ISR_X      (__IA64_UL(1) << IA64_ISR_X_BIT)
 158#define IA64_ISR_W      (__IA64_UL(1) << IA64_ISR_W_BIT)
 159#define IA64_ISR_R      (__IA64_UL(1) << IA64_ISR_R_BIT)
 160#define IA64_ISR_NA     (__IA64_UL(1) << IA64_ISR_NA_BIT)
 161#define IA64_ISR_SP     (__IA64_UL(1) << IA64_ISR_SP_BIT)
 162#define IA64_ISR_RS     (__IA64_UL(1) << IA64_ISR_RS_BIT)
 163#define IA64_ISR_IR     (__IA64_UL(1) << IA64_ISR_IR_BIT)
 164
 165#define IA64_THREAD_FPH_VALID   (__IA64_UL(1) << 0)     /* floating-point high state valid? */
 166#define IA64_THREAD_DBG_VALID   (__IA64_UL(1) << 1)     /* debug registers valid? */
 167#define IA64_THREAD_PM_VALID    (__IA64_UL(1) << 2)     /* performance registers valid? */
 168#define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3)     /* don't log unaligned accesses */
 169#define IA64_THREAD_UAC_SIGBUS  (__IA64_UL(1) << 4)     /* generate SIGBUS on unaligned acc. */
 170#define IA64_THREAD_KRBS_SYNCED (__IA64_UL(1) << 5)     /* krbs synced with process vm? */
 171#define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6)   /* don't log any fpswa faults */
 172#define IA64_THREAD_FPEMU_SIGFPE  (__IA64_UL(1) << 7)   /* send a SIGFPE for fpswa faults */
 173
 174#define IA64_THREAD_UAC_SHIFT   3
 175#define IA64_THREAD_UAC_MASK    (IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS)
 176#define IA64_THREAD_FPEMU_SHIFT 6
 177#define IA64_THREAD_FPEMU_MASK  (IA64_THREAD_FPEMU_NOPRINT | IA64_THREAD_FPEMU_SIGFPE)
 178
 179
 180/*
 181 * This shift should be large enough to be able to represent
 182 * 1000000/itc_freq with good accuracy while being small enough to fit
 183 * 1000000<<IA64_USEC_PER_CYC_SHIFT in 64 bits.
 184 */
 185#define IA64_USEC_PER_CYC_SHIFT 41
 186
 187#ifndef __ASSEMBLY__
 188
 189#include <linux/threads.h>
 190
 191#include <asm/fpu.h>
 192#include <asm/offsets.h>
 193#include <asm/page.h>
 194#include <asm/rse.h>
 195#include <asm/unwind.h>
 196#include <asm/atomic.h>
 197
 198/* like above but expressed as bitfields for more efficient access: */
 199struct ia64_psr {
 200        __u64 reserved0 : 1;
 201        __u64 be : 1;
 202        __u64 up : 1;
 203        __u64 ac : 1;
 204        __u64 mfl : 1;
 205        __u64 mfh : 1;
 206        __u64 reserved1 : 7;
 207        __u64 ic : 1;
 208        __u64 i : 1;
 209        __u64 pk : 1;
 210        __u64 reserved2 : 1;
 211        __u64 dt : 1;
 212        __u64 dfl : 1;
 213        __u64 dfh : 1;
 214        __u64 sp : 1;
 215        __u64 pp : 1;
 216        __u64 di : 1;
 217        __u64 si : 1;
 218        __u64 db : 1;
 219        __u64 lp : 1;
 220        __u64 tb : 1;
 221        __u64 rt : 1;
 222        __u64 reserved3 : 4;
 223        __u64 cpl : 2;
 224        __u64 is : 1;
 225        __u64 mc : 1;
 226        __u64 it : 1;
 227        __u64 id : 1;
 228        __u64 da : 1;
 229        __u64 dd : 1;
 230        __u64 ss : 1;
 231        __u64 ri : 2;
 232        __u64 ed : 1;
 233        __u64 bn : 1;
 234        __u64 reserved4 : 19;
 235};
 236
 237/*
 238 * CPU type, hardware bug flags, and per-CPU state.  Frequently used
 239 * state comes earlier:
 240 */
 241struct cpuinfo_ia64 {
 242        /* irq_stat must be 64-bit aligned */
 243        union {
 244                struct {
 245                        __u32 irq_count;
 246                        __u32 bh_count;
 247                } f;
 248                __u64 irq_and_bh_counts;
 249        } irq_stat;
 250        __u32 softirq_pending;
 251        __u32 phys_stacked_size_p8;     /* size of physical stacked registers + 8 */
 252        __u64 itm_delta;        /* # of clock cycles between clock ticks */
 253        __u64 itm_next;         /* interval timer mask value to use for next clock tick */
 254        __u64 *pgd_quick;
 255        __u64 *pmd_quick;
 256        __u64 *pte_quick;
 257        __u64 pgtable_cache_sz;
 258        /* CPUID-derived information: */
 259        __u64 ppn;
 260        __u64 features;
 261        __u8 number;
 262        __u8 revision;
 263        __u8 model;
 264        __u8 family;
 265        __u8 archrev;
 266        char vendor[16];
 267        __u64 itc_freq;         /* frequency of ITC counter */
 268        __u64 proc_freq;        /* frequency of processor */
 269        __u64 cyc_per_usec;     /* itc_freq/1000000 */
 270        __u64 usec_per_cyc;     /* 2^IA64_USEC_PER_CYC_SHIFT*1000000/itc_freq */
 271        __u64 unimpl_va_mask;   /* mask of unimplemented virtual address bits (from PAL) */
 272        __u64 unimpl_pa_mask;   /* mask of unimplemented physical address bits (from PAL) */
 273        __u64 ptce_base;
 274        __u32 ptce_count[2];
 275        __u32 ptce_stride[2];
 276        struct task_struct *ksoftirqd;  /* kernel softirq daemon for this CPU */
 277#ifdef CONFIG_SMP
 278        __u64 loops_per_jiffy;
 279        __u64 ipi_count;
 280        __u64 prof_counter;
 281        __u64 prof_multiplier;
 282        __u64 ipi_operation;
 283#endif
 284#ifdef CONFIG_NUMA
 285        struct cpuinfo_ia64 *cpu_data[NR_CPUS];
 286#endif
 287} __attribute__ ((aligned (PAGE_SIZE))) ;
 288
 289/*
 290 * The "local" data pointer.  It points to the per-CPU data of the currently executing
 291 * CPU, much like "current" points to the per-task data of the currently executing task.
 292 */
 293#define local_cpu_data          ((struct cpuinfo_ia64 *) PERCPU_ADDR)
 294
 295/*
 296 * On NUMA systems, cpu_data for each cpu is allocated during cpu_init() & is allocated on
 297 * the node that contains the cpu. This minimizes off-node memory references.  cpu_data
 298 * for each cpu contains an array of pointers to the cpu_data structures of each of the
 299 * other cpus.
 300 *
 301 * On non-NUMA systems, cpu_data is a static array allocated at compile time.  References
 302 * to the cpu_data of another cpu is done by direct references to the appropriate entry of
 303 * the array.
 304 */
 305#ifdef CONFIG_NUMA
 306# define cpu_data(cpu)          local_cpu_data->cpu_data_ptrs[cpu]
 307#else
 308  extern struct cpuinfo_ia64 _cpu_data[NR_CPUS];
 309# define cpu_data(cpu)          (&_cpu_data[cpu])
 310#endif
 311
 312extern void identify_cpu (struct cpuinfo_ia64 *);
 313extern void print_cpu_info (struct cpuinfo_ia64 *);
 314
 315typedef struct {
 316        unsigned long seg;
 317} mm_segment_t;
 318
 319#define SET_UNALIGN_CTL(task,value)                                                             \
 320({                                                                                              \
 321        (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK)                  \
 322                                | (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK)); \
 323        0;                                                                                      \
 324})
 325#define GET_UNALIGN_CTL(task,addr)                                                              \
 326({                                                                                              \
 327        put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT,        \
 328                 (int *) (addr));                                                               \
 329})
 330
 331#define SET_FPEMU_CTL(task,value)                                                               \
 332({                                                                                              \
 333        (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_FPEMU_MASK)                \
 334                          | (((value) << IA64_THREAD_FPEMU_SHIFT) & IA64_THREAD_FPEMU_MASK));   \
 335        0;                                                                                      \
 336})
 337#define GET_FPEMU_CTL(task,addr)                                                                \
 338({                                                                                              \
 339        put_user(((task)->thread.flags & IA64_THREAD_FPEMU_MASK) >> IA64_THREAD_FPEMU_SHIFT,    \
 340                 (int *) (addr));                                                               \
 341})
 342
 343struct siginfo;
 344
 345struct thread_struct {
 346        __u64 ksp;                      /* kernel stack pointer */
 347        unsigned long flags;            /* various flags */
 348        __u64 map_base;                 /* base address for get_unmapped_area() */
 349        __u64 task_size;                /* limit for task size */
 350        struct siginfo *siginfo;        /* current siginfo struct for ptrace() */
 351
 352#ifdef CONFIG_IA32_SUPPORT
 353        __u64 eflag;                    /* IA32 EFLAGS reg */
 354        __u64 fsr;                      /* IA32 floating pt status reg */
 355        __u64 fcr;                      /* IA32 floating pt control reg */
 356        __u64 fir;                      /* IA32 fp except. instr. reg */
 357        __u64 fdr;                      /* IA32 fp except. data reg */
 358        __u64 csd;                      /* IA32 code selector descriptor */
 359        __u64 ssd;                      /* IA32 stack selector descriptor */
 360        __u64 old_k1;                   /* old value of ar.k1 */
 361        __u64 old_iob;                  /* old IOBase value */
 362# define INIT_THREAD_IA32       0, 0, 0x17800000037fULL, 0, 0, 0, 0, 0, 0,
 363#else
 364# define INIT_THREAD_IA32
 365#endif /* CONFIG_IA32_SUPPORT */
 366#ifdef CONFIG_PERFMON
 367        __u64 pmc[IA64_NUM_PMC_REGS];
 368        __u64 pmd[IA64_NUM_PMD_REGS];
 369        unsigned long pfm_must_block;   /* non-zero if we need to block on overflow */
 370        void *pfm_context;              /* pointer to detailed PMU context */
 371        atomic_t pfm_notifiers_check;   /* indicate if release_thread much check tasklist */
 372# define INIT_THREAD_PM         {0, }, {0, }, 0, 0, {0},
 373#else
 374# define INIT_THREAD_PM
 375#endif
 376        __u64 dbr[IA64_NUM_DBG_REGS];
 377        __u64 ibr[IA64_NUM_DBG_REGS];
 378        struct ia64_fpreg fph[96];      /* saved/loaded on demand */
 379};
 380
 381#define INIT_THREAD {                                   \
 382        0,                              /* ksp */       \
 383        0,                              /* flags */     \
 384        DEFAULT_MAP_BASE,               /* map_base */  \
 385        DEFAULT_TASK_SIZE,              /* task_size */ \
 386        0,                              /* siginfo */   \
 387        INIT_THREAD_IA32                                \
 388        INIT_THREAD_PM                                  \
 389        {0, },                          /* dbr */       \
 390        {0, },                          /* ibr */       \
 391        {{{{0}}}, }                     /* fph */       \
 392}
 393
 394#define start_thread(regs,new_ip,new_sp) do {                                                   \
 395        set_fs(USER_DS);                                                                        \
 396        ia64_psr(regs)->dfh = 1;        /* disable fph */                                       \
 397        ia64_psr(regs)->mfh = 0;        /* clear mfh */                                         \
 398        ia64_psr(regs)->cpl = 3;        /* set user mode */                                     \
 399        ia64_psr(regs)->ri = 0;         /* clear return slot number */                          \
 400        ia64_psr(regs)->is = 0;         /* IA-64 instruction set */                             \
 401        regs->cr_iip = new_ip;                                                                  \
 402        regs->ar_rsc = 0xf;             /* eager mode, privilege level 3 */                     \
 403        regs->ar_rnat = 0;                                                                      \
 404        regs->ar_bspstore = IA64_RBS_BOT;                                                       \
 405        regs->ar_fpsr = FPSR_DEFAULT;                                                           \
 406        regs->loadrs = 0;                                                                       \
 407        regs->r8 = current->mm->dumpable;       /* set "don't zap registers" flag */            \
 408        regs->r12 = new_sp - 16;        /* allocate 16 byte scratch area */                     \
 409        if (!__builtin_expect (current->mm->dumpable, 1)) {                                     \
 410                /*                                                                              \
 411                 * Zap scratch regs to avoid leaking bits between processes with different      \
 412                 * uid/privileges.                                                              \
 413                 */                                                                             \
 414                regs->ar_pfs = 0;                                                               \
 415                regs->pr = 0;                                                                   \
 416                /*                                                                              \
 417                 * XXX fix me: everything below can go away once we stop preserving scratch     \
 418                 * regs on a system call.                                                       \
 419                 */                                                                             \
 420                regs->b6 = 0;                                                                   \
 421                regs->r1 = 0; regs->r2 = 0; regs->r3 = 0;                                       \
 422                regs->r13 = 0; regs->r14 = 0; regs->r15 = 0;                                    \
 423                regs->r9  = 0; regs->r11 = 0;                                                   \
 424                regs->r16 = 0; regs->r17 = 0; regs->r18 = 0; regs->r19 = 0;                     \
 425                regs->r20 = 0; regs->r21 = 0; regs->r22 = 0; regs->r23 = 0;                     \
 426                regs->r24 = 0; regs->r25 = 0; regs->r26 = 0; regs->r27 = 0;                     \
 427                regs->r28 = 0; regs->r29 = 0; regs->r30 = 0; regs->r31 = 0;                     \
 428                regs->ar_ccv = 0;                                                               \
 429                regs->b0 = 0; regs->b7 = 0;                                                     \
 430                regs->f6.u.bits[0] = 0; regs->f6.u.bits[1] = 0;                                 \
 431                regs->f7.u.bits[0] = 0; regs->f7.u.bits[1] = 0;                                 \
 432                regs->f8.u.bits[0] = 0; regs->f8.u.bits[1] = 0;                                 \
 433                regs->f9.u.bits[0] = 0; regs->f9.u.bits[1] = 0;                                 \
 434        }                                                                                       \
 435} while (0)
 436
 437/* Forward declarations, a strange C thing... */
 438struct mm_struct;
 439struct task_struct;
 440
 441/*
 442 * Free all resources held by a thread. This is called after the
 443 * parent of DEAD_TASK has collected the exist status of the task via
 444 * wait().
 445 */
 446#ifdef CONFIG_PERFMON
 447  extern void release_thread (struct task_struct *task);
 448#else
 449# define release_thread(dead_task)
 450#endif
 451
 452/*
 453 * This is the mechanism for creating a new kernel thread.
 454 *
 455 * NOTE 1: Only a kernel-only process (ie the swapper or direct
 456 * descendants who haven't done an "execve()") should use this: it
 457 * will work within a system call from a "real" process, but the
 458 * process memory space will not be free'd until both the parent and
 459 * the child have exited.
 460 *
 461 * NOTE 2: This MUST NOT be an inlined function.  Otherwise, we get
 462 * into trouble in init/main.c when the child thread returns to
 463 * do_basic_setup() and the timing is such that free_initmem() has
 464 * been called already.
 465 */
 466extern int kernel_thread (int (*fn)(void *), void *arg, unsigned long flags);
 467
 468/* Copy and release all segment info associated with a VM */
 469#define copy_segments(tsk, mm)                  do { } while (0)
 470#define release_segments(mm)                    do { } while (0)
 471
 472/* Get wait channel for task P.  */
 473extern unsigned long get_wchan (struct task_struct *p);
 474
 475/* Return instruction pointer of blocked task TSK.  */
 476#define KSTK_EIP(tsk)                                   \
 477  ({                                                    \
 478        struct pt_regs *_regs = ia64_task_regs(tsk);    \
 479        _regs->cr_iip + ia64_psr(_regs)->ri;            \
 480  })
 481
 482/* Return stack pointer of blocked task TSK.  */
 483#define KSTK_ESP(tsk)  ((tsk)->thread.ksp)
 484
 485static inline unsigned long
 486ia64_get_kr (unsigned long regnum)
 487{
 488        unsigned long r;
 489
 490        switch (regnum) {
 491              case 0: asm volatile ("mov %0=ar.k0" : "=r"(r)); break;
 492              case 1: asm volatile ("mov %0=ar.k1" : "=r"(r)); break;
 493              case 2: asm volatile ("mov %0=ar.k2" : "=r"(r)); break;
 494              case 3: asm volatile ("mov %0=ar.k3" : "=r"(r)); break;
 495              case 4: asm volatile ("mov %0=ar.k4" : "=r"(r)); break;
 496              case 5: asm volatile ("mov %0=ar.k5" : "=r"(r)); break;
 497              case 6: asm volatile ("mov %0=ar.k6" : "=r"(r)); break;
 498              case 7: asm volatile ("mov %0=ar.k7" : "=r"(r)); break;
 499        }
 500        return r;
 501}
 502
 503static inline void
 504ia64_set_kr (unsigned long regnum, unsigned long r)
 505{
 506        switch (regnum) {
 507              case 0: asm volatile ("mov ar.k0=%0" :: "r"(r)); break;
 508              case 1: asm volatile ("mov ar.k1=%0" :: "r"(r)); break;
 509              case 2: asm volatile ("mov ar.k2=%0" :: "r"(r)); break;
 510              case 3: asm volatile ("mov ar.k3=%0" :: "r"(r)); break;
 511              case 4: asm volatile ("mov ar.k4=%0" :: "r"(r)); break;
 512              case 5: asm volatile ("mov ar.k5=%0" :: "r"(r)); break;
 513              case 6: asm volatile ("mov ar.k6=%0" :: "r"(r)); break;
 514              case 7: asm volatile ("mov ar.k7=%0" :: "r"(r)); break;
 515        }
 516}
 517
 518#ifndef CONFIG_SMP
 519
 520static inline struct task_struct *
 521ia64_get_fpu_owner (void)
 522{
 523        return (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER);
 524}
 525
 526static inline void
 527ia64_set_fpu_owner (struct task_struct *t)
 528{
 529        ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) t);
 530}
 531
 532#endif /* !CONFIG_SMP */
 533
 534extern void __ia64_init_fpu (void);
 535extern void __ia64_save_fpu (struct ia64_fpreg *fph);
 536extern void __ia64_load_fpu (struct ia64_fpreg *fph);
 537extern void ia64_save_debug_regs (unsigned long *save_area);
 538extern void ia64_load_debug_regs (unsigned long *save_area);
 539
 540#ifdef CONFIG_IA32_SUPPORT
 541extern void ia32_save_state (struct task_struct *task);
 542extern void ia32_load_state (struct task_struct *task);
 543#endif
 544
 545#ifdef CONFIG_PERFMON
 546extern void ia64_save_pm_regs (struct task_struct *task);
 547extern void ia64_load_pm_regs (struct task_struct *task);
 548#endif
 549
 550#define ia64_fph_enable()       asm volatile (";; rsm psr.dfh;; srlz.d;;" ::: "memory");
 551#define ia64_fph_disable()      asm volatile (";; ssm psr.dfh;; srlz.d;;" ::: "memory");
 552
 553/* load fp 0.0 into fph */
 554static inline void
 555ia64_init_fpu (void) {
 556        ia64_fph_enable();
 557        __ia64_init_fpu();
 558        ia64_fph_disable();
 559}
 560
 561/* save f32-f127 at FPH */
 562static inline void
 563ia64_save_fpu (struct ia64_fpreg *fph) {
 564        ia64_fph_enable();
 565        __ia64_save_fpu(fph);
 566        ia64_fph_disable();
 567}
 568
 569/* load f32-f127 from FPH */
 570static inline void
 571ia64_load_fpu (struct ia64_fpreg *fph) {
 572        ia64_fph_enable();
 573        __ia64_load_fpu(fph);
 574        ia64_fph_disable();
 575}
 576
 577static inline void
 578ia64_fc (void *addr)
 579{
 580        asm volatile ("fc %0" :: "r"(addr) : "memory");
 581}
 582
 583static inline void
 584ia64_sync_i (void)
 585{
 586        asm volatile (";; sync.i" ::: "memory");
 587}
 588
 589static inline void
 590ia64_srlz_i (void)
 591{
 592        asm volatile (";; srlz.i ;;" ::: "memory");
 593}
 594
 595static inline void
 596ia64_srlz_d (void)
 597{
 598        asm volatile (";; srlz.d" ::: "memory");
 599}
 600
 601static inline __u64
 602ia64_get_rr (__u64 reg_bits)
 603{
 604        __u64 r;
 605        asm volatile ("mov %0=rr[%1]" : "=r"(r) : "r"(reg_bits) : "memory");
 606        return r;
 607}
 608
 609static inline void
 610ia64_set_rr (__u64 reg_bits, __u64 rr_val)
 611{
 612        asm volatile ("mov rr[%0]=%1" :: "r"(reg_bits), "r"(rr_val) : "memory");
 613}
 614
 615static inline __u64
 616ia64_get_dcr (void)
 617{
 618        __u64 r;
 619        asm volatile ("mov %0=cr.dcr" : "=r"(r));
 620        return r;
 621}
 622
 623static inline void
 624ia64_set_dcr (__u64 val)
 625{
 626        asm volatile ("mov cr.dcr=%0;;" :: "r"(val) : "memory");
 627        ia64_srlz_d();
 628}
 629
 630static inline __u64
 631ia64_get_lid (void)
 632{
 633        __u64 r;
 634        asm volatile ("mov %0=cr.lid" : "=r"(r));
 635        return r;
 636}
 637
 638static inline void
 639ia64_invala (void)
 640{
 641        asm volatile ("invala" ::: "memory");
 642}
 643
 644/*
 645 * Save the processor status flags in FLAGS and then clear the interrupt collection and
 646 * interrupt enable bits.  Don't trigger any mandatory RSE references while this bit is
 647 * off!
 648 */
 649#define ia64_clear_ic(flags)                                            \
 650        asm volatile ("mov %0=psr;; rsm psr.i | psr.ic;; srlz.i;;"      \
 651                              : "=r"(flags) :: "memory");
 652
 653/*
 654 * Insert a translation into an instruction and/or data translation
 655 * register.
 656 */
 657static inline void
 658ia64_itr (__u64 target_mask, __u64 tr_num,
 659          __u64 vmaddr, __u64 pte,
 660          __u64 log_page_size)
 661{
 662        asm volatile ("mov cr.itir=%0" :: "r"(log_page_size << 2) : "memory");
 663        asm volatile ("mov cr.ifa=%0;;" :: "r"(vmaddr) : "memory");
 664        if (target_mask & 0x1)
 665                asm volatile ("itr.i itr[%0]=%1"
 666                                      :: "r"(tr_num), "r"(pte) : "memory");
 667        if (target_mask & 0x2)
 668                asm volatile (";;itr.d dtr[%0]=%1"
 669                                      :: "r"(tr_num), "r"(pte) : "memory");
 670}
 671
 672/*
 673 * Insert a translation into the instruction and/or data translation
 674 * cache.
 675 */
 676static inline void
 677ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte,
 678          __u64 log_page_size)
 679{
 680        asm volatile ("mov cr.itir=%0" :: "r"(log_page_size << 2) : "memory");
 681        asm volatile ("mov cr.ifa=%0;;" :: "r"(vmaddr) : "memory");
 682        /* as per EAS2.6, itc must be the last instruction in an instruction group */
 683        if (target_mask & 0x1)
 684                asm volatile ("itc.i %0;;" :: "r"(pte) : "memory");
 685        if (target_mask & 0x2)
 686                asm volatile (";;itc.d %0;;" :: "r"(pte) : "memory");
 687}
 688
 689/*
 690 * Purge a range of addresses from instruction and/or data translation
 691 * register(s).
 692 */
 693static inline void
 694ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size)
 695{
 696        if (target_mask & 0x1)
 697                asm volatile ("ptr.i %0,%1" :: "r"(vmaddr), "r"(log_size << 2));
 698        if (target_mask & 0x2)
 699                asm volatile ("ptr.d %0,%1" :: "r"(vmaddr), "r"(log_size << 2));
 700}
 701
 702/* Set the interrupt vector address.  The address must be suitably aligned (32KB).  */
 703static inline void
 704ia64_set_iva (void *ivt_addr)
 705{
 706        asm volatile ("mov cr.iva=%0;; srlz.i;;" :: "r"(ivt_addr) : "memory");
 707}
 708
 709/* Set the page table address and control bits.  */
 710static inline void
 711ia64_set_pta (__u64 pta)
 712{
 713        /* Note: srlz.i implies srlz.d */
 714        asm volatile ("mov cr.pta=%0;; srlz.i;;" :: "r"(pta) : "memory");
 715}
 716
 717static inline __u64
 718ia64_get_cpuid (__u64 regnum)
 719{
 720        __u64 r;
 721
 722        asm ("mov %0=cpuid[%r1]" : "=r"(r) : "rO"(regnum));
 723        return r;
 724}
 725
 726static inline void
 727ia64_eoi (void)
 728{
 729        asm ("mov cr.eoi=r0;; srlz.d;;" ::: "memory");
 730}
 731
 732static inline void
 733ia64_set_lrr0 (unsigned long val)
 734{
 735        asm volatile ("mov cr.lrr0=%0;; srlz.d" :: "r"(val) : "memory");
 736}
 737
 738#define cpu_relax()     do { } while (0)
 739
 740
 741static inline void
 742ia64_set_lrr1 (unsigned long val)
 743{
 744        asm volatile ("mov cr.lrr1=%0;; srlz.d" :: "r"(val) : "memory");
 745}
 746
 747static inline void
 748ia64_set_pmv (__u64 val)
 749{
 750        asm volatile ("mov cr.pmv=%0" :: "r"(val) : "memory");
 751}
 752
 753static inline __u64
 754ia64_get_pmc (__u64 regnum)
 755{
 756        __u64 retval;
 757
 758        asm volatile ("mov %0=pmc[%1]" : "=r"(retval) : "r"(regnum));
 759        return retval;
 760}
 761
 762static inline void
 763ia64_set_pmc (__u64 regnum, __u64 value)
 764{
 765        asm volatile ("mov pmc[%0]=%1" :: "r"(regnum), "r"(value));
 766}
 767
 768static inline __u64
 769ia64_get_pmd (__u64 regnum)
 770{
 771        __u64 retval;
 772
 773        asm volatile ("mov %0=pmd[%1]" : "=r"(retval) : "r"(regnum));
 774        return retval;
 775}
 776
 777static inline void
 778ia64_set_pmd (__u64 regnum, __u64 value)
 779{
 780        asm volatile ("mov pmd[%0]=%1" :: "r"(regnum), "r"(value));
 781}
 782
 783/*
 784 * Given the address to which a spill occurred, return the unat bit
 785 * number that corresponds to this address.
 786 */
 787static inline __u64
 788ia64_unat_pos (void *spill_addr)
 789{
 790        return ((__u64) spill_addr >> 3) & 0x3f;
 791}
 792
 793/*
 794 * Set the NaT bit of an integer register which was spilled at address
 795 * SPILL_ADDR.  UNAT is the mask to be updated.
 796 */
 797static inline void
 798ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat)
 799{
 800        __u64 bit = ia64_unat_pos(spill_addr);
 801        __u64 mask = 1UL << bit;
 802
 803        *unat = (*unat & ~mask) | (nat << bit);
 804}
 805
 806/*
 807 * Return saved PC of a blocked thread.
 808 * Note that the only way T can block is through a call to schedule() -> switch_to().
 809 */
 810static inline unsigned long
 811thread_saved_pc (struct thread_struct *t)
 812{
 813        struct unw_frame_info info;
 814        unsigned long ip;
 815
 816        /* XXX ouch: Linus, please pass the task pointer to thread_saved_pc() instead! */
 817        struct task_struct *p = (void *) ((unsigned long) t - IA64_TASK_THREAD_OFFSET);
 818
 819        unw_init_from_blocked_task(&info, p);
 820        if (unw_unwind(&info) < 0)
 821                return 0;
 822        unw_get_ip(&info, &ip);
 823        return ip;
 824}
 825
 826/*
 827 * Get the current instruction/program counter value.
 828 */
 829#define current_text_addr() \
 830        ({ void *_pc; asm volatile ("mov %0=ip" : "=r" (_pc)); _pc; })
 831
 832#define THREAD_SIZE     IA64_STK_OFFSET
 833/* NOTE: The task struct and the stacks are allocated together.  */
 834#define alloc_task_struct() \
 835        ((struct task_struct *) __get_free_pages(GFP_KERNEL, IA64_TASK_STRUCT_LOG_NUM_PAGES))
 836#define free_task_struct(p)     free_pages((unsigned long)(p), IA64_TASK_STRUCT_LOG_NUM_PAGES)
 837#define get_task_struct(tsk)    atomic_inc(&virt_to_page(tsk)->count)
 838
 839#define init_task       (init_task_union.task)
 840#define init_stack      (init_task_union.stack)
 841
 842/*
 843 * Set the correctable machine check vector register
 844 */
 845static inline void
 846ia64_set_cmcv (__u64 val)
 847{
 848        asm volatile ("mov cr.cmcv=%0" :: "r"(val) : "memory");
 849}
 850
 851/*
 852 * Read the correctable machine check vector register
 853 */
 854static inline __u64
 855ia64_get_cmcv (void)
 856{
 857        __u64 val;
 858
 859        asm volatile ("mov %0=cr.cmcv" : "=r"(val) :: "memory");
 860        return val;
 861}
 862
 863static inline __u64
 864ia64_get_ivr (void)
 865{
 866        __u64 r;
 867        asm volatile ("srlz.d;; mov %0=cr.ivr;; srlz.d;;" : "=r"(r));
 868        return r;
 869}
 870
 871static inline void
 872ia64_set_tpr (__u64 val)
 873{
 874        asm volatile ("mov cr.tpr=%0" :: "r"(val));
 875}
 876
 877static inline __u64
 878ia64_get_tpr (void)
 879{
 880        __u64 r;
 881        asm volatile ("mov %0=cr.tpr" : "=r"(r));
 882        return r;
 883}
 884
 885static inline void
 886ia64_set_irr0 (__u64 val)
 887{
 888        asm volatile("mov cr.irr0=%0;;" :: "r"(val) : "memory");
 889        ia64_srlz_d();
 890}
 891
 892static inline __u64
 893ia64_get_irr0 (void)
 894{
 895        __u64 val;
 896
 897        /* this is volatile because irr may change unbeknownst to gcc... */
 898        asm volatile("mov %0=cr.irr0" : "=r"(val));
 899        return val;
 900}
 901
 902static inline void
 903ia64_set_irr1 (__u64 val)
 904{
 905        asm volatile("mov cr.irr1=%0;;" :: "r"(val) : "memory");
 906        ia64_srlz_d();
 907}
 908
 909static inline __u64
 910ia64_get_irr1 (void)
 911{
 912        __u64 val;
 913
 914        /* this is volatile because irr may change unbeknownst to gcc... */
 915        asm volatile("mov %0=cr.irr1" : "=r"(val));
 916        return val;
 917}
 918
 919static inline void
 920ia64_set_irr2 (__u64 val)
 921{
 922        asm volatile("mov cr.irr2=%0;;" :: "r"(val) : "memory");
 923        ia64_srlz_d();
 924}
 925
 926static inline __u64
 927ia64_get_irr2 (void)
 928{
 929        __u64 val;
 930
 931        /* this is volatile because irr may change unbeknownst to gcc... */
 932        asm volatile("mov %0=cr.irr2" : "=r"(val));
 933        return val;
 934}
 935
 936static inline void
 937ia64_set_irr3 (__u64 val)
 938{
 939        asm volatile("mov cr.irr3=%0;;" :: "r"(val) : "memory");
 940        ia64_srlz_d();
 941}
 942
 943static inline __u64
 944ia64_get_irr3 (void)
 945{
 946        __u64 val;
 947
 948        /* this is volatile because irr may change unbeknownst to gcc... */
 949        asm volatile ("mov %0=cr.irr3" : "=r"(val));
 950        return val;
 951}
 952
 953static inline __u64
 954ia64_get_gp(void)
 955{
 956        __u64 val;
 957
 958        asm ("mov %0=gp" : "=r"(val));
 959        return val;
 960}
 961
 962static inline void
 963ia64_set_ibr (__u64 regnum, __u64 value)
 964{
 965        asm volatile ("mov ibr[%0]=%1" :: "r"(regnum), "r"(value));
 966}
 967
 968static inline void
 969ia64_set_dbr (__u64 regnum, __u64 value)
 970{
 971        asm volatile ("mov dbr[%0]=%1" :: "r"(regnum), "r"(value));
 972#ifdef CONFIG_ITANIUM
 973        asm volatile (";; srlz.d");
 974#endif
 975}
 976
 977static inline __u64
 978ia64_get_ibr (__u64 regnum)
 979{
 980        __u64 retval;
 981
 982        asm volatile ("mov %0=ibr[%1]" : "=r"(retval) : "r"(regnum));
 983        return retval;
 984}
 985
 986static inline __u64
 987ia64_get_dbr (__u64 regnum)
 988{
 989        __u64 retval;
 990
 991        asm volatile ("mov %0=dbr[%1]" : "=r"(retval) : "r"(regnum));
 992#ifdef CONFIG_ITANIUM
 993        asm volatile (";; srlz.d");
 994#endif
 995        return retval;
 996}
 997
 998/* XXX remove the handcoded version once we have a sufficiently clever compiler... */
 999#ifdef SMART_COMPILER
1000# define ia64_rotr(w,n)                         \

1001  ({                                            \
1002        __u64 _w = (w), _n = (n);               \
1003                                                \
1004        (_w >> _n) | (_w << (64 - _n));         \
1005  })
1006#else
1007# define ia64_rotr(w,n)                                                 \
1008  ({                                                                    \
1009        __u64 result;                                                   \
1010        asm ("shrp %0=%1,%1,%2" : "=r"(result) : "r"(w), "i"(n));       \
1011        result;                                                         \
1012  })
1013#endif
1014
1015#define ia64_rotl(w,n)  ia64_rotr((w),(64)-(n))
1016
1017static inline __u64
1018ia64_thash (__u64 addr)
1019{
1020        __u64 result;
1021        asm ("thash %0=%1" : "=r"(result) : "r" (addr));
1022        return result;
1023}
1024
1025static inline __u64
1026ia64_tpa (__u64 addr)
1027{
1028        __u64 result;
1029        asm ("tpa %0=%1" : "=r"(result) : "r"(addr));
1030        return result;
1031}
1032
1033#define ARCH_HAS_PREFETCH
1034#define ARCH_HAS_PREFETCHW
1035#define ARCH_HAS_SPINLOCK_PREFETCH
1036#define PREFETCH_STRIDE 256
1037
1038extern inline void
1039prefetch (const void *x)
1040{
1041         __asm__ __volatile__ ("lfetch [%0]" : : "r"(x));
1042}
1043
1044extern inline void
1045prefetchw (const void *x)
1046{
1047        __asm__ __volatile__ ("lfetch.excl [%0]" : : "r"(x));
1048}
1049
1050#define spin_lock_prefetch(x)   prefetchw(x)
1051
1052#endif /* !__ASSEMBLY__ */
1053
1054#endif /* _ASM_IA64_PROCESSOR_H */
1055