LXR linux-old/drivers/char/agp/agp.h

   1/*
   2 * AGPGART module version 0.99
   3 * Copyright (C) 1999 Jeff Hartmann
   4 * Copyright (C) 1999 Precision Insight, Inc.
   5 * Copyright (C) 1999 Xi Graphics, Inc.
   6 *
   7 * Permission is hereby granted, free of charge, to any person obtaining a
   8 * copy of this software and associated documentation files (the "Software"),
   9 * to deal in the Software without restriction, including without limitation
  10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11 * and/or sell copies of the Software, and to permit persons to whom the
  12 * Software is furnished to do so, subject to the following conditions:
  13 *
  14 * The above copyright notice and this permission notice shall be included
  15 * in all copies or substantial portions of the Software.
  16 *
  17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20 * JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, 
  21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 
  22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE 
  23 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24 *
  25 */
  26
  27#ifndef _AGP_BACKEND_PRIV_H
  28#define _AGP_BACKEND_PRIV_H 1
  29
  30enum aper_size_type {
  31        U8_APER_SIZE,
  32        U16_APER_SIZE,
  33        U32_APER_SIZE,
  34        LVL2_APER_SIZE,
  35        FIXED_APER_SIZE
  36};
  37
  38typedef struct _gatt_mask {
  39        unsigned long mask;
  40        u32 type;
  41        /* totally device specific, for integrated chipsets that 
  42         * might have different types of memory masks.  For other
  43         * devices this will probably be ignored */
  44} gatt_mask;
  45
  46typedef struct _aper_size_info_8 {
  47        int size;
  48        int num_entries;
  49        int page_order;
  50        u8 size_value;
  51} aper_size_info_8;
  52
  53typedef struct _aper_size_info_16 {
  54        int size;
  55        int num_entries;
  56        int page_order;
  57        u16 size_value;
  58} aper_size_info_16;
  59
  60typedef struct _aper_size_info_32 {
  61        int size;
  62        int num_entries;
  63        int page_order;
  64        u32 size_value;
  65} aper_size_info_32;
  66
  67typedef struct _aper_size_info_lvl2 {
  68        int size;
  69        int num_entries;
  70        u32 size_value;
  71} aper_size_info_lvl2;
  72
  73typedef struct _aper_size_info_fixed {
  74        int size;
  75        int num_entries;
  76        int page_order;
  77} aper_size_info_fixed;
  78
  79struct agp_bridge_data {
  80        agp_version *version;
  81        void *aperture_sizes;
  82        void *previous_size;
  83        void *current_size;
  84        void *dev_private_data;
  85        struct pci_dev *dev;
  86        gatt_mask *masks;
  87        unsigned long *gatt_table;
  88        unsigned long *gatt_table_real;
  89        unsigned long scratch_page;
  90        unsigned long gart_bus_addr;
  91        unsigned long gatt_bus_addr;
  92        u32 mode;
  93        enum chipset_type type;
  94        enum aper_size_type size_type;
  95        unsigned long *key_list;
  96        atomic_t current_memory_agp;
  97        atomic_t agp_in_use;
  98        int max_memory_agp;     /* in number of pages */
  99        int needs_scratch_page;
 100        int aperture_size_idx;
 101        int num_aperture_sizes;
 102        int num_of_masks;
 103        int capndx;
 104        int cant_use_aperture;
 105
 106        /* Links to driver specific functions */
 107
 108        int (*fetch_size) (void);
 109        int (*configure) (void);
 110        void (*agp_enable) (u32);
 111        void (*cleanup) (void);
 112        void (*tlb_flush) (agp_memory *);
 113        unsigned long (*mask_memory) (unsigned long, int);
 114        void (*cache_flush) (void);
 115        int (*create_gatt_table) (void);
 116        int (*free_gatt_table) (void);
 117        int (*insert_memory) (agp_memory *, off_t, int);
 118        int (*remove_memory) (agp_memory *, off_t, int);
 119        agp_memory *(*alloc_by_type) (size_t, int);
 120        void (*free_by_type) (agp_memory *);
 121        unsigned long (*agp_alloc_page) (void);
 122        void (*agp_destroy_page) (unsigned long);
 123        int (*suspend)(void);
 124        void (*resume)(void);
 125        
 126};
 127
 128#define OUTREG32(mmap, addr, val)   __raw_writel((val), (mmap)+(addr))
 129#define OUTREG16(mmap, addr, val)   __raw_writew((val), (mmap)+(addr))
 130#define OUTREG8(mmap, addr, val)   __raw_writeb((val), (mmap)+(addr))
 131
 132#define INREG32(mmap, addr)         __raw_readl((mmap)+(addr))
 133#define INREG16(mmap, addr)         __raw_readw((mmap)+(addr))
 134#define INREG8(mmap, addr)         __raw_readb((mmap)+(addr))
 135
 136#define KB(x) ((x) * 1024)
 137#define MB(x) (KB (KB (x)))
 138#define GB(x) (MB (KB (x)))
 139
 140#define CACHE_FLUSH     agp_bridge.cache_flush
 141#define A_SIZE_8(x)     ((aper_size_info_8 *) x)
 142#define A_SIZE_16(x)    ((aper_size_info_16 *) x)
 143#define A_SIZE_32(x)    ((aper_size_info_32 *) x)
 144#define A_SIZE_LVL2(x)  ((aper_size_info_lvl2 *) x)
 145#define A_SIZE_FIX(x)   ((aper_size_info_fixed *) x)
 146#define A_IDX8()        (A_SIZE_8(agp_bridge.aperture_sizes) + i)
 147#define A_IDX16()       (A_SIZE_16(agp_bridge.aperture_sizes) + i)
 148#define A_IDX32()       (A_SIZE_32(agp_bridge.aperture_sizes) + i)
 149#define A_IDXLVL2()     (A_SIZE_LVL2(agp_bridge.aperture_sizes) + i)
 150#define A_IDXFIX()      (A_SIZE_FIX(agp_bridge.aperture_sizes) + i)
 151#define MAXKEY          (4096 * 32)
 152
 153#define AGPGART_MODULE_NAME     "agpgart"
 154#define PFX                     AGPGART_MODULE_NAME ": "
 155
 156#define PGE_EMPTY(p) (!(p) || (p) == (unsigned long) agp_bridge.scratch_page)
 157
 158#ifndef PCI_DEVICE_ID_VIA_82C691_0
 159#define PCI_DEVICE_ID_VIA_82C691_0      0x0691
 160#endif
 161#ifndef PCI_DEVICE_ID_VIA_8371_0
 162#define PCI_DEVICE_ID_VIA_8371_0      0x0391
 163#endif
 164#ifndef PCI_DEVICE_ID_VIA_8363_0
 165#define PCI_DEVICE_ID_VIA_8363_0      0x0305
 166#endif
 167#ifndef PCI_DEVICE_ID_VIA_82C694X_0
 168#define PCI_DEVICE_ID_VIA_82C694X_0      0x0605
 169#endif
 170#ifndef PCI_DEVICE_ID_INTEL_810_0
 171#define PCI_DEVICE_ID_INTEL_810_0       0x7120
 172#endif
 173#ifndef PCI_DEVICE_ID_INTEL_830_M_0
 174#define PCI_DEVICE_ID_INTEL_830_M_0     0x3575
 175#endif
 176#ifndef PCI_DEVICE_ID_INTEL_830_M_1
 177#define PCI_DEVICE_ID_INTEL_830_M_1     0x3577
 178#endif
 179#ifndef PCI_DEVICE_ID_INTEL_820_0
 180#define PCI_DEVICE_ID_INTEL_820_0       0x2500
 181#endif
 182#ifndef PCI_DEVICE_ID_INTEL_820_UP_0
 183#define PCI_DEVICE_ID_INTEL_820_UP_0    0x2501
 184#endif
 185#ifndef PCI_DEVICE_ID_INTEL_840_0
 186#define PCI_DEVICE_ID_INTEL_840_0               0x1a21
 187#endif
 188#ifndef PCI_DEVICE_ID_INTEL_845_0
 189#define PCI_DEVICE_ID_INTEL_845_0     0x1a30
 190#endif
 191#ifndef PCI_DEVICE_ID_INTEL_850_0
 192#define PCI_DEVICE_ID_INTEL_850_0     0x2530
 193#endif
 194#ifndef PCI_DEVICE_ID_INTEL_860_0
 195#define PCI_DEVICE_ID_INTEL_860_0     0x2531
 196#endif
 197#ifndef PCI_DEVICE_ID_INTEL_810_DC100_0
 198#define PCI_DEVICE_ID_INTEL_810_DC100_0 0x7122
 199#endif
 200#ifndef PCI_DEVICE_ID_INTEL_810_E_0
 201#define PCI_DEVICE_ID_INTEL_810_E_0     0x7124
 202#endif
 203#ifndef PCI_DEVICE_ID_INTEL_82443GX_0
 204#define PCI_DEVICE_ID_INTEL_82443GX_0   0x71a0
 205#endif
 206#ifndef PCI_DEVICE_ID_INTEL_810_1
 207#define PCI_DEVICE_ID_INTEL_810_1       0x7121
 208#endif
 209#ifndef PCI_DEVICE_ID_INTEL_810_DC100_1
 210#define PCI_DEVICE_ID_INTEL_810_DC100_1 0x7123
 211#endif
 212#ifndef PCI_DEVICE_ID_INTEL_810_E_1
 213#define PCI_DEVICE_ID_INTEL_810_E_1     0x7125
 214#endif
 215#ifndef PCI_DEVICE_ID_INTEL_815_0
 216#define PCI_DEVICE_ID_INTEL_815_0       0x1130
 217#endif
 218#ifndef PCI_DEVICE_ID_INTEL_815_1
 219#define PCI_DEVICE_ID_INTEL_815_1       0x1132
 220#endif
 221#ifndef PCI_DEVICE_ID_INTEL_82443GX_1
 222#define PCI_DEVICE_ID_INTEL_82443GX_1   0x71a1
 223#endif
 224#ifndef PCI_DEVICE_ID_AMD_IRONGATE_0
 225#define PCI_DEVICE_ID_AMD_IRONGATE_0    0x7006
 226#endif
 227#ifndef PCI_DEVICE_ID_AMD_761_0
 228#define PCI_DEVICE_ID_AMD_761_0         0x700e
 229#endif
 230#ifndef PCI_DEVICE_ID_AMD_762_0
 231#define PCI_DEVICE_ID_AMD_762_0         0x700C
 232#endif
 233#ifndef PCI_VENDOR_ID_AL
 234#define PCI_VENDOR_ID_AL                0x10b9
 235#endif
 236#ifndef PCI_DEVICE_ID_AL_M1541_0
 237#define PCI_DEVICE_ID_AL_M1541_0        0x1541
 238#endif
 239#ifndef PCI_DEVICE_ID_AL_M1621_0
 240#define PCI_DEVICE_ID_AL_M1621_0        0x1621
 241#endif
 242#ifndef PCI_DEVICE_ID_AL_M1631_0
 243#define PCI_DEVICE_ID_AL_M1631_0        0x1631
 244#endif
 245#ifndef PCI_DEVICE_ID_AL_M1632_0
 246#define PCI_DEVICE_ID_AL_M1632_0        0x1632
 247#endif
 248#ifndef PCI_DEVICE_ID_AL_M1641_0
 249#define PCI_DEVICE_ID_AL_M1641_0        0x1641
 250#endif
 251#ifndef PCI_DEVICE_ID_AL_M1647_0
 252#define PCI_DEVICE_ID_AL_M1647_0        0x1647
 253#endif
 254#ifndef PCI_DEVICE_ID_AL_M1651_0
 255#define PCI_DEVICE_ID_AL_M1651_0        0x1651
 256#endif
 257
 258/* intel register */
 259#define INTEL_APBASE    0x10
 260#define INTEL_APSIZE    0xb4
 261#define INTEL_ATTBASE   0xb8
 262#define INTEL_AGPCTRL   0xb0
 263#define INTEL_NBXCFG    0x50
 264#define INTEL_ERRSTS    0x91
 265
 266/* intel i830 registers */
 267#define I830_GMCH_CTRL             0x52
 268#define I830_GMCH_ENABLED          0x4
 269#define I830_GMCH_MEM_MASK         0x1
 270#define I830_GMCH_MEM_64M          0x1
 271#define I830_GMCH_MEM_128M         0
 272#define I830_GMCH_GMS_MASK         0x70
 273#define I830_GMCH_GMS_DISABLED     0x00
 274#define I830_GMCH_GMS_LOCAL        0x10
 275#define I830_GMCH_GMS_STOLEN_512   0x20
 276#define I830_GMCH_GMS_STOLEN_1024  0x30
 277#define I830_GMCH_GMS_STOLEN_8192  0x40
 278#define I830_RDRAM_CHANNEL_TYPE    0x03010
 279#define I830_RDRAM_ND(x)           (((x) & 0x20) >> 5)
 280#define I830_RDRAM_DDT(x)          (((x) & 0x18) >> 3)
 281
 282/* This one is for I830MP w. an external graphic card */
 283#define INTEL_I830_ERRSTS          0x92
 284
 285/* intel i820 registers */
 286#define INTEL_I820_RDCR     0x51
 287#define INTEL_I820_ERRSTS   0xc8
 288
 289/* intel i840 registers */
 290#define INTEL_I840_MCHCFG   0x50
 291#define INTEL_I840_ERRSTS   0xc8
 292 
 293/* intel i845 registers */
 294#define INTEL_I845_AGPM     0x51
 295#define INTEL_I845_ERRSTS   0xc8
 296
 297/* intel i850 registers */
 298#define INTEL_I850_MCHCFG   0x50
 299#define INTEL_I850_ERRSTS   0xc8
 300
 301/* intel i860 registers */
 302#define INTEL_I860_MCHCFG       0x50
 303#define INTEL_I860_ERRSTS       0xc8
 304
 305/* intel i810 registers */
 306#define I810_GMADDR 0x10
 307#define I810_MMADDR 0x14
 308#define I810_PTE_BASE          0x10000
 309#define I810_PTE_MAIN_UNCACHED 0x00000000
 310#define I810_PTE_LOCAL         0x00000002
 311#define I810_PTE_VALID         0x00000001
 312#define I810_SMRAM_MISCC       0x70
 313#define I810_GFX_MEM_WIN_SIZE  0x00010000
 314#define I810_GFX_MEM_WIN_32M   0x00010000
 315#define I810_GMS               0x000000c0
 316#define I810_GMS_DISABLE       0x00000000
 317#define I810_PGETBL_CTL        0x2020
 318#define I810_PGETBL_ENABLED    0x00000001
 319#define I810_DRAM_CTL          0x3000
 320#define I810_DRAM_ROW_0        0x00000001
 321#define I810_DRAM_ROW_0_SDRAM  0x00000001
 322
 323
 324
 325/* VIA register */
 326#define VIA_APBASE      0x10
 327#define VIA_GARTCTRL    0x80
 328#define VIA_APSIZE      0x84
 329#define VIA_ATTBASE     0x88
 330
 331/* SiS registers */
 332#define SIS_APBASE      0x10
 333#define SIS_ATTBASE     0x90
 334#define SIS_APSIZE      0x94
 335#define SIS_TLBCNTRL    0x97
 336#define SIS_TLBFLUSH    0x98
 337
 338/* AMD registers */
 339#define AMD_APBASE      0x10
 340#define AMD_MMBASE      0x14
 341#define AMD_APSIZE      0xac
 342#define AMD_MODECNTL    0xb0
 343#define AMD_MODECNTL2   0xb2
 344#define AMD_GARTENABLE  0x02    /* In mmio region (16-bit register) */
 345#define AMD_ATTBASE     0x04    /* In mmio region (32-bit register) */
 346#define AMD_TLBFLUSH    0x0c    /* In mmio region (32-bit register) */
 347#define AMD_CACHEENTRY  0x10    /* In mmio region (32-bit register) */
 348
 349/* ALi registers */
 350#define ALI_APBASE      0x10
 351#define ALI_AGPCTRL     0xb8
 352#define ALI_ATTBASE     0xbc
 353#define ALI_TLBCTRL     0xc0
 354#define ALI_TAGCTRL     0xc4
 355#define ALI_CACHE_FLUSH_CTRL    0xD0
 356#define ALI_CACHE_FLUSH_ADDR_MASK       0xFFFFF000
 357#define ALI_CACHE_FLUSH_EN      0x100
 358
 359/* Serverworks Registers */
 360#define SVWRKS_APSIZE 0x10
 361#define SVWRKS_SIZE_MASK 0xfe000000
 362
 363#define SVWRKS_MMBASE 0x14
 364#define SVWRKS_CACHING 0x4b
 365#define SVWRKS_FEATURE 0x68
 366
 367/* func 1 registers */
 368#define SVWRKS_AGP_ENABLE 0x60
 369#define SVWRKS_COMMAND 0x04
 370
 371/* Memory mapped registers */
 372#define SVWRKS_GART_CACHE 0x02
 373#define SVWRKS_GATTBASE   0x04
 374#define SVWRKS_TLBFLUSH   0x10
 375#define SVWRKS_POSTFLUSH  0x14
 376#define SVWRKS_DIRFLUSH   0x0c
 377
 378#endif                          /* _AGP_BACKEND_PRIV_H */
 379