1/* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM 2 * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993 3 * derived from Data Sheet, Copyright Motorola 1984 (!). 4 * It was written to be part of the Linux operating system. 5 */ 6/* permission is hereby granted to copy, modify and redistribute this code 7 * in terms of the GNU Library General Public License, Version 2 or later, 8 * at your option. 9 */ 10 11#ifndef _MC146818RTC_H 12#define _MC146818RTC_H 13#include <asm/io.h> 14 15#ifndef RTC_PORT 16#define RTC_PORT(x) (0x70 + (x)) 17#define RTC_ADDR(x) (0x80 | (x)) 18#define RTC_ALWAYS_BCD 1 19#endif 20 21#define CMOS_READ(addr) ({ \ 22outb_p(RTC_ADDR(addr),RTC_PORT(0)); \ 23inb_p(RTC_PORT(1)); \ 24}) 25#define CMOS_WRITE(val, addr) ({ \ 26outb_p(RTC_ADDR(addr),RTC_PORT(0)); \ 27outb_p(val,RTC_PORT(1)); \ 28}) 29 30/********************************************************************** 31 * register summary 32 **********************************************************************/ 33#define RTC_SECONDS 0 34#define RTC_SECONDS_ALARM 1 35#define RTC_MINUTES 2 36#define RTC_MINUTES_ALARM 3 37#define RTC_HOURS 4 38#define RTC_HOURS_ALARM 5 39/* RTC_*_alarm is always true if 2 MSBs are set */ 40# define RTC_ALARM_DONT_CARE 0xC0 41 42#define RTC_DAY_OF_WEEK 6 43#define RTC_DAY_OF_MONTH 7 44#define RTC_MONTH 8 45#define RTC_YEAR 9 46 47/* control registers - Moto names 48 */ 49#define RTC_REG_A 10 50#define RTC_REG_B 11 51#define RTC_REG_C 12 52#define RTC_REG_D 13 53 54/********************************************************************** 55 * register details 56 **********************************************************************/ 57#define RTC_FREQ_SELECT RTC_REG_A 58 59/* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus, 60 * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete, 61 * totalling to a max high interval of 2.228 ms. 62 */ 63# define RTC_UIP 0x80 64# define RTC_DIV_CTL 0x70 65 /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */ 66# define RTC_REF_CLCK_4MHZ 0x00 67# define RTC_REF_CLCK_1MHZ 0x10 68# define RTC_REF_CLCK_32KHZ 0x20 69 /* 2 values for divider stage reset, others for "testing purposes only" */ 70# define RTC_DIV_RESET1 0x60 71# define RTC_DIV_RESET2 0x70 72 /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */ 73# define RTC_RATE_SELECT 0x0F 74 75/**********************************************************************/ 76#define RTC_CONTROL RTC_REG_B 77# define RTC_SET 0x80 /* disable updates for clock setting */ 78# define RTC_PIE 0x40 /* periodic interrupt enable */ 79# define RTC_AIE 0x20 /* alarm interrupt enable */ 80# define RTC_UIE 0x10 /* update-finished interrupt enable */ 81# define RTC_SQWE 0x08 /* enable square-wave output */ 82# define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ 83# define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ 84# define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ 85 86/**********************************************************************/ 87#define RTC_INTR_FLAGS RTC_REG_C 88/* caution - cleared by read */ 89# define RTC_IRQF 0x80 /* any of the following 3 is active */ 90# define RTC_PF 0x40 91# define RTC_AF 0x20 92# define RTC_UF 0x10 93 94/**********************************************************************/ 95#define RTC_VALID RTC_REG_D 96# define RTC_VRT 0x80 /* valid RAM and time */ 97/**********************************************************************/ 98 99/* example: !(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) 100 * determines if the following two #defines are needed 101 */ 102#ifndef BCD_TO_BIN 103#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) 104#endif 105 106#ifndef BIN_TO_BCD 107#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10) 108#endif 109 110#endif /* _MC146818RTC_H */ 111